11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 220848903SChaotian Jing /* 320848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 420848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 520848903SChaotian Jing */ 620848903SChaotian Jing 720848903SChaotian Jing #include <linux/module.h> 84fe54318SAngeloGioacchino Del Regno #include <linux/bitops.h> 920848903SChaotian Jing #include <linux/clk.h> 1020848903SChaotian Jing #include <linux/delay.h> 1120848903SChaotian Jing #include <linux/dma-mapping.h> 1243e5fee3SDerong Liu #include <linux/iopoll.h> 1320848903SChaotian Jing #include <linux/ioport.h> 1420848903SChaotian Jing #include <linux/irq.h> 1520848903SChaotian Jing #include <linux/of_address.h> 16909b3456SRyder Lee #include <linux/of_device.h> 1720848903SChaotian Jing #include <linux/of_irq.h> 1820848903SChaotian Jing #include <linux/of_gpio.h> 1920848903SChaotian Jing #include <linux/pinctrl/consumer.h> 2020848903SChaotian Jing #include <linux/platform_device.h> 214b8a43e9SChaotian Jing #include <linux/pm.h> 224b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2320848903SChaotian Jing #include <linux/regulator/consumer.h> 246397b7f5SChaotian Jing #include <linux/slab.h> 2520848903SChaotian Jing #include <linux/spinlock.h> 26b8789ec4SUlf Hansson #include <linux/interrupt.h> 27855d388dSWenbin Mei #include <linux/reset.h> 2820848903SChaotian Jing 2920848903SChaotian Jing #include <linux/mmc/card.h> 3020848903SChaotian Jing #include <linux/mmc/core.h> 3120848903SChaotian Jing #include <linux/mmc/host.h> 3220848903SChaotian Jing #include <linux/mmc/mmc.h> 3320848903SChaotian Jing #include <linux/mmc/sd.h> 3420848903SChaotian Jing #include <linux/mmc/sdio.h> 358d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 3620848903SChaotian Jing 3788bd652bSChun-Hung Wu #include "cqhci.h" 3888bd652bSChun-Hung Wu 3920848903SChaotian Jing #define MAX_BD_NUM 1024 40f5eccd94SWenbin Mei #define MSDC_NR_CLOCKS 3 4120848903SChaotian Jing 4220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4320848903SChaotian Jing /* Common Definition */ 4420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4520848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4620848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4720848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4820848903SChaotian Jing 4920848903SChaotian Jing #define MSDC_BURST_64B 0x6 5020848903SChaotian Jing 5120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5220848903SChaotian Jing /* Register Offset */ 5320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5420848903SChaotian Jing #define MSDC_CFG 0x0 5520848903SChaotian Jing #define MSDC_IOCON 0x04 5620848903SChaotian Jing #define MSDC_PS 0x08 5720848903SChaotian Jing #define MSDC_INT 0x0c 5820848903SChaotian Jing #define MSDC_INTEN 0x10 5920848903SChaotian Jing #define MSDC_FIFOCS 0x14 6020848903SChaotian Jing #define SDC_CFG 0x30 6120848903SChaotian Jing #define SDC_CMD 0x34 6220848903SChaotian Jing #define SDC_ARG 0x38 6320848903SChaotian Jing #define SDC_STS 0x3c 6420848903SChaotian Jing #define SDC_RESP0 0x40 6520848903SChaotian Jing #define SDC_RESP1 0x44 6620848903SChaotian Jing #define SDC_RESP2 0x48 6720848903SChaotian Jing #define SDC_RESP3 0x4c 6820848903SChaotian Jing #define SDC_BLK_NUM 0x50 69d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 70c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 7120848903SChaotian Jing #define SDC_ACMD_RESP 0x80 722a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 7320848903SChaotian Jing #define MSDC_DMA_SA 0x90 7420848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7520848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7620848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7720848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 782fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 7920848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 8039add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 816397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 821ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 8313b4e1e9SWenbin Mei #define EMMC51_CFG0 0x204 846397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 8513b4e1e9SWenbin Mei #define EMMC50_CFG1 0x20c 86c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 87d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 8813b4e1e9SWenbin Mei #define CQHCI_SETTING 0x7fc 8920848903SChaotian Jing 9020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 91a2e6d1f6SChaotian Jing /* Top Pad Register Offset */ 92a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 93a2e6d1f6SChaotian Jing #define EMMC_TOP_CONTROL 0x00 94a2e6d1f6SChaotian Jing #define EMMC_TOP_CMD 0x04 95a2e6d1f6SChaotian Jing #define EMMC50_PAD_DS_TUNE 0x0c 96a2e6d1f6SChaotian Jing 97a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 9820848903SChaotian Jing /* Register Mask */ 9920848903SChaotian Jing /*--------------------------------------------------------------------------*/ 10020848903SChaotian Jing 10120848903SChaotian Jing /* MSDC_CFG mask */ 1024fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_MODE BIT(0) /* RW */ 1034fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKPDN BIT(1) /* RW */ 1044fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_RST BIT(2) /* RW */ 1054fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_PIO BIT(3) /* RW */ 1064fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 1074fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 1084fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_BV18PSS BIT(6) /* R */ 1094fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKSTB BIT(7) /* R */ 1104fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 1114fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 1124fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 1134fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 1144fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 1154fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 11620848903SChaotian Jing 11720848903SChaotian Jing /* MSDC_IOCON mask */ 1184fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 1194fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_RSPL BIT(1) /* RW */ 1204fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DSPL BIT(2) /* RW */ 1214fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 1224fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 1234fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 1244fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 1254fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 1264fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 1274fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 1284fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 1294fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 1304fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 1314fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 1324fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 1334fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 13420848903SChaotian Jing 13520848903SChaotian Jing /* MSDC_PS mask */ 1364fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDEN BIT(0) /* RW */ 1374fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDSTS BIT(1) /* R */ 1384fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 1394fe54318SAngeloGioacchino Del Regno #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 1404fe54318SAngeloGioacchino Del Regno #define MSDC_PS_DATA1 BIT(17) /* R */ 1414fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CMD BIT(24) /* R */ 1424fe54318SAngeloGioacchino Del Regno #define MSDC_PS_WP BIT(31) /* R */ 14320848903SChaotian Jing 14420848903SChaotian Jing /* MSDC_INT mask */ 1454fe54318SAngeloGioacchino Del Regno #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 1464fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CDSC BIT(1) /* W1C */ 1474fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 1484fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 1494fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 1504fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 1514fe54318SAngeloGioacchino Del Regno #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 1524fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 1534fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 1544fe54318SAngeloGioacchino Del Regno #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 1554fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CSTA BIT(11) /* R */ 1564fe54318SAngeloGioacchino Del Regno #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 1574fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 1584fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DATTMO BIT(14) /* W1C */ 1594fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 1604fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 1614fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 1624fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 1634fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 1644fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDQ BIT(28) /* W1C */ 16520848903SChaotian Jing 16620848903SChaotian Jing /* MSDC_INTEN mask */ 1674fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 1684fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CDSC BIT(1) /* RW */ 1694fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 1704fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 1714fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 1724fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 1734fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 1744fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 1754fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 1764fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 1774fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CSTA BIT(11) /* RW */ 1784fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 1794fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 1804fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 1814fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 1824fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 1834fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 1844fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 1854fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 18620848903SChaotian Jing 18720848903SChaotian Jing /* MSDC_FIFOCS mask */ 1884fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 1894fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 1904fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 19120848903SChaotian Jing 19220848903SChaotian Jing /* SDC_CFG mask */ 1934fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 1944fe54318SAngeloGioacchino Del Regno #define SDC_CFG_INSWKUP BIT(1) /* RW */ 1954fe54318SAngeloGioacchino Del Regno #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 1964fe54318SAngeloGioacchino Del Regno #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 1974fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIO BIT(19) /* RW */ 1984fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 1994fe54318SAngeloGioacchino Del Regno #define SDC_CFG_INTATGAP BIT(21) /* RW */ 2004fe54318SAngeloGioacchino Del Regno #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 20120848903SChaotian Jing 20220848903SChaotian Jing /* SDC_STS mask */ 2034fe54318SAngeloGioacchino Del Regno #define SDC_STS_SDCBUSY BIT(0) /* RW */ 2044fe54318SAngeloGioacchino Del Regno #define SDC_STS_CMDBUSY BIT(1) /* RW */ 2054fe54318SAngeloGioacchino Del Regno #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 20620848903SChaotian Jing 2074fe54318SAngeloGioacchino Del Regno #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 208d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 2094fe54318SAngeloGioacchino Del Regno #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 210d9dcbfc8SChaotian Jing 2112a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2124fe54318SAngeloGioacchino Del Regno #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 2132a9bde19SChaotian Jing 21420848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 2154fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_START BIT(0) /* W */ 2164fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 2174fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 2184fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 2194fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 2204fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 22120848903SChaotian Jing 22220848903SChaotian Jing /* MSDC_DMA_CFG mask */ 2234fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_STS BIT(0) /* R */ 2244fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 2254fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 2264fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 2274fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 22820848903SChaotian Jing 22920848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 2304fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 2314fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 2324fe54318SAngeloGioacchino Del Regno #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 2334fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 2344fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 2354fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 2364fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 2374fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 2384fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 2394fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 2404fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 2414fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 24220848903SChaotian Jing 2434fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 2444fe54318SAngeloGioacchino Del Regno #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 2454fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 246d9dcbfc8SChaotian Jing 2474fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 2484fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 2494fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 2504fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 2514fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 2524fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 2532fea5819SChaotian Jing 2544fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 2554fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 2564fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 2574fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 2584fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 2594fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 2604fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 2614fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 2626397b7f5SChaotian Jing 2634fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 2644fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 2654fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 2664fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 2676397b7f5SChaotian Jing 2684fe54318SAngeloGioacchino Del Regno #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 2691ede5cb8Syong mao 27013b4e1e9SWenbin Mei /* EMMC51_CFG0 mask */ 2714fe54318SAngeloGioacchino Del Regno #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 27213b4e1e9SWenbin Mei 2734fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 2744fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 2754fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 2764fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 27713b4e1e9SWenbin Mei 27813b4e1e9SWenbin Mei /* EMMC50_CFG1 mask */ 2794fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 2806397b7f5SChaotian Jing 2814fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 282c8609b22SChaotian Jing 2834fe54318SAngeloGioacchino Del Regno #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 2844fe54318SAngeloGioacchino Del Regno #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 285d9dcbfc8SChaotian Jing 28613b4e1e9SWenbin Mei /* CQHCI_SETTING */ 2874fe54318SAngeloGioacchino Del Regno #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 2884fe54318SAngeloGioacchino Del Regno #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 28913b4e1e9SWenbin Mei 290a2e6d1f6SChaotian Jing /* EMMC_TOP_CONTROL mask */ 2914fe54318SAngeloGioacchino Del Regno #define PAD_RXDLY_SEL BIT(0) /* RW */ 2924fe54318SAngeloGioacchino Del Regno #define DELAY_EN BIT(1) /* RW */ 2934fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 2944fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 2954fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 2964fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 2974fe54318SAngeloGioacchino Del Regno #define DATA_K_VALUE_SEL BIT(14) /* RW */ 2984fe54318SAngeloGioacchino Del Regno #define SDC_RX_ENH_EN BIT(15) /* TW */ 299a2e6d1f6SChaotian Jing 300a2e6d1f6SChaotian Jing /* EMMC_TOP_CMD mask */ 3014fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 3024fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 3034fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 3044fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 3054fe54318SAngeloGioacchino Del Regno #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 306a2e6d1f6SChaotian Jing 307c4ac38c6SWenbin Mei /* EMMC50_PAD_DS_TUNE mask */ 3084fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY_SEL BIT(16) /* RW */ 3094fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 3104fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 311c4ac38c6SWenbin Mei 3124fe54318SAngeloGioacchino Del Regno #define REQ_CMD_EIO BIT(0) 3134fe54318SAngeloGioacchino Del Regno #define REQ_CMD_TMO BIT(1) 3144fe54318SAngeloGioacchino Del Regno #define REQ_DAT_ERR BIT(2) 3154fe54318SAngeloGioacchino Del Regno #define REQ_STOP_EIO BIT(3) 3164fe54318SAngeloGioacchino Del Regno #define REQ_STOP_TMO BIT(4) 3174fe54318SAngeloGioacchino Del Regno #define REQ_CMD_BUSY BIT(5) 31820848903SChaotian Jing 3194fe54318SAngeloGioacchino Del Regno #define MSDC_PREPARE_FLAG BIT(0) 3204fe54318SAngeloGioacchino Del Regno #define MSDC_ASYNC_FLAG BIT(1) 3214fe54318SAngeloGioacchino Del Regno #define MSDC_MMAP_FLAG BIT(2) 32220848903SChaotian Jing 3234b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 32420848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 32520848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 32620848903SChaotian Jing 327d087bde5SNeilBrown #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 328d087bde5SNeilBrown 3296397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 33020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 33120848903SChaotian Jing /* Descriptor Structure */ 33220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 33320848903SChaotian Jing struct mt_gpdma_desc { 33420848903SChaotian Jing u32 gpd_info; 3354fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_HWO BIT(0) 3364fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_BDP BIT(1) 3374fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 3384fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_INT BIT(16) 3394fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 3404fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 34120848903SChaotian Jing u32 next; 34220848903SChaotian Jing u32 ptr; 34320848903SChaotian Jing u32 gpd_data_len; 3444fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 3454fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 34620848903SChaotian Jing u32 arg; 34720848903SChaotian Jing u32 blknum; 34820848903SChaotian Jing u32 cmd; 34920848903SChaotian Jing }; 35020848903SChaotian Jing 35120848903SChaotian Jing struct mt_bdma_desc { 35220848903SChaotian Jing u32 bd_info; 3534fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_EOL BIT(0) 3544fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 3554fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BLKPAD BIT(17) 3564fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_DWPAD BIT(18) 3574fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 3584fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 35920848903SChaotian Jing u32 next; 36020848903SChaotian Jing u32 ptr; 36120848903SChaotian Jing u32 bd_data_len; 3624fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BUFLEN GENMASK(15, 0) 3634fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 36420848903SChaotian Jing }; 36520848903SChaotian Jing 36620848903SChaotian Jing struct msdc_dma { 36720848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 36820848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 36920848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 37020848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 37120848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 37220848903SChaotian Jing }; 37320848903SChaotian Jing 3744b8a43e9SChaotian Jing struct msdc_save_para { 3754b8a43e9SChaotian Jing u32 msdc_cfg; 3764b8a43e9SChaotian Jing u32 iocon; 3774b8a43e9SChaotian Jing u32 sdc_cfg; 3784b8a43e9SChaotian Jing u32 pad_tune; 3794b8a43e9SChaotian Jing u32 patch_bit0; 3804b8a43e9SChaotian Jing u32 patch_bit1; 3812fea5819SChaotian Jing u32 patch_bit2; 3826397b7f5SChaotian Jing u32 pad_ds_tune; 3831ede5cb8Syong mao u32 pad_cmd_tune; 3846397b7f5SChaotian Jing u32 emmc50_cfg0; 385c8609b22SChaotian Jing u32 emmc50_cfg3; 386d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 387a2e6d1f6SChaotian Jing u32 emmc_top_control; 388a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 389a2e6d1f6SChaotian Jing u32 emmc50_pad_ds_tune; 3906397b7f5SChaotian Jing }; 3916397b7f5SChaotian Jing 392762d491aSChaotian Jing struct mtk_mmc_compatible { 393762d491aSChaotian Jing u8 clk_div_bits; 3949e2582e5Syong mao bool recheck_sdio_irq; 3957f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 39639add252SChaotian Jing u32 pad_tune_reg; 3972fea5819SChaotian Jing bool async_fifo; 3982fea5819SChaotian Jing bool data_tune; 399acde28c4SChaotian Jing bool busy_check; 400d9dcbfc8SChaotian Jing bool stop_clk_fix; 401d9dcbfc8SChaotian Jing bool enhance_rx; 4022a9bde19SChaotian Jing bool support_64g; 403d087bde5SNeilBrown bool use_internal_cd; 404762d491aSChaotian Jing }; 405762d491aSChaotian Jing 40686beac37SChaotian Jing struct msdc_tune_para { 40786beac37SChaotian Jing u32 iocon; 40886beac37SChaotian Jing u32 pad_tune; 4091ede5cb8Syong mao u32 pad_cmd_tune; 410a2e6d1f6SChaotian Jing u32 emmc_top_control; 411a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 41286beac37SChaotian Jing }; 41386beac37SChaotian Jing 4146397b7f5SChaotian Jing struct msdc_delay_phase { 4156397b7f5SChaotian Jing u8 maxlen; 4166397b7f5SChaotian Jing u8 start; 4176397b7f5SChaotian Jing u8 final_phase; 4184b8a43e9SChaotian Jing }; 4194b8a43e9SChaotian Jing 42020848903SChaotian Jing struct msdc_host { 42120848903SChaotian Jing struct device *dev; 422762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 42320848903SChaotian Jing int cmd_rsp; 42420848903SChaotian Jing 42520848903SChaotian Jing spinlock_t lock; 42620848903SChaotian Jing struct mmc_request *mrq; 42720848903SChaotian Jing struct mmc_command *cmd; 42820848903SChaotian Jing struct mmc_data *data; 42920848903SChaotian Jing int error; 43020848903SChaotian Jing 43120848903SChaotian Jing void __iomem *base; /* host base address */ 432a2e6d1f6SChaotian Jing void __iomem *top_base; /* host top register base address */ 43320848903SChaotian Jing 43420848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 43520848903SChaotian Jing u64 dma_mask; 43620848903SChaotian Jing 43720848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 43820848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 43920848903SChaotian Jing 44020848903SChaotian Jing struct pinctrl *pinctrl; 44120848903SChaotian Jing struct pinctrl_state *pins_default; 44220848903SChaotian Jing struct pinctrl_state *pins_uhs; 44320848903SChaotian Jing struct delayed_work req_timeout; 44420848903SChaotian Jing int irq; /* host interrupt */ 445855d388dSWenbin Mei struct reset_control *reset; 44620848903SChaotian Jing 44720848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 44820848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 449258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 4503c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 451f5eccd94SWenbin Mei struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 452f5eccd94SWenbin Mei struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 45320848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 45420848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 4556e622947SChaotian Jing unsigned char timing; 45620848903SChaotian Jing bool vqmmc_enabled; 457d17bb71cSChaotian Jing u32 latch_ck; 4586397b7f5SChaotian Jing u32 hs400_ds_delay; 459c4ac38c6SWenbin Mei u32 hs400_ds_dly3; 4601ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 4611ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4621ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4631ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4645462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 465c4ac38c6SWenbin Mei bool hs400_tuning; /* hs400 mode online tuning */ 466d087bde5SNeilBrown bool internal_cd; /* Use internal card-detect logic */ 46788bd652bSChun-Hung Wu bool cqhci; /* support eMMC hw cmdq */ 4684b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 46986beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 47086beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 47188bd652bSChun-Hung Wu struct cqhci_host *cq_host; 47220848903SChaotian Jing }; 47320848903SChaotian Jing 474762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 475762d491aSChaotian Jing .clk_div_bits = 8, 476903a72ecSyong mao .recheck_sdio_irq = true, 4777f3d5852SChaotian Jing .hs400_tune = false, 47839add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4792fea5819SChaotian Jing .async_fifo = false, 4802fea5819SChaotian Jing .data_tune = false, 481acde28c4SChaotian Jing .busy_check = false, 482d9dcbfc8SChaotian Jing .stop_clk_fix = false, 483d9dcbfc8SChaotian Jing .enhance_rx = false, 4842a9bde19SChaotian Jing .support_64g = false, 485762d491aSChaotian Jing }; 486762d491aSChaotian Jing 487762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 488762d491aSChaotian Jing .clk_div_bits = 8, 4899e2582e5Syong mao .recheck_sdio_irq = true, 4907f3d5852SChaotian Jing .hs400_tune = true, 49139add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4922fea5819SChaotian Jing .async_fifo = false, 4932fea5819SChaotian Jing .data_tune = false, 494acde28c4SChaotian Jing .busy_check = false, 495d9dcbfc8SChaotian Jing .stop_clk_fix = false, 496d9dcbfc8SChaotian Jing .enhance_rx = false, 4972a9bde19SChaotian Jing .support_64g = false, 498762d491aSChaotian Jing }; 499762d491aSChaotian Jing 500a2e6d1f6SChaotian Jing static const struct mtk_mmc_compatible mt8183_compat = { 501a2e6d1f6SChaotian Jing .clk_div_bits = 12, 5029e2582e5Syong mao .recheck_sdio_irq = false, 503a2e6d1f6SChaotian Jing .hs400_tune = false, 504a2e6d1f6SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 505a2e6d1f6SChaotian Jing .async_fifo = true, 506a2e6d1f6SChaotian Jing .data_tune = true, 507a2e6d1f6SChaotian Jing .busy_check = true, 508a2e6d1f6SChaotian Jing .stop_clk_fix = true, 509a2e6d1f6SChaotian Jing .enhance_rx = true, 510a2e6d1f6SChaotian Jing .support_64g = true, 511a2e6d1f6SChaotian Jing }; 512a2e6d1f6SChaotian Jing 513762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2701_compat = { 514762d491aSChaotian Jing .clk_div_bits = 12, 515903a72ecSyong mao .recheck_sdio_irq = true, 5167f3d5852SChaotian Jing .hs400_tune = false, 51739add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5182fea5819SChaotian Jing .async_fifo = true, 5192fea5819SChaotian Jing .data_tune = true, 520acde28c4SChaotian Jing .busy_check = false, 521d9dcbfc8SChaotian Jing .stop_clk_fix = false, 522d9dcbfc8SChaotian Jing .enhance_rx = false, 5232a9bde19SChaotian Jing .support_64g = false, 524762d491aSChaotian Jing }; 525762d491aSChaotian Jing 526762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2712_compat = { 527762d491aSChaotian Jing .clk_div_bits = 12, 5289e2582e5Syong mao .recheck_sdio_irq = false, 5297f3d5852SChaotian Jing .hs400_tune = false, 53039add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5312fea5819SChaotian Jing .async_fifo = true, 5322fea5819SChaotian Jing .data_tune = true, 533acde28c4SChaotian Jing .busy_check = true, 534d9dcbfc8SChaotian Jing .stop_clk_fix = true, 535d9dcbfc8SChaotian Jing .enhance_rx = true, 5362a9bde19SChaotian Jing .support_64g = true, 537762d491aSChaotian Jing }; 538762d491aSChaotian Jing 539966580adSSean Wang static const struct mtk_mmc_compatible mt7622_compat = { 540966580adSSean Wang .clk_div_bits = 12, 541903a72ecSyong mao .recheck_sdio_irq = true, 542966580adSSean Wang .hs400_tune = false, 543966580adSSean Wang .pad_tune_reg = MSDC_PAD_TUNE0, 544966580adSSean Wang .async_fifo = true, 545966580adSSean Wang .data_tune = true, 546966580adSSean Wang .busy_check = true, 547966580adSSean Wang .stop_clk_fix = true, 548966580adSSean Wang .enhance_rx = true, 5492a9bde19SChaotian Jing .support_64g = false, 550966580adSSean Wang }; 551966580adSSean Wang 55289822b73SFabien Parent static const struct mtk_mmc_compatible mt8516_compat = { 55389822b73SFabien Parent .clk_div_bits = 12, 554903a72ecSyong mao .recheck_sdio_irq = true, 55589822b73SFabien Parent .hs400_tune = false, 55689822b73SFabien Parent .pad_tune_reg = MSDC_PAD_TUNE0, 55789822b73SFabien Parent .async_fifo = true, 55889822b73SFabien Parent .data_tune = true, 55989822b73SFabien Parent .busy_check = true, 56089822b73SFabien Parent .stop_clk_fix = true, 56189822b73SFabien Parent }; 56289822b73SFabien Parent 563afb7c791SNeilBrown static const struct mtk_mmc_compatible mt7620_compat = { 564afb7c791SNeilBrown .clk_div_bits = 8, 565903a72ecSyong mao .recheck_sdio_irq = true, 566afb7c791SNeilBrown .hs400_tune = false, 567afb7c791SNeilBrown .pad_tune_reg = MSDC_PAD_TUNE, 568afb7c791SNeilBrown .async_fifo = false, 569afb7c791SNeilBrown .data_tune = false, 570afb7c791SNeilBrown .busy_check = false, 571afb7c791SNeilBrown .stop_clk_fix = false, 572afb7c791SNeilBrown .enhance_rx = false, 573d087bde5SNeilBrown .use_internal_cd = true, 574afb7c791SNeilBrown }; 575afb7c791SNeilBrown 5767d176b0eSChun-Hung Wu static const struct mtk_mmc_compatible mt6779_compat = { 5777d176b0eSChun-Hung Wu .clk_div_bits = 12, 578903a72ecSyong mao .recheck_sdio_irq = false, 5797d176b0eSChun-Hung Wu .hs400_tune = false, 5807d176b0eSChun-Hung Wu .pad_tune_reg = MSDC_PAD_TUNE0, 5817d176b0eSChun-Hung Wu .async_fifo = true, 5827d176b0eSChun-Hung Wu .data_tune = true, 5837d176b0eSChun-Hung Wu .busy_check = true, 5847d176b0eSChun-Hung Wu .stop_clk_fix = true, 5857d176b0eSChun-Hung Wu .enhance_rx = true, 5867d176b0eSChun-Hung Wu .support_64g = true, 5877d176b0eSChun-Hung Wu }; 5887d176b0eSChun-Hung Wu 589762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 590762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 591762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 592a2e6d1f6SChaotian Jing { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 593762d491aSChaotian Jing { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 594762d491aSChaotian Jing { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 595966580adSSean Wang { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 59689822b73SFabien Parent { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 597afb7c791SNeilBrown { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 5987d176b0eSChun-Hung Wu { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 599762d491aSChaotian Jing {} 600762d491aSChaotian Jing }; 601762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 602762d491aSChaotian Jing 60320848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 60420848903SChaotian Jing { 60520848903SChaotian Jing u32 val = readl(reg); 60620848903SChaotian Jing 60720848903SChaotian Jing val |= bs; 60820848903SChaotian Jing writel(val, reg); 60920848903SChaotian Jing } 61020848903SChaotian Jing 61120848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 61220848903SChaotian Jing { 61320848903SChaotian Jing u32 val = readl(reg); 61420848903SChaotian Jing 61520848903SChaotian Jing val &= ~bs; 61620848903SChaotian Jing writel(val, reg); 61720848903SChaotian Jing } 61820848903SChaotian Jing 61920848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 62020848903SChaotian Jing { 62120848903SChaotian Jing unsigned int tv = readl(reg); 62220848903SChaotian Jing 62320848903SChaotian Jing tv &= ~field; 62420848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 62520848903SChaotian Jing writel(tv, reg); 62620848903SChaotian Jing } 62720848903SChaotian Jing 62820848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 62920848903SChaotian Jing { 63020848903SChaotian Jing unsigned int tv = readl(reg); 63120848903SChaotian Jing 63220848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 63320848903SChaotian Jing } 63420848903SChaotian Jing 63520848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 63620848903SChaotian Jing { 63720848903SChaotian Jing u32 val; 63820848903SChaotian Jing 63920848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 640ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 64120848903SChaotian Jing 64220848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 643ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_FIFOCS, val, 644ffaea6ebSAngeloGioacchino Del Regno !(val & MSDC_FIFOCS_CLR), 0, 0); 64520848903SChaotian Jing 64620848903SChaotian Jing val = readl(host->base + MSDC_INT); 64720848903SChaotian Jing writel(val, host->base + MSDC_INT); 64820848903SChaotian Jing } 64920848903SChaotian Jing 65020848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 65120848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 6529e2582e5Syong mao static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 65320848903SChaotian Jing 654726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 655726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 656726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 657726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 65820848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 65920848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 66020848903SChaotian Jing 66120848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 66220848903SChaotian Jing { 66320848903SChaotian Jing u32 i, sum = 0; 66420848903SChaotian Jing 66520848903SChaotian Jing for (i = 0; i < len; i++) 66620848903SChaotian Jing sum += buf[i]; 66720848903SChaotian Jing return 0xff - (u8) sum; 66820848903SChaotian Jing } 66920848903SChaotian Jing 67020848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 67120848903SChaotian Jing struct mmc_data *data) 67220848903SChaotian Jing { 67320848903SChaotian Jing unsigned int j, dma_len; 67420848903SChaotian Jing dma_addr_t dma_address; 67520848903SChaotian Jing u32 dma_ctrl; 67620848903SChaotian Jing struct scatterlist *sg; 67720848903SChaotian Jing struct mt_gpdma_desc *gpd; 67820848903SChaotian Jing struct mt_bdma_desc *bd; 67920848903SChaotian Jing 68020848903SChaotian Jing sg = data->sg; 68120848903SChaotian Jing 68220848903SChaotian Jing gpd = dma->gpd; 68320848903SChaotian Jing bd = dma->bd; 68420848903SChaotian Jing 68520848903SChaotian Jing /* modify gpd */ 68620848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 68720848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 68820848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 68920848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 69020848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 69120848903SChaotian Jing 69220848903SChaotian Jing /* modify bd */ 69320848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 69420848903SChaotian Jing dma_address = sg_dma_address(sg); 69520848903SChaotian Jing dma_len = sg_dma_len(sg); 69620848903SChaotian Jing 69720848903SChaotian Jing /* init bd */ 69820848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 69920848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 7002a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 7012a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 7022a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 7032a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 7042a9bde19SChaotian Jing << 28; 7052a9bde19SChaotian Jing } 7066ef042bdSChaotian Jing 7076ef042bdSChaotian Jing if (host->dev_comp->support_64g) { 7086ef042bdSChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 7096ef042bdSChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 7106ef042bdSChaotian Jing } else { 71120848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 71220848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 7136ef042bdSChaotian Jing } 71420848903SChaotian Jing 71520848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 71620848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 71720848903SChaotian Jing else 71820848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 71920848903SChaotian Jing 72020848903SChaotian Jing /* checksume need to clear first */ 72120848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 72220848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 72320848903SChaotian Jing } 72420848903SChaotian Jing 72520848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 72620848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 72720848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 7284fe54318SAngeloGioacchino Del Regno dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 72920848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 7302a9bde19SChaotian Jing if (host->dev_comp->support_64g) 7312a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 7322a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 7332a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 73420848903SChaotian Jing } 73520848903SChaotian Jing 73615107135SYue Hu static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 73720848903SChaotian Jing { 73820848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 73920848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 74020848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 741feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 74220848903SChaotian Jing } 74320848903SChaotian Jing } 74420848903SChaotian Jing 74515107135SYue Hu static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 74620848903SChaotian Jing { 74720848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 74820848903SChaotian Jing return; 74920848903SChaotian Jing 75020848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 75120848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 752feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 75320848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 75420848903SChaotian Jing } 75520848903SChaotian Jing } 75620848903SChaotian Jing 757557011b6SChun-Hung Wu static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 75820848903SChaotian Jing { 7590caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 760557011b6SChun-Hung Wu u64 timeout, clk_ns; 76120848903SChaotian Jing u32 mode = 0; 76220848903SChaotian Jing 7630caf60c4SAmey Narkhede if (mmc->actual_clock == 0) { 76420848903SChaotian Jing timeout = 0; 76520848903SChaotian Jing } else { 766557011b6SChun-Hung Wu clk_ns = 1000000000ULL; 7670caf60c4SAmey Narkhede do_div(clk_ns, mmc->actual_clock); 768557011b6SChun-Hung Wu timeout = ns + clk_ns - 1; 769557011b6SChun-Hung Wu do_div(timeout, clk_ns); 770557011b6SChun-Hung Wu timeout += clks; 77120848903SChaotian Jing /* in 1048576 sclk cycle unit */ 7724fe54318SAngeloGioacchino Del Regno timeout = DIV_ROUND_UP(timeout, BIT(20)); 773762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 774762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 775762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 776762d491aSChaotian Jing else 777762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 778762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 77920848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 78020848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 78120848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 78220848903SChaotian Jing } 783557011b6SChun-Hung Wu return timeout; 784557011b6SChun-Hung Wu } 785557011b6SChun-Hung Wu 786557011b6SChun-Hung Wu /* clock control primitives */ 787557011b6SChun-Hung Wu static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 788557011b6SChun-Hung Wu { 789557011b6SChun-Hung Wu u64 timeout; 790557011b6SChun-Hung Wu 791557011b6SChun-Hung Wu host->timeout_ns = ns; 792557011b6SChun-Hung Wu host->timeout_clks = clks; 793557011b6SChun-Hung Wu 794557011b6SChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 795557011b6SChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 796557011b6SChun-Hung Wu (u32)(timeout > 255 ? 255 : timeout)); 79720848903SChaotian Jing } 79820848903SChaotian Jing 79988bd652bSChun-Hung Wu static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 80088bd652bSChun-Hung Wu { 80188bd652bSChun-Hung Wu u64 timeout; 80288bd652bSChun-Hung Wu 80388bd652bSChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 80488bd652bSChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 80588bd652bSChun-Hung Wu (u32)(timeout > 8191 ? 8191 : timeout)); 80688bd652bSChun-Hung Wu } 80788bd652bSChun-Hung Wu 80820848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 80920848903SChaotian Jing { 810f5eccd94SWenbin Mei clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 8113c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 81220848903SChaotian Jing clk_disable_unprepare(host->src_clk); 813258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 81420848903SChaotian Jing clk_disable_unprepare(host->h_clk); 81520848903SChaotian Jing } 81620848903SChaotian Jing 817ffaea6ebSAngeloGioacchino Del Regno static int msdc_ungate_clock(struct msdc_host *host) 81820848903SChaotian Jing { 819ffaea6ebSAngeloGioacchino Del Regno u32 val; 820f5eccd94SWenbin Mei int ret; 821f5eccd94SWenbin Mei 82220848903SChaotian Jing clk_prepare_enable(host->h_clk); 823258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 82420848903SChaotian Jing clk_prepare_enable(host->src_clk); 8253c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 826f5eccd94SWenbin Mei ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 827f5eccd94SWenbin Mei if (ret) { 828f5eccd94SWenbin Mei dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 829ffaea6ebSAngeloGioacchino Del Regno return ret; 830f5eccd94SWenbin Mei } 831f5eccd94SWenbin Mei 832ffaea6ebSAngeloGioacchino Del Regno return readl_poll_timeout(host->base + MSDC_CFG, val, 833ffaea6ebSAngeloGioacchino Del Regno (val & MSDC_CFG_CKSTB), 1, 20000); 83420848903SChaotian Jing } 83520848903SChaotian Jing 8366e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 83720848903SChaotian Jing { 8380caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 83920848903SChaotian Jing u32 mode; 84020848903SChaotian Jing u32 flags; 84120848903SChaotian Jing u32 div; 84220848903SChaotian Jing u32 sclk; 84339add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 844ffaea6ebSAngeloGioacchino Del Regno u32 val; 84520848903SChaotian Jing 84620848903SChaotian Jing if (!hz) { 84720848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 84820848903SChaotian Jing host->mclk = 0; 8490caf60c4SAmey Narkhede mmc->actual_clock = 0; 85020848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 85120848903SChaotian Jing return; 85220848903SChaotian Jing } 85320848903SChaotian Jing 85420848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 85520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 856762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8576397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 858762d491aSChaotian Jing else 859762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 860762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8616e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 8626397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 8636397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 8646397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 8656397b7f5SChaotian Jing mode = 0x3; 8666397b7f5SChaotian Jing else 86720848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 8686397b7f5SChaotian Jing 86920848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 87020848903SChaotian Jing div = 0; /* mean div = 1/4 */ 87120848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 87220848903SChaotian Jing } else { 87320848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 87420848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 87520848903SChaotian Jing div = (div >> 1); 87620848903SChaotian Jing } 8776397b7f5SChaotian Jing 8786397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 8796397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 880762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8816397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 8826397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 883762d491aSChaotian Jing else 884762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 885762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8866397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 8876397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 8886397b7f5SChaotian Jing } 88920848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 89020848903SChaotian Jing mode = 0x1; /* no divisor */ 89120848903SChaotian Jing div = 0; 89220848903SChaotian Jing sclk = host->src_clk_freq; 89320848903SChaotian Jing } else { 89420848903SChaotian Jing mode = 0x0; /* use divisor */ 89520848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 89620848903SChaotian Jing div = 0; /* mean div = 1/2 */ 89720848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 89820848903SChaotian Jing } else { 89920848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 90020848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 90120848903SChaotian Jing } 90220848903SChaotian Jing } 9033c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 904*e5e8b224SAngeloGioacchino Del Regno 9053c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 906762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 907762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 908762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 90940ceda09Syong mao (mode << 8) | div); 910762d491aSChaotian Jing else 911762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 912762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 913762d491aSChaotian Jing (mode << 12) | div); 914762d491aSChaotian Jing 915*e5e8b224SAngeloGioacchino Del Regno clk_prepare_enable(host->src_clk_cg); 916ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 9173c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 9180caf60c4SAmey Narkhede mmc->actual_clock = sclk; 91920848903SChaotian Jing host->mclk = hz; 9206e622947SChaotian Jing host->timing = timing; 92120848903SChaotian Jing /* need because clk changed. */ 92220848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 92320848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 92420848903SChaotian Jing 92586beac37SChaotian Jing /* 92686beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 92786beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 92886beac37SChaotian Jing */ 9290caf60c4SAmey Narkhede if (mmc->actual_clock <= 52000000) { 93086beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 931a2e6d1f6SChaotian Jing if (host->top_base) { 932a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_control, 933a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 934a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_cmd, 935a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 936a2e6d1f6SChaotian Jing } else { 937a2e6d1f6SChaotian Jing writel(host->def_tune_para.pad_tune, 938a2e6d1f6SChaotian Jing host->base + tune_reg); 939a2e6d1f6SChaotian Jing } 94086beac37SChaotian Jing } else { 94186beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 9421ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 9431ede5cb8Syong mao host->base + PAD_CMD_TUNE); 944a2e6d1f6SChaotian Jing if (host->top_base) { 945a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_control, 946a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 947a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_cmd, 948a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 949a2e6d1f6SChaotian Jing } else { 950a2e6d1f6SChaotian Jing writel(host->saved_tune_para.pad_tune, 951a2e6d1f6SChaotian Jing host->base + tune_reg); 952a2e6d1f6SChaotian Jing } 95386beac37SChaotian Jing } 95486beac37SChaotian Jing 9557f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 9567f3d5852SChaotian Jing host->dev_comp->hs400_tune) 9573751e008SChaotian Jing sdr_set_field(host->base + tune_reg, 9581ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 9591ede5cb8Syong mao host->hs400_cmd_int_delay); 9600caf60c4SAmey Narkhede dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 96156f6cbbeSChaotian Jing timing); 96220848903SChaotian Jing } 96320848903SChaotian Jing 96420848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 965961e40f7SChanWoo Lee struct mmc_command *cmd) 96620848903SChaotian Jing { 96720848903SChaotian Jing u32 resp; 96820848903SChaotian Jing 96920848903SChaotian Jing switch (mmc_resp_type(cmd)) { 97020848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 97120848903SChaotian Jing case MMC_RSP_R1: 97220848903SChaotian Jing resp = 0x1; 97320848903SChaotian Jing break; 97420848903SChaotian Jing case MMC_RSP_R1B: 97520848903SChaotian Jing resp = 0x7; 97620848903SChaotian Jing break; 97720848903SChaotian Jing case MMC_RSP_R2: 97820848903SChaotian Jing resp = 0x2; 97920848903SChaotian Jing break; 98020848903SChaotian Jing case MMC_RSP_R3: 98120848903SChaotian Jing resp = 0x3; 98220848903SChaotian Jing break; 98320848903SChaotian Jing case MMC_RSP_NONE: 98420848903SChaotian Jing default: 98520848903SChaotian Jing resp = 0x0; 98620848903SChaotian Jing break; 98720848903SChaotian Jing } 98820848903SChaotian Jing 98920848903SChaotian Jing return resp; 99020848903SChaotian Jing } 99120848903SChaotian Jing 99220848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 99320848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 99420848903SChaotian Jing { 9950caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 99620848903SChaotian Jing /* rawcmd : 99720848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 99820848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 99920848903SChaotian Jing */ 100020848903SChaotian Jing u32 opcode = cmd->opcode; 1001961e40f7SChanWoo Lee u32 resp = msdc_cmd_find_resp(host, cmd); 100220848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 100320848903SChaotian Jing 100420848903SChaotian Jing host->cmd_rsp = resp; 100520848903SChaotian Jing 100620848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 100720848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 10084fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(14); 100920848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 10104fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(30); 101120848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 101220848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 101320848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 101420848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 101520848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 10164fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(11); 101720848903SChaotian Jing 101820848903SChaotian Jing if (cmd->data) { 101920848903SChaotian Jing struct mmc_data *data = cmd->data; 102020848903SChaotian Jing 102120848903SChaotian Jing if (mmc_op_multi(opcode)) { 10220caf60c4SAmey Narkhede if (mmc_card_mmc(mmc->card) && mrq->sbc && 102320848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 10244fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(29); /* AutoCMD23 */ 102520848903SChaotian Jing } 102620848903SChaotian Jing 102720848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 102820848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 10294fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(13); 103020848903SChaotian Jing if (data->blocks > 1) 10314fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(12); 103220848903SChaotian Jing else 10334fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(11); 103420848903SChaotian Jing /* Always use dma mode */ 103520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 103620848903SChaotian Jing 103720848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 103820848903SChaotian Jing host->timeout_clks != data->timeout_clks) 103920848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 104020848903SChaotian Jing data->timeout_clks); 104120848903SChaotian Jing 104220848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 104320848903SChaotian Jing } 104420848903SChaotian Jing return rawcmd; 104520848903SChaotian Jing } 104620848903SChaotian Jing 1047d74179b8SChanWoo Lee static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1048d74179b8SChanWoo Lee struct mmc_data *data) 104920848903SChaotian Jing { 105020848903SChaotian Jing bool read; 105120848903SChaotian Jing 105220848903SChaotian Jing WARN_ON(host->data); 105320848903SChaotian Jing host->data = data; 105420848903SChaotian Jing read = data->flags & MMC_DATA_READ; 105520848903SChaotian Jing 105620848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 105720848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 105820848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 105920848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 106020848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 106120848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 106220848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 106320848903SChaotian Jing } 106420848903SChaotian Jing 106520848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 106620848903SChaotian Jing struct mmc_command *cmd) 106720848903SChaotian Jing { 106820848903SChaotian Jing u32 *rsp = cmd->resp; 106920848903SChaotian Jing 107020848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 107120848903SChaotian Jing 107220848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 107320848903SChaotian Jing cmd->error = 0; 107420848903SChaotian Jing } else { 107520848903SChaotian Jing msdc_reset_hw(host); 107620848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 107720848903SChaotian Jing cmd->error = -EILSEQ; 107820848903SChaotian Jing host->error |= REQ_STOP_EIO; 107920848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 108020848903SChaotian Jing cmd->error = -ETIMEDOUT; 108120848903SChaotian Jing host->error |= REQ_STOP_TMO; 108220848903SChaotian Jing } 108320848903SChaotian Jing dev_err(host->dev, 108420848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 108520848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 108620848903SChaotian Jing } 108720848903SChaotian Jing return cmd->error; 108820848903SChaotian Jing } 108920848903SChaotian Jing 10906ec5a7b7SLee Jones /* 10919e2582e5Syong mao * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 10929e2582e5Syong mao * 10939e2582e5Syong mao * Host controller may lost interrupt in some special case. 10949e2582e5Syong mao * Add SDIO irq recheck mechanism to make sure all interrupts 10959e2582e5Syong mao * can be processed immediately 10969e2582e5Syong mao */ 10979e2582e5Syong mao static void msdc_recheck_sdio_irq(struct msdc_host *host) 10989e2582e5Syong mao { 10990caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 11009e2582e5Syong mao u32 reg_int, reg_inten, reg_ps; 11019e2582e5Syong mao 11020caf60c4SAmey Narkhede if (mmc->caps & MMC_CAP_SDIO_IRQ) { 11039e2582e5Syong mao reg_inten = readl(host->base + MSDC_INTEN); 11049e2582e5Syong mao if (reg_inten & MSDC_INTEN_SDIOIRQ) { 11059e2582e5Syong mao reg_int = readl(host->base + MSDC_INT); 11069e2582e5Syong mao reg_ps = readl(host->base + MSDC_PS); 11079e2582e5Syong mao if (!(reg_int & MSDC_INT_SDIOIRQ || 11089e2582e5Syong mao reg_ps & MSDC_PS_DATA1)) { 11099e2582e5Syong mao __msdc_enable_sdio_irq(host, 0); 11100caf60c4SAmey Narkhede sdio_signal_irq(mmc); 11119e2582e5Syong mao } 11129e2582e5Syong mao } 11139e2582e5Syong mao } 11149e2582e5Syong mao } 11159e2582e5Syong mao 1116d74179b8SChanWoo Lee static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 111720848903SChaotian Jing { 111820848903SChaotian Jing if (host->error) 111920848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 112020848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 112120848903SChaotian Jing } 112220848903SChaotian Jing 112320848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 112420848903SChaotian Jing { 112520848903SChaotian Jing unsigned long flags; 112620848903SChaotian Jing 11270354ca6eSChaotian Jing /* 11280354ca6eSChaotian Jing * No need check the return value of cancel_delayed_work, as only ONE 11290354ca6eSChaotian Jing * path will go here! 11300354ca6eSChaotian Jing */ 11310354ca6eSChaotian Jing cancel_delayed_work(&host->req_timeout); 11320354ca6eSChaotian Jing 113320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 113420848903SChaotian Jing host->mrq = NULL; 113520848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 113620848903SChaotian Jing 1137d74179b8SChanWoo Lee msdc_track_cmd_data(host, mrq->cmd); 113820848903SChaotian Jing if (mrq->data) 113915107135SYue Hu msdc_unprepare_data(host, mrq->data); 114020314ce3Sjjian zhou if (host->error) 114120314ce3Sjjian zhou msdc_reset_hw(host); 11420caf60c4SAmey Narkhede mmc_request_done(mmc_from_priv(host), mrq); 11439e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 11449e2582e5Syong mao msdc_recheck_sdio_irq(host); 114520848903SChaotian Jing } 114620848903SChaotian Jing 114720848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 114820848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 114920848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 115020848903SChaotian Jing { 115120848903SChaotian Jing bool done = false; 115220848903SChaotian Jing bool sbc_error; 115320848903SChaotian Jing unsigned long flags; 11540354ca6eSChaotian Jing u32 *rsp; 115520848903SChaotian Jing 115620848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 115720848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 115820848903SChaotian Jing | MSDC_INT_ACMDTMO))) 115920848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 116020848903SChaotian Jing 116120848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 116220848903SChaotian Jing 116320848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 116420848903SChaotian Jing | MSDC_INT_RSPCRCERR 116520848903SChaotian Jing | MSDC_INT_CMDTMO))) 116620848903SChaotian Jing return done; 116720848903SChaotian Jing 116820848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 116920848903SChaotian Jing done = !host->cmd; 117020848903SChaotian Jing host->cmd = NULL; 117120848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 117220848903SChaotian Jing 117320848903SChaotian Jing if (done) 117420848903SChaotian Jing return true; 11750354ca6eSChaotian Jing rsp = cmd->resp; 117620848903SChaotian Jing 1177726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 117820848903SChaotian Jing 117920848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 118020848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 118120848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 118220848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 118320848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 118420848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 118520848903SChaotian Jing } else { 118620848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 118720848903SChaotian Jing } 118820848903SChaotian Jing } 118920848903SChaotian Jing 119020848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1191da6e0f70SChaotian Jing if (events & MSDC_INT_CMDTMO || 1192da6e0f70SChaotian Jing (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1193c4ac38c6SWenbin Mei cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1194c4ac38c6SWenbin Mei !host->hs400_tuning)) 1195ddc71387SChaotian Jing /* 1196ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 1197da6e0f70SChaotian Jing * may have alreay come when cmd19/cmd21 gets response 1198da6e0f70SChaotian Jing * CRC error. 1199ddc71387SChaotian Jing */ 120020848903SChaotian Jing msdc_reset_hw(host); 120120848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 120220848903SChaotian Jing cmd->error = -EILSEQ; 120320848903SChaotian Jing host->error |= REQ_CMD_EIO; 120420848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 120520848903SChaotian Jing cmd->error = -ETIMEDOUT; 120620848903SChaotian Jing host->error |= REQ_CMD_TMO; 120720848903SChaotian Jing } 120820848903SChaotian Jing } 120920848903SChaotian Jing if (cmd->error) 121020848903SChaotian Jing dev_dbg(host->dev, 121120848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 121220848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 121320848903SChaotian Jing cmd->error); 121420848903SChaotian Jing 121520848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 121620848903SChaotian Jing return true; 121720848903SChaotian Jing } 121820848903SChaotian Jing 121920848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 122020848903SChaotian Jing * is correct before issue a request. but host design do below 122120848903SChaotian Jing * checks recommended. 122220848903SChaotian Jing */ 122320848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 122420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 122520848903SChaotian Jing { 1226ffaea6ebSAngeloGioacchino Del Regno u32 val; 1227ffaea6ebSAngeloGioacchino Del Regno int ret; 122820848903SChaotian Jing 1229ffaea6ebSAngeloGioacchino Del Regno /* The max busy time we can endure is 20ms */ 1230ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1231ffaea6ebSAngeloGioacchino Del Regno !(val & SDC_STS_CMDBUSY), 1, 20000); 1232ffaea6ebSAngeloGioacchino Del Regno if (ret) { 123320848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 123420848903SChaotian Jing host->error |= REQ_CMD_BUSY; 123520848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 123620848903SChaotian Jing return false; 123720848903SChaotian Jing } 123820848903SChaotian Jing 123920848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 124020848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 1241ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1242ffaea6ebSAngeloGioacchino Del Regno !(val & SDC_STS_SDCBUSY), 1, 20000); 1243ffaea6ebSAngeloGioacchino Del Regno if (ret) { 124420848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 124520848903SChaotian Jing host->error |= REQ_CMD_BUSY; 124620848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 124720848903SChaotian Jing return false; 124820848903SChaotian Jing } 124920848903SChaotian Jing } 125020848903SChaotian Jing return true; 125120848903SChaotian Jing } 125220848903SChaotian Jing 125320848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 125420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 125520848903SChaotian Jing { 125620848903SChaotian Jing u32 rawcmd; 12575215b2e9Sjjian zhou unsigned long flags; 125820848903SChaotian Jing 125920848903SChaotian Jing WARN_ON(host->cmd); 126020848903SChaotian Jing host->cmd = cmd; 126120848903SChaotian Jing 1262f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 126320848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 126420848903SChaotian Jing return; 126520848903SChaotian Jing 126620848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 126720848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 126820848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 126920848903SChaotian Jing msdc_reset_hw(host); 127020848903SChaotian Jing } 127120848903SChaotian Jing 127220848903SChaotian Jing cmd->error = 0; 127320848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 127420848903SChaotian Jing 12755215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 1276726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 12775215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 12785215b2e9Sjjian zhou 127920848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 128020848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 128120848903SChaotian Jing } 128220848903SChaotian Jing 128320848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 128420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 128520848903SChaotian Jing { 1286ddc71387SChaotian Jing if ((cmd->error && 1287ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1288ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1289c4ac38c6SWenbin Mei cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1290c4ac38c6SWenbin Mei host->hs400_tuning))) || 1291ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 129220848903SChaotian Jing msdc_request_done(host, mrq); 129320848903SChaotian Jing else if (cmd == mrq->sbc) 129420848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 129520848903SChaotian Jing else if (!cmd->data) 129620848903SChaotian Jing msdc_request_done(host, mrq); 129720848903SChaotian Jing else 1298d74179b8SChanWoo Lee msdc_start_data(host, cmd, cmd->data); 129920848903SChaotian Jing } 130020848903SChaotian Jing 130120848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 130220848903SChaotian Jing { 130320848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 130420848903SChaotian Jing 130520848903SChaotian Jing host->error = 0; 130620848903SChaotian Jing WARN_ON(host->mrq); 130720848903SChaotian Jing host->mrq = mrq; 130820848903SChaotian Jing 130920848903SChaotian Jing if (mrq->data) 131015107135SYue Hu msdc_prepare_data(host, mrq->data); 131120848903SChaotian Jing 131220848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 131320848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 131420848903SChaotian Jing * use HW option, otherwise use SW option 131520848903SChaotian Jing */ 131620848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 131720848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 131820848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 131920848903SChaotian Jing else 132020848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 132120848903SChaotian Jing } 132220848903SChaotian Jing 1323d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 132420848903SChaotian Jing { 132520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 132620848903SChaotian Jing struct mmc_data *data = mrq->data; 132720848903SChaotian Jing 132820848903SChaotian Jing if (!data) 132920848903SChaotian Jing return; 133020848903SChaotian Jing 133115107135SYue Hu msdc_prepare_data(host, data); 133220848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 133320848903SChaotian Jing } 133420848903SChaotian Jing 133520848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 133620848903SChaotian Jing int err) 133720848903SChaotian Jing { 133820848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 133915107135SYue Hu struct mmc_data *data = mrq->data; 134020848903SChaotian Jing 134120848903SChaotian Jing if (!data) 134220848903SChaotian Jing return; 134315107135SYue Hu 134420848903SChaotian Jing if (data->host_cookie) { 134520848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 134615107135SYue Hu msdc_unprepare_data(host, data); 134720848903SChaotian Jing } 134820848903SChaotian Jing } 134920848903SChaotian Jing 1350f0ed43edSYue Hu static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 135120848903SChaotian Jing { 135220848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 13536397b7f5SChaotian Jing !mrq->sbc) 135420848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 135520848903SChaotian Jing else 135620848903SChaotian Jing msdc_request_done(host, mrq); 135720848903SChaotian Jing } 135820848903SChaotian Jing 135920848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 136020848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 136120848903SChaotian Jing { 13620354ca6eSChaotian Jing struct mmc_command *stop; 136320848903SChaotian Jing unsigned long flags; 136420848903SChaotian Jing bool done; 136520848903SChaotian Jing unsigned int check_data = events & 136620848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 136720848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 136820848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 1369ffaea6ebSAngeloGioacchino Del Regno u32 val; 1370ffaea6ebSAngeloGioacchino Del Regno int ret; 137120848903SChaotian Jing 137220848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 137320848903SChaotian Jing done = !host->data; 137420848903SChaotian Jing if (check_data) 137520848903SChaotian Jing host->data = NULL; 137620848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 137720848903SChaotian Jing 137820848903SChaotian Jing if (done) 137920848903SChaotian Jing return true; 13800354ca6eSChaotian Jing stop = data->stop; 138120848903SChaotian Jing 138220848903SChaotian Jing if (check_data || (stop && stop->error)) { 138320848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 138420848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 138520848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 138620848903SChaotian Jing 1); 1387ffaea6ebSAngeloGioacchino Del Regno 1388ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1389ffaea6ebSAngeloGioacchino Del Regno !(val & MSDC_DMA_CFG_STS), 1, 20000); 1390ffaea6ebSAngeloGioacchino Del Regno if (ret) { 1391ffaea6ebSAngeloGioacchino Del Regno dev_dbg(host->dev, "DMA stop timed out\n"); 1392ffaea6ebSAngeloGioacchino Del Regno return false; 1393ffaea6ebSAngeloGioacchino Del Regno } 1394ffaea6ebSAngeloGioacchino Del Regno 139520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 139620848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 139720848903SChaotian Jing 139820848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 139920848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 140020848903SChaotian Jing } else { 14012066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 140220848903SChaotian Jing msdc_reset_hw(host); 140320848903SChaotian Jing host->error |= REQ_DAT_ERR; 140420848903SChaotian Jing data->bytes_xfered = 0; 140520848903SChaotian Jing 140620848903SChaotian Jing if (events & MSDC_INT_DATTMO) 140720848903SChaotian Jing data->error = -ETIMEDOUT; 14086397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 14096397b7f5SChaotian Jing data->error = -EILSEQ; 141020848903SChaotian Jing 14112066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 141220848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 14132066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 141420848903SChaotian Jing (int)data->error, data->bytes_xfered); 141520848903SChaotian Jing } 141620848903SChaotian Jing 1417f0ed43edSYue Hu msdc_data_xfer_next(host, mrq); 141820848903SChaotian Jing done = true; 141920848903SChaotian Jing } 142020848903SChaotian Jing return done; 142120848903SChaotian Jing } 142220848903SChaotian Jing 142320848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 142420848903SChaotian Jing { 142520848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 142620848903SChaotian Jing 142720848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 142820848903SChaotian Jing 142920848903SChaotian Jing switch (width) { 143020848903SChaotian Jing default: 143120848903SChaotian Jing case MMC_BUS_WIDTH_1: 143220848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 143320848903SChaotian Jing break; 143420848903SChaotian Jing case MMC_BUS_WIDTH_4: 143520848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 143620848903SChaotian Jing break; 143720848903SChaotian Jing case MMC_BUS_WIDTH_8: 143820848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 143920848903SChaotian Jing break; 144020848903SChaotian Jing } 144120848903SChaotian Jing 144220848903SChaotian Jing writel(val, host->base + SDC_CFG); 144320848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 144420848903SChaotian Jing } 144520848903SChaotian Jing 144620848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 144720848903SChaotian Jing { 144820848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14499cbe0fc8SMarek Vasut int ret; 145020848903SChaotian Jing 145120848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1452fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1453fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 145420848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 145520848903SChaotian Jing return -EINVAL; 145620848903SChaotian Jing } 145720848903SChaotian Jing 1458fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 14599cbe0fc8SMarek Vasut if (ret < 0) { 1460fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1461fac49ce5SNicolas Boichat ret, ios->signal_voltage); 14629cbe0fc8SMarek Vasut return ret; 14639cbe0fc8SMarek Vasut } 14649cbe0fc8SMarek Vasut 146520848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 146620848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 146720848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 146820848903SChaotian Jing else 146920848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 147020848903SChaotian Jing } 14719cbe0fc8SMarek Vasut return 0; 147220848903SChaotian Jing } 147320848903SChaotian Jing 147420848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 147520848903SChaotian Jing { 147620848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 147720848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 147820848903SChaotian Jing 14793bc702edSyong mao /* only check if data0 is low */ 14803bc702edSyong mao return !(status & BIT(16)); 148120848903SChaotian Jing } 148220848903SChaotian Jing 148320848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 148420848903SChaotian Jing { 148520848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 148620848903SChaotian Jing req_timeout.work); 148720848903SChaotian Jing 148820848903SChaotian Jing /* simulate HW timeout status */ 148920848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 149020848903SChaotian Jing if (host->mrq) { 149120848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 149220848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 149320848903SChaotian Jing if (host->cmd) { 149420848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 149520848903SChaotian Jing __func__, host->cmd->opcode); 149620848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 149720848903SChaotian Jing host->cmd); 149820848903SChaotian Jing } else if (host->data) { 149920848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 150020848903SChaotian Jing __func__, host->mrq->cmd->opcode, 150120848903SChaotian Jing host->data->blocks); 150220848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 150320848903SChaotian Jing host->data); 150420848903SChaotian Jing } 150520848903SChaotian Jing } 150620848903SChaotian Jing } 150720848903SChaotian Jing 15088a5df8acSjjian zhou static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 15098a5df8acSjjian zhou { 15108a5df8acSjjian zhou if (enb) { 15118a5df8acSjjian zhou sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15128a5df8acSjjian zhou sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15139e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 15149e2582e5Syong mao msdc_recheck_sdio_irq(host); 15158a5df8acSjjian zhou } else { 15168a5df8acSjjian zhou sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15178a5df8acSjjian zhou sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15188a5df8acSjjian zhou } 15198a5df8acSjjian zhou } 15208a5df8acSjjian zhou 15218a5df8acSjjian zhou static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 15225215b2e9Sjjian zhou { 15235215b2e9Sjjian zhou unsigned long flags; 15245215b2e9Sjjian zhou struct msdc_host *host = mmc_priv(mmc); 15255215b2e9Sjjian zhou 15265215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 15278a5df8acSjjian zhou __msdc_enable_sdio_irq(host, enb); 15285215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 15295215b2e9Sjjian zhou 15305215b2e9Sjjian zhou if (enb) 15315215b2e9Sjjian zhou pm_runtime_get_noresume(host->dev); 15325215b2e9Sjjian zhou else 15335215b2e9Sjjian zhou pm_runtime_put_noidle(host->dev); 15345215b2e9Sjjian zhou } 15355215b2e9Sjjian zhou 153688bd652bSChun-Hung Wu static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 153788bd652bSChun-Hung Wu { 15380caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 153988bd652bSChun-Hung Wu int cmd_err = 0, dat_err = 0; 154088bd652bSChun-Hung Wu 154188bd652bSChun-Hung Wu if (intsts & MSDC_INT_RSPCRCERR) { 154288bd652bSChun-Hung Wu cmd_err = -EILSEQ; 154388bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD CRC ERR", __func__); 154488bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_CMDTMO) { 154588bd652bSChun-Hung Wu cmd_err = -ETIMEDOUT; 154688bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 154788bd652bSChun-Hung Wu } 154888bd652bSChun-Hung Wu 154988bd652bSChun-Hung Wu if (intsts & MSDC_INT_DATCRCERR) { 155088bd652bSChun-Hung Wu dat_err = -EILSEQ; 155188bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA CRC ERR", __func__); 155288bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_DATTMO) { 155388bd652bSChun-Hung Wu dat_err = -ETIMEDOUT; 155488bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 155588bd652bSChun-Hung Wu } 155688bd652bSChun-Hung Wu 155788bd652bSChun-Hung Wu if (cmd_err || dat_err) { 155888bd652bSChun-Hung Wu dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 155988bd652bSChun-Hung Wu cmd_err, dat_err, intsts); 156088bd652bSChun-Hung Wu } 156188bd652bSChun-Hung Wu 15620caf60c4SAmey Narkhede return cqhci_irq(mmc, 0, cmd_err, dat_err); 156388bd652bSChun-Hung Wu } 156488bd652bSChun-Hung Wu 156520848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 156620848903SChaotian Jing { 156720848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 15680caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 156920848903SChaotian Jing 157020848903SChaotian Jing while (true) { 157120848903SChaotian Jing struct mmc_request *mrq; 157220848903SChaotian Jing struct mmc_command *cmd; 157320848903SChaotian Jing struct mmc_data *data; 157420848903SChaotian Jing u32 events, event_mask; 157520848903SChaotian Jing 15769baf7c5eSTian Tao spin_lock(&host->lock); 157720848903SChaotian Jing events = readl(host->base + MSDC_INT); 157820848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 15798a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 15808a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 0); 158120848903SChaotian Jing /* clear interrupts */ 158220848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 158320848903SChaotian Jing 158420848903SChaotian Jing mrq = host->mrq; 158520848903SChaotian Jing cmd = host->cmd; 158620848903SChaotian Jing data = host->data; 15879baf7c5eSTian Tao spin_unlock(&host->lock); 158820848903SChaotian Jing 15898a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 15900caf60c4SAmey Narkhede sdio_signal_irq(mmc); 15915215b2e9Sjjian zhou 1592d087bde5SNeilBrown if ((events & event_mask) & MSDC_INT_CDSC) { 1593d087bde5SNeilBrown if (host->internal_cd) 15940caf60c4SAmey Narkhede mmc_detect_change(mmc, msecs_to_jiffies(20)); 1595d087bde5SNeilBrown events &= ~MSDC_INT_CDSC; 1596d087bde5SNeilBrown } 1597d087bde5SNeilBrown 15985215b2e9Sjjian zhou if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 159920848903SChaotian Jing break; 160020848903SChaotian Jing 16010caf60c4SAmey Narkhede if ((mmc->caps2 & MMC_CAP2_CQE) && 160288bd652bSChun-Hung Wu (events & MSDC_INT_CMDQ)) { 160388bd652bSChun-Hung Wu msdc_cmdq_irq(host, events); 160488bd652bSChun-Hung Wu /* clear interrupts */ 160588bd652bSChun-Hung Wu writel(events, host->base + MSDC_INT); 160688bd652bSChun-Hung Wu return IRQ_HANDLED; 160788bd652bSChun-Hung Wu } 160888bd652bSChun-Hung Wu 160920848903SChaotian Jing if (!mrq) { 161020848903SChaotian Jing dev_err(host->dev, 161120848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 161220848903SChaotian Jing __func__, events, event_mask); 161320848903SChaotian Jing WARN_ON(1); 161420848903SChaotian Jing break; 161520848903SChaotian Jing } 161620848903SChaotian Jing 161720848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 161820848903SChaotian Jing 161920848903SChaotian Jing if (cmd) 162020848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 162120848903SChaotian Jing else if (data) 162220848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 162320848903SChaotian Jing } 162420848903SChaotian Jing 162520848903SChaotian Jing return IRQ_HANDLED; 162620848903SChaotian Jing } 162720848903SChaotian Jing 162820848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 162920848903SChaotian Jing { 163020848903SChaotian Jing u32 val; 163139add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 163283b27217SAngeloGioacchino Del Regno struct mmc_host *mmc = mmc_from_priv(host); 163320848903SChaotian Jing 1634855d388dSWenbin Mei if (host->reset) { 1635855d388dSWenbin Mei reset_control_assert(host->reset); 1636855d388dSWenbin Mei usleep_range(10, 50); 1637855d388dSWenbin Mei reset_control_deassert(host->reset); 1638855d388dSWenbin Mei } 1639855d388dSWenbin Mei 164020848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 164120848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 164220848903SChaotian Jing 164320848903SChaotian Jing /* Reset */ 164420848903SChaotian Jing msdc_reset_hw(host); 164520848903SChaotian Jing 164620848903SChaotian Jing /* Disable and clear all interrupts */ 164720848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 164820848903SChaotian Jing val = readl(host->base + MSDC_INT); 164920848903SChaotian Jing writel(val, host->base + MSDC_INT); 165020848903SChaotian Jing 1651d087bde5SNeilBrown /* Configure card detection */ 1652d087bde5SNeilBrown if (host->internal_cd) { 1653d087bde5SNeilBrown sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1654d087bde5SNeilBrown DEFAULT_DEBOUNCE); 1655d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1656d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1657d087bde5SNeilBrown sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1658d087bde5SNeilBrown } else { 1659d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1660d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1661d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1662d087bde5SNeilBrown } 1663d087bde5SNeilBrown 1664a2e6d1f6SChaotian Jing if (host->top_base) { 1665a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CONTROL); 1666a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CMD); 1667a2e6d1f6SChaotian Jing } else { 166839add252SChaotian Jing writel(0, host->base + tune_reg); 1669a2e6d1f6SChaotian Jing } 167020848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 16716397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 16726397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 167320848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 16742fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 16756397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1676d9dcbfc8SChaotian Jing 1677d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1678d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1679d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1680d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1681d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1682d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1683d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1684d9dcbfc8SChaotian Jing } 1685d9dcbfc8SChaotian Jing 1686acde28c4SChaotian Jing if (host->dev_comp->busy_check) 16874fe54318SAngeloGioacchino Del Regno sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1688d9dcbfc8SChaotian Jing 16892fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 16902fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16912fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1692d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1693a2e6d1f6SChaotian Jing if (host->top_base) 1694a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1695a2e6d1f6SChaotian Jing SDC_RX_ENH_EN); 1696a2e6d1f6SChaotian Jing else 1697d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1698d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1699d9dcbfc8SChaotian Jing } else { 17002fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17012fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 17022fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17032fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1704d9dcbfc8SChaotian Jing } 17052fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 17062fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 17072fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 17082fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17092fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 17102fea5819SChaotian Jing } 17112fea5819SChaotian Jing 17122a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17132a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17142a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 17152fea5819SChaotian Jing if (host->dev_comp->data_tune) { 1716a2e6d1f6SChaotian Jing if (host->top_base) { 1717a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1718a2e6d1f6SChaotian Jing PAD_DAT_RD_RXDLY_SEL); 1719a2e6d1f6SChaotian Jing sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1720a2e6d1f6SChaotian Jing DATA_K_VALUE_SEL); 1721a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1722a2e6d1f6SChaotian Jing PAD_CMD_RD_RXDLY_SEL); 1723a2e6d1f6SChaotian Jing } else { 17242fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 1725a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RD_SEL | 1726a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_CMD_SEL); 1727a2e6d1f6SChaotian Jing } 17282fea5819SChaotian Jing } else { 17292fea5819SChaotian Jing /* choose clock tune */ 1730a2e6d1f6SChaotian Jing if (host->top_base) 1731a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1732a2e6d1f6SChaotian Jing PAD_RXDLY_SEL); 1733a2e6d1f6SChaotian Jing else 1734a2e6d1f6SChaotian Jing sdr_set_bits(host->base + tune_reg, 1735a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RXDLYSEL); 17362fea5819SChaotian Jing } 17376397b7f5SChaotian Jing 173883b27217SAngeloGioacchino Del Regno if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 173983b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 174083b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 174183b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 174283b27217SAngeloGioacchino Del Regno } else { 174383b27217SAngeloGioacchino Del Regno /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 174420848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 174520848903SChaotian Jing 17465215b2e9Sjjian zhou /* Config SDIO device detect interrupt function */ 174720848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 174826c71a13Syong mao sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 174983b27217SAngeloGioacchino Del Regno } 175020848903SChaotian Jing 175120848903SChaotian Jing /* Configure to default data timeout */ 175220848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 175320848903SChaotian Jing 175486beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 17552fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1756a2e6d1f6SChaotian Jing if (host->top_base) { 1757a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_control = 1758a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1759a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_cmd = 1760a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1761a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = 1762a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1763a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = 1764a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1765a2e6d1f6SChaotian Jing } else { 1766a2e6d1f6SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 17672fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1768a2e6d1f6SChaotian Jing } 176920848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 177020848903SChaotian Jing } 177120848903SChaotian Jing 177220848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 177320848903SChaotian Jing { 177420848903SChaotian Jing u32 val; 1775d087bde5SNeilBrown 1776d087bde5SNeilBrown if (host->internal_cd) { 1777d087bde5SNeilBrown /* Disabled card-detect */ 1778d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1779d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1780d087bde5SNeilBrown } 1781d087bde5SNeilBrown 178220848903SChaotian Jing /* Disable and clear all interrupts */ 178320848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 178420848903SChaotian Jing 178520848903SChaotian Jing val = readl(host->base + MSDC_INT); 178620848903SChaotian Jing writel(val, host->base + MSDC_INT); 178720848903SChaotian Jing } 178820848903SChaotian Jing 178920848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 179020848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 179120848903SChaotian Jing { 179220848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 179320848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 17942a9bde19SChaotian Jing dma_addr_t dma_addr; 179520848903SChaotian Jing int i; 179620848903SChaotian Jing 179762b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 179820848903SChaotian Jing 17992a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 180020848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 180162b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 180262b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 180362b0d27aSChaotian Jing */ 18042a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 18052a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18062a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18072a9bde19SChaotian Jing 18082a9bde19SChaotian Jing dma_addr = dma->bd_addr; 18092a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 18102a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18112a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 18122a9bde19SChaotian Jing 181320848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 18142a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 18152a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 18162a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 18172a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18182a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18192a9bde19SChaotian Jing } 182020848903SChaotian Jing } 182120848903SChaotian Jing 182220848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 182320848903SChaotian Jing { 182420848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 182520848903SChaotian Jing int ret; 182620848903SChaotian Jing 182720848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 182820848903SChaotian Jing 182920848903SChaotian Jing /* Suspend/Resume will do power off/on */ 183020848903SChaotian Jing switch (ios->power_mode) { 183120848903SChaotian Jing case MMC_POWER_UP: 183220848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 18336397b7f5SChaotian Jing msdc_init_hw(host); 183420848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 183520848903SChaotian Jing ios->vdd); 183620848903SChaotian Jing if (ret) { 183720848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1838567979fbSUlf Hansson return; 183920848903SChaotian Jing } 184020848903SChaotian Jing } 184120848903SChaotian Jing break; 184220848903SChaotian Jing case MMC_POWER_ON: 184320848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 184420848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 184520848903SChaotian Jing if (ret) 184620848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 184720848903SChaotian Jing else 184820848903SChaotian Jing host->vqmmc_enabled = true; 184920848903SChaotian Jing } 185020848903SChaotian Jing break; 185120848903SChaotian Jing case MMC_POWER_OFF: 185220848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 185320848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 185420848903SChaotian Jing 185520848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 185620848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 185720848903SChaotian Jing host->vqmmc_enabled = false; 185820848903SChaotian Jing } 185920848903SChaotian Jing break; 186020848903SChaotian Jing default: 186120848903SChaotian Jing break; 186220848903SChaotian Jing } 186320848903SChaotian Jing 18646e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 18656e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 186620848903SChaotian Jing } 186720848903SChaotian Jing 18686397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 18696397b7f5SChaotian Jing { 18706397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 18714fe54318SAngeloGioacchino Del Regno return delay & BIT(bit); 18726397b7f5SChaotian Jing } 18736397b7f5SChaotian Jing 18746397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 18756397b7f5SChaotian Jing { 18766397b7f5SChaotian Jing int i; 18776397b7f5SChaotian Jing 18786397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 18796397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 18806397b7f5SChaotian Jing return i; 18816397b7f5SChaotian Jing } 18826397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 18836397b7f5SChaotian Jing } 18846397b7f5SChaotian Jing 18856397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 18866397b7f5SChaotian Jing { 18876397b7f5SChaotian Jing int start = 0, len = 0; 18886397b7f5SChaotian Jing int start_final = 0, len_final = 0; 18896397b7f5SChaotian Jing u8 final_phase = 0xff; 189062d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 18916397b7f5SChaotian Jing 18926397b7f5SChaotian Jing if (delay == 0) { 18936397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 18946397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 18956397b7f5SChaotian Jing return delay_phase; 18966397b7f5SChaotian Jing } 18976397b7f5SChaotian Jing 18986397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 18996397b7f5SChaotian Jing len = get_delay_len(delay, start); 19006397b7f5SChaotian Jing if (len_final < len) { 19016397b7f5SChaotian Jing start_final = start; 19026397b7f5SChaotian Jing len_final = len; 19036397b7f5SChaotian Jing } 19046397b7f5SChaotian Jing start += len ? len : 1; 19051ede5cb8Syong mao if (len >= 12 && start_final < 4) 19066397b7f5SChaotian Jing break; 19076397b7f5SChaotian Jing } 19086397b7f5SChaotian Jing 19096397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 19106397b7f5SChaotian Jing if (start_final == 0) 19116397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 19126397b7f5SChaotian Jing else 19136397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 19146397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 19156397b7f5SChaotian Jing delay, len_final, final_phase); 19166397b7f5SChaotian Jing 19176397b7f5SChaotian Jing delay_phase.maxlen = len_final; 19186397b7f5SChaotian Jing delay_phase.start = start_final; 19196397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 19206397b7f5SChaotian Jing return delay_phase; 19216397b7f5SChaotian Jing } 19226397b7f5SChaotian Jing 1923fd82cc30SChaotian Jing static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1924fd82cc30SChaotian Jing { 1925fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1926fd82cc30SChaotian Jing 1927fd82cc30SChaotian Jing if (host->top_base) 1928fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1929fd82cc30SChaotian Jing value); 1930fd82cc30SChaotian Jing else 1931fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1932fd82cc30SChaotian Jing value); 1933fd82cc30SChaotian Jing } 1934fd82cc30SChaotian Jing 1935fd82cc30SChaotian Jing static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1936fd82cc30SChaotian Jing { 1937fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1938fd82cc30SChaotian Jing 1939fd82cc30SChaotian Jing if (host->top_base) 1940fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1941fd82cc30SChaotian Jing PAD_DAT_RD_RXDLY, value); 1942fd82cc30SChaotian Jing else 1943fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1944fd82cc30SChaotian Jing value); 1945fd82cc30SChaotian Jing } 1946fd82cc30SChaotian Jing 19476397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 19486397b7f5SChaotian Jing { 19496397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 19506397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1951ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 19521ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 19536397b7f5SChaotian Jing u8 final_delay, final_maxlen; 19541ede5cb8Syong mao u32 internal_delay = 0; 195539add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 19566397b7f5SChaotian Jing int cmd_err; 19571ede5cb8Syong mao int i, j; 19581ede5cb8Syong mao 19591ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 19601ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 196139add252SChaotian Jing sdr_set_field(host->base + tune_reg, 19621ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 19631ede5cb8Syong mao host->hs200_cmd_int_delay); 19646397b7f5SChaotian Jing 19656397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19666397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1967fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 19681ede5cb8Syong mao /* 19691ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19701ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19711ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19721ede5cb8Syong mao */ 19731ede5cb8Syong mao for (j = 0; j < 3; j++) { 19746397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 19751ede5cb8Syong mao if (!cmd_err) { 19764fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 19771ede5cb8Syong mao } else { 19784fe54318SAngeloGioacchino Del Regno rise_delay &= ~BIT(i); 19791ede5cb8Syong mao break; 19801ede5cb8Syong mao } 19811ede5cb8Syong mao } 19826397b7f5SChaotian Jing } 1983ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1984ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 19856b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 19866b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1987ae9c657eSChaotian Jing goto skip_fall; 19886397b7f5SChaotian Jing 19896397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19906397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 1991fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 19921ede5cb8Syong mao /* 19931ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19941ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19951ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19961ede5cb8Syong mao */ 19971ede5cb8Syong mao for (j = 0; j < 3; j++) { 19986397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 19991ede5cb8Syong mao if (!cmd_err) { 20004fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 20011ede5cb8Syong mao } else { 20024fe54318SAngeloGioacchino Del Regno fall_delay &= ~BIT(i); 20031ede5cb8Syong mao break; 20041ede5cb8Syong mao } 20051ede5cb8Syong mao } 20066397b7f5SChaotian Jing } 20076397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 20086397b7f5SChaotian Jing 2009ae9c657eSChaotian Jing skip_fall: 20106397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 20111ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 20121ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 20136397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 20146397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20156397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 20166397b7f5SChaotian Jing } else { 20176397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20186397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 20196397b7f5SChaotian Jing } 2020fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2021fd82cc30SChaotian Jing 20222fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 20231ede5cb8Syong mao goto skip_internal; 20246397b7f5SChaotian Jing 20251ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 202639add252SChaotian Jing sdr_set_field(host->base + tune_reg, 20271ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 20281ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20291ede5cb8Syong mao if (!cmd_err) 20304fe54318SAngeloGioacchino Del Regno internal_delay |= BIT(i); 20311ede5cb8Syong mao } 20321ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 20331ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 203439add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 20351ede5cb8Syong mao internal_delay_phase.final_phase); 20361ede5cb8Syong mao skip_internal: 20371ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20381ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 20391ede5cb8Syong mao } 20401ede5cb8Syong mao 20411ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 20421ede5cb8Syong mao { 20431ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 20441ede5cb8Syong mao u32 cmd_delay = 0; 20451ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 20461ede5cb8Syong mao u8 final_delay; 20471ede5cb8Syong mao int cmd_err; 20481ede5cb8Syong mao int i, j; 20491ede5cb8Syong mao 20501ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 20511ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 20528f34e5bdSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 20531ede5cb8Syong mao 20541ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 20551ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 20561ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 20571ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 20581ede5cb8Syong mao host->hs200_cmd_int_delay); 20591ede5cb8Syong mao 20601ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 20611ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20621ede5cb8Syong mao else 20631ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20641ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 20651ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 20661ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 20671ede5cb8Syong mao /* 20681ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20691ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20701ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20711ede5cb8Syong mao */ 20721ede5cb8Syong mao for (j = 0; j < 3; j++) { 20731ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20741ede5cb8Syong mao if (!cmd_err) { 20754fe54318SAngeloGioacchino Del Regno cmd_delay |= BIT(i); 20761ede5cb8Syong mao } else { 20774fe54318SAngeloGioacchino Del Regno cmd_delay &= ~BIT(i); 20781ede5cb8Syong mao break; 20791ede5cb8Syong mao } 20801ede5cb8Syong mao } 20811ede5cb8Syong mao } 20821ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 20831ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 20841ede5cb8Syong mao final_cmd_delay.final_phase); 20851ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 20861ede5cb8Syong mao 20871ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20886397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 20896397b7f5SChaotian Jing } 20906397b7f5SChaotian Jing 20916397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 20926397b7f5SChaotian Jing { 20936397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 20946397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 2095ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 20966397b7f5SChaotian Jing u8 final_delay, final_maxlen; 20976397b7f5SChaotian Jing int i, ret; 20986397b7f5SChaotian Jing 2099d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2100d17bb71cSChaotian Jing host->latch_ck); 21016397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21026397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21036397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2104fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21056397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21066397b7f5SChaotian Jing if (!ret) 21074fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 21086397b7f5SChaotian Jing } 2109ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2110ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 21111ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 2112ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2113ae9c657eSChaotian Jing goto skip_fall; 21146397b7f5SChaotian Jing 21156397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21166397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21176397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2118fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21196397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21206397b7f5SChaotian Jing if (!ret) 21214fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 21226397b7f5SChaotian Jing } 21236397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 21246397b7f5SChaotian Jing 2125ae9c657eSChaotian Jing skip_fall: 21266397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 21276397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 21286397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21296397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21306397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 21316397b7f5SChaotian Jing } else { 21326397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21336397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21346397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 21356397b7f5SChaotian Jing } 2136fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 21376397b7f5SChaotian Jing 21381ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 21396397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 21406397b7f5SChaotian Jing } 21416397b7f5SChaotian Jing 214286601d0eSChaotian Jing /* 214386601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 214486601d0eSChaotian Jing * together, which can save the tuning time. 214586601d0eSChaotian Jing */ 214686601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 214786601d0eSChaotian Jing { 214886601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 214986601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 215086601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 215186601d0eSChaotian Jing u8 final_delay, final_maxlen; 215286601d0eSChaotian Jing int i, ret; 215386601d0eSChaotian Jing 215486601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 215586601d0eSChaotian Jing host->latch_ck); 215686601d0eSChaotian Jing 215786601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 215886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 215986601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 216086601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2161fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2162fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 216386601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 216486601d0eSChaotian Jing if (!ret) 21654fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 216686601d0eSChaotian Jing } 216786601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 216886601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 216986601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 217086601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 217186601d0eSChaotian Jing goto skip_fall; 217286601d0eSChaotian Jing 217386601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 217486601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 217586601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 217686601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2177fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2178fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 217986601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 218086601d0eSChaotian Jing if (!ret) 21814fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 218286601d0eSChaotian Jing } 218386601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 218486601d0eSChaotian Jing 218586601d0eSChaotian Jing skip_fall: 218686601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 218786601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 218886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 218986601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 219086601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 219186601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 219286601d0eSChaotian Jing } else { 219386601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 219486601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 219586601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 219686601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 219786601d0eSChaotian Jing } 219886601d0eSChaotian Jing 2199fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2200fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 2201a2e6d1f6SChaotian Jing 220286601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 220386601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 220486601d0eSChaotian Jing } 220586601d0eSChaotian Jing 22066397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 22076397b7f5SChaotian Jing { 22086397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22096397b7f5SChaotian Jing int ret; 221039add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 22116397b7f5SChaotian Jing 221286601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 221386601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 221486601d0eSChaotian Jing if (host->hs400_mode) { 221586601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 221686601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2217fd82cc30SChaotian Jing msdc_set_data_delay(host, 0); 221886601d0eSChaotian Jing } 221986601d0eSChaotian Jing goto tune_done; 222086601d0eSChaotian Jing } 22217f3d5852SChaotian Jing if (host->hs400_mode && 22227f3d5852SChaotian Jing host->dev_comp->hs400_tune) 22231ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 22241ede5cb8Syong mao else 22256397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 22266397b7f5SChaotian Jing if (ret == -EIO) { 22276397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 2228567979fbSUlf Hansson return ret; 22296397b7f5SChaotian Jing } 22305462ff39SChaotian Jing if (host->hs400_mode == false) { 22316397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 22326397b7f5SChaotian Jing if (ret == -EIO) 22336397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 22345462ff39SChaotian Jing } 22356397b7f5SChaotian Jing 223686601d0eSChaotian Jing tune_done: 223786beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 223839add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 22391ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2240a2e6d1f6SChaotian Jing if (host->top_base) { 2241a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = readl(host->top_base + 2242a2e6d1f6SChaotian Jing EMMC_TOP_CONTROL); 2243a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2244a2e6d1f6SChaotian Jing EMMC_TOP_CMD); 2245a2e6d1f6SChaotian Jing } 22466397b7f5SChaotian Jing return ret; 22476397b7f5SChaotian Jing } 22486397b7f5SChaotian Jing 22496397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 22506397b7f5SChaotian Jing { 22516397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22525462ff39SChaotian Jing host->hs400_mode = true; 22536397b7f5SChaotian Jing 2254a2e6d1f6SChaotian Jing if (host->top_base) 2255a2e6d1f6SChaotian Jing writel(host->hs400_ds_delay, 2256a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2257a2e6d1f6SChaotian Jing else 22586397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 22592fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 22602fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2261c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 2262c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2263c8609b22SChaotian Jing 22646397b7f5SChaotian Jing return 0; 22656397b7f5SChaotian Jing } 22666397b7f5SChaotian Jing 2267c4ac38c6SWenbin Mei static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2268c4ac38c6SWenbin Mei { 2269c4ac38c6SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 2270c4ac38c6SWenbin Mei struct msdc_delay_phase dly1_delay; 2271c4ac38c6SWenbin Mei u32 val, result_dly1 = 0; 2272c4ac38c6SWenbin Mei u8 *ext_csd; 2273c4ac38c6SWenbin Mei int i, ret; 2274c4ac38c6SWenbin Mei 2275c4ac38c6SWenbin Mei if (host->top_base) { 2276c4ac38c6SWenbin Mei sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2277c4ac38c6SWenbin Mei PAD_DS_DLY_SEL); 2278c4ac38c6SWenbin Mei if (host->hs400_ds_dly3) 2279c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2280c4ac38c6SWenbin Mei PAD_DS_DLY3, host->hs400_ds_dly3); 2281c4ac38c6SWenbin Mei } else { 2282c4ac38c6SWenbin Mei sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2283c4ac38c6SWenbin Mei if (host->hs400_ds_dly3) 2284c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2285c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2286c4ac38c6SWenbin Mei } 2287c4ac38c6SWenbin Mei 2288c4ac38c6SWenbin Mei host->hs400_tuning = true; 2289c4ac38c6SWenbin Mei for (i = 0; i < PAD_DELAY_MAX; i++) { 2290c4ac38c6SWenbin Mei if (host->top_base) 2291c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2292c4ac38c6SWenbin Mei PAD_DS_DLY1, i); 2293c4ac38c6SWenbin Mei else 2294c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2295c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY1, i); 2296c4ac38c6SWenbin Mei ret = mmc_get_ext_csd(card, &ext_csd); 2297d594b35dSWenbin Mei if (!ret) { 22984fe54318SAngeloGioacchino Del Regno result_dly1 |= BIT(i); 2299d594b35dSWenbin Mei kfree(ext_csd); 2300d594b35dSWenbin Mei } 2301c4ac38c6SWenbin Mei } 2302c4ac38c6SWenbin Mei host->hs400_tuning = false; 2303c4ac38c6SWenbin Mei 2304c4ac38c6SWenbin Mei dly1_delay = get_best_delay(host, result_dly1); 2305c4ac38c6SWenbin Mei if (dly1_delay.maxlen == 0) { 2306c4ac38c6SWenbin Mei dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2307c4ac38c6SWenbin Mei goto fail; 2308c4ac38c6SWenbin Mei } 2309c4ac38c6SWenbin Mei if (host->top_base) 2310c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2311c4ac38c6SWenbin Mei PAD_DS_DLY1, dly1_delay.final_phase); 2312c4ac38c6SWenbin Mei else 2313c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2314c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2315c4ac38c6SWenbin Mei 2316c4ac38c6SWenbin Mei if (host->top_base) 2317c4ac38c6SWenbin Mei val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2318c4ac38c6SWenbin Mei else 2319c4ac38c6SWenbin Mei val = readl(host->base + PAD_DS_TUNE); 2320c4ac38c6SWenbin Mei 2321c4ac38c6SWenbin Mei dev_info(host->dev, "Fianl PAD_DS_TUNE: 0x%x\n", val); 2322c4ac38c6SWenbin Mei 2323c4ac38c6SWenbin Mei return 0; 2324c4ac38c6SWenbin Mei 2325c4ac38c6SWenbin Mei fail: 2326c4ac38c6SWenbin Mei dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2327c4ac38c6SWenbin Mei return -EIO; 2328c4ac38c6SWenbin Mei } 2329c4ac38c6SWenbin Mei 2330c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 2331c9b5061eSChaotian Jing { 2332c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2333c9b5061eSChaotian Jing 2334c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 2335c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 2336c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 2337c9b5061eSChaotian Jing } 2338c9b5061eSChaotian Jing 23395215b2e9Sjjian zhou static void msdc_ack_sdio_irq(struct mmc_host *mmc) 23405215b2e9Sjjian zhou { 23418a5df8acSjjian zhou unsigned long flags; 23428a5df8acSjjian zhou struct msdc_host *host = mmc_priv(mmc); 23438a5df8acSjjian zhou 23448a5df8acSjjian zhou spin_lock_irqsave(&host->lock, flags); 23458a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 1); 23468a5df8acSjjian zhou spin_unlock_irqrestore(&host->lock, flags); 23475215b2e9Sjjian zhou } 23485215b2e9Sjjian zhou 2349d087bde5SNeilBrown static int msdc_get_cd(struct mmc_host *mmc) 2350d087bde5SNeilBrown { 2351d087bde5SNeilBrown struct msdc_host *host = mmc_priv(mmc); 2352d087bde5SNeilBrown int val; 2353d087bde5SNeilBrown 2354d087bde5SNeilBrown if (mmc->caps & MMC_CAP_NONREMOVABLE) 2355d087bde5SNeilBrown return 1; 2356d087bde5SNeilBrown 2357d087bde5SNeilBrown if (!host->internal_cd) 2358d087bde5SNeilBrown return mmc_gpio_get_cd(mmc); 2359d087bde5SNeilBrown 2360d087bde5SNeilBrown val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2361d087bde5SNeilBrown if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2362d087bde5SNeilBrown return !!val; 2363d087bde5SNeilBrown else 2364d087bde5SNeilBrown return !val; 2365d087bde5SNeilBrown } 2366d087bde5SNeilBrown 236713b4e1e9SWenbin Mei static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 236813b4e1e9SWenbin Mei struct mmc_ios *ios) 236913b4e1e9SWenbin Mei { 237013b4e1e9SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 237113b4e1e9SWenbin Mei 237213b4e1e9SWenbin Mei if (ios->enhanced_strobe) { 237313b4e1e9SWenbin Mei msdc_prepare_hs400_tuning(mmc, ios); 237413b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 237513b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 237613b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 237713b4e1e9SWenbin Mei 237813b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 237913b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 238013b4e1e9SWenbin Mei sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 238113b4e1e9SWenbin Mei } else { 238213b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 238313b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 238413b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 238513b4e1e9SWenbin Mei 238613b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 238713b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 238813b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 238913b4e1e9SWenbin Mei } 239013b4e1e9SWenbin Mei } 239113b4e1e9SWenbin Mei 239288bd652bSChun-Hung Wu static void msdc_cqe_enable(struct mmc_host *mmc) 239388bd652bSChun-Hung Wu { 239488bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 239588bd652bSChun-Hung Wu 239688bd652bSChun-Hung Wu /* enable cmdq irq */ 239788bd652bSChun-Hung Wu writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 239888bd652bSChun-Hung Wu /* enable busy check */ 239988bd652bSChun-Hung Wu sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 240088bd652bSChun-Hung Wu /* default write data / busy timeout 20s */ 240188bd652bSChun-Hung Wu msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 240288bd652bSChun-Hung Wu /* default read data timeout 1s */ 240388bd652bSChun-Hung Wu msdc_set_timeout(host, 1000000000ULL, 0); 240488bd652bSChun-Hung Wu } 240588bd652bSChun-Hung Wu 24067f4bc2e8SWei Yongjun static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 240788bd652bSChun-Hung Wu { 240888bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 240943e5fee3SDerong Liu unsigned int val = 0; 241088bd652bSChun-Hung Wu 241188bd652bSChun-Hung Wu /* disable cmdq irq */ 241288bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 241388bd652bSChun-Hung Wu /* disable busy check */ 241488bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 241588bd652bSChun-Hung Wu 241688bd652bSChun-Hung Wu if (recovery) { 241788bd652bSChun-Hung Wu sdr_set_field(host->base + MSDC_DMA_CTRL, 241888bd652bSChun-Hung Wu MSDC_DMA_CTRL_STOP, 1); 241943e5fee3SDerong Liu if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 242043e5fee3SDerong Liu !(val & MSDC_DMA_CFG_STS), 1, 3000))) 242143e5fee3SDerong Liu return; 242288bd652bSChun-Hung Wu msdc_reset_hw(host); 242388bd652bSChun-Hung Wu } 242488bd652bSChun-Hung Wu } 242588bd652bSChun-Hung Wu 2426e282f204SChun-Hung Wu static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2427e282f204SChun-Hung Wu { 2428e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2429e282f204SChun-Hung Wu u32 reg; 2430e282f204SChun-Hung Wu 2431e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2432e282f204SChun-Hung Wu reg |= CQHCI_ENABLE; 2433e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2434e282f204SChun-Hung Wu } 2435e282f204SChun-Hung Wu 2436e282f204SChun-Hung Wu static void msdc_cqe_post_disable(struct mmc_host *mmc) 2437e282f204SChun-Hung Wu { 2438e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2439e282f204SChun-Hung Wu u32 reg; 2440e282f204SChun-Hung Wu 2441e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2442e282f204SChun-Hung Wu reg &= ~CQHCI_ENABLE; 2443e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2444e282f204SChun-Hung Wu } 2445e282f204SChun-Hung Wu 2446be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 244720848903SChaotian Jing .post_req = msdc_post_req, 244820848903SChaotian Jing .pre_req = msdc_pre_req, 244920848903SChaotian Jing .request = msdc_ops_request, 245020848903SChaotian Jing .set_ios = msdc_ops_set_ios, 24518d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 2452d087bde5SNeilBrown .get_cd = msdc_get_cd, 245313b4e1e9SWenbin Mei .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 24545215b2e9Sjjian zhou .enable_sdio_irq = msdc_enable_sdio_irq, 24555215b2e9Sjjian zhou .ack_sdio_irq = msdc_ack_sdio_irq, 245620848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 245720848903SChaotian Jing .card_busy = msdc_card_busy, 24586397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 24596397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2460c4ac38c6SWenbin Mei .execute_hs400_tuning = msdc_execute_hs400_tuning, 2461c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 246220848903SChaotian Jing }; 246320848903SChaotian Jing 246488bd652bSChun-Hung Wu static const struct cqhci_host_ops msdc_cmdq_ops = { 246588bd652bSChun-Hung Wu .enable = msdc_cqe_enable, 246688bd652bSChun-Hung Wu .disable = msdc_cqe_disable, 2467e282f204SChun-Hung Wu .pre_enable = msdc_cqe_pre_enable, 2468e282f204SChun-Hung Wu .post_disable = msdc_cqe_post_disable, 246988bd652bSChun-Hung Wu }; 247088bd652bSChun-Hung Wu 24711ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 24721ede5cb8Syong mao struct msdc_host *host) 24731ede5cb8Syong mao { 2474d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2475d17bb71cSChaotian Jing &host->latch_ck); 2476d17bb71cSChaotian Jing 24771ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 24781ede5cb8Syong mao &host->hs400_ds_delay); 24791ede5cb8Syong mao 2480c4ac38c6SWenbin Mei of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2481c4ac38c6SWenbin Mei &host->hs400_ds_dly3); 2482c4ac38c6SWenbin Mei 24831ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 24841ede5cb8Syong mao &host->hs200_cmd_int_delay); 24851ede5cb8Syong mao 24861ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 24871ede5cb8Syong mao &host->hs400_cmd_int_delay); 24881ede5cb8Syong mao 24891ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 24901ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 24911ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 24921ede5cb8Syong mao else 24931ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 249488bd652bSChun-Hung Wu 249588bd652bSChun-Hung Wu if (of_property_read_bool(pdev->dev.of_node, 249688bd652bSChun-Hung Wu "supports-cqe")) 249788bd652bSChun-Hung Wu host->cqhci = true; 249888bd652bSChun-Hung Wu else 249988bd652bSChun-Hung Wu host->cqhci = false; 25001ede5cb8Syong mao } 25011ede5cb8Syong mao 2502f5eccd94SWenbin Mei static int msdc_of_clock_parse(struct platform_device *pdev, 2503f5eccd94SWenbin Mei struct msdc_host *host) 2504f5eccd94SWenbin Mei { 2505f5eccd94SWenbin Mei int ret; 2506f5eccd94SWenbin Mei 2507f5eccd94SWenbin Mei host->src_clk = devm_clk_get(&pdev->dev, "source"); 2508f5eccd94SWenbin Mei if (IS_ERR(host->src_clk)) 2509f5eccd94SWenbin Mei return PTR_ERR(host->src_clk); 2510f5eccd94SWenbin Mei 2511f5eccd94SWenbin Mei host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2512f5eccd94SWenbin Mei if (IS_ERR(host->h_clk)) 2513f5eccd94SWenbin Mei return PTR_ERR(host->h_clk); 2514f5eccd94SWenbin Mei 2515f5eccd94SWenbin Mei host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2516f5eccd94SWenbin Mei if (IS_ERR(host->bus_clk)) 2517f5eccd94SWenbin Mei host->bus_clk = NULL; 2518f5eccd94SWenbin Mei 2519f5eccd94SWenbin Mei /*source clock control gate is optional clock*/ 2520f5eccd94SWenbin Mei host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2521f5eccd94SWenbin Mei if (IS_ERR(host->src_clk_cg)) 2522996be7b7SAngeloGioacchino Del Regno return PTR_ERR(host->src_clk_cg); 2523f5eccd94SWenbin Mei 2524*e5e8b224SAngeloGioacchino Del Regno /* 2525*e5e8b224SAngeloGioacchino Del Regno * Fallback for legacy device-trees: src_clk and HCLK use the same 2526*e5e8b224SAngeloGioacchino Del Regno * bit to control gating but they are parented to a different mux, 2527*e5e8b224SAngeloGioacchino Del Regno * hence if our intention is to gate only the source, required 2528*e5e8b224SAngeloGioacchino Del Regno * during a clk mode switch to avoid hw hangs, we need to gate 2529*e5e8b224SAngeloGioacchino Del Regno * its parent (specified as a different clock only on new DTs). 2530*e5e8b224SAngeloGioacchino Del Regno */ 2531*e5e8b224SAngeloGioacchino Del Regno if (!host->src_clk_cg) { 2532*e5e8b224SAngeloGioacchino Del Regno host->src_clk_cg = clk_get_parent(host->src_clk); 2533*e5e8b224SAngeloGioacchino Del Regno if (IS_ERR(host->src_clk_cg)) 2534*e5e8b224SAngeloGioacchino Del Regno return PTR_ERR(host->src_clk_cg); 2535*e5e8b224SAngeloGioacchino Del Regno } 2536*e5e8b224SAngeloGioacchino Del Regno 2537f5eccd94SWenbin Mei host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2538f5eccd94SWenbin Mei if (IS_ERR(host->sys_clk_cg)) 2539f5eccd94SWenbin Mei host->sys_clk_cg = NULL; 2540f5eccd94SWenbin Mei 2541f5eccd94SWenbin Mei /* If present, always enable for this clock gate */ 2542f5eccd94SWenbin Mei clk_prepare_enable(host->sys_clk_cg); 2543f5eccd94SWenbin Mei 2544f5eccd94SWenbin Mei host->bulk_clks[0].id = "pclk_cg"; 2545f5eccd94SWenbin Mei host->bulk_clks[1].id = "axi_cg"; 2546f5eccd94SWenbin Mei host->bulk_clks[2].id = "ahb_cg"; 2547f5eccd94SWenbin Mei ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2548f5eccd94SWenbin Mei host->bulk_clks); 2549f5eccd94SWenbin Mei if (ret) { 2550f5eccd94SWenbin Mei dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2551f5eccd94SWenbin Mei return ret; 2552f5eccd94SWenbin Mei } 2553f5eccd94SWenbin Mei 2554f5eccd94SWenbin Mei return 0; 2555f5eccd94SWenbin Mei } 2556f5eccd94SWenbin Mei 255720848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 255820848903SChaotian Jing { 255920848903SChaotian Jing struct mmc_host *mmc; 256020848903SChaotian Jing struct msdc_host *host; 256120848903SChaotian Jing struct resource *res; 256220848903SChaotian Jing int ret; 256320848903SChaotian Jing 256420848903SChaotian Jing if (!pdev->dev.of_node) { 256520848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 256620848903SChaotian Jing return -EINVAL; 256720848903SChaotian Jing } 2568762d491aSChaotian Jing 256920848903SChaotian Jing /* Allocate MMC host for this device */ 257020848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 257120848903SChaotian Jing if (!mmc) 257220848903SChaotian Jing return -ENOMEM; 257320848903SChaotian Jing 257420848903SChaotian Jing host = mmc_priv(mmc); 257520848903SChaotian Jing ret = mmc_of_parse(mmc); 257620848903SChaotian Jing if (ret) 257720848903SChaotian Jing goto host_free; 257820848903SChaotian Jing 2579bc068d38SYangtao Li host->base = devm_platform_ioremap_resource(pdev, 0); 258020848903SChaotian Jing if (IS_ERR(host->base)) { 258120848903SChaotian Jing ret = PTR_ERR(host->base); 258220848903SChaotian Jing goto host_free; 258320848903SChaotian Jing } 258420848903SChaotian Jing 2585a2e6d1f6SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2586b65be635SFabien Parent if (res) { 2587a2e6d1f6SChaotian Jing host->top_base = devm_ioremap_resource(&pdev->dev, res); 2588a2e6d1f6SChaotian Jing if (IS_ERR(host->top_base)) 2589a2e6d1f6SChaotian Jing host->top_base = NULL; 2590b65be635SFabien Parent } 2591a2e6d1f6SChaotian Jing 259220848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 25932f98ef63SWolfram Sang if (ret) 259420848903SChaotian Jing goto host_free; 259520848903SChaotian Jing 2596f5eccd94SWenbin Mei ret = msdc_of_clock_parse(pdev, host); 2597f5eccd94SWenbin Mei if (ret) 259820848903SChaotian Jing goto host_free; 25993c1a8844SChaotian Jing 2600855d388dSWenbin Mei host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2601855d388dSWenbin Mei "hrst"); 2602bbba85faSZheng Liang if (IS_ERR(host->reset)) { 2603bbba85faSZheng Liang ret = PTR_ERR(host->reset); 2604bbba85faSZheng Liang goto host_free; 2605bbba85faSZheng Liang } 2606855d388dSWenbin Mei 260720848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 260820848903SChaotian Jing if (host->irq < 0) { 260920848903SChaotian Jing ret = -EINVAL; 261020848903SChaotian Jing goto host_free; 261120848903SChaotian Jing } 261220848903SChaotian Jing 261320848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 261420848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 261520848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 261620848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 261720848903SChaotian Jing goto host_free; 261820848903SChaotian Jing } 261920848903SChaotian Jing 262020848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 262120848903SChaotian Jing if (IS_ERR(host->pins_default)) { 262220848903SChaotian Jing ret = PTR_ERR(host->pins_default); 262320848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 262420848903SChaotian Jing goto host_free; 262520848903SChaotian Jing } 262620848903SChaotian Jing 262720848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 262820848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 262920848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 263020848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 263120848903SChaotian Jing goto host_free; 263220848903SChaotian Jing } 263320848903SChaotian Jing 26341ede5cb8Syong mao msdc_of_property_parse(pdev, host); 26356397b7f5SChaotian Jing 263620848903SChaotian Jing host->dev = &pdev->dev; 2637909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 263820848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 263920848903SChaotian Jing /* Set host parameters to mmc */ 264020848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2641762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 264240ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2643762d491aSChaotian Jing else 2644762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 264520848903SChaotian Jing 2646d087bde5SNeilBrown if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2647d087bde5SNeilBrown !mmc_can_gpio_cd(mmc) && 2648d087bde5SNeilBrown host->dev_comp->use_internal_cd) { 2649d087bde5SNeilBrown /* 2650d087bde5SNeilBrown * Is removable but no GPIO declared, so 2651d087bde5SNeilBrown * use internal functionality. 2652d087bde5SNeilBrown */ 2653d087bde5SNeilBrown host->internal_cd = true; 2654d087bde5SNeilBrown } 2655d087bde5SNeilBrown 26565215b2e9Sjjian zhou if (mmc->caps & MMC_CAP_SDIO_IRQ) 26575215b2e9Sjjian zhou mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 26585215b2e9Sjjian zhou 26591be64c79SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 266088bd652bSChun-Hung Wu if (host->cqhci) 266188bd652bSChun-Hung Wu mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 266220848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 266320848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 26646ef042bdSChaotian Jing if (host->dev_comp->support_64g) 26656ef042bdSChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 26666ef042bdSChaotian Jing else 266720848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 266820848903SChaotian Jing mmc->max_blk_size = 2048; 266920848903SChaotian Jing mmc->max_req_size = 512 * 1024; 267020848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 26712a9bde19SChaotian Jing if (host->dev_comp->support_64g) 26722a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 26732a9bde19SChaotian Jing else 267420848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 267520848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 267620848903SChaotian Jing 2677e8a1ff65SWenbin Mei host->timeout_clks = 3 * 1048576; 2678e8a1ff65SWenbin Mei host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2679e8a1ff65SWenbin Mei 2 * sizeof(struct mt_gpdma_desc), 2680e8a1ff65SWenbin Mei &host->dma.gpd_addr, GFP_KERNEL); 2681e8a1ff65SWenbin Mei host->dma.bd = dma_alloc_coherent(&pdev->dev, 2682e8a1ff65SWenbin Mei MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2683e8a1ff65SWenbin Mei &host->dma.bd_addr, GFP_KERNEL); 2684e8a1ff65SWenbin Mei if (!host->dma.gpd || !host->dma.bd) { 2685e8a1ff65SWenbin Mei ret = -ENOMEM; 2686e8a1ff65SWenbin Mei goto release_mem; 2687e8a1ff65SWenbin Mei } 2688e8a1ff65SWenbin Mei msdc_init_gpd_bd(host, &host->dma); 2689e8a1ff65SWenbin Mei INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2690e8a1ff65SWenbin Mei spin_lock_init(&host->lock); 2691e8a1ff65SWenbin Mei 2692e8a1ff65SWenbin Mei platform_set_drvdata(pdev, mmc); 2693ffaea6ebSAngeloGioacchino Del Regno ret = msdc_ungate_clock(host); 2694ffaea6ebSAngeloGioacchino Del Regno if (ret) { 2695ffaea6ebSAngeloGioacchino Del Regno dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2696ffaea6ebSAngeloGioacchino Del Regno goto release_mem; 2697ffaea6ebSAngeloGioacchino Del Regno } 2698e8a1ff65SWenbin Mei msdc_init_hw(host); 2699e8a1ff65SWenbin Mei 270088bd652bSChun-Hung Wu if (mmc->caps2 & MMC_CAP2_CQE) { 27010caf60c4SAmey Narkhede host->cq_host = devm_kzalloc(mmc->parent, 270288bd652bSChun-Hung Wu sizeof(*host->cq_host), 270388bd652bSChun-Hung Wu GFP_KERNEL); 270488bd652bSChun-Hung Wu if (!host->cq_host) { 270588bd652bSChun-Hung Wu ret = -ENOMEM; 270688bd652bSChun-Hung Wu goto host_free; 270788bd652bSChun-Hung Wu } 270888bd652bSChun-Hung Wu host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 270988bd652bSChun-Hung Wu host->cq_host->mmio = host->base + 0x800; 271088bd652bSChun-Hung Wu host->cq_host->ops = &msdc_cmdq_ops; 271188bd652bSChun-Hung Wu ret = cqhci_init(host->cq_host, mmc, true); 271288bd652bSChun-Hung Wu if (ret) 271388bd652bSChun-Hung Wu goto host_free; 271488bd652bSChun-Hung Wu mmc->max_segs = 128; 271588bd652bSChun-Hung Wu /* cqhci 16bit length */ 271688bd652bSChun-Hung Wu /* 0 size, means 65536 so we don't have to -1 here */ 271788bd652bSChun-Hung Wu mmc->max_seg_size = 64 * 1024; 271888bd652bSChun-Hung Wu } 271988bd652bSChun-Hung Wu 272020848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 272142edb0d5SNeilBrown IRQF_TRIGGER_NONE, pdev->name, host); 272220848903SChaotian Jing if (ret) 272320848903SChaotian Jing goto release; 272420848903SChaotian Jing 27254b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 27264b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 27274b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 27284b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 272920848903SChaotian Jing ret = mmc_add_host(mmc); 27304b8a43e9SChaotian Jing 273120848903SChaotian Jing if (ret) 27324b8a43e9SChaotian Jing goto end; 273320848903SChaotian Jing 273420848903SChaotian Jing return 0; 27354b8a43e9SChaotian Jing end: 27364b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 273720848903SChaotian Jing release: 273820848903SChaotian Jing platform_set_drvdata(pdev, NULL); 273920848903SChaotian Jing msdc_deinit_hw(host); 274020848903SChaotian Jing msdc_gate_clock(host); 274120848903SChaotian Jing release_mem: 274220848903SChaotian Jing if (host->dma.gpd) 274320848903SChaotian Jing dma_free_coherent(&pdev->dev, 274462b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 274520848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 274620848903SChaotian Jing if (host->dma.bd) 274720848903SChaotian Jing dma_free_coherent(&pdev->dev, 274820848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 274920848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 275020848903SChaotian Jing host_free: 275120848903SChaotian Jing mmc_free_host(mmc); 275220848903SChaotian Jing 275320848903SChaotian Jing return ret; 275420848903SChaotian Jing } 275520848903SChaotian Jing 275620848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 275720848903SChaotian Jing { 275820848903SChaotian Jing struct mmc_host *mmc; 275920848903SChaotian Jing struct msdc_host *host; 276020848903SChaotian Jing 276120848903SChaotian Jing mmc = platform_get_drvdata(pdev); 276220848903SChaotian Jing host = mmc_priv(mmc); 276320848903SChaotian Jing 27644b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 27654b8a43e9SChaotian Jing 276620848903SChaotian Jing platform_set_drvdata(pdev, NULL); 27670caf60c4SAmey Narkhede mmc_remove_host(mmc); 276820848903SChaotian Jing msdc_deinit_hw(host); 276920848903SChaotian Jing msdc_gate_clock(host); 277020848903SChaotian Jing 27714b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 27724b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 277320848903SChaotian Jing dma_free_coherent(&pdev->dev, 277416f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 277520848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 277620848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 277720848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 277820848903SChaotian Jing 27790caf60c4SAmey Narkhede mmc_free_host(mmc); 278020848903SChaotian Jing 278120848903SChaotian Jing return 0; 278220848903SChaotian Jing } 278320848903SChaotian Jing 27844b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 27854b8a43e9SChaotian Jing { 278639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 278739add252SChaotian Jing 27884b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 27894b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 27904b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 27914b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 27924b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 27932fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 27946397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 27951ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 27966397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2797c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2798d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2799a2e6d1f6SChaotian Jing if (host->top_base) { 2800a2e6d1f6SChaotian Jing host->save_para.emmc_top_control = 2801a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 2802a2e6d1f6SChaotian Jing host->save_para.emmc_top_cmd = 2803a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 2804a2e6d1f6SChaotian Jing host->save_para.emmc50_pad_ds_tune = 2805a2e6d1f6SChaotian Jing readl(host->top_base + EMMC50_PAD_DS_TUNE); 2806a2e6d1f6SChaotian Jing } else { 2807a2e6d1f6SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 2808a2e6d1f6SChaotian Jing } 28094b8a43e9SChaotian Jing } 28104b8a43e9SChaotian Jing 28114b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 28124b8a43e9SChaotian Jing { 28130caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 281439add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 281539add252SChaotian Jing 28164b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 28174b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 28184b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 28194b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 28204b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 28212fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 28226397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 28231ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 28246397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2825c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2826d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2827a2e6d1f6SChaotian Jing if (host->top_base) { 2828a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_control, 2829a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 2830a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_cmd, 2831a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 2832a2e6d1f6SChaotian Jing writel(host->save_para.emmc50_pad_ds_tune, 2833a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2834a2e6d1f6SChaotian Jing } else { 2835a2e6d1f6SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 2836a2e6d1f6SChaotian Jing } 28371c81d69dSUlf Hansson 28380caf60c4SAmey Narkhede if (sdio_irq_claimed(mmc)) 28391c81d69dSUlf Hansson __msdc_enable_sdio_irq(host, 1); 28404b8a43e9SChaotian Jing } 28414b8a43e9SChaotian Jing 2842c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_suspend(struct device *dev) 28434b8a43e9SChaotian Jing { 28444b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 28454b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 28464b8a43e9SChaotian Jing 28474b8a43e9SChaotian Jing msdc_save_reg(host); 28484b8a43e9SChaotian Jing msdc_gate_clock(host); 28494b8a43e9SChaotian Jing return 0; 28504b8a43e9SChaotian Jing } 28514b8a43e9SChaotian Jing 2852c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_resume(struct device *dev) 28534b8a43e9SChaotian Jing { 28544b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 28554b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2856ffaea6ebSAngeloGioacchino Del Regno int ret; 28574b8a43e9SChaotian Jing 2858ffaea6ebSAngeloGioacchino Del Regno ret = msdc_ungate_clock(host); 2859ffaea6ebSAngeloGioacchino Del Regno if (ret) 2860ffaea6ebSAngeloGioacchino Del Regno return ret; 2861ffaea6ebSAngeloGioacchino Del Regno 28624b8a43e9SChaotian Jing msdc_restore_reg(host); 28634b8a43e9SChaotian Jing return 0; 28644b8a43e9SChaotian Jing } 2865c0a2074aSWenbin Mei 2866c0d638a0SArnd Bergmann static int __maybe_unused msdc_suspend(struct device *dev) 2867c0a2074aSWenbin Mei { 2868c0a2074aSWenbin Mei struct mmc_host *mmc = dev_get_drvdata(dev); 2869c0a2074aSWenbin Mei int ret; 2870c0a2074aSWenbin Mei 2871c0a2074aSWenbin Mei if (mmc->caps2 & MMC_CAP2_CQE) { 2872c0a2074aSWenbin Mei ret = cqhci_suspend(mmc); 2873c0a2074aSWenbin Mei if (ret) 2874c0a2074aSWenbin Mei return ret; 2875c0a2074aSWenbin Mei } 2876c0a2074aSWenbin Mei 2877c0a2074aSWenbin Mei return pm_runtime_force_suspend(dev); 2878c0a2074aSWenbin Mei } 2879c0a2074aSWenbin Mei 2880c0d638a0SArnd Bergmann static int __maybe_unused msdc_resume(struct device *dev) 2881c0a2074aSWenbin Mei { 2882c0a2074aSWenbin Mei return pm_runtime_force_resume(dev); 2883c0a2074aSWenbin Mei } 28844b8a43e9SChaotian Jing 28854b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 2886c0a2074aSWenbin Mei SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 28874b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 28884b8a43e9SChaotian Jing }; 28894b8a43e9SChaotian Jing 289020848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 289120848903SChaotian Jing .probe = msdc_drv_probe, 289220848903SChaotian Jing .remove = msdc_drv_remove, 289320848903SChaotian Jing .driver = { 289420848903SChaotian Jing .name = "mtk-msdc", 289521b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 289620848903SChaotian Jing .of_match_table = msdc_of_ids, 28974b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 289820848903SChaotian Jing }, 289920848903SChaotian Jing }; 290020848903SChaotian Jing 290120848903SChaotian Jing module_platform_driver(mt_msdc_driver); 290220848903SChaotian Jing MODULE_LICENSE("GPL v2"); 290320848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2904