11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 220848903SChaotian Jing /* 320848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 420848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 520848903SChaotian Jing */ 620848903SChaotian Jing 720848903SChaotian Jing #include <linux/module.h> 820848903SChaotian Jing #include <linux/clk.h> 920848903SChaotian Jing #include <linux/delay.h> 1020848903SChaotian Jing #include <linux/dma-mapping.h> 1120848903SChaotian Jing #include <linux/ioport.h> 1220848903SChaotian Jing #include <linux/irq.h> 1320848903SChaotian Jing #include <linux/of_address.h> 14909b3456SRyder Lee #include <linux/of_device.h> 1520848903SChaotian Jing #include <linux/of_irq.h> 1620848903SChaotian Jing #include <linux/of_gpio.h> 1720848903SChaotian Jing #include <linux/pinctrl/consumer.h> 1820848903SChaotian Jing #include <linux/platform_device.h> 194b8a43e9SChaotian Jing #include <linux/pm.h> 204b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2120848903SChaotian Jing #include <linux/regulator/consumer.h> 226397b7f5SChaotian Jing #include <linux/slab.h> 2320848903SChaotian Jing #include <linux/spinlock.h> 24b8789ec4SUlf Hansson #include <linux/interrupt.h> 25855d388dSWenbin Mei #include <linux/reset.h> 2620848903SChaotian Jing 2720848903SChaotian Jing #include <linux/mmc/card.h> 2820848903SChaotian Jing #include <linux/mmc/core.h> 2920848903SChaotian Jing #include <linux/mmc/host.h> 3020848903SChaotian Jing #include <linux/mmc/mmc.h> 3120848903SChaotian Jing #include <linux/mmc/sd.h> 3220848903SChaotian Jing #include <linux/mmc/sdio.h> 338d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 3420848903SChaotian Jing 3588bd652bSChun-Hung Wu #include "cqhci.h" 3688bd652bSChun-Hung Wu 3720848903SChaotian Jing #define MAX_BD_NUM 1024 3820848903SChaotian Jing 3920848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4020848903SChaotian Jing /* Common Definition */ 4120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4220848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4320848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4420848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4520848903SChaotian Jing 4620848903SChaotian Jing #define MSDC_BURST_64B 0x6 4720848903SChaotian Jing 4820848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4920848903SChaotian Jing /* Register Offset */ 5020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5120848903SChaotian Jing #define MSDC_CFG 0x0 5220848903SChaotian Jing #define MSDC_IOCON 0x04 5320848903SChaotian Jing #define MSDC_PS 0x08 5420848903SChaotian Jing #define MSDC_INT 0x0c 5520848903SChaotian Jing #define MSDC_INTEN 0x10 5620848903SChaotian Jing #define MSDC_FIFOCS 0x14 5720848903SChaotian Jing #define SDC_CFG 0x30 5820848903SChaotian Jing #define SDC_CMD 0x34 5920848903SChaotian Jing #define SDC_ARG 0x38 6020848903SChaotian Jing #define SDC_STS 0x3c 6120848903SChaotian Jing #define SDC_RESP0 0x40 6220848903SChaotian Jing #define SDC_RESP1 0x44 6320848903SChaotian Jing #define SDC_RESP2 0x48 6420848903SChaotian Jing #define SDC_RESP3 0x4c 6520848903SChaotian Jing #define SDC_BLK_NUM 0x50 66d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 67c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 6820848903SChaotian Jing #define SDC_ACMD_RESP 0x80 692a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 7020848903SChaotian Jing #define MSDC_DMA_SA 0x90 7120848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7220848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7320848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7420848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 752fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 7620848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 7739add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 786397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 791ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 806397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 81c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 82d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 8320848903SChaotian Jing 8420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 85a2e6d1f6SChaotian Jing /* Top Pad Register Offset */ 86a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 87a2e6d1f6SChaotian Jing #define EMMC_TOP_CONTROL 0x00 88a2e6d1f6SChaotian Jing #define EMMC_TOP_CMD 0x04 89a2e6d1f6SChaotian Jing #define EMMC50_PAD_DS_TUNE 0x0c 90a2e6d1f6SChaotian Jing 91a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 9220848903SChaotian Jing /* Register Mask */ 9320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 9420848903SChaotian Jing 9520848903SChaotian Jing /* MSDC_CFG mask */ 9620848903SChaotian Jing #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 9720848903SChaotian Jing #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 9820848903SChaotian Jing #define MSDC_CFG_RST (0x1 << 2) /* RW */ 9920848903SChaotian Jing #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 10020848903SChaotian Jing #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 10120848903SChaotian Jing #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 10220848903SChaotian Jing #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 10320848903SChaotian Jing #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 10420848903SChaotian Jing #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 10520848903SChaotian Jing #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 1066397b7f5SChaotian Jing #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 107762d491aSChaotian Jing #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 108762d491aSChaotian Jing #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 109762d491aSChaotian Jing #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 11020848903SChaotian Jing 11120848903SChaotian Jing /* MSDC_IOCON mask */ 11220848903SChaotian Jing #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 11320848903SChaotian Jing #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 11420848903SChaotian Jing #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 11520848903SChaotian Jing #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 11620848903SChaotian Jing #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 11720848903SChaotian Jing #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 11820848903SChaotian Jing #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 11920848903SChaotian Jing #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 12020848903SChaotian Jing #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 12120848903SChaotian Jing #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 12220848903SChaotian Jing #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 12320848903SChaotian Jing #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 12420848903SChaotian Jing #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 12520848903SChaotian Jing #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 12620848903SChaotian Jing #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 12720848903SChaotian Jing #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 12820848903SChaotian Jing 12920848903SChaotian Jing /* MSDC_PS mask */ 13020848903SChaotian Jing #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 13120848903SChaotian Jing #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 13220848903SChaotian Jing #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 13320848903SChaotian Jing #define MSDC_PS_DAT (0xff << 16) /* R */ 1349e2582e5Syong mao #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 13520848903SChaotian Jing #define MSDC_PS_CMD (0x1 << 24) /* R */ 13620848903SChaotian Jing #define MSDC_PS_WP (0x1 << 31) /* R */ 13720848903SChaotian Jing 13820848903SChaotian Jing /* MSDC_INT mask */ 13920848903SChaotian Jing #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 14020848903SChaotian Jing #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 14120848903SChaotian Jing #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 14220848903SChaotian Jing #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 14320848903SChaotian Jing #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 14420848903SChaotian Jing #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 14520848903SChaotian Jing #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 14620848903SChaotian Jing #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 14720848903SChaotian Jing #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 14820848903SChaotian Jing #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 14920848903SChaotian Jing #define MSDC_INT_CSTA (0x1 << 11) /* R */ 15020848903SChaotian Jing #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 15120848903SChaotian Jing #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 15220848903SChaotian Jing #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 15320848903SChaotian Jing #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 15420848903SChaotian Jing #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 15520848903SChaotian Jing #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 15620848903SChaotian Jing #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 15720848903SChaotian Jing #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 15888bd652bSChun-Hung Wu #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 15920848903SChaotian Jing 16020848903SChaotian Jing /* MSDC_INTEN mask */ 16120848903SChaotian Jing #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 16220848903SChaotian Jing #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 16320848903SChaotian Jing #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 16420848903SChaotian Jing #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 16520848903SChaotian Jing #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 16620848903SChaotian Jing #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 16720848903SChaotian Jing #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 16820848903SChaotian Jing #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 16920848903SChaotian Jing #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 17020848903SChaotian Jing #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 17120848903SChaotian Jing #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 17220848903SChaotian Jing #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 17320848903SChaotian Jing #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 17420848903SChaotian Jing #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 17520848903SChaotian Jing #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 17620848903SChaotian Jing #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 17720848903SChaotian Jing #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 17820848903SChaotian Jing #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 17920848903SChaotian Jing #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 18020848903SChaotian Jing 18120848903SChaotian Jing /* MSDC_FIFOCS mask */ 18220848903SChaotian Jing #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 18320848903SChaotian Jing #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 18420848903SChaotian Jing #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 18520848903SChaotian Jing 18620848903SChaotian Jing /* SDC_CFG mask */ 18720848903SChaotian Jing #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 18820848903SChaotian Jing #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 18988bd652bSChun-Hung Wu #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 19020848903SChaotian Jing #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 19120848903SChaotian Jing #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 19220848903SChaotian Jing #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 19320848903SChaotian Jing #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 19420848903SChaotian Jing #define SDC_CFG_DTOC (0xff << 24) /* RW */ 19520848903SChaotian Jing 19620848903SChaotian Jing /* SDC_STS mask */ 19720848903SChaotian Jing #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 19820848903SChaotian Jing #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 19920848903SChaotian Jing #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 20020848903SChaotian Jing 20126c71a13Syong mao #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 202d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 203d9dcbfc8SChaotian Jing #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 204d9dcbfc8SChaotian Jing 2052a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2062a9bde19SChaotian Jing #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 2072a9bde19SChaotian Jing 20820848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 20920848903SChaotian Jing #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 21020848903SChaotian Jing #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 21120848903SChaotian Jing #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 21220848903SChaotian Jing #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 21320848903SChaotian Jing #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 21420848903SChaotian Jing #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 21520848903SChaotian Jing 21620848903SChaotian Jing /* MSDC_DMA_CFG mask */ 21720848903SChaotian Jing #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 21820848903SChaotian Jing #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 21920848903SChaotian Jing #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 22020848903SChaotian Jing #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 22120848903SChaotian Jing #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 22220848903SChaotian Jing 22320848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 22420848903SChaotian Jing #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 22520848903SChaotian Jing #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 22620848903SChaotian Jing #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 22720848903SChaotian Jing #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 22820848903SChaotian Jing #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 22920848903SChaotian Jing #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 23020848903SChaotian Jing #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 23120848903SChaotian Jing #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 23220848903SChaotian Jing #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 23320848903SChaotian Jing #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 23420848903SChaotian Jing #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 23520848903SChaotian Jing #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 23620848903SChaotian Jing 2378f34e5bdSChaotian Jing #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 23888bd652bSChun-Hung Wu #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 239d9dcbfc8SChaotian Jing #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 240d9dcbfc8SChaotian Jing 2412fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 2422fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 2432a9bde19SChaotian Jing #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 2442fea5819SChaotian Jing #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 2452fea5819SChaotian Jing #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 2462fea5819SChaotian Jing #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 2472fea5819SChaotian Jing 2481ede5cb8Syong mao #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 2496397b7f5SChaotian Jing #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 2506397b7f5SChaotian Jing #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 2511ede5cb8Syong mao #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 2521ede5cb8Syong mao #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 2532fea5819SChaotian Jing #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 2542fea5819SChaotian Jing #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 2552fea5819SChaotian Jing #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 2566397b7f5SChaotian Jing 2576397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 2586397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 2596397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 2606397b7f5SChaotian Jing 2611ede5cb8Syong mao #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 2621ede5cb8Syong mao 2636397b7f5SChaotian Jing #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 2646397b7f5SChaotian Jing #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 2656397b7f5SChaotian Jing #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 2666397b7f5SChaotian Jing 267c8609b22SChaotian Jing #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 268c8609b22SChaotian Jing 269d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 270d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 271d9dcbfc8SChaotian Jing 272a2e6d1f6SChaotian Jing /* EMMC_TOP_CONTROL mask */ 273a2e6d1f6SChaotian Jing #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 274a2e6d1f6SChaotian Jing #define DELAY_EN (0x1 << 1) /* RW */ 275a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 276a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 277a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 278a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 279a2e6d1f6SChaotian Jing #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 280a2e6d1f6SChaotian Jing #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 281a2e6d1f6SChaotian Jing 282a2e6d1f6SChaotian Jing /* EMMC_TOP_CMD mask */ 283a2e6d1f6SChaotian Jing #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 284a2e6d1f6SChaotian Jing #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 285a2e6d1f6SChaotian Jing #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 286a2e6d1f6SChaotian Jing #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 287a2e6d1f6SChaotian Jing #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 288a2e6d1f6SChaotian Jing 28920848903SChaotian Jing #define REQ_CMD_EIO (0x1 << 0) 29020848903SChaotian Jing #define REQ_CMD_TMO (0x1 << 1) 29120848903SChaotian Jing #define REQ_DAT_ERR (0x1 << 2) 29220848903SChaotian Jing #define REQ_STOP_EIO (0x1 << 3) 29320848903SChaotian Jing #define REQ_STOP_TMO (0x1 << 4) 29420848903SChaotian Jing #define REQ_CMD_BUSY (0x1 << 5) 29520848903SChaotian Jing 29620848903SChaotian Jing #define MSDC_PREPARE_FLAG (0x1 << 0) 29720848903SChaotian Jing #define MSDC_ASYNC_FLAG (0x1 << 1) 29820848903SChaotian Jing #define MSDC_MMAP_FLAG (0x1 << 2) 29920848903SChaotian Jing 3004b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 30120848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 30220848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 30320848903SChaotian Jing 304d087bde5SNeilBrown #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 305d087bde5SNeilBrown 3066397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 30720848903SChaotian Jing /*--------------------------------------------------------------------------*/ 30820848903SChaotian Jing /* Descriptor Structure */ 30920848903SChaotian Jing /*--------------------------------------------------------------------------*/ 31020848903SChaotian Jing struct mt_gpdma_desc { 31120848903SChaotian Jing u32 gpd_info; 31220848903SChaotian Jing #define GPDMA_DESC_HWO (0x1 << 0) 31320848903SChaotian Jing #define GPDMA_DESC_BDP (0x1 << 1) 31420848903SChaotian Jing #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 31520848903SChaotian Jing #define GPDMA_DESC_INT (0x1 << 16) 3162a9bde19SChaotian Jing #define GPDMA_DESC_NEXT_H4 (0xf << 24) 3172a9bde19SChaotian Jing #define GPDMA_DESC_PTR_H4 (0xf << 28) 31820848903SChaotian Jing u32 next; 31920848903SChaotian Jing u32 ptr; 32020848903SChaotian Jing u32 gpd_data_len; 32120848903SChaotian Jing #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 32220848903SChaotian Jing #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 32320848903SChaotian Jing u32 arg; 32420848903SChaotian Jing u32 blknum; 32520848903SChaotian Jing u32 cmd; 32620848903SChaotian Jing }; 32720848903SChaotian Jing 32820848903SChaotian Jing struct mt_bdma_desc { 32920848903SChaotian Jing u32 bd_info; 33020848903SChaotian Jing #define BDMA_DESC_EOL (0x1 << 0) 33120848903SChaotian Jing #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 33220848903SChaotian Jing #define BDMA_DESC_BLKPAD (0x1 << 17) 33320848903SChaotian Jing #define BDMA_DESC_DWPAD (0x1 << 18) 3342a9bde19SChaotian Jing #define BDMA_DESC_NEXT_H4 (0xf << 24) 3352a9bde19SChaotian Jing #define BDMA_DESC_PTR_H4 (0xf << 28) 33620848903SChaotian Jing u32 next; 33720848903SChaotian Jing u32 ptr; 33820848903SChaotian Jing u32 bd_data_len; 33920848903SChaotian Jing #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 3406ef042bdSChaotian Jing #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 34120848903SChaotian Jing }; 34220848903SChaotian Jing 34320848903SChaotian Jing struct msdc_dma { 34420848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 34520848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 34620848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 34720848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 34820848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 34920848903SChaotian Jing }; 35020848903SChaotian Jing 3514b8a43e9SChaotian Jing struct msdc_save_para { 3524b8a43e9SChaotian Jing u32 msdc_cfg; 3534b8a43e9SChaotian Jing u32 iocon; 3544b8a43e9SChaotian Jing u32 sdc_cfg; 3554b8a43e9SChaotian Jing u32 pad_tune; 3564b8a43e9SChaotian Jing u32 patch_bit0; 3574b8a43e9SChaotian Jing u32 patch_bit1; 3582fea5819SChaotian Jing u32 patch_bit2; 3596397b7f5SChaotian Jing u32 pad_ds_tune; 3601ede5cb8Syong mao u32 pad_cmd_tune; 3616397b7f5SChaotian Jing u32 emmc50_cfg0; 362c8609b22SChaotian Jing u32 emmc50_cfg3; 363d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 364a2e6d1f6SChaotian Jing u32 emmc_top_control; 365a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 366a2e6d1f6SChaotian Jing u32 emmc50_pad_ds_tune; 3676397b7f5SChaotian Jing }; 3686397b7f5SChaotian Jing 369762d491aSChaotian Jing struct mtk_mmc_compatible { 370762d491aSChaotian Jing u8 clk_div_bits; 3719e2582e5Syong mao bool recheck_sdio_irq; 3727f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 37339add252SChaotian Jing u32 pad_tune_reg; 3742fea5819SChaotian Jing bool async_fifo; 3752fea5819SChaotian Jing bool data_tune; 376acde28c4SChaotian Jing bool busy_check; 377d9dcbfc8SChaotian Jing bool stop_clk_fix; 378d9dcbfc8SChaotian Jing bool enhance_rx; 3792a9bde19SChaotian Jing bool support_64g; 380d087bde5SNeilBrown bool use_internal_cd; 381762d491aSChaotian Jing }; 382762d491aSChaotian Jing 38386beac37SChaotian Jing struct msdc_tune_para { 38486beac37SChaotian Jing u32 iocon; 38586beac37SChaotian Jing u32 pad_tune; 3861ede5cb8Syong mao u32 pad_cmd_tune; 387a2e6d1f6SChaotian Jing u32 emmc_top_control; 388a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 38986beac37SChaotian Jing }; 39086beac37SChaotian Jing 3916397b7f5SChaotian Jing struct msdc_delay_phase { 3926397b7f5SChaotian Jing u8 maxlen; 3936397b7f5SChaotian Jing u8 start; 3946397b7f5SChaotian Jing u8 final_phase; 3954b8a43e9SChaotian Jing }; 3964b8a43e9SChaotian Jing 39720848903SChaotian Jing struct msdc_host { 39820848903SChaotian Jing struct device *dev; 399762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 40020848903SChaotian Jing int cmd_rsp; 40120848903SChaotian Jing 40220848903SChaotian Jing spinlock_t lock; 40320848903SChaotian Jing struct mmc_request *mrq; 40420848903SChaotian Jing struct mmc_command *cmd; 40520848903SChaotian Jing struct mmc_data *data; 40620848903SChaotian Jing int error; 40720848903SChaotian Jing 40820848903SChaotian Jing void __iomem *base; /* host base address */ 409a2e6d1f6SChaotian Jing void __iomem *top_base; /* host top register base address */ 41020848903SChaotian Jing 41120848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 41220848903SChaotian Jing u64 dma_mask; 41320848903SChaotian Jing 41420848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 41520848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 41620848903SChaotian Jing 41720848903SChaotian Jing struct pinctrl *pinctrl; 41820848903SChaotian Jing struct pinctrl_state *pins_default; 41920848903SChaotian Jing struct pinctrl_state *pins_uhs; 42020848903SChaotian Jing struct delayed_work req_timeout; 42120848903SChaotian Jing int irq; /* host interrupt */ 422855d388dSWenbin Mei struct reset_control *reset; 42320848903SChaotian Jing 42420848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 42520848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 426258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 4273c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 42820848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 42920848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 4306e622947SChaotian Jing unsigned char timing; 43120848903SChaotian Jing bool vqmmc_enabled; 432d17bb71cSChaotian Jing u32 latch_ck; 4336397b7f5SChaotian Jing u32 hs400_ds_delay; 4341ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 4351ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4361ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4371ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4385462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 439d087bde5SNeilBrown bool internal_cd; /* Use internal card-detect logic */ 44088bd652bSChun-Hung Wu bool cqhci; /* support eMMC hw cmdq */ 4414b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 44286beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 44386beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 44488bd652bSChun-Hung Wu struct cqhci_host *cq_host; 44520848903SChaotian Jing }; 44620848903SChaotian Jing 447762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 448762d491aSChaotian Jing .clk_div_bits = 8, 449903a72ecSyong mao .recheck_sdio_irq = true, 4507f3d5852SChaotian Jing .hs400_tune = false, 45139add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4522fea5819SChaotian Jing .async_fifo = false, 4532fea5819SChaotian Jing .data_tune = false, 454acde28c4SChaotian Jing .busy_check = false, 455d9dcbfc8SChaotian Jing .stop_clk_fix = false, 456d9dcbfc8SChaotian Jing .enhance_rx = false, 4572a9bde19SChaotian Jing .support_64g = false, 458762d491aSChaotian Jing }; 459762d491aSChaotian Jing 460762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 461762d491aSChaotian Jing .clk_div_bits = 8, 4629e2582e5Syong mao .recheck_sdio_irq = true, 4637f3d5852SChaotian Jing .hs400_tune = true, 46439add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4652fea5819SChaotian Jing .async_fifo = false, 4662fea5819SChaotian Jing .data_tune = false, 467acde28c4SChaotian Jing .busy_check = false, 468d9dcbfc8SChaotian Jing .stop_clk_fix = false, 469d9dcbfc8SChaotian Jing .enhance_rx = false, 4702a9bde19SChaotian Jing .support_64g = false, 471762d491aSChaotian Jing }; 472762d491aSChaotian Jing 473a2e6d1f6SChaotian Jing static const struct mtk_mmc_compatible mt8183_compat = { 474a2e6d1f6SChaotian Jing .clk_div_bits = 12, 4759e2582e5Syong mao .recheck_sdio_irq = false, 476a2e6d1f6SChaotian Jing .hs400_tune = false, 477a2e6d1f6SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 478a2e6d1f6SChaotian Jing .async_fifo = true, 479a2e6d1f6SChaotian Jing .data_tune = true, 480a2e6d1f6SChaotian Jing .busy_check = true, 481a2e6d1f6SChaotian Jing .stop_clk_fix = true, 482a2e6d1f6SChaotian Jing .enhance_rx = true, 483a2e6d1f6SChaotian Jing .support_64g = true, 484a2e6d1f6SChaotian Jing }; 485a2e6d1f6SChaotian Jing 486762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2701_compat = { 487762d491aSChaotian Jing .clk_div_bits = 12, 488903a72ecSyong mao .recheck_sdio_irq = true, 4897f3d5852SChaotian Jing .hs400_tune = false, 49039add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 4912fea5819SChaotian Jing .async_fifo = true, 4922fea5819SChaotian Jing .data_tune = true, 493acde28c4SChaotian Jing .busy_check = false, 494d9dcbfc8SChaotian Jing .stop_clk_fix = false, 495d9dcbfc8SChaotian Jing .enhance_rx = false, 4962a9bde19SChaotian Jing .support_64g = false, 497762d491aSChaotian Jing }; 498762d491aSChaotian Jing 499762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2712_compat = { 500762d491aSChaotian Jing .clk_div_bits = 12, 5019e2582e5Syong mao .recheck_sdio_irq = false, 5027f3d5852SChaotian Jing .hs400_tune = false, 50339add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5042fea5819SChaotian Jing .async_fifo = true, 5052fea5819SChaotian Jing .data_tune = true, 506acde28c4SChaotian Jing .busy_check = true, 507d9dcbfc8SChaotian Jing .stop_clk_fix = true, 508d9dcbfc8SChaotian Jing .enhance_rx = true, 5092a9bde19SChaotian Jing .support_64g = true, 510762d491aSChaotian Jing }; 511762d491aSChaotian Jing 512966580adSSean Wang static const struct mtk_mmc_compatible mt7622_compat = { 513966580adSSean Wang .clk_div_bits = 12, 514903a72ecSyong mao .recheck_sdio_irq = true, 515966580adSSean Wang .hs400_tune = false, 516966580adSSean Wang .pad_tune_reg = MSDC_PAD_TUNE0, 517966580adSSean Wang .async_fifo = true, 518966580adSSean Wang .data_tune = true, 519966580adSSean Wang .busy_check = true, 520966580adSSean Wang .stop_clk_fix = true, 521966580adSSean Wang .enhance_rx = true, 5222a9bde19SChaotian Jing .support_64g = false, 523966580adSSean Wang }; 524966580adSSean Wang 52589822b73SFabien Parent static const struct mtk_mmc_compatible mt8516_compat = { 52689822b73SFabien Parent .clk_div_bits = 12, 527903a72ecSyong mao .recheck_sdio_irq = true, 52889822b73SFabien Parent .hs400_tune = false, 52989822b73SFabien Parent .pad_tune_reg = MSDC_PAD_TUNE0, 53089822b73SFabien Parent .async_fifo = true, 53189822b73SFabien Parent .data_tune = true, 53289822b73SFabien Parent .busy_check = true, 53389822b73SFabien Parent .stop_clk_fix = true, 53489822b73SFabien Parent }; 53589822b73SFabien Parent 536afb7c791SNeilBrown static const struct mtk_mmc_compatible mt7620_compat = { 537afb7c791SNeilBrown .clk_div_bits = 8, 538903a72ecSyong mao .recheck_sdio_irq = true, 539afb7c791SNeilBrown .hs400_tune = false, 540afb7c791SNeilBrown .pad_tune_reg = MSDC_PAD_TUNE, 541afb7c791SNeilBrown .async_fifo = false, 542afb7c791SNeilBrown .data_tune = false, 543afb7c791SNeilBrown .busy_check = false, 544afb7c791SNeilBrown .stop_clk_fix = false, 545afb7c791SNeilBrown .enhance_rx = false, 546d087bde5SNeilBrown .use_internal_cd = true, 547afb7c791SNeilBrown }; 548afb7c791SNeilBrown 5497d176b0eSChun-Hung Wu static const struct mtk_mmc_compatible mt6779_compat = { 5507d176b0eSChun-Hung Wu .clk_div_bits = 12, 551903a72ecSyong mao .recheck_sdio_irq = false, 5527d176b0eSChun-Hung Wu .hs400_tune = false, 5537d176b0eSChun-Hung Wu .pad_tune_reg = MSDC_PAD_TUNE0, 5547d176b0eSChun-Hung Wu .async_fifo = true, 5557d176b0eSChun-Hung Wu .data_tune = true, 5567d176b0eSChun-Hung Wu .busy_check = true, 5577d176b0eSChun-Hung Wu .stop_clk_fix = true, 5587d176b0eSChun-Hung Wu .enhance_rx = true, 5597d176b0eSChun-Hung Wu .support_64g = true, 5607d176b0eSChun-Hung Wu }; 5617d176b0eSChun-Hung Wu 562762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 563762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 564762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 565a2e6d1f6SChaotian Jing { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 566762d491aSChaotian Jing { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 567762d491aSChaotian Jing { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 568966580adSSean Wang { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 56989822b73SFabien Parent { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 570afb7c791SNeilBrown { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 5717d176b0eSChun-Hung Wu { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 572762d491aSChaotian Jing {} 573762d491aSChaotian Jing }; 574762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 575762d491aSChaotian Jing 57620848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 57720848903SChaotian Jing { 57820848903SChaotian Jing u32 val = readl(reg); 57920848903SChaotian Jing 58020848903SChaotian Jing val |= bs; 58120848903SChaotian Jing writel(val, reg); 58220848903SChaotian Jing } 58320848903SChaotian Jing 58420848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 58520848903SChaotian Jing { 58620848903SChaotian Jing u32 val = readl(reg); 58720848903SChaotian Jing 58820848903SChaotian Jing val &= ~bs; 58920848903SChaotian Jing writel(val, reg); 59020848903SChaotian Jing } 59120848903SChaotian Jing 59220848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 59320848903SChaotian Jing { 59420848903SChaotian Jing unsigned int tv = readl(reg); 59520848903SChaotian Jing 59620848903SChaotian Jing tv &= ~field; 59720848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 59820848903SChaotian Jing writel(tv, reg); 59920848903SChaotian Jing } 60020848903SChaotian Jing 60120848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 60220848903SChaotian Jing { 60320848903SChaotian Jing unsigned int tv = readl(reg); 60420848903SChaotian Jing 60520848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 60620848903SChaotian Jing } 60720848903SChaotian Jing 60820848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 60920848903SChaotian Jing { 61020848903SChaotian Jing u32 val; 61120848903SChaotian Jing 61220848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 61320848903SChaotian Jing while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 61420848903SChaotian Jing cpu_relax(); 61520848903SChaotian Jing 61620848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 61720848903SChaotian Jing while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 61820848903SChaotian Jing cpu_relax(); 61920848903SChaotian Jing 62020848903SChaotian Jing val = readl(host->base + MSDC_INT); 62120848903SChaotian Jing writel(val, host->base + MSDC_INT); 62220848903SChaotian Jing } 62320848903SChaotian Jing 62420848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 62520848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 6269e2582e5Syong mao static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 62720848903SChaotian Jing 628726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 629726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 630726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 631726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 63220848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 63320848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 63420848903SChaotian Jing 63520848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 63620848903SChaotian Jing { 63720848903SChaotian Jing u32 i, sum = 0; 63820848903SChaotian Jing 63920848903SChaotian Jing for (i = 0; i < len; i++) 64020848903SChaotian Jing sum += buf[i]; 64120848903SChaotian Jing return 0xff - (u8) sum; 64220848903SChaotian Jing } 64320848903SChaotian Jing 64420848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 64520848903SChaotian Jing struct mmc_data *data) 64620848903SChaotian Jing { 64720848903SChaotian Jing unsigned int j, dma_len; 64820848903SChaotian Jing dma_addr_t dma_address; 64920848903SChaotian Jing u32 dma_ctrl; 65020848903SChaotian Jing struct scatterlist *sg; 65120848903SChaotian Jing struct mt_gpdma_desc *gpd; 65220848903SChaotian Jing struct mt_bdma_desc *bd; 65320848903SChaotian Jing 65420848903SChaotian Jing sg = data->sg; 65520848903SChaotian Jing 65620848903SChaotian Jing gpd = dma->gpd; 65720848903SChaotian Jing bd = dma->bd; 65820848903SChaotian Jing 65920848903SChaotian Jing /* modify gpd */ 66020848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 66120848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 66220848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 66320848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 66420848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 66520848903SChaotian Jing 66620848903SChaotian Jing /* modify bd */ 66720848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 66820848903SChaotian Jing dma_address = sg_dma_address(sg); 66920848903SChaotian Jing dma_len = sg_dma_len(sg); 67020848903SChaotian Jing 67120848903SChaotian Jing /* init bd */ 67220848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 67320848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 6742a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 6752a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 6762a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 6772a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 6782a9bde19SChaotian Jing << 28; 6792a9bde19SChaotian Jing } 6806ef042bdSChaotian Jing 6816ef042bdSChaotian Jing if (host->dev_comp->support_64g) { 6826ef042bdSChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 6836ef042bdSChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 6846ef042bdSChaotian Jing } else { 68520848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 68620848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 6876ef042bdSChaotian Jing } 68820848903SChaotian Jing 68920848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 69020848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 69120848903SChaotian Jing else 69220848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 69320848903SChaotian Jing 69420848903SChaotian Jing /* checksume need to clear first */ 69520848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 69620848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 69720848903SChaotian Jing } 69820848903SChaotian Jing 69920848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 70020848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 70120848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 70220848903SChaotian Jing dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 70320848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 7042a9bde19SChaotian Jing if (host->dev_comp->support_64g) 7052a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 7062a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 7072a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 70820848903SChaotian Jing } 70920848903SChaotian Jing 71020848903SChaotian Jing static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 71120848903SChaotian Jing { 71220848903SChaotian Jing struct mmc_data *data = mrq->data; 71320848903SChaotian Jing 71420848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 71520848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 71620848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 717feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 71820848903SChaotian Jing } 71920848903SChaotian Jing } 72020848903SChaotian Jing 72120848903SChaotian Jing static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 72220848903SChaotian Jing { 72320848903SChaotian Jing struct mmc_data *data = mrq->data; 72420848903SChaotian Jing 72520848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 72620848903SChaotian Jing return; 72720848903SChaotian Jing 72820848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 72920848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 730feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 73120848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 73220848903SChaotian Jing } 73320848903SChaotian Jing } 73420848903SChaotian Jing 735557011b6SChun-Hung Wu static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 73620848903SChaotian Jing { 7370caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 738557011b6SChun-Hung Wu u64 timeout, clk_ns; 73920848903SChaotian Jing u32 mode = 0; 74020848903SChaotian Jing 7410caf60c4SAmey Narkhede if (mmc->actual_clock == 0) { 74220848903SChaotian Jing timeout = 0; 74320848903SChaotian Jing } else { 744557011b6SChun-Hung Wu clk_ns = 1000000000ULL; 7450caf60c4SAmey Narkhede do_div(clk_ns, mmc->actual_clock); 746557011b6SChun-Hung Wu timeout = ns + clk_ns - 1; 747557011b6SChun-Hung Wu do_div(timeout, clk_ns); 748557011b6SChun-Hung Wu timeout += clks; 74920848903SChaotian Jing /* in 1048576 sclk cycle unit */ 750557011b6SChun-Hung Wu timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 751762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 752762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 753762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 754762d491aSChaotian Jing else 755762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 756762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 75720848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 75820848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 75920848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 76020848903SChaotian Jing } 761557011b6SChun-Hung Wu return timeout; 762557011b6SChun-Hung Wu } 763557011b6SChun-Hung Wu 764557011b6SChun-Hung Wu /* clock control primitives */ 765557011b6SChun-Hung Wu static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 766557011b6SChun-Hung Wu { 767557011b6SChun-Hung Wu u64 timeout; 768557011b6SChun-Hung Wu 769557011b6SChun-Hung Wu host->timeout_ns = ns; 770557011b6SChun-Hung Wu host->timeout_clks = clks; 771557011b6SChun-Hung Wu 772557011b6SChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 773557011b6SChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 774557011b6SChun-Hung Wu (u32)(timeout > 255 ? 255 : timeout)); 77520848903SChaotian Jing } 77620848903SChaotian Jing 77788bd652bSChun-Hung Wu static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 77888bd652bSChun-Hung Wu { 77988bd652bSChun-Hung Wu u64 timeout; 78088bd652bSChun-Hung Wu 78188bd652bSChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 78288bd652bSChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 78388bd652bSChun-Hung Wu (u32)(timeout > 8191 ? 8191 : timeout)); 78488bd652bSChun-Hung Wu } 78588bd652bSChun-Hung Wu 78620848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 78720848903SChaotian Jing { 7883c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 78920848903SChaotian Jing clk_disable_unprepare(host->src_clk); 790258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 79120848903SChaotian Jing clk_disable_unprepare(host->h_clk); 79220848903SChaotian Jing } 79320848903SChaotian Jing 79420848903SChaotian Jing static void msdc_ungate_clock(struct msdc_host *host) 79520848903SChaotian Jing { 79620848903SChaotian Jing clk_prepare_enable(host->h_clk); 797258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 79820848903SChaotian Jing clk_prepare_enable(host->src_clk); 7993c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 80020848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 80120848903SChaotian Jing cpu_relax(); 80220848903SChaotian Jing } 80320848903SChaotian Jing 8046e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 80520848903SChaotian Jing { 8060caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 80720848903SChaotian Jing u32 mode; 80820848903SChaotian Jing u32 flags; 80920848903SChaotian Jing u32 div; 81020848903SChaotian Jing u32 sclk; 81139add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 81220848903SChaotian Jing 81320848903SChaotian Jing if (!hz) { 81420848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 81520848903SChaotian Jing host->mclk = 0; 8160caf60c4SAmey Narkhede mmc->actual_clock = 0; 81720848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 81820848903SChaotian Jing return; 81920848903SChaotian Jing } 82020848903SChaotian Jing 82120848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 82220848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 823762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8246397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 825762d491aSChaotian Jing else 826762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 827762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8286e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 8296397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 8306397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 8316397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 8326397b7f5SChaotian Jing mode = 0x3; 8336397b7f5SChaotian Jing else 83420848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 8356397b7f5SChaotian Jing 83620848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 83720848903SChaotian Jing div = 0; /* mean div = 1/4 */ 83820848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 83920848903SChaotian Jing } else { 84020848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 84120848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 84220848903SChaotian Jing div = (div >> 1); 84320848903SChaotian Jing } 8446397b7f5SChaotian Jing 8456397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 8466397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 847762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8486397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 8496397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 850762d491aSChaotian Jing else 851762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 852762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8536397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 8546397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 8556397b7f5SChaotian Jing } 85620848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 85720848903SChaotian Jing mode = 0x1; /* no divisor */ 85820848903SChaotian Jing div = 0; 85920848903SChaotian Jing sclk = host->src_clk_freq; 86020848903SChaotian Jing } else { 86120848903SChaotian Jing mode = 0x0; /* use divisor */ 86220848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 86320848903SChaotian Jing div = 0; /* mean div = 1/2 */ 86420848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 86520848903SChaotian Jing } else { 86620848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 86720848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 86820848903SChaotian Jing } 86920848903SChaotian Jing } 8703c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 8713c1a8844SChaotian Jing /* 8723c1a8844SChaotian Jing * As src_clk/HCLK use the same bit to gate/ungate, 8733c1a8844SChaotian Jing * So if want to only gate src_clk, need gate its parent(mux). 8743c1a8844SChaotian Jing */ 8753c1a8844SChaotian Jing if (host->src_clk_cg) 8763c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 8773c1a8844SChaotian Jing else 8783c1a8844SChaotian Jing clk_disable_unprepare(clk_get_parent(host->src_clk)); 879762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 880762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 881762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 88240ceda09Syong mao (mode << 8) | div); 883762d491aSChaotian Jing else 884762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 885762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 886762d491aSChaotian Jing (mode << 12) | div); 8873c1a8844SChaotian Jing if (host->src_clk_cg) 8883c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 8893c1a8844SChaotian Jing else 8903c1a8844SChaotian Jing clk_prepare_enable(clk_get_parent(host->src_clk)); 891762d491aSChaotian Jing 89220848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 89320848903SChaotian Jing cpu_relax(); 8943c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 8950caf60c4SAmey Narkhede mmc->actual_clock = sclk; 89620848903SChaotian Jing host->mclk = hz; 8976e622947SChaotian Jing host->timing = timing; 89820848903SChaotian Jing /* need because clk changed. */ 89920848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 90020848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 90120848903SChaotian Jing 90286beac37SChaotian Jing /* 90386beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 90486beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 90586beac37SChaotian Jing */ 9060caf60c4SAmey Narkhede if (mmc->actual_clock <= 52000000) { 90786beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 908a2e6d1f6SChaotian Jing if (host->top_base) { 909a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_control, 910a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 911a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_cmd, 912a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 913a2e6d1f6SChaotian Jing } else { 914a2e6d1f6SChaotian Jing writel(host->def_tune_para.pad_tune, 915a2e6d1f6SChaotian Jing host->base + tune_reg); 916a2e6d1f6SChaotian Jing } 91786beac37SChaotian Jing } else { 91886beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 9191ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 9201ede5cb8Syong mao host->base + PAD_CMD_TUNE); 921a2e6d1f6SChaotian Jing if (host->top_base) { 922a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_control, 923a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 924a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_cmd, 925a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 926a2e6d1f6SChaotian Jing } else { 927a2e6d1f6SChaotian Jing writel(host->saved_tune_para.pad_tune, 928a2e6d1f6SChaotian Jing host->base + tune_reg); 929a2e6d1f6SChaotian Jing } 93086beac37SChaotian Jing } 93186beac37SChaotian Jing 9327f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 9337f3d5852SChaotian Jing host->dev_comp->hs400_tune) 9343751e008SChaotian Jing sdr_set_field(host->base + tune_reg, 9351ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 9361ede5cb8Syong mao host->hs400_cmd_int_delay); 9370caf60c4SAmey Narkhede dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 93856f6cbbeSChaotian Jing timing); 93920848903SChaotian Jing } 94020848903SChaotian Jing 94120848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 94220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 94320848903SChaotian Jing { 94420848903SChaotian Jing u32 resp; 94520848903SChaotian Jing 94620848903SChaotian Jing switch (mmc_resp_type(cmd)) { 94720848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 94820848903SChaotian Jing case MMC_RSP_R1: 94920848903SChaotian Jing resp = 0x1; 95020848903SChaotian Jing break; 95120848903SChaotian Jing case MMC_RSP_R1B: 95220848903SChaotian Jing resp = 0x7; 95320848903SChaotian Jing break; 95420848903SChaotian Jing case MMC_RSP_R2: 95520848903SChaotian Jing resp = 0x2; 95620848903SChaotian Jing break; 95720848903SChaotian Jing case MMC_RSP_R3: 95820848903SChaotian Jing resp = 0x3; 95920848903SChaotian Jing break; 96020848903SChaotian Jing case MMC_RSP_NONE: 96120848903SChaotian Jing default: 96220848903SChaotian Jing resp = 0x0; 96320848903SChaotian Jing break; 96420848903SChaotian Jing } 96520848903SChaotian Jing 96620848903SChaotian Jing return resp; 96720848903SChaotian Jing } 96820848903SChaotian Jing 96920848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 97020848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 97120848903SChaotian Jing { 9720caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 97320848903SChaotian Jing /* rawcmd : 97420848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 97520848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 97620848903SChaotian Jing */ 97720848903SChaotian Jing u32 opcode = cmd->opcode; 97820848903SChaotian Jing u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 97920848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 98020848903SChaotian Jing 98120848903SChaotian Jing host->cmd_rsp = resp; 98220848903SChaotian Jing 98320848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 98420848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 98520848903SChaotian Jing rawcmd |= (0x1 << 14); 98620848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 98720848903SChaotian Jing rawcmd |= (0x1 << 30); 98820848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 98920848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 99020848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 99120848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 99220848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 99320848903SChaotian Jing rawcmd |= (0x1 << 11); 99420848903SChaotian Jing 99520848903SChaotian Jing if (cmd->data) { 99620848903SChaotian Jing struct mmc_data *data = cmd->data; 99720848903SChaotian Jing 99820848903SChaotian Jing if (mmc_op_multi(opcode)) { 9990caf60c4SAmey Narkhede if (mmc_card_mmc(mmc->card) && mrq->sbc && 100020848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 100120848903SChaotian Jing rawcmd |= 0x2 << 28; /* AutoCMD23 */ 100220848903SChaotian Jing } 100320848903SChaotian Jing 100420848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 100520848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 100620848903SChaotian Jing rawcmd |= (0x1 << 13); 100720848903SChaotian Jing if (data->blocks > 1) 100820848903SChaotian Jing rawcmd |= (0x2 << 11); 100920848903SChaotian Jing else 101020848903SChaotian Jing rawcmd |= (0x1 << 11); 101120848903SChaotian Jing /* Always use dma mode */ 101220848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 101320848903SChaotian Jing 101420848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 101520848903SChaotian Jing host->timeout_clks != data->timeout_clks) 101620848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 101720848903SChaotian Jing data->timeout_clks); 101820848903SChaotian Jing 101920848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 102020848903SChaotian Jing } 102120848903SChaotian Jing return rawcmd; 102220848903SChaotian Jing } 102320848903SChaotian Jing 102420848903SChaotian Jing static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 102520848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 102620848903SChaotian Jing { 102720848903SChaotian Jing bool read; 102820848903SChaotian Jing 102920848903SChaotian Jing WARN_ON(host->data); 103020848903SChaotian Jing host->data = data; 103120848903SChaotian Jing read = data->flags & MMC_DATA_READ; 103220848903SChaotian Jing 103320848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 103420848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 103520848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 103620848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 103720848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 103820848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 103920848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 104020848903SChaotian Jing } 104120848903SChaotian Jing 104220848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 104320848903SChaotian Jing struct mmc_command *cmd) 104420848903SChaotian Jing { 104520848903SChaotian Jing u32 *rsp = cmd->resp; 104620848903SChaotian Jing 104720848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 104820848903SChaotian Jing 104920848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 105020848903SChaotian Jing cmd->error = 0; 105120848903SChaotian Jing } else { 105220848903SChaotian Jing msdc_reset_hw(host); 105320848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 105420848903SChaotian Jing cmd->error = -EILSEQ; 105520848903SChaotian Jing host->error |= REQ_STOP_EIO; 105620848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 105720848903SChaotian Jing cmd->error = -ETIMEDOUT; 105820848903SChaotian Jing host->error |= REQ_STOP_TMO; 105920848903SChaotian Jing } 106020848903SChaotian Jing dev_err(host->dev, 106120848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 106220848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 106320848903SChaotian Jing } 106420848903SChaotian Jing return cmd->error; 106520848903SChaotian Jing } 106620848903SChaotian Jing 10676ec5a7b7SLee Jones /* 10689e2582e5Syong mao * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 10699e2582e5Syong mao * 10709e2582e5Syong mao * Host controller may lost interrupt in some special case. 10719e2582e5Syong mao * Add SDIO irq recheck mechanism to make sure all interrupts 10729e2582e5Syong mao * can be processed immediately 10739e2582e5Syong mao */ 10749e2582e5Syong mao static void msdc_recheck_sdio_irq(struct msdc_host *host) 10759e2582e5Syong mao { 10760caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 10779e2582e5Syong mao u32 reg_int, reg_inten, reg_ps; 10789e2582e5Syong mao 10790caf60c4SAmey Narkhede if (mmc->caps & MMC_CAP_SDIO_IRQ) { 10809e2582e5Syong mao reg_inten = readl(host->base + MSDC_INTEN); 10819e2582e5Syong mao if (reg_inten & MSDC_INTEN_SDIOIRQ) { 10829e2582e5Syong mao reg_int = readl(host->base + MSDC_INT); 10839e2582e5Syong mao reg_ps = readl(host->base + MSDC_PS); 10849e2582e5Syong mao if (!(reg_int & MSDC_INT_SDIOIRQ || 10859e2582e5Syong mao reg_ps & MSDC_PS_DATA1)) { 10869e2582e5Syong mao __msdc_enable_sdio_irq(host, 0); 10870caf60c4SAmey Narkhede sdio_signal_irq(mmc); 10889e2582e5Syong mao } 10899e2582e5Syong mao } 10909e2582e5Syong mao } 10919e2582e5Syong mao } 10929e2582e5Syong mao 109320848903SChaotian Jing static void msdc_track_cmd_data(struct msdc_host *host, 109420848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 109520848903SChaotian Jing { 109620848903SChaotian Jing if (host->error) 109720848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 109820848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 109920848903SChaotian Jing } 110020848903SChaotian Jing 110120848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 110220848903SChaotian Jing { 110320848903SChaotian Jing unsigned long flags; 110420848903SChaotian Jing bool ret; 110520848903SChaotian Jing 110620848903SChaotian Jing ret = cancel_delayed_work(&host->req_timeout); 110720848903SChaotian Jing if (!ret) { 110820848903SChaotian Jing /* delay work already running */ 110920848903SChaotian Jing return; 111020848903SChaotian Jing } 111120848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 111220848903SChaotian Jing host->mrq = NULL; 111320848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 111420848903SChaotian Jing 111520848903SChaotian Jing msdc_track_cmd_data(host, mrq->cmd, mrq->data); 111620848903SChaotian Jing if (mrq->data) 111720848903SChaotian Jing msdc_unprepare_data(host, mrq); 111820314ce3Sjjian zhou if (host->error) 111920314ce3Sjjian zhou msdc_reset_hw(host); 11200caf60c4SAmey Narkhede mmc_request_done(mmc_from_priv(host), mrq); 11219e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 11229e2582e5Syong mao msdc_recheck_sdio_irq(host); 112320848903SChaotian Jing } 112420848903SChaotian Jing 112520848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 112620848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 112720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 112820848903SChaotian Jing { 112920848903SChaotian Jing bool done = false; 113020848903SChaotian Jing bool sbc_error; 113120848903SChaotian Jing unsigned long flags; 113220848903SChaotian Jing u32 *rsp = cmd->resp; 113320848903SChaotian Jing 113420848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 113520848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 113620848903SChaotian Jing | MSDC_INT_ACMDTMO))) 113720848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 113820848903SChaotian Jing 113920848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 114020848903SChaotian Jing 114120848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 114220848903SChaotian Jing | MSDC_INT_RSPCRCERR 114320848903SChaotian Jing | MSDC_INT_CMDTMO))) 114420848903SChaotian Jing return done; 114520848903SChaotian Jing 114620848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 114720848903SChaotian Jing done = !host->cmd; 114820848903SChaotian Jing host->cmd = NULL; 114920848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 115020848903SChaotian Jing 115120848903SChaotian Jing if (done) 115220848903SChaotian Jing return true; 115320848903SChaotian Jing 1154726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 115520848903SChaotian Jing 115620848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 115720848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 115820848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 115920848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 116020848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 116120848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 116220848903SChaotian Jing } else { 116320848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 116420848903SChaotian Jing } 116520848903SChaotian Jing } 116620848903SChaotian Jing 116720848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1168da6e0f70SChaotian Jing if (events & MSDC_INT_CMDTMO || 1169da6e0f70SChaotian Jing (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1170da6e0f70SChaotian Jing cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1171ddc71387SChaotian Jing /* 1172ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 1173da6e0f70SChaotian Jing * may have alreay come when cmd19/cmd21 gets response 1174da6e0f70SChaotian Jing * CRC error. 1175ddc71387SChaotian Jing */ 117620848903SChaotian Jing msdc_reset_hw(host); 117720848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 117820848903SChaotian Jing cmd->error = -EILSEQ; 117920848903SChaotian Jing host->error |= REQ_CMD_EIO; 118020848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 118120848903SChaotian Jing cmd->error = -ETIMEDOUT; 118220848903SChaotian Jing host->error |= REQ_CMD_TMO; 118320848903SChaotian Jing } 118420848903SChaotian Jing } 118520848903SChaotian Jing if (cmd->error) 118620848903SChaotian Jing dev_dbg(host->dev, 118720848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 118820848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 118920848903SChaotian Jing cmd->error); 119020848903SChaotian Jing 119120848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 119220848903SChaotian Jing return true; 119320848903SChaotian Jing } 119420848903SChaotian Jing 119520848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 119620848903SChaotian Jing * is correct before issue a request. but host design do below 119720848903SChaotian Jing * checks recommended. 119820848903SChaotian Jing */ 119920848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 120020848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 120120848903SChaotian Jing { 120220848903SChaotian Jing /* The max busy time we can endure is 20ms */ 120320848903SChaotian Jing unsigned long tmo = jiffies + msecs_to_jiffies(20); 120420848903SChaotian Jing 120520848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 120620848903SChaotian Jing time_before(jiffies, tmo)) 120720848903SChaotian Jing cpu_relax(); 120820848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 120920848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 121020848903SChaotian Jing host->error |= REQ_CMD_BUSY; 121120848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 121220848903SChaotian Jing return false; 121320848903SChaotian Jing } 121420848903SChaotian Jing 121520848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 121620848903SChaotian Jing tmo = jiffies + msecs_to_jiffies(20); 121720848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 121820848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 121920848903SChaotian Jing time_before(jiffies, tmo)) 122020848903SChaotian Jing cpu_relax(); 122120848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 122220848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 122320848903SChaotian Jing host->error |= REQ_CMD_BUSY; 122420848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 122520848903SChaotian Jing return false; 122620848903SChaotian Jing } 122720848903SChaotian Jing } 122820848903SChaotian Jing return true; 122920848903SChaotian Jing } 123020848903SChaotian Jing 123120848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 123220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 123320848903SChaotian Jing { 123420848903SChaotian Jing u32 rawcmd; 12355215b2e9Sjjian zhou unsigned long flags; 123620848903SChaotian Jing 123720848903SChaotian Jing WARN_ON(host->cmd); 123820848903SChaotian Jing host->cmd = cmd; 123920848903SChaotian Jing 1240f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 124120848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 124220848903SChaotian Jing return; 124320848903SChaotian Jing 124420848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 124520848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 124620848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 124720848903SChaotian Jing msdc_reset_hw(host); 124820848903SChaotian Jing } 124920848903SChaotian Jing 125020848903SChaotian Jing cmd->error = 0; 125120848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 125220848903SChaotian Jing 12535215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 1254726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 12555215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 12565215b2e9Sjjian zhou 125720848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 125820848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 125920848903SChaotian Jing } 126020848903SChaotian Jing 126120848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 126220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 126320848903SChaotian Jing { 1264ddc71387SChaotian Jing if ((cmd->error && 1265ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1266ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1267ddc71387SChaotian Jing cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1268ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 126920848903SChaotian Jing msdc_request_done(host, mrq); 127020848903SChaotian Jing else if (cmd == mrq->sbc) 127120848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 127220848903SChaotian Jing else if (!cmd->data) 127320848903SChaotian Jing msdc_request_done(host, mrq); 127420848903SChaotian Jing else 127520848903SChaotian Jing msdc_start_data(host, mrq, cmd, cmd->data); 127620848903SChaotian Jing } 127720848903SChaotian Jing 127820848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 127920848903SChaotian Jing { 128020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 128120848903SChaotian Jing 128220848903SChaotian Jing host->error = 0; 128320848903SChaotian Jing WARN_ON(host->mrq); 128420848903SChaotian Jing host->mrq = mrq; 128520848903SChaotian Jing 128620848903SChaotian Jing if (mrq->data) 128720848903SChaotian Jing msdc_prepare_data(host, mrq); 128820848903SChaotian Jing 128920848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 129020848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 129120848903SChaotian Jing * use HW option, otherwise use SW option 129220848903SChaotian Jing */ 129320848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 129420848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 129520848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 129620848903SChaotian Jing else 129720848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 129820848903SChaotian Jing } 129920848903SChaotian Jing 1300d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 130120848903SChaotian Jing { 130220848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 130320848903SChaotian Jing struct mmc_data *data = mrq->data; 130420848903SChaotian Jing 130520848903SChaotian Jing if (!data) 130620848903SChaotian Jing return; 130720848903SChaotian Jing 130820848903SChaotian Jing msdc_prepare_data(host, mrq); 130920848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 131020848903SChaotian Jing } 131120848903SChaotian Jing 131220848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 131320848903SChaotian Jing int err) 131420848903SChaotian Jing { 131520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 131620848903SChaotian Jing struct mmc_data *data; 131720848903SChaotian Jing 131820848903SChaotian Jing data = mrq->data; 131920848903SChaotian Jing if (!data) 132020848903SChaotian Jing return; 132120848903SChaotian Jing if (data->host_cookie) { 132220848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 132320848903SChaotian Jing msdc_unprepare_data(host, mrq); 132420848903SChaotian Jing } 132520848903SChaotian Jing } 132620848903SChaotian Jing 132720848903SChaotian Jing static void msdc_data_xfer_next(struct msdc_host *host, 132820848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 132920848903SChaotian Jing { 133020848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 13316397b7f5SChaotian Jing !mrq->sbc) 133220848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 133320848903SChaotian Jing else 133420848903SChaotian Jing msdc_request_done(host, mrq); 133520848903SChaotian Jing } 133620848903SChaotian Jing 133720848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 133820848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 133920848903SChaotian Jing { 134020848903SChaotian Jing struct mmc_command *stop = data->stop; 134120848903SChaotian Jing unsigned long flags; 134220848903SChaotian Jing bool done; 134320848903SChaotian Jing unsigned int check_data = events & 134420848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 134520848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 134620848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 134720848903SChaotian Jing 134820848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 134920848903SChaotian Jing done = !host->data; 135020848903SChaotian Jing if (check_data) 135120848903SChaotian Jing host->data = NULL; 135220848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 135320848903SChaotian Jing 135420848903SChaotian Jing if (done) 135520848903SChaotian Jing return true; 135620848903SChaotian Jing 135720848903SChaotian Jing if (check_data || (stop && stop->error)) { 135820848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 135920848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 136020848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 136120848903SChaotian Jing 1); 136220848903SChaotian Jing while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 136320848903SChaotian Jing cpu_relax(); 136420848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 136520848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 136620848903SChaotian Jing 136720848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 136820848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 136920848903SChaotian Jing } else { 13702066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 137120848903SChaotian Jing msdc_reset_hw(host); 137220848903SChaotian Jing host->error |= REQ_DAT_ERR; 137320848903SChaotian Jing data->bytes_xfered = 0; 137420848903SChaotian Jing 137520848903SChaotian Jing if (events & MSDC_INT_DATTMO) 137620848903SChaotian Jing data->error = -ETIMEDOUT; 13776397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 13786397b7f5SChaotian Jing data->error = -EILSEQ; 137920848903SChaotian Jing 13802066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 138120848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 13822066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 138320848903SChaotian Jing (int)data->error, data->bytes_xfered); 138420848903SChaotian Jing } 138520848903SChaotian Jing 138620848903SChaotian Jing msdc_data_xfer_next(host, mrq, data); 138720848903SChaotian Jing done = true; 138820848903SChaotian Jing } 138920848903SChaotian Jing return done; 139020848903SChaotian Jing } 139120848903SChaotian Jing 139220848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 139320848903SChaotian Jing { 139420848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 139520848903SChaotian Jing 139620848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 139720848903SChaotian Jing 139820848903SChaotian Jing switch (width) { 139920848903SChaotian Jing default: 140020848903SChaotian Jing case MMC_BUS_WIDTH_1: 140120848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 140220848903SChaotian Jing break; 140320848903SChaotian Jing case MMC_BUS_WIDTH_4: 140420848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 140520848903SChaotian Jing break; 140620848903SChaotian Jing case MMC_BUS_WIDTH_8: 140720848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 140820848903SChaotian Jing break; 140920848903SChaotian Jing } 141020848903SChaotian Jing 141120848903SChaotian Jing writel(val, host->base + SDC_CFG); 141220848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 141320848903SChaotian Jing } 141420848903SChaotian Jing 141520848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 141620848903SChaotian Jing { 141720848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14189cbe0fc8SMarek Vasut int ret; 141920848903SChaotian Jing 142020848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1421fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1422fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 142320848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 142420848903SChaotian Jing return -EINVAL; 142520848903SChaotian Jing } 142620848903SChaotian Jing 1427fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 14289cbe0fc8SMarek Vasut if (ret < 0) { 1429fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1430fac49ce5SNicolas Boichat ret, ios->signal_voltage); 14319cbe0fc8SMarek Vasut return ret; 14329cbe0fc8SMarek Vasut } 14339cbe0fc8SMarek Vasut 143420848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 143520848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 143620848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 143720848903SChaotian Jing else 143820848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 143920848903SChaotian Jing } 14409cbe0fc8SMarek Vasut return 0; 144120848903SChaotian Jing } 144220848903SChaotian Jing 144320848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 144420848903SChaotian Jing { 144520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 144620848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 144720848903SChaotian Jing 14483bc702edSyong mao /* only check if data0 is low */ 14493bc702edSyong mao return !(status & BIT(16)); 145020848903SChaotian Jing } 145120848903SChaotian Jing 145220848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 145320848903SChaotian Jing { 145420848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 145520848903SChaotian Jing req_timeout.work); 145620848903SChaotian Jing 145720848903SChaotian Jing /* simulate HW timeout status */ 145820848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 145920848903SChaotian Jing if (host->mrq) { 146020848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 146120848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 146220848903SChaotian Jing if (host->cmd) { 146320848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 146420848903SChaotian Jing __func__, host->cmd->opcode); 146520848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 146620848903SChaotian Jing host->cmd); 146720848903SChaotian Jing } else if (host->data) { 146820848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 146920848903SChaotian Jing __func__, host->mrq->cmd->opcode, 147020848903SChaotian Jing host->data->blocks); 147120848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 147220848903SChaotian Jing host->data); 147320848903SChaotian Jing } 147420848903SChaotian Jing } 147520848903SChaotian Jing } 147620848903SChaotian Jing 14778a5df8acSjjian zhou static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 14788a5df8acSjjian zhou { 14798a5df8acSjjian zhou if (enb) { 14808a5df8acSjjian zhou sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 14818a5df8acSjjian zhou sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 14829e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 14839e2582e5Syong mao msdc_recheck_sdio_irq(host); 14848a5df8acSjjian zhou } else { 14858a5df8acSjjian zhou sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 14868a5df8acSjjian zhou sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 14878a5df8acSjjian zhou } 14888a5df8acSjjian zhou } 14898a5df8acSjjian zhou 14908a5df8acSjjian zhou static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 14915215b2e9Sjjian zhou { 14925215b2e9Sjjian zhou unsigned long flags; 14935215b2e9Sjjian zhou struct msdc_host *host = mmc_priv(mmc); 14945215b2e9Sjjian zhou 14955215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 14968a5df8acSjjian zhou __msdc_enable_sdio_irq(host, enb); 14975215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 14985215b2e9Sjjian zhou 14995215b2e9Sjjian zhou if (enb) 15005215b2e9Sjjian zhou pm_runtime_get_noresume(host->dev); 15015215b2e9Sjjian zhou else 15025215b2e9Sjjian zhou pm_runtime_put_noidle(host->dev); 15035215b2e9Sjjian zhou } 15045215b2e9Sjjian zhou 150588bd652bSChun-Hung Wu static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 150688bd652bSChun-Hung Wu { 15070caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 150888bd652bSChun-Hung Wu int cmd_err = 0, dat_err = 0; 150988bd652bSChun-Hung Wu 151088bd652bSChun-Hung Wu if (intsts & MSDC_INT_RSPCRCERR) { 151188bd652bSChun-Hung Wu cmd_err = -EILSEQ; 151288bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD CRC ERR", __func__); 151388bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_CMDTMO) { 151488bd652bSChun-Hung Wu cmd_err = -ETIMEDOUT; 151588bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 151688bd652bSChun-Hung Wu } 151788bd652bSChun-Hung Wu 151888bd652bSChun-Hung Wu if (intsts & MSDC_INT_DATCRCERR) { 151988bd652bSChun-Hung Wu dat_err = -EILSEQ; 152088bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA CRC ERR", __func__); 152188bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_DATTMO) { 152288bd652bSChun-Hung Wu dat_err = -ETIMEDOUT; 152388bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 152488bd652bSChun-Hung Wu } 152588bd652bSChun-Hung Wu 152688bd652bSChun-Hung Wu if (cmd_err || dat_err) { 152788bd652bSChun-Hung Wu dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 152888bd652bSChun-Hung Wu cmd_err, dat_err, intsts); 152988bd652bSChun-Hung Wu } 153088bd652bSChun-Hung Wu 15310caf60c4SAmey Narkhede return cqhci_irq(mmc, 0, cmd_err, dat_err); 153288bd652bSChun-Hung Wu } 153388bd652bSChun-Hung Wu 153420848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 153520848903SChaotian Jing { 153620848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 15370caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 153820848903SChaotian Jing 153920848903SChaotian Jing while (true) { 154020848903SChaotian Jing unsigned long flags; 154120848903SChaotian Jing struct mmc_request *mrq; 154220848903SChaotian Jing struct mmc_command *cmd; 154320848903SChaotian Jing struct mmc_data *data; 154420848903SChaotian Jing u32 events, event_mask; 154520848903SChaotian Jing 154620848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 154720848903SChaotian Jing events = readl(host->base + MSDC_INT); 154820848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 15498a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 15508a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 0); 155120848903SChaotian Jing /* clear interrupts */ 155220848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 155320848903SChaotian Jing 155420848903SChaotian Jing mrq = host->mrq; 155520848903SChaotian Jing cmd = host->cmd; 155620848903SChaotian Jing data = host->data; 155720848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 155820848903SChaotian Jing 15598a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 15600caf60c4SAmey Narkhede sdio_signal_irq(mmc); 15615215b2e9Sjjian zhou 1562d087bde5SNeilBrown if ((events & event_mask) & MSDC_INT_CDSC) { 1563d087bde5SNeilBrown if (host->internal_cd) 15640caf60c4SAmey Narkhede mmc_detect_change(mmc, msecs_to_jiffies(20)); 1565d087bde5SNeilBrown events &= ~MSDC_INT_CDSC; 1566d087bde5SNeilBrown } 1567d087bde5SNeilBrown 15685215b2e9Sjjian zhou if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 156920848903SChaotian Jing break; 157020848903SChaotian Jing 15710caf60c4SAmey Narkhede if ((mmc->caps2 & MMC_CAP2_CQE) && 157288bd652bSChun-Hung Wu (events & MSDC_INT_CMDQ)) { 157388bd652bSChun-Hung Wu msdc_cmdq_irq(host, events); 157488bd652bSChun-Hung Wu /* clear interrupts */ 157588bd652bSChun-Hung Wu writel(events, host->base + MSDC_INT); 157688bd652bSChun-Hung Wu return IRQ_HANDLED; 157788bd652bSChun-Hung Wu } 157888bd652bSChun-Hung Wu 157920848903SChaotian Jing if (!mrq) { 158020848903SChaotian Jing dev_err(host->dev, 158120848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 158220848903SChaotian Jing __func__, events, event_mask); 158320848903SChaotian Jing WARN_ON(1); 158420848903SChaotian Jing break; 158520848903SChaotian Jing } 158620848903SChaotian Jing 158720848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 158820848903SChaotian Jing 158920848903SChaotian Jing if (cmd) 159020848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 159120848903SChaotian Jing else if (data) 159220848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 159320848903SChaotian Jing } 159420848903SChaotian Jing 159520848903SChaotian Jing return IRQ_HANDLED; 159620848903SChaotian Jing } 159720848903SChaotian Jing 159820848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 159920848903SChaotian Jing { 160020848903SChaotian Jing u32 val; 160139add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 160220848903SChaotian Jing 1603855d388dSWenbin Mei if (host->reset) { 1604855d388dSWenbin Mei reset_control_assert(host->reset); 1605855d388dSWenbin Mei usleep_range(10, 50); 1606855d388dSWenbin Mei reset_control_deassert(host->reset); 1607855d388dSWenbin Mei } 1608855d388dSWenbin Mei 160920848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 161020848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 161120848903SChaotian Jing 161220848903SChaotian Jing /* Reset */ 161320848903SChaotian Jing msdc_reset_hw(host); 161420848903SChaotian Jing 161520848903SChaotian Jing /* Disable and clear all interrupts */ 161620848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 161720848903SChaotian Jing val = readl(host->base + MSDC_INT); 161820848903SChaotian Jing writel(val, host->base + MSDC_INT); 161920848903SChaotian Jing 1620d087bde5SNeilBrown /* Configure card detection */ 1621d087bde5SNeilBrown if (host->internal_cd) { 1622d087bde5SNeilBrown sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1623d087bde5SNeilBrown DEFAULT_DEBOUNCE); 1624d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1625d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1626d087bde5SNeilBrown sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1627d087bde5SNeilBrown } else { 1628d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1629d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1630d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1631d087bde5SNeilBrown } 1632d087bde5SNeilBrown 1633a2e6d1f6SChaotian Jing if (host->top_base) { 1634a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CONTROL); 1635a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CMD); 1636a2e6d1f6SChaotian Jing } else { 163739add252SChaotian Jing writel(0, host->base + tune_reg); 1638a2e6d1f6SChaotian Jing } 163920848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 16406397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 16416397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 164220848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 16432fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 16446397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1645d9dcbfc8SChaotian Jing 1646d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1647d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1648d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1649d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1650d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1651d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1652d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1653d9dcbfc8SChaotian Jing } 1654d9dcbfc8SChaotian Jing 1655acde28c4SChaotian Jing if (host->dev_comp->busy_check) 1656acde28c4SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1657d9dcbfc8SChaotian Jing 16582fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 16592fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16602fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1661d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1662a2e6d1f6SChaotian Jing if (host->top_base) 1663a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1664a2e6d1f6SChaotian Jing SDC_RX_ENH_EN); 1665a2e6d1f6SChaotian Jing else 1666d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1667d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1668d9dcbfc8SChaotian Jing } else { 16692fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16702fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 16712fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16722fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1673d9dcbfc8SChaotian Jing } 16742fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 16752fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 16762fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 16772fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 16782fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 16792fea5819SChaotian Jing } 16802fea5819SChaotian Jing 16812a9bde19SChaotian Jing if (host->dev_comp->support_64g) 16822a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 16832a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 16842fea5819SChaotian Jing if (host->dev_comp->data_tune) { 1685a2e6d1f6SChaotian Jing if (host->top_base) { 1686a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1687a2e6d1f6SChaotian Jing PAD_DAT_RD_RXDLY_SEL); 1688a2e6d1f6SChaotian Jing sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1689a2e6d1f6SChaotian Jing DATA_K_VALUE_SEL); 1690a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1691a2e6d1f6SChaotian Jing PAD_CMD_RD_RXDLY_SEL); 1692a2e6d1f6SChaotian Jing } else { 16932fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 1694a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RD_SEL | 1695a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_CMD_SEL); 1696a2e6d1f6SChaotian Jing } 16972fea5819SChaotian Jing } else { 16982fea5819SChaotian Jing /* choose clock tune */ 1699a2e6d1f6SChaotian Jing if (host->top_base) 1700a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1701a2e6d1f6SChaotian Jing PAD_RXDLY_SEL); 1702a2e6d1f6SChaotian Jing else 1703a2e6d1f6SChaotian Jing sdr_set_bits(host->base + tune_reg, 1704a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RXDLYSEL); 17052fea5819SChaotian Jing } 17066397b7f5SChaotian Jing 170720848903SChaotian Jing /* Configure to enable SDIO mode. 170820848903SChaotian Jing * it's must otherwise sdio cmd5 failed 170920848903SChaotian Jing */ 171020848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 171120848903SChaotian Jing 17125215b2e9Sjjian zhou /* Config SDIO device detect interrupt function */ 171320848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 171426c71a13Syong mao sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 171520848903SChaotian Jing 171620848903SChaotian Jing /* Configure to default data timeout */ 171720848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 171820848903SChaotian Jing 171986beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 17202fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1721a2e6d1f6SChaotian Jing if (host->top_base) { 1722a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_control = 1723a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1724a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_cmd = 1725a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1726a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = 1727a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1728a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = 1729a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1730a2e6d1f6SChaotian Jing } else { 1731a2e6d1f6SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 17322fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1733a2e6d1f6SChaotian Jing } 173420848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 173520848903SChaotian Jing } 173620848903SChaotian Jing 173720848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 173820848903SChaotian Jing { 173920848903SChaotian Jing u32 val; 1740d087bde5SNeilBrown 1741d087bde5SNeilBrown if (host->internal_cd) { 1742d087bde5SNeilBrown /* Disabled card-detect */ 1743d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1744d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1745d087bde5SNeilBrown } 1746d087bde5SNeilBrown 174720848903SChaotian Jing /* Disable and clear all interrupts */ 174820848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 174920848903SChaotian Jing 175020848903SChaotian Jing val = readl(host->base + MSDC_INT); 175120848903SChaotian Jing writel(val, host->base + MSDC_INT); 175220848903SChaotian Jing } 175320848903SChaotian Jing 175420848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 175520848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 175620848903SChaotian Jing { 175720848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 175820848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 17592a9bde19SChaotian Jing dma_addr_t dma_addr; 176020848903SChaotian Jing int i; 176120848903SChaotian Jing 176262b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 176320848903SChaotian Jing 17642a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 176520848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 176662b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 176762b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 176862b0d27aSChaotian Jing */ 17692a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 17702a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17712a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 17722a9bde19SChaotian Jing 17732a9bde19SChaotian Jing dma_addr = dma->bd_addr; 17742a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 17752a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17762a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 17772a9bde19SChaotian Jing 177820848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 17792a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 17802a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 17812a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 17822a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17832a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 17842a9bde19SChaotian Jing } 178520848903SChaotian Jing } 178620848903SChaotian Jing 178720848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 178820848903SChaotian Jing { 178920848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 179020848903SChaotian Jing int ret; 179120848903SChaotian Jing 179220848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 179320848903SChaotian Jing 179420848903SChaotian Jing /* Suspend/Resume will do power off/on */ 179520848903SChaotian Jing switch (ios->power_mode) { 179620848903SChaotian Jing case MMC_POWER_UP: 179720848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 17986397b7f5SChaotian Jing msdc_init_hw(host); 179920848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 180020848903SChaotian Jing ios->vdd); 180120848903SChaotian Jing if (ret) { 180220848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1803567979fbSUlf Hansson return; 180420848903SChaotian Jing } 180520848903SChaotian Jing } 180620848903SChaotian Jing break; 180720848903SChaotian Jing case MMC_POWER_ON: 180820848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 180920848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 181020848903SChaotian Jing if (ret) 181120848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 181220848903SChaotian Jing else 181320848903SChaotian Jing host->vqmmc_enabled = true; 181420848903SChaotian Jing } 181520848903SChaotian Jing break; 181620848903SChaotian Jing case MMC_POWER_OFF: 181720848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 181820848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 181920848903SChaotian Jing 182020848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 182120848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 182220848903SChaotian Jing host->vqmmc_enabled = false; 182320848903SChaotian Jing } 182420848903SChaotian Jing break; 182520848903SChaotian Jing default: 182620848903SChaotian Jing break; 182720848903SChaotian Jing } 182820848903SChaotian Jing 18296e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 18306e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 183120848903SChaotian Jing } 183220848903SChaotian Jing 18336397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 18346397b7f5SChaotian Jing { 18356397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 18366397b7f5SChaotian Jing return delay & (1 << bit); 18376397b7f5SChaotian Jing } 18386397b7f5SChaotian Jing 18396397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 18406397b7f5SChaotian Jing { 18416397b7f5SChaotian Jing int i; 18426397b7f5SChaotian Jing 18436397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 18446397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 18456397b7f5SChaotian Jing return i; 18466397b7f5SChaotian Jing } 18476397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 18486397b7f5SChaotian Jing } 18496397b7f5SChaotian Jing 18506397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 18516397b7f5SChaotian Jing { 18526397b7f5SChaotian Jing int start = 0, len = 0; 18536397b7f5SChaotian Jing int start_final = 0, len_final = 0; 18546397b7f5SChaotian Jing u8 final_phase = 0xff; 185562d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 18566397b7f5SChaotian Jing 18576397b7f5SChaotian Jing if (delay == 0) { 18586397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 18596397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 18606397b7f5SChaotian Jing return delay_phase; 18616397b7f5SChaotian Jing } 18626397b7f5SChaotian Jing 18636397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 18646397b7f5SChaotian Jing len = get_delay_len(delay, start); 18656397b7f5SChaotian Jing if (len_final < len) { 18666397b7f5SChaotian Jing start_final = start; 18676397b7f5SChaotian Jing len_final = len; 18686397b7f5SChaotian Jing } 18696397b7f5SChaotian Jing start += len ? len : 1; 18701ede5cb8Syong mao if (len >= 12 && start_final < 4) 18716397b7f5SChaotian Jing break; 18726397b7f5SChaotian Jing } 18736397b7f5SChaotian Jing 18746397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 18756397b7f5SChaotian Jing if (start_final == 0) 18766397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 18776397b7f5SChaotian Jing else 18786397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 18796397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 18806397b7f5SChaotian Jing delay, len_final, final_phase); 18816397b7f5SChaotian Jing 18826397b7f5SChaotian Jing delay_phase.maxlen = len_final; 18836397b7f5SChaotian Jing delay_phase.start = start_final; 18846397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 18856397b7f5SChaotian Jing return delay_phase; 18866397b7f5SChaotian Jing } 18876397b7f5SChaotian Jing 1888fd82cc30SChaotian Jing static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1889fd82cc30SChaotian Jing { 1890fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1891fd82cc30SChaotian Jing 1892fd82cc30SChaotian Jing if (host->top_base) 1893fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1894fd82cc30SChaotian Jing value); 1895fd82cc30SChaotian Jing else 1896fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1897fd82cc30SChaotian Jing value); 1898fd82cc30SChaotian Jing } 1899fd82cc30SChaotian Jing 1900fd82cc30SChaotian Jing static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1901fd82cc30SChaotian Jing { 1902fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1903fd82cc30SChaotian Jing 1904fd82cc30SChaotian Jing if (host->top_base) 1905fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1906fd82cc30SChaotian Jing PAD_DAT_RD_RXDLY, value); 1907fd82cc30SChaotian Jing else 1908fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1909fd82cc30SChaotian Jing value); 1910fd82cc30SChaotian Jing } 1911fd82cc30SChaotian Jing 19126397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 19136397b7f5SChaotian Jing { 19146397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 19156397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1916ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 19171ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 19186397b7f5SChaotian Jing u8 final_delay, final_maxlen; 19191ede5cb8Syong mao u32 internal_delay = 0; 192039add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 19216397b7f5SChaotian Jing int cmd_err; 19221ede5cb8Syong mao int i, j; 19231ede5cb8Syong mao 19241ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 19251ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 192639add252SChaotian Jing sdr_set_field(host->base + tune_reg, 19271ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 19281ede5cb8Syong mao host->hs200_cmd_int_delay); 19296397b7f5SChaotian Jing 19306397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19316397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1932fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 19331ede5cb8Syong mao /* 19341ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19351ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19361ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19371ede5cb8Syong mao */ 19381ede5cb8Syong mao for (j = 0; j < 3; j++) { 19396397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 19401ede5cb8Syong mao if (!cmd_err) { 19416397b7f5SChaotian Jing rise_delay |= (1 << i); 19421ede5cb8Syong mao } else { 19431ede5cb8Syong mao rise_delay &= ~(1 << i); 19441ede5cb8Syong mao break; 19451ede5cb8Syong mao } 19461ede5cb8Syong mao } 19476397b7f5SChaotian Jing } 1948ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1949ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 19506b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 19516b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1952ae9c657eSChaotian Jing goto skip_fall; 19536397b7f5SChaotian Jing 19546397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19556397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 1956fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 19571ede5cb8Syong mao /* 19581ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19591ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19601ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19611ede5cb8Syong mao */ 19621ede5cb8Syong mao for (j = 0; j < 3; j++) { 19636397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 19641ede5cb8Syong mao if (!cmd_err) { 19656397b7f5SChaotian Jing fall_delay |= (1 << i); 19661ede5cb8Syong mao } else { 19671ede5cb8Syong mao fall_delay &= ~(1 << i); 19681ede5cb8Syong mao break; 19691ede5cb8Syong mao } 19701ede5cb8Syong mao } 19716397b7f5SChaotian Jing } 19726397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 19736397b7f5SChaotian Jing 1974ae9c657eSChaotian Jing skip_fall: 19756397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 19761ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 19771ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 19786397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 19796397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19806397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 19816397b7f5SChaotian Jing } else { 19826397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19836397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 19846397b7f5SChaotian Jing } 1985fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 1986fd82cc30SChaotian Jing 19872fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 19881ede5cb8Syong mao goto skip_internal; 19896397b7f5SChaotian Jing 19901ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 199139add252SChaotian Jing sdr_set_field(host->base + tune_reg, 19921ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 19931ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 19941ede5cb8Syong mao if (!cmd_err) 19951ede5cb8Syong mao internal_delay |= (1 << i); 19961ede5cb8Syong mao } 19971ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 19981ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 199939add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 20001ede5cb8Syong mao internal_delay_phase.final_phase); 20011ede5cb8Syong mao skip_internal: 20021ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20031ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 20041ede5cb8Syong mao } 20051ede5cb8Syong mao 20061ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 20071ede5cb8Syong mao { 20081ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 20091ede5cb8Syong mao u32 cmd_delay = 0; 20101ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 20111ede5cb8Syong mao u8 final_delay; 20121ede5cb8Syong mao int cmd_err; 20131ede5cb8Syong mao int i, j; 20141ede5cb8Syong mao 20151ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 20161ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 20178f34e5bdSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 20181ede5cb8Syong mao 20191ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 20201ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 20211ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 20221ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 20231ede5cb8Syong mao host->hs200_cmd_int_delay); 20241ede5cb8Syong mao 20251ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 20261ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20271ede5cb8Syong mao else 20281ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20291ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 20301ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 20311ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 20321ede5cb8Syong mao /* 20331ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20341ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20351ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20361ede5cb8Syong mao */ 20371ede5cb8Syong mao for (j = 0; j < 3; j++) { 20381ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20391ede5cb8Syong mao if (!cmd_err) { 20401ede5cb8Syong mao cmd_delay |= (1 << i); 20411ede5cb8Syong mao } else { 20421ede5cb8Syong mao cmd_delay &= ~(1 << i); 20431ede5cb8Syong mao break; 20441ede5cb8Syong mao } 20451ede5cb8Syong mao } 20461ede5cb8Syong mao } 20471ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 20481ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 20491ede5cb8Syong mao final_cmd_delay.final_phase); 20501ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 20511ede5cb8Syong mao 20521ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20536397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 20546397b7f5SChaotian Jing } 20556397b7f5SChaotian Jing 20566397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 20576397b7f5SChaotian Jing { 20586397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 20596397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 2060ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 20616397b7f5SChaotian Jing u8 final_delay, final_maxlen; 20626397b7f5SChaotian Jing int i, ret; 20636397b7f5SChaotian Jing 2064d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2065d17bb71cSChaotian Jing host->latch_ck); 20666397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 20676397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 20686397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2069fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 20706397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 20716397b7f5SChaotian Jing if (!ret) 20726397b7f5SChaotian Jing rise_delay |= (1 << i); 20736397b7f5SChaotian Jing } 2074ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2075ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 20761ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 2077ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2078ae9c657eSChaotian Jing goto skip_fall; 20796397b7f5SChaotian Jing 20806397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 20816397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 20826397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2083fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 20846397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 20856397b7f5SChaotian Jing if (!ret) 20866397b7f5SChaotian Jing fall_delay |= (1 << i); 20876397b7f5SChaotian Jing } 20886397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 20896397b7f5SChaotian Jing 2090ae9c657eSChaotian Jing skip_fall: 20916397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 20926397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 20936397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 20946397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 20956397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 20966397b7f5SChaotian Jing } else { 20976397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 20986397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 20996397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 21006397b7f5SChaotian Jing } 2101fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 21026397b7f5SChaotian Jing 21031ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 21046397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 21056397b7f5SChaotian Jing } 21066397b7f5SChaotian Jing 210786601d0eSChaotian Jing /* 210886601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 210986601d0eSChaotian Jing * together, which can save the tuning time. 211086601d0eSChaotian Jing */ 211186601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 211286601d0eSChaotian Jing { 211386601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 211486601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 211586601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 211686601d0eSChaotian Jing u8 final_delay, final_maxlen; 211786601d0eSChaotian Jing int i, ret; 211886601d0eSChaotian Jing 211986601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 212086601d0eSChaotian Jing host->latch_ck); 212186601d0eSChaotian Jing 212286601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 212386601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 212486601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 212586601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2126fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2127fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 212886601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 212986601d0eSChaotian Jing if (!ret) 213086601d0eSChaotian Jing rise_delay |= (1 << i); 213186601d0eSChaotian Jing } 213286601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 213386601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 213486601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 213586601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 213686601d0eSChaotian Jing goto skip_fall; 213786601d0eSChaotian Jing 213886601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 213986601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 214086601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 214186601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2142fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2143fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 214486601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 214586601d0eSChaotian Jing if (!ret) 214686601d0eSChaotian Jing fall_delay |= (1 << i); 214786601d0eSChaotian Jing } 214886601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 214986601d0eSChaotian Jing 215086601d0eSChaotian Jing skip_fall: 215186601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 215286601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 215386601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 215486601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 215586601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 215686601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 215786601d0eSChaotian Jing } else { 215886601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 215986601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 216086601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 216186601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 216286601d0eSChaotian Jing } 216386601d0eSChaotian Jing 2164fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2165fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 2166a2e6d1f6SChaotian Jing 216786601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 216886601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 216986601d0eSChaotian Jing } 217086601d0eSChaotian Jing 21716397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 21726397b7f5SChaotian Jing { 21736397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 21746397b7f5SChaotian Jing int ret; 217539add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 21766397b7f5SChaotian Jing 217786601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 217886601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 217986601d0eSChaotian Jing if (host->hs400_mode) { 218086601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 218186601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2182fd82cc30SChaotian Jing msdc_set_data_delay(host, 0); 218386601d0eSChaotian Jing } 218486601d0eSChaotian Jing goto tune_done; 218586601d0eSChaotian Jing } 21867f3d5852SChaotian Jing if (host->hs400_mode && 21877f3d5852SChaotian Jing host->dev_comp->hs400_tune) 21881ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 21891ede5cb8Syong mao else 21906397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 21916397b7f5SChaotian Jing if (ret == -EIO) { 21926397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 2193567979fbSUlf Hansson return ret; 21946397b7f5SChaotian Jing } 21955462ff39SChaotian Jing if (host->hs400_mode == false) { 21966397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 21976397b7f5SChaotian Jing if (ret == -EIO) 21986397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 21995462ff39SChaotian Jing } 22006397b7f5SChaotian Jing 220186601d0eSChaotian Jing tune_done: 220286beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 220339add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 22041ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2205a2e6d1f6SChaotian Jing if (host->top_base) { 2206a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = readl(host->top_base + 2207a2e6d1f6SChaotian Jing EMMC_TOP_CONTROL); 2208a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2209a2e6d1f6SChaotian Jing EMMC_TOP_CMD); 2210a2e6d1f6SChaotian Jing } 22116397b7f5SChaotian Jing return ret; 22126397b7f5SChaotian Jing } 22136397b7f5SChaotian Jing 22146397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 22156397b7f5SChaotian Jing { 22166397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22175462ff39SChaotian Jing host->hs400_mode = true; 22186397b7f5SChaotian Jing 2219a2e6d1f6SChaotian Jing if (host->top_base) 2220a2e6d1f6SChaotian Jing writel(host->hs400_ds_delay, 2221a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2222a2e6d1f6SChaotian Jing else 22236397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 22242fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 22252fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2226c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 2227c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2228c8609b22SChaotian Jing 22296397b7f5SChaotian Jing return 0; 22306397b7f5SChaotian Jing } 22316397b7f5SChaotian Jing 2232c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 2233c9b5061eSChaotian Jing { 2234c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2235c9b5061eSChaotian Jing 2236c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 2237c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 2238c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 2239c9b5061eSChaotian Jing } 2240c9b5061eSChaotian Jing 22415215b2e9Sjjian zhou static void msdc_ack_sdio_irq(struct mmc_host *mmc) 22425215b2e9Sjjian zhou { 22438a5df8acSjjian zhou unsigned long flags; 22448a5df8acSjjian zhou struct msdc_host *host = mmc_priv(mmc); 22458a5df8acSjjian zhou 22468a5df8acSjjian zhou spin_lock_irqsave(&host->lock, flags); 22478a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 1); 22488a5df8acSjjian zhou spin_unlock_irqrestore(&host->lock, flags); 22495215b2e9Sjjian zhou } 22505215b2e9Sjjian zhou 2251d087bde5SNeilBrown static int msdc_get_cd(struct mmc_host *mmc) 2252d087bde5SNeilBrown { 2253d087bde5SNeilBrown struct msdc_host *host = mmc_priv(mmc); 2254d087bde5SNeilBrown int val; 2255d087bde5SNeilBrown 2256d087bde5SNeilBrown if (mmc->caps & MMC_CAP_NONREMOVABLE) 2257d087bde5SNeilBrown return 1; 2258d087bde5SNeilBrown 2259d087bde5SNeilBrown if (!host->internal_cd) 2260d087bde5SNeilBrown return mmc_gpio_get_cd(mmc); 2261d087bde5SNeilBrown 2262d087bde5SNeilBrown val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2263d087bde5SNeilBrown if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2264d087bde5SNeilBrown return !!val; 2265d087bde5SNeilBrown else 2266d087bde5SNeilBrown return !val; 2267d087bde5SNeilBrown } 2268d087bde5SNeilBrown 226988bd652bSChun-Hung Wu static void msdc_cqe_enable(struct mmc_host *mmc) 227088bd652bSChun-Hung Wu { 227188bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 227288bd652bSChun-Hung Wu 227388bd652bSChun-Hung Wu /* enable cmdq irq */ 227488bd652bSChun-Hung Wu writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 227588bd652bSChun-Hung Wu /* enable busy check */ 227688bd652bSChun-Hung Wu sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 227788bd652bSChun-Hung Wu /* default write data / busy timeout 20s */ 227888bd652bSChun-Hung Wu msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 227988bd652bSChun-Hung Wu /* default read data timeout 1s */ 228088bd652bSChun-Hung Wu msdc_set_timeout(host, 1000000000ULL, 0); 228188bd652bSChun-Hung Wu } 228288bd652bSChun-Hung Wu 22837f4bc2e8SWei Yongjun static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 228488bd652bSChun-Hung Wu { 228588bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 228688bd652bSChun-Hung Wu 228788bd652bSChun-Hung Wu /* disable cmdq irq */ 228888bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 228988bd652bSChun-Hung Wu /* disable busy check */ 229088bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 229188bd652bSChun-Hung Wu 229288bd652bSChun-Hung Wu if (recovery) { 229388bd652bSChun-Hung Wu sdr_set_field(host->base + MSDC_DMA_CTRL, 229488bd652bSChun-Hung Wu MSDC_DMA_CTRL_STOP, 1); 229588bd652bSChun-Hung Wu msdc_reset_hw(host); 229688bd652bSChun-Hung Wu } 229788bd652bSChun-Hung Wu } 229888bd652bSChun-Hung Wu 2299e282f204SChun-Hung Wu static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2300e282f204SChun-Hung Wu { 2301e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2302e282f204SChun-Hung Wu u32 reg; 2303e282f204SChun-Hung Wu 2304e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2305e282f204SChun-Hung Wu reg |= CQHCI_ENABLE; 2306e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2307e282f204SChun-Hung Wu } 2308e282f204SChun-Hung Wu 2309e282f204SChun-Hung Wu static void msdc_cqe_post_disable(struct mmc_host *mmc) 2310e282f204SChun-Hung Wu { 2311e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2312e282f204SChun-Hung Wu u32 reg; 2313e282f204SChun-Hung Wu 2314e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2315e282f204SChun-Hung Wu reg &= ~CQHCI_ENABLE; 2316e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2317e282f204SChun-Hung Wu } 2318e282f204SChun-Hung Wu 2319be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 232020848903SChaotian Jing .post_req = msdc_post_req, 232120848903SChaotian Jing .pre_req = msdc_pre_req, 232220848903SChaotian Jing .request = msdc_ops_request, 232320848903SChaotian Jing .set_ios = msdc_ops_set_ios, 23248d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 2325d087bde5SNeilBrown .get_cd = msdc_get_cd, 23265215b2e9Sjjian zhou .enable_sdio_irq = msdc_enable_sdio_irq, 23275215b2e9Sjjian zhou .ack_sdio_irq = msdc_ack_sdio_irq, 232820848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 232920848903SChaotian Jing .card_busy = msdc_card_busy, 23306397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 23316397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2332c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 233320848903SChaotian Jing }; 233420848903SChaotian Jing 233588bd652bSChun-Hung Wu static const struct cqhci_host_ops msdc_cmdq_ops = { 233688bd652bSChun-Hung Wu .enable = msdc_cqe_enable, 233788bd652bSChun-Hung Wu .disable = msdc_cqe_disable, 2338e282f204SChun-Hung Wu .pre_enable = msdc_cqe_pre_enable, 2339e282f204SChun-Hung Wu .post_disable = msdc_cqe_post_disable, 234088bd652bSChun-Hung Wu }; 234188bd652bSChun-Hung Wu 23421ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 23431ede5cb8Syong mao struct msdc_host *host) 23441ede5cb8Syong mao { 2345d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2346d17bb71cSChaotian Jing &host->latch_ck); 2347d17bb71cSChaotian Jing 23481ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 23491ede5cb8Syong mao &host->hs400_ds_delay); 23501ede5cb8Syong mao 23511ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 23521ede5cb8Syong mao &host->hs200_cmd_int_delay); 23531ede5cb8Syong mao 23541ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 23551ede5cb8Syong mao &host->hs400_cmd_int_delay); 23561ede5cb8Syong mao 23571ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 23581ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 23591ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 23601ede5cb8Syong mao else 23611ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 236288bd652bSChun-Hung Wu 236388bd652bSChun-Hung Wu if (of_property_read_bool(pdev->dev.of_node, 236488bd652bSChun-Hung Wu "supports-cqe")) 236588bd652bSChun-Hung Wu host->cqhci = true; 236688bd652bSChun-Hung Wu else 236788bd652bSChun-Hung Wu host->cqhci = false; 23681ede5cb8Syong mao } 23691ede5cb8Syong mao 237020848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 237120848903SChaotian Jing { 237220848903SChaotian Jing struct mmc_host *mmc; 237320848903SChaotian Jing struct msdc_host *host; 237420848903SChaotian Jing struct resource *res; 237520848903SChaotian Jing int ret; 237620848903SChaotian Jing 237720848903SChaotian Jing if (!pdev->dev.of_node) { 237820848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 237920848903SChaotian Jing return -EINVAL; 238020848903SChaotian Jing } 2381762d491aSChaotian Jing 238220848903SChaotian Jing /* Allocate MMC host for this device */ 238320848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 238420848903SChaotian Jing if (!mmc) 238520848903SChaotian Jing return -ENOMEM; 238620848903SChaotian Jing 238720848903SChaotian Jing host = mmc_priv(mmc); 238820848903SChaotian Jing ret = mmc_of_parse(mmc); 238920848903SChaotian Jing if (ret) 239020848903SChaotian Jing goto host_free; 239120848903SChaotian Jing 2392bc068d38SYangtao Li host->base = devm_platform_ioremap_resource(pdev, 0); 239320848903SChaotian Jing if (IS_ERR(host->base)) { 239420848903SChaotian Jing ret = PTR_ERR(host->base); 239520848903SChaotian Jing goto host_free; 239620848903SChaotian Jing } 239720848903SChaotian Jing 2398a2e6d1f6SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2399b65be635SFabien Parent if (res) { 2400a2e6d1f6SChaotian Jing host->top_base = devm_ioremap_resource(&pdev->dev, res); 2401a2e6d1f6SChaotian Jing if (IS_ERR(host->top_base)) 2402a2e6d1f6SChaotian Jing host->top_base = NULL; 2403b65be635SFabien Parent } 2404a2e6d1f6SChaotian Jing 240520848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 24062f98ef63SWolfram Sang if (ret) 240720848903SChaotian Jing goto host_free; 240820848903SChaotian Jing 240920848903SChaotian Jing host->src_clk = devm_clk_get(&pdev->dev, "source"); 241020848903SChaotian Jing if (IS_ERR(host->src_clk)) { 241120848903SChaotian Jing ret = PTR_ERR(host->src_clk); 241220848903SChaotian Jing goto host_free; 241320848903SChaotian Jing } 241420848903SChaotian Jing 241520848903SChaotian Jing host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 241620848903SChaotian Jing if (IS_ERR(host->h_clk)) { 241720848903SChaotian Jing ret = PTR_ERR(host->h_clk); 241820848903SChaotian Jing goto host_free; 241920848903SChaotian Jing } 242020848903SChaotian Jing 2421258bac4aSChaotian Jing host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2422258bac4aSChaotian Jing if (IS_ERR(host->bus_clk)) 2423258bac4aSChaotian Jing host->bus_clk = NULL; 24243c1a8844SChaotian Jing /*source clock control gate is optional clock*/ 24253c1a8844SChaotian Jing host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 24263c1a8844SChaotian Jing if (IS_ERR(host->src_clk_cg)) 24273c1a8844SChaotian Jing host->src_clk_cg = NULL; 24283c1a8844SChaotian Jing 2429855d388dSWenbin Mei host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2430855d388dSWenbin Mei "hrst"); 2431855d388dSWenbin Mei if (IS_ERR(host->reset)) 2432855d388dSWenbin Mei return PTR_ERR(host->reset); 2433855d388dSWenbin Mei 243420848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 243520848903SChaotian Jing if (host->irq < 0) { 243620848903SChaotian Jing ret = -EINVAL; 243720848903SChaotian Jing goto host_free; 243820848903SChaotian Jing } 243920848903SChaotian Jing 244020848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 244120848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 244220848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 244320848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 244420848903SChaotian Jing goto host_free; 244520848903SChaotian Jing } 244620848903SChaotian Jing 244720848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 244820848903SChaotian Jing if (IS_ERR(host->pins_default)) { 244920848903SChaotian Jing ret = PTR_ERR(host->pins_default); 245020848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 245120848903SChaotian Jing goto host_free; 245220848903SChaotian Jing } 245320848903SChaotian Jing 245420848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 245520848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 245620848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 245720848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 245820848903SChaotian Jing goto host_free; 245920848903SChaotian Jing } 246020848903SChaotian Jing 24611ede5cb8Syong mao msdc_of_property_parse(pdev, host); 24626397b7f5SChaotian Jing 246320848903SChaotian Jing host->dev = &pdev->dev; 2464909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 246520848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 246620848903SChaotian Jing /* Set host parameters to mmc */ 246720848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2468762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 246940ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2470762d491aSChaotian Jing else 2471762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 247220848903SChaotian Jing 2473d087bde5SNeilBrown if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2474d087bde5SNeilBrown !mmc_can_gpio_cd(mmc) && 2475d087bde5SNeilBrown host->dev_comp->use_internal_cd) { 2476d087bde5SNeilBrown /* 2477d087bde5SNeilBrown * Is removable but no GPIO declared, so 2478d087bde5SNeilBrown * use internal functionality. 2479d087bde5SNeilBrown */ 2480d087bde5SNeilBrown host->internal_cd = true; 2481d087bde5SNeilBrown } 2482d087bde5SNeilBrown 24835215b2e9Sjjian zhou if (mmc->caps & MMC_CAP_SDIO_IRQ) 24845215b2e9Sjjian zhou mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 24855215b2e9Sjjian zhou 24861be64c79SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 248788bd652bSChun-Hung Wu if (host->cqhci) 248888bd652bSChun-Hung Wu mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 248920848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 249020848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 24916ef042bdSChaotian Jing if (host->dev_comp->support_64g) 24926ef042bdSChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 24936ef042bdSChaotian Jing else 249420848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 249520848903SChaotian Jing mmc->max_blk_size = 2048; 249620848903SChaotian Jing mmc->max_req_size = 512 * 1024; 249720848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 24982a9bde19SChaotian Jing if (host->dev_comp->support_64g) 24992a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 25002a9bde19SChaotian Jing else 250120848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 250220848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 250320848903SChaotian Jing 250488bd652bSChun-Hung Wu if (mmc->caps2 & MMC_CAP2_CQE) { 25050caf60c4SAmey Narkhede host->cq_host = devm_kzalloc(mmc->parent, 250688bd652bSChun-Hung Wu sizeof(*host->cq_host), 250788bd652bSChun-Hung Wu GFP_KERNEL); 250888bd652bSChun-Hung Wu if (!host->cq_host) { 250988bd652bSChun-Hung Wu ret = -ENOMEM; 251088bd652bSChun-Hung Wu goto host_free; 251188bd652bSChun-Hung Wu } 251288bd652bSChun-Hung Wu host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 251388bd652bSChun-Hung Wu host->cq_host->mmio = host->base + 0x800; 251488bd652bSChun-Hung Wu host->cq_host->ops = &msdc_cmdq_ops; 251588bd652bSChun-Hung Wu ret = cqhci_init(host->cq_host, mmc, true); 251688bd652bSChun-Hung Wu if (ret) 251788bd652bSChun-Hung Wu goto host_free; 251888bd652bSChun-Hung Wu mmc->max_segs = 128; 251988bd652bSChun-Hung Wu /* cqhci 16bit length */ 252088bd652bSChun-Hung Wu /* 0 size, means 65536 so we don't have to -1 here */ 252188bd652bSChun-Hung Wu mmc->max_seg_size = 64 * 1024; 252288bd652bSChun-Hung Wu } 252388bd652bSChun-Hung Wu 252420848903SChaotian Jing host->timeout_clks = 3 * 1048576; 252520848903SChaotian Jing host->dma.gpd = dma_alloc_coherent(&pdev->dev, 252662b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 252720848903SChaotian Jing &host->dma.gpd_addr, GFP_KERNEL); 252820848903SChaotian Jing host->dma.bd = dma_alloc_coherent(&pdev->dev, 252920848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 253020848903SChaotian Jing &host->dma.bd_addr, GFP_KERNEL); 253120848903SChaotian Jing if (!host->dma.gpd || !host->dma.bd) { 253220848903SChaotian Jing ret = -ENOMEM; 253320848903SChaotian Jing goto release_mem; 253420848903SChaotian Jing } 253520848903SChaotian Jing msdc_init_gpd_bd(host, &host->dma); 253620848903SChaotian Jing INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 253720848903SChaotian Jing spin_lock_init(&host->lock); 253820848903SChaotian Jing 253920848903SChaotian Jing platform_set_drvdata(pdev, mmc); 254020848903SChaotian Jing msdc_ungate_clock(host); 254120848903SChaotian Jing msdc_init_hw(host); 254220848903SChaotian Jing 254320848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 254442edb0d5SNeilBrown IRQF_TRIGGER_NONE, pdev->name, host); 254520848903SChaotian Jing if (ret) 254620848903SChaotian Jing goto release; 254720848903SChaotian Jing 25484b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 25494b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 25504b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 25514b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 255220848903SChaotian Jing ret = mmc_add_host(mmc); 25534b8a43e9SChaotian Jing 255420848903SChaotian Jing if (ret) 25554b8a43e9SChaotian Jing goto end; 255620848903SChaotian Jing 255720848903SChaotian Jing return 0; 25584b8a43e9SChaotian Jing end: 25594b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 256020848903SChaotian Jing release: 256120848903SChaotian Jing platform_set_drvdata(pdev, NULL); 256220848903SChaotian Jing msdc_deinit_hw(host); 256320848903SChaotian Jing msdc_gate_clock(host); 256420848903SChaotian Jing release_mem: 256520848903SChaotian Jing if (host->dma.gpd) 256620848903SChaotian Jing dma_free_coherent(&pdev->dev, 256762b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 256820848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 256920848903SChaotian Jing if (host->dma.bd) 257020848903SChaotian Jing dma_free_coherent(&pdev->dev, 257120848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 257220848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 257320848903SChaotian Jing host_free: 257420848903SChaotian Jing mmc_free_host(mmc); 257520848903SChaotian Jing 257620848903SChaotian Jing return ret; 257720848903SChaotian Jing } 257820848903SChaotian Jing 257920848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 258020848903SChaotian Jing { 258120848903SChaotian Jing struct mmc_host *mmc; 258220848903SChaotian Jing struct msdc_host *host; 258320848903SChaotian Jing 258420848903SChaotian Jing mmc = platform_get_drvdata(pdev); 258520848903SChaotian Jing host = mmc_priv(mmc); 258620848903SChaotian Jing 25874b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 25884b8a43e9SChaotian Jing 258920848903SChaotian Jing platform_set_drvdata(pdev, NULL); 25900caf60c4SAmey Narkhede mmc_remove_host(mmc); 259120848903SChaotian Jing msdc_deinit_hw(host); 259220848903SChaotian Jing msdc_gate_clock(host); 259320848903SChaotian Jing 25944b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 25954b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 259620848903SChaotian Jing dma_free_coherent(&pdev->dev, 259716f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 259820848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 259920848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 260020848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 260120848903SChaotian Jing 26020caf60c4SAmey Narkhede mmc_free_host(mmc); 260320848903SChaotian Jing 260420848903SChaotian Jing return 0; 260520848903SChaotian Jing } 260620848903SChaotian Jing 26074b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 26084b8a43e9SChaotian Jing { 260939add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 261039add252SChaotian Jing 26114b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 26124b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 26134b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 26144b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 26154b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 26162fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 26176397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 26181ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 26196397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2620c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2621d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2622a2e6d1f6SChaotian Jing if (host->top_base) { 2623a2e6d1f6SChaotian Jing host->save_para.emmc_top_control = 2624a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 2625a2e6d1f6SChaotian Jing host->save_para.emmc_top_cmd = 2626a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 2627a2e6d1f6SChaotian Jing host->save_para.emmc50_pad_ds_tune = 2628a2e6d1f6SChaotian Jing readl(host->top_base + EMMC50_PAD_DS_TUNE); 2629a2e6d1f6SChaotian Jing } else { 2630a2e6d1f6SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 2631a2e6d1f6SChaotian Jing } 26324b8a43e9SChaotian Jing } 26334b8a43e9SChaotian Jing 26344b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 26354b8a43e9SChaotian Jing { 26360caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 263739add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 263839add252SChaotian Jing 26394b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 26404b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 26414b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 26424b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 26434b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 26442fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 26456397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 26461ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 26476397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2648c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2649d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2650a2e6d1f6SChaotian Jing if (host->top_base) { 2651a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_control, 2652a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 2653a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_cmd, 2654a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 2655a2e6d1f6SChaotian Jing writel(host->save_para.emmc50_pad_ds_tune, 2656a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2657a2e6d1f6SChaotian Jing } else { 2658a2e6d1f6SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 2659a2e6d1f6SChaotian Jing } 26601c81d69dSUlf Hansson 26610caf60c4SAmey Narkhede if (sdio_irq_claimed(mmc)) 26621c81d69dSUlf Hansson __msdc_enable_sdio_irq(host, 1); 26634b8a43e9SChaotian Jing } 26644b8a43e9SChaotian Jing 2665c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_suspend(struct device *dev) 26664b8a43e9SChaotian Jing { 26674b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 26684b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 26694b8a43e9SChaotian Jing 26704b8a43e9SChaotian Jing msdc_save_reg(host); 26714b8a43e9SChaotian Jing msdc_gate_clock(host); 26724b8a43e9SChaotian Jing return 0; 26734b8a43e9SChaotian Jing } 26744b8a43e9SChaotian Jing 2675c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_resume(struct device *dev) 26764b8a43e9SChaotian Jing { 26774b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 26784b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 26794b8a43e9SChaotian Jing 26804b8a43e9SChaotian Jing msdc_ungate_clock(host); 26814b8a43e9SChaotian Jing msdc_restore_reg(host); 26824b8a43e9SChaotian Jing return 0; 26834b8a43e9SChaotian Jing } 2684c0a2074aSWenbin Mei 2685c0d638a0SArnd Bergmann static int __maybe_unused msdc_suspend(struct device *dev) 2686c0a2074aSWenbin Mei { 2687c0a2074aSWenbin Mei struct mmc_host *mmc = dev_get_drvdata(dev); 2688c0a2074aSWenbin Mei int ret; 2689c0a2074aSWenbin Mei 2690c0a2074aSWenbin Mei if (mmc->caps2 & MMC_CAP2_CQE) { 2691c0a2074aSWenbin Mei ret = cqhci_suspend(mmc); 2692c0a2074aSWenbin Mei if (ret) 2693c0a2074aSWenbin Mei return ret; 2694c0a2074aSWenbin Mei } 2695c0a2074aSWenbin Mei 2696c0a2074aSWenbin Mei return pm_runtime_force_suspend(dev); 2697c0a2074aSWenbin Mei } 2698c0a2074aSWenbin Mei 2699c0d638a0SArnd Bergmann static int __maybe_unused msdc_resume(struct device *dev) 2700c0a2074aSWenbin Mei { 2701c0a2074aSWenbin Mei return pm_runtime_force_resume(dev); 2702c0a2074aSWenbin Mei } 27034b8a43e9SChaotian Jing 27044b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 2705c0a2074aSWenbin Mei SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 27064b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 27074b8a43e9SChaotian Jing }; 27084b8a43e9SChaotian Jing 270920848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 271020848903SChaotian Jing .probe = msdc_drv_probe, 271120848903SChaotian Jing .remove = msdc_drv_remove, 271220848903SChaotian Jing .driver = { 271320848903SChaotian Jing .name = "mtk-msdc", 271421b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 271520848903SChaotian Jing .of_match_table = msdc_of_ids, 27164b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 271720848903SChaotian Jing }, 271820848903SChaotian Jing }; 271920848903SChaotian Jing 272020848903SChaotian Jing module_platform_driver(mt_msdc_driver); 272120848903SChaotian Jing MODULE_LICENSE("GPL v2"); 272220848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2723