11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 220848903SChaotian Jing /* 3527f36f5SAxe Yang * Copyright (c) 2014-2015, 2022 MediaTek Inc. 420848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 520848903SChaotian Jing */ 620848903SChaotian Jing 720848903SChaotian Jing #include <linux/module.h> 84fe54318SAngeloGioacchino Del Regno #include <linux/bitops.h> 920848903SChaotian Jing #include <linux/clk.h> 1020848903SChaotian Jing #include <linux/delay.h> 1120848903SChaotian Jing #include <linux/dma-mapping.h> 1243e5fee3SDerong Liu #include <linux/iopoll.h> 1320848903SChaotian Jing #include <linux/ioport.h> 1420848903SChaotian Jing #include <linux/irq.h> 1520848903SChaotian Jing #include <linux/of_address.h> 16909b3456SRyder Lee #include <linux/of_device.h> 1720848903SChaotian Jing #include <linux/of_irq.h> 1820848903SChaotian Jing #include <linux/of_gpio.h> 1920848903SChaotian Jing #include <linux/pinctrl/consumer.h> 2020848903SChaotian Jing #include <linux/platform_device.h> 214b8a43e9SChaotian Jing #include <linux/pm.h> 224b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 23527f36f5SAxe Yang #include <linux/pm_wakeirq.h> 2420848903SChaotian Jing #include <linux/regulator/consumer.h> 256397b7f5SChaotian Jing #include <linux/slab.h> 2620848903SChaotian Jing #include <linux/spinlock.h> 27b8789ec4SUlf Hansson #include <linux/interrupt.h> 28855d388dSWenbin Mei #include <linux/reset.h> 2920848903SChaotian Jing 3020848903SChaotian Jing #include <linux/mmc/card.h> 3120848903SChaotian Jing #include <linux/mmc/core.h> 3220848903SChaotian Jing #include <linux/mmc/host.h> 3320848903SChaotian Jing #include <linux/mmc/mmc.h> 3420848903SChaotian Jing #include <linux/mmc/sd.h> 3520848903SChaotian Jing #include <linux/mmc/sdio.h> 368d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 3720848903SChaotian Jing 3888bd652bSChun-Hung Wu #include "cqhci.h" 3988bd652bSChun-Hung Wu 4020848903SChaotian Jing #define MAX_BD_NUM 1024 41f5eccd94SWenbin Mei #define MSDC_NR_CLOCKS 3 4220848903SChaotian Jing 4320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4420848903SChaotian Jing /* Common Definition */ 4520848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4620848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4720848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4820848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4920848903SChaotian Jing 5020848903SChaotian Jing #define MSDC_BURST_64B 0x6 5120848903SChaotian Jing 5220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5320848903SChaotian Jing /* Register Offset */ 5420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5520848903SChaotian Jing #define MSDC_CFG 0x0 5620848903SChaotian Jing #define MSDC_IOCON 0x04 5720848903SChaotian Jing #define MSDC_PS 0x08 5820848903SChaotian Jing #define MSDC_INT 0x0c 5920848903SChaotian Jing #define MSDC_INTEN 0x10 6020848903SChaotian Jing #define MSDC_FIFOCS 0x14 6120848903SChaotian Jing #define SDC_CFG 0x30 6220848903SChaotian Jing #define SDC_CMD 0x34 6320848903SChaotian Jing #define SDC_ARG 0x38 6420848903SChaotian Jing #define SDC_STS 0x3c 6520848903SChaotian Jing #define SDC_RESP0 0x40 6620848903SChaotian Jing #define SDC_RESP1 0x44 6720848903SChaotian Jing #define SDC_RESP2 0x48 6820848903SChaotian Jing #define SDC_RESP3 0x4c 6920848903SChaotian Jing #define SDC_BLK_NUM 0x50 70d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 71c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 7220848903SChaotian Jing #define SDC_ACMD_RESP 0x80 732a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 7420848903SChaotian Jing #define MSDC_DMA_SA 0x90 7520848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7620848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7720848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7820848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 792fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 8020848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 8139add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 826397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 831ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 8413b4e1e9SWenbin Mei #define EMMC51_CFG0 0x204 856397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 8613b4e1e9SWenbin Mei #define EMMC50_CFG1 0x20c 87c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 88d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 8913b4e1e9SWenbin Mei #define CQHCI_SETTING 0x7fc 9020848903SChaotian Jing 9120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 92a2e6d1f6SChaotian Jing /* Top Pad Register Offset */ 93a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 94a2e6d1f6SChaotian Jing #define EMMC_TOP_CONTROL 0x00 95a2e6d1f6SChaotian Jing #define EMMC_TOP_CMD 0x04 96a2e6d1f6SChaotian Jing #define EMMC50_PAD_DS_TUNE 0x0c 97a2e6d1f6SChaotian Jing 98a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 9920848903SChaotian Jing /* Register Mask */ 10020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 10120848903SChaotian Jing 10220848903SChaotian Jing /* MSDC_CFG mask */ 1034fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_MODE BIT(0) /* RW */ 1044fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKPDN BIT(1) /* RW */ 1054fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_RST BIT(2) /* RW */ 1064fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_PIO BIT(3) /* RW */ 1074fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 1084fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 1094fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_BV18PSS BIT(6) /* R */ 1104fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKSTB BIT(7) /* R */ 1114fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 1124fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 1134fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 1144fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 1154fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 1164fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 11720848903SChaotian Jing 11820848903SChaotian Jing /* MSDC_IOCON mask */ 1194fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 1204fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_RSPL BIT(1) /* RW */ 1214fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DSPL BIT(2) /* RW */ 1224fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 1234fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 1244fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 1254fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 1264fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 1274fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 1284fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 1294fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 1304fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 1314fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 1324fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 1334fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 1344fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 13520848903SChaotian Jing 13620848903SChaotian Jing /* MSDC_PS mask */ 1374fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDEN BIT(0) /* RW */ 1384fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDSTS BIT(1) /* R */ 1394fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 1404fe54318SAngeloGioacchino Del Regno #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 1414fe54318SAngeloGioacchino Del Regno #define MSDC_PS_DATA1 BIT(17) /* R */ 1424fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CMD BIT(24) /* R */ 1434fe54318SAngeloGioacchino Del Regno #define MSDC_PS_WP BIT(31) /* R */ 14420848903SChaotian Jing 14520848903SChaotian Jing /* MSDC_INT mask */ 1464fe54318SAngeloGioacchino Del Regno #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 1474fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CDSC BIT(1) /* W1C */ 1484fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 1494fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 1504fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 1514fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 1524fe54318SAngeloGioacchino Del Regno #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 1534fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 1544fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 1554fe54318SAngeloGioacchino Del Regno #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 1564fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CSTA BIT(11) /* R */ 1574fe54318SAngeloGioacchino Del Regno #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 1584fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 1594fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DATTMO BIT(14) /* W1C */ 1604fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 1614fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 1624fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 1634fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 1644fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 1654fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDQ BIT(28) /* W1C */ 16620848903SChaotian Jing 16720848903SChaotian Jing /* MSDC_INTEN mask */ 1684fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 1694fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CDSC BIT(1) /* RW */ 1704fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 1714fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 1724fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 1734fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 1744fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 1754fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 1764fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 1774fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 1784fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CSTA BIT(11) /* RW */ 1794fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 1804fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 1814fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 1824fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 1834fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 1844fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 1854fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 1864fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 18720848903SChaotian Jing 18820848903SChaotian Jing /* MSDC_FIFOCS mask */ 1894fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 1904fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 1914fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 19220848903SChaotian Jing 19320848903SChaotian Jing /* SDC_CFG mask */ 1944fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 1954fe54318SAngeloGioacchino Del Regno #define SDC_CFG_INSWKUP BIT(1) /* RW */ 1964fe54318SAngeloGioacchino Del Regno #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 1974fe54318SAngeloGioacchino Del Regno #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 1984fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIO BIT(19) /* RW */ 1994fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 2004fe54318SAngeloGioacchino Del Regno #define SDC_CFG_INTATGAP BIT(21) /* RW */ 2014fe54318SAngeloGioacchino Del Regno #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 20220848903SChaotian Jing 20320848903SChaotian Jing /* SDC_STS mask */ 2044fe54318SAngeloGioacchino Del Regno #define SDC_STS_SDCBUSY BIT(0) /* RW */ 2054fe54318SAngeloGioacchino Del Regno #define SDC_STS_CMDBUSY BIT(1) /* RW */ 2064fe54318SAngeloGioacchino Del Regno #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 20720848903SChaotian Jing 2084fe54318SAngeloGioacchino Del Regno #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 209d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 2104fe54318SAngeloGioacchino Del Regno #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 211d9dcbfc8SChaotian Jing 2122a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2134fe54318SAngeloGioacchino Del Regno #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 2142a9bde19SChaotian Jing 21520848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 2164fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_START BIT(0) /* W */ 2174fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 2184fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 2194fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 2204fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 2214fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 22220848903SChaotian Jing 22320848903SChaotian Jing /* MSDC_DMA_CFG mask */ 2244fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_STS BIT(0) /* R */ 2254fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 2264fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 2274fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 2284fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 22920848903SChaotian Jing 23020848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 2314fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 2324fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 2334fe54318SAngeloGioacchino Del Regno #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 2344fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 2354fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 2364fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 2374fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 2384fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 2394fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 2404fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 2414fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 2424fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 24320848903SChaotian Jing 2444fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 2454fe54318SAngeloGioacchino Del Regno #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 2464fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 247d9dcbfc8SChaotian Jing 2484fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 2494fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 2504fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 2514fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 2524fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 2534fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 2542fea5819SChaotian Jing 2554fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 2564fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 2574fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 2584fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 2594fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 2604fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 2614fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 2624fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 2636397b7f5SChaotian Jing 2644fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 2654fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 2664fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 2674fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 2686397b7f5SChaotian Jing 2694fe54318SAngeloGioacchino Del Regno #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 2701ede5cb8Syong mao 27113b4e1e9SWenbin Mei /* EMMC51_CFG0 mask */ 2724fe54318SAngeloGioacchino Del Regno #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 27313b4e1e9SWenbin Mei 2744fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 2754fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 2764fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 2774fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 27813b4e1e9SWenbin Mei 27913b4e1e9SWenbin Mei /* EMMC50_CFG1 mask */ 2804fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 2816397b7f5SChaotian Jing 2824fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 283c8609b22SChaotian Jing 2844fe54318SAngeloGioacchino Del Regno #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 2854fe54318SAngeloGioacchino Del Regno #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 286d9dcbfc8SChaotian Jing 28713b4e1e9SWenbin Mei /* CQHCI_SETTING */ 2884fe54318SAngeloGioacchino Del Regno #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 2894fe54318SAngeloGioacchino Del Regno #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 29013b4e1e9SWenbin Mei 291a2e6d1f6SChaotian Jing /* EMMC_TOP_CONTROL mask */ 2924fe54318SAngeloGioacchino Del Regno #define PAD_RXDLY_SEL BIT(0) /* RW */ 2934fe54318SAngeloGioacchino Del Regno #define DELAY_EN BIT(1) /* RW */ 2944fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 2954fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 2964fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 2974fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 2984fe54318SAngeloGioacchino Del Regno #define DATA_K_VALUE_SEL BIT(14) /* RW */ 2994fe54318SAngeloGioacchino Del Regno #define SDC_RX_ENH_EN BIT(15) /* TW */ 300a2e6d1f6SChaotian Jing 301a2e6d1f6SChaotian Jing /* EMMC_TOP_CMD mask */ 3024fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 3034fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 3044fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 3054fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 3064fe54318SAngeloGioacchino Del Regno #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 307a2e6d1f6SChaotian Jing 308c4ac38c6SWenbin Mei /* EMMC50_PAD_DS_TUNE mask */ 3094fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY_SEL BIT(16) /* RW */ 3104fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 3114fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 312c4ac38c6SWenbin Mei 3134fe54318SAngeloGioacchino Del Regno #define REQ_CMD_EIO BIT(0) 3144fe54318SAngeloGioacchino Del Regno #define REQ_CMD_TMO BIT(1) 3154fe54318SAngeloGioacchino Del Regno #define REQ_DAT_ERR BIT(2) 3164fe54318SAngeloGioacchino Del Regno #define REQ_STOP_EIO BIT(3) 3174fe54318SAngeloGioacchino Del Regno #define REQ_STOP_TMO BIT(4) 3184fe54318SAngeloGioacchino Del Regno #define REQ_CMD_BUSY BIT(5) 31920848903SChaotian Jing 3204fe54318SAngeloGioacchino Del Regno #define MSDC_PREPARE_FLAG BIT(0) 3214fe54318SAngeloGioacchino Del Regno #define MSDC_ASYNC_FLAG BIT(1) 3224fe54318SAngeloGioacchino Del Regno #define MSDC_MMAP_FLAG BIT(2) 32320848903SChaotian Jing 3244b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 32520848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 32620848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 32720848903SChaotian Jing 328d087bde5SNeilBrown #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 329d087bde5SNeilBrown 3306397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 33120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 33220848903SChaotian Jing /* Descriptor Structure */ 33320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 33420848903SChaotian Jing struct mt_gpdma_desc { 33520848903SChaotian Jing u32 gpd_info; 3364fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_HWO BIT(0) 3374fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_BDP BIT(1) 3384fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 3394fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_INT BIT(16) 3404fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 3414fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 34220848903SChaotian Jing u32 next; 34320848903SChaotian Jing u32 ptr; 34420848903SChaotian Jing u32 gpd_data_len; 3454fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 3464fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 34720848903SChaotian Jing u32 arg; 34820848903SChaotian Jing u32 blknum; 34920848903SChaotian Jing u32 cmd; 35020848903SChaotian Jing }; 35120848903SChaotian Jing 35220848903SChaotian Jing struct mt_bdma_desc { 35320848903SChaotian Jing u32 bd_info; 3544fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_EOL BIT(0) 3554fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 3564fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BLKPAD BIT(17) 3574fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_DWPAD BIT(18) 3584fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 3594fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 36020848903SChaotian Jing u32 next; 36120848903SChaotian Jing u32 ptr; 36220848903SChaotian Jing u32 bd_data_len; 3634fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BUFLEN GENMASK(15, 0) 3644fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 36520848903SChaotian Jing }; 36620848903SChaotian Jing 36720848903SChaotian Jing struct msdc_dma { 36820848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 36920848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 37020848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 37120848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 37220848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 37320848903SChaotian Jing }; 37420848903SChaotian Jing 3754b8a43e9SChaotian Jing struct msdc_save_para { 3764b8a43e9SChaotian Jing u32 msdc_cfg; 3774b8a43e9SChaotian Jing u32 iocon; 3784b8a43e9SChaotian Jing u32 sdc_cfg; 3794b8a43e9SChaotian Jing u32 pad_tune; 3804b8a43e9SChaotian Jing u32 patch_bit0; 3814b8a43e9SChaotian Jing u32 patch_bit1; 3822fea5819SChaotian Jing u32 patch_bit2; 3836397b7f5SChaotian Jing u32 pad_ds_tune; 3841ede5cb8Syong mao u32 pad_cmd_tune; 3856397b7f5SChaotian Jing u32 emmc50_cfg0; 386c8609b22SChaotian Jing u32 emmc50_cfg3; 387d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 388a2e6d1f6SChaotian Jing u32 emmc_top_control; 389a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 390a2e6d1f6SChaotian Jing u32 emmc50_pad_ds_tune; 3916397b7f5SChaotian Jing }; 3926397b7f5SChaotian Jing 393762d491aSChaotian Jing struct mtk_mmc_compatible { 394762d491aSChaotian Jing u8 clk_div_bits; 3959e2582e5Syong mao bool recheck_sdio_irq; 3967f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 39739add252SChaotian Jing u32 pad_tune_reg; 3982fea5819SChaotian Jing bool async_fifo; 3992fea5819SChaotian Jing bool data_tune; 400acde28c4SChaotian Jing bool busy_check; 401d9dcbfc8SChaotian Jing bool stop_clk_fix; 402d9dcbfc8SChaotian Jing bool enhance_rx; 4032a9bde19SChaotian Jing bool support_64g; 404d087bde5SNeilBrown bool use_internal_cd; 405762d491aSChaotian Jing }; 406762d491aSChaotian Jing 40786beac37SChaotian Jing struct msdc_tune_para { 40886beac37SChaotian Jing u32 iocon; 40986beac37SChaotian Jing u32 pad_tune; 4101ede5cb8Syong mao u32 pad_cmd_tune; 411a2e6d1f6SChaotian Jing u32 emmc_top_control; 412a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 41386beac37SChaotian Jing }; 41486beac37SChaotian Jing 4156397b7f5SChaotian Jing struct msdc_delay_phase { 4166397b7f5SChaotian Jing u8 maxlen; 4176397b7f5SChaotian Jing u8 start; 4186397b7f5SChaotian Jing u8 final_phase; 4194b8a43e9SChaotian Jing }; 4204b8a43e9SChaotian Jing 42120848903SChaotian Jing struct msdc_host { 42220848903SChaotian Jing struct device *dev; 423762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 42420848903SChaotian Jing int cmd_rsp; 42520848903SChaotian Jing 42620848903SChaotian Jing spinlock_t lock; 42720848903SChaotian Jing struct mmc_request *mrq; 42820848903SChaotian Jing struct mmc_command *cmd; 42920848903SChaotian Jing struct mmc_data *data; 43020848903SChaotian Jing int error; 43120848903SChaotian Jing 43220848903SChaotian Jing void __iomem *base; /* host base address */ 433a2e6d1f6SChaotian Jing void __iomem *top_base; /* host top register base address */ 43420848903SChaotian Jing 43520848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 43620848903SChaotian Jing u64 dma_mask; 43720848903SChaotian Jing 43820848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 43920848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 44020848903SChaotian Jing 44120848903SChaotian Jing struct pinctrl *pinctrl; 44220848903SChaotian Jing struct pinctrl_state *pins_default; 44320848903SChaotian Jing struct pinctrl_state *pins_uhs; 444527f36f5SAxe Yang struct pinctrl_state *pins_eint; 44520848903SChaotian Jing struct delayed_work req_timeout; 44620848903SChaotian Jing int irq; /* host interrupt */ 447527f36f5SAxe Yang int eint_irq; /* interrupt from sdio device for waking up system */ 448855d388dSWenbin Mei struct reset_control *reset; 44920848903SChaotian Jing 45020848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 45120848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 452258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 4533c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 454f5eccd94SWenbin Mei struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 4557b438d03SMengqi Zhang struct clk *crypto_clk; /* msdc crypto clock control gate */ 456f5eccd94SWenbin Mei struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 45720848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 45820848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 4596e622947SChaotian Jing unsigned char timing; 46020848903SChaotian Jing bool vqmmc_enabled; 461d17bb71cSChaotian Jing u32 latch_ck; 4626397b7f5SChaotian Jing u32 hs400_ds_delay; 463c4ac38c6SWenbin Mei u32 hs400_ds_dly3; 4641ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 4651ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4661ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4671ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4685462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 469c4ac38c6SWenbin Mei bool hs400_tuning; /* hs400 mode online tuning */ 470d087bde5SNeilBrown bool internal_cd; /* Use internal card-detect logic */ 47188bd652bSChun-Hung Wu bool cqhci; /* support eMMC hw cmdq */ 4724b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 47386beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 47486beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 47588bd652bSChun-Hung Wu struct cqhci_host *cq_host; 47620848903SChaotian Jing }; 47720848903SChaotian Jing 478d4dc6ecaSAngeloGioacchino Del Regno static const struct mtk_mmc_compatible mt2701_compat = { 479d4dc6ecaSAngeloGioacchino Del Regno .clk_div_bits = 12, 480d4dc6ecaSAngeloGioacchino Del Regno .recheck_sdio_irq = true, 481d4dc6ecaSAngeloGioacchino Del Regno .hs400_tune = false, 482d4dc6ecaSAngeloGioacchino Del Regno .pad_tune_reg = MSDC_PAD_TUNE0, 483d4dc6ecaSAngeloGioacchino Del Regno .async_fifo = true, 484d4dc6ecaSAngeloGioacchino Del Regno .data_tune = true, 485d4dc6ecaSAngeloGioacchino Del Regno .busy_check = false, 486d4dc6ecaSAngeloGioacchino Del Regno .stop_clk_fix = false, 487d4dc6ecaSAngeloGioacchino Del Regno .enhance_rx = false, 488d4dc6ecaSAngeloGioacchino Del Regno .support_64g = false, 489d4dc6ecaSAngeloGioacchino Del Regno }; 490d4dc6ecaSAngeloGioacchino Del Regno 491d4dc6ecaSAngeloGioacchino Del Regno static const struct mtk_mmc_compatible mt2712_compat = { 492d4dc6ecaSAngeloGioacchino Del Regno .clk_div_bits = 12, 493d4dc6ecaSAngeloGioacchino Del Regno .recheck_sdio_irq = false, 494d4dc6ecaSAngeloGioacchino Del Regno .hs400_tune = false, 495d4dc6ecaSAngeloGioacchino Del Regno .pad_tune_reg = MSDC_PAD_TUNE0, 496d4dc6ecaSAngeloGioacchino Del Regno .async_fifo = true, 497d4dc6ecaSAngeloGioacchino Del Regno .data_tune = true, 498d4dc6ecaSAngeloGioacchino Del Regno .busy_check = true, 499d4dc6ecaSAngeloGioacchino Del Regno .stop_clk_fix = true, 500d4dc6ecaSAngeloGioacchino Del Regno .enhance_rx = true, 501d4dc6ecaSAngeloGioacchino Del Regno .support_64g = true, 502d4dc6ecaSAngeloGioacchino Del Regno }; 503d4dc6ecaSAngeloGioacchino Del Regno 504d4dc6ecaSAngeloGioacchino Del Regno static const struct mtk_mmc_compatible mt6779_compat = { 505d4dc6ecaSAngeloGioacchino Del Regno .clk_div_bits = 12, 506d4dc6ecaSAngeloGioacchino Del Regno .recheck_sdio_irq = false, 507d4dc6ecaSAngeloGioacchino Del Regno .hs400_tune = false, 508d4dc6ecaSAngeloGioacchino Del Regno .pad_tune_reg = MSDC_PAD_TUNE0, 509d4dc6ecaSAngeloGioacchino Del Regno .async_fifo = true, 510d4dc6ecaSAngeloGioacchino Del Regno .data_tune = true, 511d4dc6ecaSAngeloGioacchino Del Regno .busy_check = true, 512d4dc6ecaSAngeloGioacchino Del Regno .stop_clk_fix = true, 513d4dc6ecaSAngeloGioacchino Del Regno .enhance_rx = true, 514d4dc6ecaSAngeloGioacchino Del Regno .support_64g = true, 515d4dc6ecaSAngeloGioacchino Del Regno }; 516d4dc6ecaSAngeloGioacchino Del Regno 517f7209cbfSAngeloGioacchino Del Regno static const struct mtk_mmc_compatible mt6795_compat = { 518f7209cbfSAngeloGioacchino Del Regno .clk_div_bits = 8, 519f7209cbfSAngeloGioacchino Del Regno .recheck_sdio_irq = false, 520f7209cbfSAngeloGioacchino Del Regno .hs400_tune = true, 521f7209cbfSAngeloGioacchino Del Regno .pad_tune_reg = MSDC_PAD_TUNE, 522f7209cbfSAngeloGioacchino Del Regno .async_fifo = false, 523f7209cbfSAngeloGioacchino Del Regno .data_tune = false, 524f7209cbfSAngeloGioacchino Del Regno .busy_check = false, 525f7209cbfSAngeloGioacchino Del Regno .stop_clk_fix = false, 526f7209cbfSAngeloGioacchino Del Regno .enhance_rx = false, 527f7209cbfSAngeloGioacchino Del Regno .support_64g = false, 528f7209cbfSAngeloGioacchino Del Regno }; 529f7209cbfSAngeloGioacchino Del Regno 530d4dc6ecaSAngeloGioacchino Del Regno static const struct mtk_mmc_compatible mt7620_compat = { 531d4dc6ecaSAngeloGioacchino Del Regno .clk_div_bits = 8, 532d4dc6ecaSAngeloGioacchino Del Regno .recheck_sdio_irq = true, 533d4dc6ecaSAngeloGioacchino Del Regno .hs400_tune = false, 534d4dc6ecaSAngeloGioacchino Del Regno .pad_tune_reg = MSDC_PAD_TUNE, 535d4dc6ecaSAngeloGioacchino Del Regno .async_fifo = false, 536d4dc6ecaSAngeloGioacchino Del Regno .data_tune = false, 537d4dc6ecaSAngeloGioacchino Del Regno .busy_check = false, 538d4dc6ecaSAngeloGioacchino Del Regno .stop_clk_fix = false, 539d4dc6ecaSAngeloGioacchino Del Regno .enhance_rx = false, 540d4dc6ecaSAngeloGioacchino Del Regno .use_internal_cd = true, 541d4dc6ecaSAngeloGioacchino Del Regno }; 542d4dc6ecaSAngeloGioacchino Del Regno 543d4dc6ecaSAngeloGioacchino Del Regno static const struct mtk_mmc_compatible mt7622_compat = { 544d4dc6ecaSAngeloGioacchino Del Regno .clk_div_bits = 12, 545d4dc6ecaSAngeloGioacchino Del Regno .recheck_sdio_irq = true, 546d4dc6ecaSAngeloGioacchino Del Regno .hs400_tune = false, 547d4dc6ecaSAngeloGioacchino Del Regno .pad_tune_reg = MSDC_PAD_TUNE0, 548d4dc6ecaSAngeloGioacchino Del Regno .async_fifo = true, 549d4dc6ecaSAngeloGioacchino Del Regno .data_tune = true, 550d4dc6ecaSAngeloGioacchino Del Regno .busy_check = true, 551d4dc6ecaSAngeloGioacchino Del Regno .stop_clk_fix = true, 552d4dc6ecaSAngeloGioacchino Del Regno .enhance_rx = true, 553d4dc6ecaSAngeloGioacchino Del Regno .support_64g = false, 554d4dc6ecaSAngeloGioacchino Del Regno }; 555d4dc6ecaSAngeloGioacchino Del Regno 55624e961b9SSam Shih static const struct mtk_mmc_compatible mt7986_compat = { 55724e961b9SSam Shih .clk_div_bits = 12, 55824e961b9SSam Shih .recheck_sdio_irq = true, 55924e961b9SSam Shih .hs400_tune = false, 56024e961b9SSam Shih .pad_tune_reg = MSDC_PAD_TUNE0, 56124e961b9SSam Shih .async_fifo = true, 56224e961b9SSam Shih .data_tune = true, 56324e961b9SSam Shih .busy_check = true, 56424e961b9SSam Shih .stop_clk_fix = true, 56524e961b9SSam Shih .enhance_rx = true, 56624e961b9SSam Shih .support_64g = true, 56724e961b9SSam Shih }; 56824e961b9SSam Shih 569762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 570762d491aSChaotian Jing .clk_div_bits = 8, 571903a72ecSyong mao .recheck_sdio_irq = true, 5727f3d5852SChaotian Jing .hs400_tune = false, 57339add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 5742fea5819SChaotian Jing .async_fifo = false, 5752fea5819SChaotian Jing .data_tune = false, 576acde28c4SChaotian Jing .busy_check = false, 577d9dcbfc8SChaotian Jing .stop_clk_fix = false, 578d9dcbfc8SChaotian Jing .enhance_rx = false, 5792a9bde19SChaotian Jing .support_64g = false, 580762d491aSChaotian Jing }; 581762d491aSChaotian Jing 582762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 583762d491aSChaotian Jing .clk_div_bits = 8, 5849e2582e5Syong mao .recheck_sdio_irq = true, 5857f3d5852SChaotian Jing .hs400_tune = true, 58639add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 5872fea5819SChaotian Jing .async_fifo = false, 5882fea5819SChaotian Jing .data_tune = false, 589acde28c4SChaotian Jing .busy_check = false, 590d9dcbfc8SChaotian Jing .stop_clk_fix = false, 591d9dcbfc8SChaotian Jing .enhance_rx = false, 5922a9bde19SChaotian Jing .support_64g = false, 593762d491aSChaotian Jing }; 594762d491aSChaotian Jing 595a2e6d1f6SChaotian Jing static const struct mtk_mmc_compatible mt8183_compat = { 596a2e6d1f6SChaotian Jing .clk_div_bits = 12, 5979e2582e5Syong mao .recheck_sdio_irq = false, 598a2e6d1f6SChaotian Jing .hs400_tune = false, 599a2e6d1f6SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 600a2e6d1f6SChaotian Jing .async_fifo = true, 601a2e6d1f6SChaotian Jing .data_tune = true, 602a2e6d1f6SChaotian Jing .busy_check = true, 603a2e6d1f6SChaotian Jing .stop_clk_fix = true, 604a2e6d1f6SChaotian Jing .enhance_rx = true, 605a2e6d1f6SChaotian Jing .support_64g = true, 606a2e6d1f6SChaotian Jing }; 607a2e6d1f6SChaotian Jing 60889822b73SFabien Parent static const struct mtk_mmc_compatible mt8516_compat = { 60989822b73SFabien Parent .clk_div_bits = 12, 610903a72ecSyong mao .recheck_sdio_irq = true, 61189822b73SFabien Parent .hs400_tune = false, 61289822b73SFabien Parent .pad_tune_reg = MSDC_PAD_TUNE0, 61389822b73SFabien Parent .async_fifo = true, 61489822b73SFabien Parent .data_tune = true, 61589822b73SFabien Parent .busy_check = true, 61689822b73SFabien Parent .stop_clk_fix = true, 61789822b73SFabien Parent }; 61889822b73SFabien Parent 619762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 620d4dc6ecaSAngeloGioacchino Del Regno { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 621d4dc6ecaSAngeloGioacchino Del Regno { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 622d4dc6ecaSAngeloGioacchino Del Regno { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 623f7209cbfSAngeloGioacchino Del Regno { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, 624d4dc6ecaSAngeloGioacchino Del Regno { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 625d4dc6ecaSAngeloGioacchino Del Regno { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 62624e961b9SSam Shih { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, 627762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 628762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 629a2e6d1f6SChaotian Jing { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 63089822b73SFabien Parent { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 631d4dc6ecaSAngeloGioacchino Del Regno 632762d491aSChaotian Jing {} 633762d491aSChaotian Jing }; 634762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 635762d491aSChaotian Jing 63620848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 63720848903SChaotian Jing { 63820848903SChaotian Jing u32 val = readl(reg); 63920848903SChaotian Jing 64020848903SChaotian Jing val |= bs; 64120848903SChaotian Jing writel(val, reg); 64220848903SChaotian Jing } 64320848903SChaotian Jing 64420848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 64520848903SChaotian Jing { 64620848903SChaotian Jing u32 val = readl(reg); 64720848903SChaotian Jing 64820848903SChaotian Jing val &= ~bs; 64920848903SChaotian Jing writel(val, reg); 65020848903SChaotian Jing } 65120848903SChaotian Jing 65220848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 65320848903SChaotian Jing { 65420848903SChaotian Jing unsigned int tv = readl(reg); 65520848903SChaotian Jing 65620848903SChaotian Jing tv &= ~field; 65720848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 65820848903SChaotian Jing writel(tv, reg); 65920848903SChaotian Jing } 66020848903SChaotian Jing 66120848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 66220848903SChaotian Jing { 66320848903SChaotian Jing unsigned int tv = readl(reg); 66420848903SChaotian Jing 66520848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 66620848903SChaotian Jing } 66720848903SChaotian Jing 66820848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 66920848903SChaotian Jing { 67020848903SChaotian Jing u32 val; 67120848903SChaotian Jing 67220848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 673ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 67420848903SChaotian Jing 67520848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 676ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_FIFOCS, val, 677ffaea6ebSAngeloGioacchino Del Regno !(val & MSDC_FIFOCS_CLR), 0, 0); 67820848903SChaotian Jing 67920848903SChaotian Jing val = readl(host->base + MSDC_INT); 68020848903SChaotian Jing writel(val, host->base + MSDC_INT); 68120848903SChaotian Jing } 68220848903SChaotian Jing 68320848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 68420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 6859e2582e5Syong mao static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 68620848903SChaotian Jing 687726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 688726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 689726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 690726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 69120848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 69220848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 69320848903SChaotian Jing 69420848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 69520848903SChaotian Jing { 69620848903SChaotian Jing u32 i, sum = 0; 69720848903SChaotian Jing 69820848903SChaotian Jing for (i = 0; i < len; i++) 69920848903SChaotian Jing sum += buf[i]; 70020848903SChaotian Jing return 0xff - (u8) sum; 70120848903SChaotian Jing } 70220848903SChaotian Jing 70320848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 70420848903SChaotian Jing struct mmc_data *data) 70520848903SChaotian Jing { 70620848903SChaotian Jing unsigned int j, dma_len; 70720848903SChaotian Jing dma_addr_t dma_address; 70820848903SChaotian Jing u32 dma_ctrl; 70920848903SChaotian Jing struct scatterlist *sg; 71020848903SChaotian Jing struct mt_gpdma_desc *gpd; 71120848903SChaotian Jing struct mt_bdma_desc *bd; 71220848903SChaotian Jing 71320848903SChaotian Jing sg = data->sg; 71420848903SChaotian Jing 71520848903SChaotian Jing gpd = dma->gpd; 71620848903SChaotian Jing bd = dma->bd; 71720848903SChaotian Jing 71820848903SChaotian Jing /* modify gpd */ 71920848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 72020848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 72120848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 72220848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 72320848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 72420848903SChaotian Jing 72520848903SChaotian Jing /* modify bd */ 72620848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 72720848903SChaotian Jing dma_address = sg_dma_address(sg); 72820848903SChaotian Jing dma_len = sg_dma_len(sg); 72920848903SChaotian Jing 73020848903SChaotian Jing /* init bd */ 73120848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 73220848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 7332a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 7342a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 7352a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 7362a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 7372a9bde19SChaotian Jing << 28; 7382a9bde19SChaotian Jing } 7396ef042bdSChaotian Jing 7406ef042bdSChaotian Jing if (host->dev_comp->support_64g) { 7416ef042bdSChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 7426ef042bdSChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 7436ef042bdSChaotian Jing } else { 74420848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 74520848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 7466ef042bdSChaotian Jing } 74720848903SChaotian Jing 74820848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 74920848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 75020848903SChaotian Jing else 75120848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 75220848903SChaotian Jing 7534b323f02SYu Zhe /* checksum need to clear first */ 75420848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 75520848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 75620848903SChaotian Jing } 75720848903SChaotian Jing 75820848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 75920848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 76020848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 7614fe54318SAngeloGioacchino Del Regno dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 76220848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 7632a9bde19SChaotian Jing if (host->dev_comp->support_64g) 7642a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 7652a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 7662a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 76720848903SChaotian Jing } 76820848903SChaotian Jing 76915107135SYue Hu static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 77020848903SChaotian Jing { 77120848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 77220848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 77320848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 774feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 77520848903SChaotian Jing } 77620848903SChaotian Jing } 77720848903SChaotian Jing 77815107135SYue Hu static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 77920848903SChaotian Jing { 78020848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 78120848903SChaotian Jing return; 78220848903SChaotian Jing 78320848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 78420848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 785feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 78620848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 78720848903SChaotian Jing } 78820848903SChaotian Jing } 78920848903SChaotian Jing 790557011b6SChun-Hung Wu static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 79120848903SChaotian Jing { 7920caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 793557011b6SChun-Hung Wu u64 timeout, clk_ns; 79420848903SChaotian Jing u32 mode = 0; 79520848903SChaotian Jing 7960caf60c4SAmey Narkhede if (mmc->actual_clock == 0) { 79720848903SChaotian Jing timeout = 0; 79820848903SChaotian Jing } else { 799557011b6SChun-Hung Wu clk_ns = 1000000000ULL; 8000caf60c4SAmey Narkhede do_div(clk_ns, mmc->actual_clock); 801557011b6SChun-Hung Wu timeout = ns + clk_ns - 1; 802557011b6SChun-Hung Wu do_div(timeout, clk_ns); 803557011b6SChun-Hung Wu timeout += clks; 80420848903SChaotian Jing /* in 1048576 sclk cycle unit */ 8054fe54318SAngeloGioacchino Del Regno timeout = DIV_ROUND_UP(timeout, BIT(20)); 806762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 807762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 808762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 809762d491aSChaotian Jing else 810762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 811762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 81220848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 81320848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 81420848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 81520848903SChaotian Jing } 816557011b6SChun-Hung Wu return timeout; 817557011b6SChun-Hung Wu } 818557011b6SChun-Hung Wu 819557011b6SChun-Hung Wu /* clock control primitives */ 820557011b6SChun-Hung Wu static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 821557011b6SChun-Hung Wu { 822557011b6SChun-Hung Wu u64 timeout; 823557011b6SChun-Hung Wu 824557011b6SChun-Hung Wu host->timeout_ns = ns; 825557011b6SChun-Hung Wu host->timeout_clks = clks; 826557011b6SChun-Hung Wu 827557011b6SChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 828557011b6SChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 829557011b6SChun-Hung Wu (u32)(timeout > 255 ? 255 : timeout)); 83020848903SChaotian Jing } 83120848903SChaotian Jing 83288bd652bSChun-Hung Wu static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 83388bd652bSChun-Hung Wu { 83488bd652bSChun-Hung Wu u64 timeout; 83588bd652bSChun-Hung Wu 83688bd652bSChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 83788bd652bSChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 83888bd652bSChun-Hung Wu (u32)(timeout > 8191 ? 8191 : timeout)); 83988bd652bSChun-Hung Wu } 84088bd652bSChun-Hung Wu 84120848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 84220848903SChaotian Jing { 843f5eccd94SWenbin Mei clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 8447b438d03SMengqi Zhang clk_disable_unprepare(host->crypto_clk); 8453c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 84620848903SChaotian Jing clk_disable_unprepare(host->src_clk); 847258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 84820848903SChaotian Jing clk_disable_unprepare(host->h_clk); 84920848903SChaotian Jing } 85020848903SChaotian Jing 851ffaea6ebSAngeloGioacchino Del Regno static int msdc_ungate_clock(struct msdc_host *host) 85220848903SChaotian Jing { 853ffaea6ebSAngeloGioacchino Del Regno u32 val; 854f5eccd94SWenbin Mei int ret; 855f5eccd94SWenbin Mei 85620848903SChaotian Jing clk_prepare_enable(host->h_clk); 857258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 85820848903SChaotian Jing clk_prepare_enable(host->src_clk); 8593c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 8607b438d03SMengqi Zhang clk_prepare_enable(host->crypto_clk); 861f5eccd94SWenbin Mei ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 862f5eccd94SWenbin Mei if (ret) { 863f5eccd94SWenbin Mei dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 864ffaea6ebSAngeloGioacchino Del Regno return ret; 865f5eccd94SWenbin Mei } 866f5eccd94SWenbin Mei 867ffaea6ebSAngeloGioacchino Del Regno return readl_poll_timeout(host->base + MSDC_CFG, val, 868ffaea6ebSAngeloGioacchino Del Regno (val & MSDC_CFG_CKSTB), 1, 20000); 86920848903SChaotian Jing } 87020848903SChaotian Jing 8716e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 87220848903SChaotian Jing { 8730caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 87420848903SChaotian Jing u32 mode; 87520848903SChaotian Jing u32 flags; 87620848903SChaotian Jing u32 div; 87720848903SChaotian Jing u32 sclk; 87839add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 879ffaea6ebSAngeloGioacchino Del Regno u32 val; 88020848903SChaotian Jing 88120848903SChaotian Jing if (!hz) { 88220848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 88320848903SChaotian Jing host->mclk = 0; 8840caf60c4SAmey Narkhede mmc->actual_clock = 0; 88520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 88620848903SChaotian Jing return; 88720848903SChaotian Jing } 88820848903SChaotian Jing 88920848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 89020848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 891762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8926397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 893762d491aSChaotian Jing else 894762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 895762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8966e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 8976397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 8986397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 8996397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 9006397b7f5SChaotian Jing mode = 0x3; 9016397b7f5SChaotian Jing else 90220848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 9036397b7f5SChaotian Jing 90420848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 90520848903SChaotian Jing div = 0; /* mean div = 1/4 */ 90620848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 90720848903SChaotian Jing } else { 90820848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 90920848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 91020848903SChaotian Jing div = (div >> 1); 91120848903SChaotian Jing } 9126397b7f5SChaotian Jing 9136397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 9146397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 915762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 9166397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 9176397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 918762d491aSChaotian Jing else 919762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 920762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 9216397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 9226397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 9236397b7f5SChaotian Jing } 92420848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 92520848903SChaotian Jing mode = 0x1; /* no divisor */ 92620848903SChaotian Jing div = 0; 92720848903SChaotian Jing sclk = host->src_clk_freq; 92820848903SChaotian Jing } else { 92920848903SChaotian Jing mode = 0x0; /* use divisor */ 93020848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 93120848903SChaotian Jing div = 0; /* mean div = 1/2 */ 93220848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 93320848903SChaotian Jing } else { 93420848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 93520848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 93620848903SChaotian Jing } 93720848903SChaotian Jing } 9383c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 939e5e8b224SAngeloGioacchino Del Regno 9403c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 941762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 942762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 943762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 94440ceda09Syong mao (mode << 8) | div); 945762d491aSChaotian Jing else 946762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 947762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 948762d491aSChaotian Jing (mode << 12) | div); 949762d491aSChaotian Jing 950e5e8b224SAngeloGioacchino Del Regno clk_prepare_enable(host->src_clk_cg); 951ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 9523c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 9530caf60c4SAmey Narkhede mmc->actual_clock = sclk; 95420848903SChaotian Jing host->mclk = hz; 9556e622947SChaotian Jing host->timing = timing; 95620848903SChaotian Jing /* need because clk changed. */ 95720848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 95820848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 95920848903SChaotian Jing 96086beac37SChaotian Jing /* 96186beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 96286beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 96386beac37SChaotian Jing */ 9640caf60c4SAmey Narkhede if (mmc->actual_clock <= 52000000) { 96586beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 966a2e6d1f6SChaotian Jing if (host->top_base) { 967a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_control, 968a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 969a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_cmd, 970a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 971a2e6d1f6SChaotian Jing } else { 972a2e6d1f6SChaotian Jing writel(host->def_tune_para.pad_tune, 973a2e6d1f6SChaotian Jing host->base + tune_reg); 974a2e6d1f6SChaotian Jing } 97586beac37SChaotian Jing } else { 97686beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 9771ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 9781ede5cb8Syong mao host->base + PAD_CMD_TUNE); 979a2e6d1f6SChaotian Jing if (host->top_base) { 980a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_control, 981a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 982a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_cmd, 983a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 984a2e6d1f6SChaotian Jing } else { 985a2e6d1f6SChaotian Jing writel(host->saved_tune_para.pad_tune, 986a2e6d1f6SChaotian Jing host->base + tune_reg); 987a2e6d1f6SChaotian Jing } 98886beac37SChaotian Jing } 98986beac37SChaotian Jing 9907f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 9917f3d5852SChaotian Jing host->dev_comp->hs400_tune) 9923751e008SChaotian Jing sdr_set_field(host->base + tune_reg, 9931ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 9941ede5cb8Syong mao host->hs400_cmd_int_delay); 9950caf60c4SAmey Narkhede dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 99656f6cbbeSChaotian Jing timing); 99720848903SChaotian Jing } 99820848903SChaotian Jing 99920848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 1000961e40f7SChanWoo Lee struct mmc_command *cmd) 100120848903SChaotian Jing { 100220848903SChaotian Jing u32 resp; 100320848903SChaotian Jing 100420848903SChaotian Jing switch (mmc_resp_type(cmd)) { 100520848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 100620848903SChaotian Jing case MMC_RSP_R1: 100720848903SChaotian Jing resp = 0x1; 100820848903SChaotian Jing break; 100920848903SChaotian Jing case MMC_RSP_R1B: 101020848903SChaotian Jing resp = 0x7; 101120848903SChaotian Jing break; 101220848903SChaotian Jing case MMC_RSP_R2: 101320848903SChaotian Jing resp = 0x2; 101420848903SChaotian Jing break; 101520848903SChaotian Jing case MMC_RSP_R3: 101620848903SChaotian Jing resp = 0x3; 101720848903SChaotian Jing break; 101820848903SChaotian Jing case MMC_RSP_NONE: 101920848903SChaotian Jing default: 102020848903SChaotian Jing resp = 0x0; 102120848903SChaotian Jing break; 102220848903SChaotian Jing } 102320848903SChaotian Jing 102420848903SChaotian Jing return resp; 102520848903SChaotian Jing } 102620848903SChaotian Jing 102720848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 102820848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 102920848903SChaotian Jing { 10300caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 103120848903SChaotian Jing /* rawcmd : 103220848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 103320848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 103420848903SChaotian Jing */ 103520848903SChaotian Jing u32 opcode = cmd->opcode; 1036961e40f7SChanWoo Lee u32 resp = msdc_cmd_find_resp(host, cmd); 103720848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 103820848903SChaotian Jing 103920848903SChaotian Jing host->cmd_rsp = resp; 104020848903SChaotian Jing 104120848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 104220848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 10434fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(14); 104420848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 10454fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(30); 104620848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 104720848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 104820848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 104920848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 105020848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 10514fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(11); 105220848903SChaotian Jing 105320848903SChaotian Jing if (cmd->data) { 105420848903SChaotian Jing struct mmc_data *data = cmd->data; 105520848903SChaotian Jing 105620848903SChaotian Jing if (mmc_op_multi(opcode)) { 10570caf60c4SAmey Narkhede if (mmc_card_mmc(mmc->card) && mrq->sbc && 105820848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 10594fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(29); /* AutoCMD23 */ 106020848903SChaotian Jing } 106120848903SChaotian Jing 106220848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 106320848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 10644fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(13); 106520848903SChaotian Jing if (data->blocks > 1) 10664fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(12); 106720848903SChaotian Jing else 10684fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(11); 106920848903SChaotian Jing /* Always use dma mode */ 107020848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 107120848903SChaotian Jing 107220848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 107320848903SChaotian Jing host->timeout_clks != data->timeout_clks) 107420848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 107520848903SChaotian Jing data->timeout_clks); 107620848903SChaotian Jing 107720848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 107820848903SChaotian Jing } 107920848903SChaotian Jing return rawcmd; 108020848903SChaotian Jing } 108120848903SChaotian Jing 1082d74179b8SChanWoo Lee static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1083d74179b8SChanWoo Lee struct mmc_data *data) 108420848903SChaotian Jing { 108520848903SChaotian Jing bool read; 108620848903SChaotian Jing 108720848903SChaotian Jing WARN_ON(host->data); 108820848903SChaotian Jing host->data = data; 108920848903SChaotian Jing read = data->flags & MMC_DATA_READ; 109020848903SChaotian Jing 109120848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 109220848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 109320848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 109420848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 109520848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 109620848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 109720848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 109820848903SChaotian Jing } 109920848903SChaotian Jing 110020848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 110120848903SChaotian Jing struct mmc_command *cmd) 110220848903SChaotian Jing { 110320848903SChaotian Jing u32 *rsp = cmd->resp; 110420848903SChaotian Jing 110520848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 110620848903SChaotian Jing 110720848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 110820848903SChaotian Jing cmd->error = 0; 110920848903SChaotian Jing } else { 111020848903SChaotian Jing msdc_reset_hw(host); 111120848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 111220848903SChaotian Jing cmd->error = -EILSEQ; 111320848903SChaotian Jing host->error |= REQ_STOP_EIO; 111420848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 111520848903SChaotian Jing cmd->error = -ETIMEDOUT; 111620848903SChaotian Jing host->error |= REQ_STOP_TMO; 111720848903SChaotian Jing } 111820848903SChaotian Jing dev_err(host->dev, 111920848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 112020848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 112120848903SChaotian Jing } 112220848903SChaotian Jing return cmd->error; 112320848903SChaotian Jing } 112420848903SChaotian Jing 11256ec5a7b7SLee Jones /* 11269e2582e5Syong mao * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 11279e2582e5Syong mao * 11289e2582e5Syong mao * Host controller may lost interrupt in some special case. 11299e2582e5Syong mao * Add SDIO irq recheck mechanism to make sure all interrupts 11309e2582e5Syong mao * can be processed immediately 11319e2582e5Syong mao */ 11329e2582e5Syong mao static void msdc_recheck_sdio_irq(struct msdc_host *host) 11339e2582e5Syong mao { 11340caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 11359e2582e5Syong mao u32 reg_int, reg_inten, reg_ps; 11369e2582e5Syong mao 11370caf60c4SAmey Narkhede if (mmc->caps & MMC_CAP_SDIO_IRQ) { 11389e2582e5Syong mao reg_inten = readl(host->base + MSDC_INTEN); 11399e2582e5Syong mao if (reg_inten & MSDC_INTEN_SDIOIRQ) { 11409e2582e5Syong mao reg_int = readl(host->base + MSDC_INT); 11419e2582e5Syong mao reg_ps = readl(host->base + MSDC_PS); 11429e2582e5Syong mao if (!(reg_int & MSDC_INT_SDIOIRQ || 11439e2582e5Syong mao reg_ps & MSDC_PS_DATA1)) { 11449e2582e5Syong mao __msdc_enable_sdio_irq(host, 0); 11450caf60c4SAmey Narkhede sdio_signal_irq(mmc); 11469e2582e5Syong mao } 11479e2582e5Syong mao } 11489e2582e5Syong mao } 11499e2582e5Syong mao } 11509e2582e5Syong mao 1151d74179b8SChanWoo Lee static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 115220848903SChaotian Jing { 115320848903SChaotian Jing if (host->error) 115420848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 115520848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 115620848903SChaotian Jing } 115720848903SChaotian Jing 115820848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 115920848903SChaotian Jing { 116020848903SChaotian Jing unsigned long flags; 116120848903SChaotian Jing 11620354ca6eSChaotian Jing /* 11630354ca6eSChaotian Jing * No need check the return value of cancel_delayed_work, as only ONE 11640354ca6eSChaotian Jing * path will go here! 11650354ca6eSChaotian Jing */ 11660354ca6eSChaotian Jing cancel_delayed_work(&host->req_timeout); 11670354ca6eSChaotian Jing 116820848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 116920848903SChaotian Jing host->mrq = NULL; 117020848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 117120848903SChaotian Jing 1172d74179b8SChanWoo Lee msdc_track_cmd_data(host, mrq->cmd); 117320848903SChaotian Jing if (mrq->data) 117415107135SYue Hu msdc_unprepare_data(host, mrq->data); 117520314ce3Sjjian zhou if (host->error) 117620314ce3Sjjian zhou msdc_reset_hw(host); 11770caf60c4SAmey Narkhede mmc_request_done(mmc_from_priv(host), mrq); 11789e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 11799e2582e5Syong mao msdc_recheck_sdio_irq(host); 118020848903SChaotian Jing } 118120848903SChaotian Jing 118220848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 118320848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 118420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 118520848903SChaotian Jing { 118620848903SChaotian Jing bool done = false; 118720848903SChaotian Jing bool sbc_error; 118820848903SChaotian Jing unsigned long flags; 11890354ca6eSChaotian Jing u32 *rsp; 119020848903SChaotian Jing 119120848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 119220848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 119320848903SChaotian Jing | MSDC_INT_ACMDTMO))) 119420848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 119520848903SChaotian Jing 119620848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 119720848903SChaotian Jing 119820848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 119920848903SChaotian Jing | MSDC_INT_RSPCRCERR 120020848903SChaotian Jing | MSDC_INT_CMDTMO))) 120120848903SChaotian Jing return done; 120220848903SChaotian Jing 120320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 120420848903SChaotian Jing done = !host->cmd; 120520848903SChaotian Jing host->cmd = NULL; 120620848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 120720848903SChaotian Jing 120820848903SChaotian Jing if (done) 120920848903SChaotian Jing return true; 12100354ca6eSChaotian Jing rsp = cmd->resp; 121120848903SChaotian Jing 1212726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 121320848903SChaotian Jing 121420848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 121520848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 121620848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 121720848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 121820848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 121920848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 122020848903SChaotian Jing } else { 122120848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 122220848903SChaotian Jing } 122320848903SChaotian Jing } 122420848903SChaotian Jing 122520848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1226da6e0f70SChaotian Jing if (events & MSDC_INT_CMDTMO || 1227*b98e7e8dSChanWoo Lee (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) 1228ddc71387SChaotian Jing /* 1229ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 12304b323f02SYu Zhe * may have already come when cmd19/cmd21 gets response 1231da6e0f70SChaotian Jing * CRC error. 1232ddc71387SChaotian Jing */ 123320848903SChaotian Jing msdc_reset_hw(host); 123420848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 123520848903SChaotian Jing cmd->error = -EILSEQ; 123620848903SChaotian Jing host->error |= REQ_CMD_EIO; 123720848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 123820848903SChaotian Jing cmd->error = -ETIMEDOUT; 123920848903SChaotian Jing host->error |= REQ_CMD_TMO; 124020848903SChaotian Jing } 124120848903SChaotian Jing } 124220848903SChaotian Jing if (cmd->error) 124320848903SChaotian Jing dev_dbg(host->dev, 124420848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 124520848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 124620848903SChaotian Jing cmd->error); 124720848903SChaotian Jing 124820848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 124920848903SChaotian Jing return true; 125020848903SChaotian Jing } 125120848903SChaotian Jing 125220848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 125320848903SChaotian Jing * is correct before issue a request. but host design do below 125420848903SChaotian Jing * checks recommended. 125520848903SChaotian Jing */ 125620848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 125720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 125820848903SChaotian Jing { 1259ffaea6ebSAngeloGioacchino Del Regno u32 val; 1260ffaea6ebSAngeloGioacchino Del Regno int ret; 126120848903SChaotian Jing 1262ffaea6ebSAngeloGioacchino Del Regno /* The max busy time we can endure is 20ms */ 1263ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1264ffaea6ebSAngeloGioacchino Del Regno !(val & SDC_STS_CMDBUSY), 1, 20000); 1265ffaea6ebSAngeloGioacchino Del Regno if (ret) { 126620848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 126720848903SChaotian Jing host->error |= REQ_CMD_BUSY; 126820848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 126920848903SChaotian Jing return false; 127020848903SChaotian Jing } 127120848903SChaotian Jing 127220848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 127320848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 1274ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1275ffaea6ebSAngeloGioacchino Del Regno !(val & SDC_STS_SDCBUSY), 1, 20000); 1276ffaea6ebSAngeloGioacchino Del Regno if (ret) { 127720848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 127820848903SChaotian Jing host->error |= REQ_CMD_BUSY; 127920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 128020848903SChaotian Jing return false; 128120848903SChaotian Jing } 128220848903SChaotian Jing } 128320848903SChaotian Jing return true; 128420848903SChaotian Jing } 128520848903SChaotian Jing 128620848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 128720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 128820848903SChaotian Jing { 128920848903SChaotian Jing u32 rawcmd; 12905215b2e9Sjjian zhou unsigned long flags; 129120848903SChaotian Jing 129220848903SChaotian Jing WARN_ON(host->cmd); 129320848903SChaotian Jing host->cmd = cmd; 129420848903SChaotian Jing 1295f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 129620848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 129720848903SChaotian Jing return; 129820848903SChaotian Jing 129920848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 130020848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 130120848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 130220848903SChaotian Jing msdc_reset_hw(host); 130320848903SChaotian Jing } 130420848903SChaotian Jing 130520848903SChaotian Jing cmd->error = 0; 130620848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 130720848903SChaotian Jing 13085215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 1309726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 13105215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 13115215b2e9Sjjian zhou 131220848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 131320848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 131420848903SChaotian Jing } 131520848903SChaotian Jing 131620848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 131720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 131820848903SChaotian Jing { 1319ddc71387SChaotian Jing if ((cmd->error && 1320ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1321*b98e7e8dSChanWoo Lee (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || 1322ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 132320848903SChaotian Jing msdc_request_done(host, mrq); 132420848903SChaotian Jing else if (cmd == mrq->sbc) 132520848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 132620848903SChaotian Jing else if (!cmd->data) 132720848903SChaotian Jing msdc_request_done(host, mrq); 132820848903SChaotian Jing else 1329d74179b8SChanWoo Lee msdc_start_data(host, cmd, cmd->data); 133020848903SChaotian Jing } 133120848903SChaotian Jing 133220848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 133320848903SChaotian Jing { 133420848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 133520848903SChaotian Jing 133620848903SChaotian Jing host->error = 0; 133720848903SChaotian Jing WARN_ON(host->mrq); 133820848903SChaotian Jing host->mrq = mrq; 133920848903SChaotian Jing 134020848903SChaotian Jing if (mrq->data) 134115107135SYue Hu msdc_prepare_data(host, mrq->data); 134220848903SChaotian Jing 134320848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 134420848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 134520848903SChaotian Jing * use HW option, otherwise use SW option 134620848903SChaotian Jing */ 134720848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 134820848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 134920848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 135020848903SChaotian Jing else 135120848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 135220848903SChaotian Jing } 135320848903SChaotian Jing 1354d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 135520848903SChaotian Jing { 135620848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 135720848903SChaotian Jing struct mmc_data *data = mrq->data; 135820848903SChaotian Jing 135920848903SChaotian Jing if (!data) 136020848903SChaotian Jing return; 136120848903SChaotian Jing 136215107135SYue Hu msdc_prepare_data(host, data); 136320848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 136420848903SChaotian Jing } 136520848903SChaotian Jing 136620848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 136720848903SChaotian Jing int err) 136820848903SChaotian Jing { 136920848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 137015107135SYue Hu struct mmc_data *data = mrq->data; 137120848903SChaotian Jing 137220848903SChaotian Jing if (!data) 137320848903SChaotian Jing return; 137415107135SYue Hu 137520848903SChaotian Jing if (data->host_cookie) { 137620848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 137715107135SYue Hu msdc_unprepare_data(host, data); 137820848903SChaotian Jing } 137920848903SChaotian Jing } 138020848903SChaotian Jing 1381f0ed43edSYue Hu static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 138220848903SChaotian Jing { 138320848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 13846397b7f5SChaotian Jing !mrq->sbc) 138520848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 138620848903SChaotian Jing else 138720848903SChaotian Jing msdc_request_done(host, mrq); 138820848903SChaotian Jing } 138920848903SChaotian Jing 139089bcd9a6SMengqi Zhang static void msdc_data_xfer_done(struct msdc_host *host, u32 events, 139120848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 139220848903SChaotian Jing { 13930354ca6eSChaotian Jing struct mmc_command *stop; 139420848903SChaotian Jing unsigned long flags; 139520848903SChaotian Jing bool done; 139620848903SChaotian Jing unsigned int check_data = events & 139720848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 139820848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 139920848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 1400ffaea6ebSAngeloGioacchino Del Regno u32 val; 1401ffaea6ebSAngeloGioacchino Del Regno int ret; 140220848903SChaotian Jing 140320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 140420848903SChaotian Jing done = !host->data; 140520848903SChaotian Jing if (check_data) 140620848903SChaotian Jing host->data = NULL; 140720848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 140820848903SChaotian Jing 140920848903SChaotian Jing if (done) 141089bcd9a6SMengqi Zhang return; 14110354ca6eSChaotian Jing stop = data->stop; 141220848903SChaotian Jing 141320848903SChaotian Jing if (check_data || (stop && stop->error)) { 141420848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 141520848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 141620848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 141720848903SChaotian Jing 1); 1418ffaea6ebSAngeloGioacchino Del Regno 141989bcd9a6SMengqi Zhang ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, 142089bcd9a6SMengqi Zhang !(val & MSDC_DMA_CTRL_STOP), 1, 20000); 142189bcd9a6SMengqi Zhang if (ret) 142289bcd9a6SMengqi Zhang dev_dbg(host->dev, "DMA stop timed out\n"); 142389bcd9a6SMengqi Zhang 1424ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1425ffaea6ebSAngeloGioacchino Del Regno !(val & MSDC_DMA_CFG_STS), 1, 20000); 142689bcd9a6SMengqi Zhang if (ret) 142789bcd9a6SMengqi Zhang dev_dbg(host->dev, "DMA inactive timed out\n"); 1428ffaea6ebSAngeloGioacchino Del Regno 142920848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 143020848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 143120848903SChaotian Jing 143220848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 143320848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 143420848903SChaotian Jing } else { 14352066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 143620848903SChaotian Jing msdc_reset_hw(host); 143720848903SChaotian Jing host->error |= REQ_DAT_ERR; 143820848903SChaotian Jing data->bytes_xfered = 0; 143920848903SChaotian Jing 144020848903SChaotian Jing if (events & MSDC_INT_DATTMO) 144120848903SChaotian Jing data->error = -ETIMEDOUT; 14426397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 14436397b7f5SChaotian Jing data->error = -EILSEQ; 144420848903SChaotian Jing 14452066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 144620848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 14472066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 144820848903SChaotian Jing (int)data->error, data->bytes_xfered); 144920848903SChaotian Jing } 145020848903SChaotian Jing 1451f0ed43edSYue Hu msdc_data_xfer_next(host, mrq); 145220848903SChaotian Jing } 145320848903SChaotian Jing } 145420848903SChaotian Jing 145520848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 145620848903SChaotian Jing { 145720848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 145820848903SChaotian Jing 145920848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 146020848903SChaotian Jing 146120848903SChaotian Jing switch (width) { 146220848903SChaotian Jing default: 146320848903SChaotian Jing case MMC_BUS_WIDTH_1: 146420848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 146520848903SChaotian Jing break; 146620848903SChaotian Jing case MMC_BUS_WIDTH_4: 146720848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 146820848903SChaotian Jing break; 146920848903SChaotian Jing case MMC_BUS_WIDTH_8: 147020848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 147120848903SChaotian Jing break; 147220848903SChaotian Jing } 147320848903SChaotian Jing 147420848903SChaotian Jing writel(val, host->base + SDC_CFG); 147520848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 147620848903SChaotian Jing } 147720848903SChaotian Jing 147820848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 147920848903SChaotian Jing { 148020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14819cbe0fc8SMarek Vasut int ret; 148220848903SChaotian Jing 148320848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1484fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1485fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 148620848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 148720848903SChaotian Jing return -EINVAL; 148820848903SChaotian Jing } 148920848903SChaotian Jing 1490fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 14919cbe0fc8SMarek Vasut if (ret < 0) { 1492fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1493fac49ce5SNicolas Boichat ret, ios->signal_voltage); 14949cbe0fc8SMarek Vasut return ret; 14959cbe0fc8SMarek Vasut } 14969cbe0fc8SMarek Vasut 149720848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 149820848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 149920848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 150020848903SChaotian Jing else 150120848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 150220848903SChaotian Jing } 15039cbe0fc8SMarek Vasut return 0; 150420848903SChaotian Jing } 150520848903SChaotian Jing 150620848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 150720848903SChaotian Jing { 150820848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 150920848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 151020848903SChaotian Jing 15113bc702edSyong mao /* only check if data0 is low */ 15123bc702edSyong mao return !(status & BIT(16)); 151320848903SChaotian Jing } 151420848903SChaotian Jing 151520848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 151620848903SChaotian Jing { 151720848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 151820848903SChaotian Jing req_timeout.work); 151920848903SChaotian Jing 152020848903SChaotian Jing /* simulate HW timeout status */ 152120848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 152220848903SChaotian Jing if (host->mrq) { 152320848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 152420848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 152520848903SChaotian Jing if (host->cmd) { 152620848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 152720848903SChaotian Jing __func__, host->cmd->opcode); 152820848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 152920848903SChaotian Jing host->cmd); 153020848903SChaotian Jing } else if (host->data) { 153120848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 153220848903SChaotian Jing __func__, host->mrq->cmd->opcode, 153320848903SChaotian Jing host->data->blocks); 153420848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 153520848903SChaotian Jing host->data); 153620848903SChaotian Jing } 153720848903SChaotian Jing } 153820848903SChaotian Jing } 153920848903SChaotian Jing 15408a5df8acSjjian zhou static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 15418a5df8acSjjian zhou { 15428a5df8acSjjian zhou if (enb) { 15438a5df8acSjjian zhou sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15448a5df8acSjjian zhou sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15459e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 15469e2582e5Syong mao msdc_recheck_sdio_irq(host); 15478a5df8acSjjian zhou } else { 15488a5df8acSjjian zhou sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15498a5df8acSjjian zhou sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15508a5df8acSjjian zhou } 15518a5df8acSjjian zhou } 15528a5df8acSjjian zhou 15538a5df8acSjjian zhou static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 15545215b2e9Sjjian zhou { 15555215b2e9Sjjian zhou struct msdc_host *host = mmc_priv(mmc); 1556527f36f5SAxe Yang unsigned long flags; 1557527f36f5SAxe Yang int ret; 15585215b2e9Sjjian zhou 15595215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 15608a5df8acSjjian zhou __msdc_enable_sdio_irq(host, enb); 15615215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 15625215b2e9Sjjian zhou 1563527f36f5SAxe Yang if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { 1564527f36f5SAxe Yang if (enb) { 1565527f36f5SAxe Yang /* 1566527f36f5SAxe Yang * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to 1567527f36f5SAxe Yang * GPIO mode. We need to restore it to SDIO DAT1 mode after that. 1568527f36f5SAxe Yang * Since the current pinstate is pins_uhs, to ensure pinctrl select take 1569527f36f5SAxe Yang * affect successfully, we change the pinstate to pins_eint firstly. 1570527f36f5SAxe Yang */ 1571527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_eint); 1572527f36f5SAxe Yang ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); 1573527f36f5SAxe Yang 1574527f36f5SAxe Yang if (ret) { 1575527f36f5SAxe Yang dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); 1576527f36f5SAxe Yang host->pins_eint = NULL; 15775215b2e9Sjjian zhou pm_runtime_get_noresume(host->dev); 1578527f36f5SAxe Yang } else { 1579527f36f5SAxe Yang dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); 1580527f36f5SAxe Yang } 1581527f36f5SAxe Yang 1582527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_uhs); 1583527f36f5SAxe Yang } else { 1584527f36f5SAxe Yang dev_pm_clear_wake_irq(host->dev); 1585527f36f5SAxe Yang } 1586527f36f5SAxe Yang } else { 1587527f36f5SAxe Yang if (enb) { 1588527f36f5SAxe Yang /* Ensure host->pins_eint is NULL */ 1589527f36f5SAxe Yang host->pins_eint = NULL; 1590527f36f5SAxe Yang pm_runtime_get_noresume(host->dev); 1591527f36f5SAxe Yang } else { 15925215b2e9Sjjian zhou pm_runtime_put_noidle(host->dev); 15935215b2e9Sjjian zhou } 1594527f36f5SAxe Yang } 1595527f36f5SAxe Yang } 15965215b2e9Sjjian zhou 159788bd652bSChun-Hung Wu static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 159888bd652bSChun-Hung Wu { 15990caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 160088bd652bSChun-Hung Wu int cmd_err = 0, dat_err = 0; 160188bd652bSChun-Hung Wu 160288bd652bSChun-Hung Wu if (intsts & MSDC_INT_RSPCRCERR) { 160388bd652bSChun-Hung Wu cmd_err = -EILSEQ; 160488bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD CRC ERR", __func__); 160588bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_CMDTMO) { 160688bd652bSChun-Hung Wu cmd_err = -ETIMEDOUT; 160788bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 160888bd652bSChun-Hung Wu } 160988bd652bSChun-Hung Wu 161088bd652bSChun-Hung Wu if (intsts & MSDC_INT_DATCRCERR) { 161188bd652bSChun-Hung Wu dat_err = -EILSEQ; 161288bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA CRC ERR", __func__); 161388bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_DATTMO) { 161488bd652bSChun-Hung Wu dat_err = -ETIMEDOUT; 161588bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 161688bd652bSChun-Hung Wu } 161788bd652bSChun-Hung Wu 161888bd652bSChun-Hung Wu if (cmd_err || dat_err) { 161988bd652bSChun-Hung Wu dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 162088bd652bSChun-Hung Wu cmd_err, dat_err, intsts); 162188bd652bSChun-Hung Wu } 162288bd652bSChun-Hung Wu 16230caf60c4SAmey Narkhede return cqhci_irq(mmc, 0, cmd_err, dat_err); 162488bd652bSChun-Hung Wu } 162588bd652bSChun-Hung Wu 162620848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 162720848903SChaotian Jing { 162820848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 16290caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 163020848903SChaotian Jing 163120848903SChaotian Jing while (true) { 163220848903SChaotian Jing struct mmc_request *mrq; 163320848903SChaotian Jing struct mmc_command *cmd; 163420848903SChaotian Jing struct mmc_data *data; 163520848903SChaotian Jing u32 events, event_mask; 163620848903SChaotian Jing 16379baf7c5eSTian Tao spin_lock(&host->lock); 163820848903SChaotian Jing events = readl(host->base + MSDC_INT); 163920848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 16408a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 16418a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 0); 164220848903SChaotian Jing /* clear interrupts */ 164320848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 164420848903SChaotian Jing 164520848903SChaotian Jing mrq = host->mrq; 164620848903SChaotian Jing cmd = host->cmd; 164720848903SChaotian Jing data = host->data; 16489baf7c5eSTian Tao spin_unlock(&host->lock); 164920848903SChaotian Jing 16508a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 16510caf60c4SAmey Narkhede sdio_signal_irq(mmc); 16525215b2e9Sjjian zhou 1653d087bde5SNeilBrown if ((events & event_mask) & MSDC_INT_CDSC) { 1654d087bde5SNeilBrown if (host->internal_cd) 16550caf60c4SAmey Narkhede mmc_detect_change(mmc, msecs_to_jiffies(20)); 1656d087bde5SNeilBrown events &= ~MSDC_INT_CDSC; 1657d087bde5SNeilBrown } 1658d087bde5SNeilBrown 16595215b2e9Sjjian zhou if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 166020848903SChaotian Jing break; 166120848903SChaotian Jing 16620caf60c4SAmey Narkhede if ((mmc->caps2 & MMC_CAP2_CQE) && 166388bd652bSChun-Hung Wu (events & MSDC_INT_CMDQ)) { 166488bd652bSChun-Hung Wu msdc_cmdq_irq(host, events); 166588bd652bSChun-Hung Wu /* clear interrupts */ 166688bd652bSChun-Hung Wu writel(events, host->base + MSDC_INT); 166788bd652bSChun-Hung Wu return IRQ_HANDLED; 166888bd652bSChun-Hung Wu } 166988bd652bSChun-Hung Wu 167020848903SChaotian Jing if (!mrq) { 167120848903SChaotian Jing dev_err(host->dev, 167220848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 167320848903SChaotian Jing __func__, events, event_mask); 167420848903SChaotian Jing WARN_ON(1); 167520848903SChaotian Jing break; 167620848903SChaotian Jing } 167720848903SChaotian Jing 167820848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 167920848903SChaotian Jing 168020848903SChaotian Jing if (cmd) 168120848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 168220848903SChaotian Jing else if (data) 168320848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 168420848903SChaotian Jing } 168520848903SChaotian Jing 168620848903SChaotian Jing return IRQ_HANDLED; 168720848903SChaotian Jing } 168820848903SChaotian Jing 168920848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 169020848903SChaotian Jing { 169120848903SChaotian Jing u32 val; 169239add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 169383b27217SAngeloGioacchino Del Regno struct mmc_host *mmc = mmc_from_priv(host); 169420848903SChaotian Jing 1695855d388dSWenbin Mei if (host->reset) { 1696855d388dSWenbin Mei reset_control_assert(host->reset); 1697855d388dSWenbin Mei usleep_range(10, 50); 1698855d388dSWenbin Mei reset_control_deassert(host->reset); 1699855d388dSWenbin Mei } 1700855d388dSWenbin Mei 170120848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 170220848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 170320848903SChaotian Jing 170420848903SChaotian Jing /* Reset */ 170520848903SChaotian Jing msdc_reset_hw(host); 170620848903SChaotian Jing 170720848903SChaotian Jing /* Disable and clear all interrupts */ 170820848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 170920848903SChaotian Jing val = readl(host->base + MSDC_INT); 171020848903SChaotian Jing writel(val, host->base + MSDC_INT); 171120848903SChaotian Jing 1712d087bde5SNeilBrown /* Configure card detection */ 1713d087bde5SNeilBrown if (host->internal_cd) { 1714d087bde5SNeilBrown sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1715d087bde5SNeilBrown DEFAULT_DEBOUNCE); 1716d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1717d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1718d087bde5SNeilBrown sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1719d087bde5SNeilBrown } else { 1720d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1721d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1722d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1723d087bde5SNeilBrown } 1724d087bde5SNeilBrown 1725a2e6d1f6SChaotian Jing if (host->top_base) { 1726a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CONTROL); 1727a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CMD); 1728a2e6d1f6SChaotian Jing } else { 172939add252SChaotian Jing writel(0, host->base + tune_reg); 1730a2e6d1f6SChaotian Jing } 173120848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 17326397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 17336397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 173420848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 17352fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 17366397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1737d9dcbfc8SChaotian Jing 1738d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1739d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1740d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1741d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1742d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1743d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1744d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1745d9dcbfc8SChaotian Jing } 1746d9dcbfc8SChaotian Jing 1747acde28c4SChaotian Jing if (host->dev_comp->busy_check) 17484fe54318SAngeloGioacchino Del Regno sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1749d9dcbfc8SChaotian Jing 17502fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 17512fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17522fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1753d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1754a2e6d1f6SChaotian Jing if (host->top_base) 1755a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1756a2e6d1f6SChaotian Jing SDC_RX_ENH_EN); 1757a2e6d1f6SChaotian Jing else 1758d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1759d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1760d9dcbfc8SChaotian Jing } else { 17612fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17622fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 17632fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17642fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1765d9dcbfc8SChaotian Jing } 17662fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 17672fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 17682fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 17692fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17702fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 17712fea5819SChaotian Jing } 17722fea5819SChaotian Jing 17732a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17742a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17752a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 17762fea5819SChaotian Jing if (host->dev_comp->data_tune) { 1777a2e6d1f6SChaotian Jing if (host->top_base) { 1778a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1779a2e6d1f6SChaotian Jing PAD_DAT_RD_RXDLY_SEL); 1780a2e6d1f6SChaotian Jing sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1781a2e6d1f6SChaotian Jing DATA_K_VALUE_SEL); 1782a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1783a2e6d1f6SChaotian Jing PAD_CMD_RD_RXDLY_SEL); 1784a2e6d1f6SChaotian Jing } else { 17852fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 1786a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RD_SEL | 1787a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_CMD_SEL); 1788a2e6d1f6SChaotian Jing } 17892fea5819SChaotian Jing } else { 17902fea5819SChaotian Jing /* choose clock tune */ 1791a2e6d1f6SChaotian Jing if (host->top_base) 1792a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1793a2e6d1f6SChaotian Jing PAD_RXDLY_SEL); 1794a2e6d1f6SChaotian Jing else 1795a2e6d1f6SChaotian Jing sdr_set_bits(host->base + tune_reg, 1796a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RXDLYSEL); 17972fea5819SChaotian Jing } 17986397b7f5SChaotian Jing 179983b27217SAngeloGioacchino Del Regno if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 180083b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 180183b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 180283b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 180383b27217SAngeloGioacchino Del Regno } else { 180483b27217SAngeloGioacchino Del Regno /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 180520848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 180620848903SChaotian Jing 18075215b2e9Sjjian zhou /* Config SDIO device detect interrupt function */ 180820848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 180926c71a13Syong mao sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 181083b27217SAngeloGioacchino Del Regno } 181120848903SChaotian Jing 181220848903SChaotian Jing /* Configure to default data timeout */ 181320848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 181420848903SChaotian Jing 181586beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 18162fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1817a2e6d1f6SChaotian Jing if (host->top_base) { 1818a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_control = 1819a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1820a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_cmd = 1821a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1822a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = 1823a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1824a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = 1825a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1826a2e6d1f6SChaotian Jing } else { 1827a2e6d1f6SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 18282fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1829a2e6d1f6SChaotian Jing } 183020848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 183120848903SChaotian Jing } 183220848903SChaotian Jing 183320848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 183420848903SChaotian Jing { 183520848903SChaotian Jing u32 val; 1836d087bde5SNeilBrown 1837d087bde5SNeilBrown if (host->internal_cd) { 1838d087bde5SNeilBrown /* Disabled card-detect */ 1839d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1840d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1841d087bde5SNeilBrown } 1842d087bde5SNeilBrown 184320848903SChaotian Jing /* Disable and clear all interrupts */ 184420848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 184520848903SChaotian Jing 184620848903SChaotian Jing val = readl(host->base + MSDC_INT); 184720848903SChaotian Jing writel(val, host->base + MSDC_INT); 184820848903SChaotian Jing } 184920848903SChaotian Jing 185020848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 185120848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 185220848903SChaotian Jing { 185320848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 185420848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 18552a9bde19SChaotian Jing dma_addr_t dma_addr; 185620848903SChaotian Jing int i; 185720848903SChaotian Jing 185862b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 185920848903SChaotian Jing 18602a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 186120848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 186262b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 186362b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 186462b0d27aSChaotian Jing */ 18652a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 18662a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18672a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18682a9bde19SChaotian Jing 18692a9bde19SChaotian Jing dma_addr = dma->bd_addr; 18702a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 18712a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18722a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 18732a9bde19SChaotian Jing 187420848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 18752a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 18762a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 18772a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 18782a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18792a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18802a9bde19SChaotian Jing } 188120848903SChaotian Jing } 188220848903SChaotian Jing 188320848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 188420848903SChaotian Jing { 188520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 188620848903SChaotian Jing int ret; 188720848903SChaotian Jing 188820848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 188920848903SChaotian Jing 189020848903SChaotian Jing /* Suspend/Resume will do power off/on */ 189120848903SChaotian Jing switch (ios->power_mode) { 189220848903SChaotian Jing case MMC_POWER_UP: 189320848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 18946397b7f5SChaotian Jing msdc_init_hw(host); 189520848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 189620848903SChaotian Jing ios->vdd); 189720848903SChaotian Jing if (ret) { 189820848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1899567979fbSUlf Hansson return; 190020848903SChaotian Jing } 190120848903SChaotian Jing } 190220848903SChaotian Jing break; 190320848903SChaotian Jing case MMC_POWER_ON: 190420848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 190520848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 190620848903SChaotian Jing if (ret) 190720848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 190820848903SChaotian Jing else 190920848903SChaotian Jing host->vqmmc_enabled = true; 191020848903SChaotian Jing } 191120848903SChaotian Jing break; 191220848903SChaotian Jing case MMC_POWER_OFF: 191320848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 191420848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 191520848903SChaotian Jing 191620848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 191720848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 191820848903SChaotian Jing host->vqmmc_enabled = false; 191920848903SChaotian Jing } 192020848903SChaotian Jing break; 192120848903SChaotian Jing default: 192220848903SChaotian Jing break; 192320848903SChaotian Jing } 192420848903SChaotian Jing 19256e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 19266e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 192720848903SChaotian Jing } 192820848903SChaotian Jing 19296397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 19306397b7f5SChaotian Jing { 19316397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 19324fe54318SAngeloGioacchino Del Regno return delay & BIT(bit); 19336397b7f5SChaotian Jing } 19346397b7f5SChaotian Jing 19356397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 19366397b7f5SChaotian Jing { 19376397b7f5SChaotian Jing int i; 19386397b7f5SChaotian Jing 19396397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 19406397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 19416397b7f5SChaotian Jing return i; 19426397b7f5SChaotian Jing } 19436397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 19446397b7f5SChaotian Jing } 19456397b7f5SChaotian Jing 19466397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 19476397b7f5SChaotian Jing { 19486397b7f5SChaotian Jing int start = 0, len = 0; 19496397b7f5SChaotian Jing int start_final = 0, len_final = 0; 19506397b7f5SChaotian Jing u8 final_phase = 0xff; 195162d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 19526397b7f5SChaotian Jing 19536397b7f5SChaotian Jing if (delay == 0) { 19546397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 19556397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 19566397b7f5SChaotian Jing return delay_phase; 19576397b7f5SChaotian Jing } 19586397b7f5SChaotian Jing 19596397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 19606397b7f5SChaotian Jing len = get_delay_len(delay, start); 19616397b7f5SChaotian Jing if (len_final < len) { 19626397b7f5SChaotian Jing start_final = start; 19636397b7f5SChaotian Jing len_final = len; 19646397b7f5SChaotian Jing } 19656397b7f5SChaotian Jing start += len ? len : 1; 19661ede5cb8Syong mao if (len >= 12 && start_final < 4) 19676397b7f5SChaotian Jing break; 19686397b7f5SChaotian Jing } 19696397b7f5SChaotian Jing 19706397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 19716397b7f5SChaotian Jing if (start_final == 0) 19726397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 19736397b7f5SChaotian Jing else 19746397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 197533106d78SAlexandre Bailon dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 19766397b7f5SChaotian Jing delay, len_final, final_phase); 19776397b7f5SChaotian Jing 19786397b7f5SChaotian Jing delay_phase.maxlen = len_final; 19796397b7f5SChaotian Jing delay_phase.start = start_final; 19806397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 19816397b7f5SChaotian Jing return delay_phase; 19826397b7f5SChaotian Jing } 19836397b7f5SChaotian Jing 1984fd82cc30SChaotian Jing static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1985fd82cc30SChaotian Jing { 1986fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1987fd82cc30SChaotian Jing 1988fd82cc30SChaotian Jing if (host->top_base) 1989fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1990fd82cc30SChaotian Jing value); 1991fd82cc30SChaotian Jing else 1992fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1993fd82cc30SChaotian Jing value); 1994fd82cc30SChaotian Jing } 1995fd82cc30SChaotian Jing 1996fd82cc30SChaotian Jing static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1997fd82cc30SChaotian Jing { 1998fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1999fd82cc30SChaotian Jing 2000fd82cc30SChaotian Jing if (host->top_base) 2001fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2002fd82cc30SChaotian Jing PAD_DAT_RD_RXDLY, value); 2003fd82cc30SChaotian Jing else 2004fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 2005fd82cc30SChaotian Jing value); 2006fd82cc30SChaotian Jing } 2007fd82cc30SChaotian Jing 20086397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 20096397b7f5SChaotian Jing { 20106397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 20116397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 2012ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 20131ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 20146397b7f5SChaotian Jing u8 final_delay, final_maxlen; 20151ede5cb8Syong mao u32 internal_delay = 0; 201639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 20176397b7f5SChaotian Jing int cmd_err; 20181ede5cb8Syong mao int i, j; 20191ede5cb8Syong mao 20201ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 20211ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 202239add252SChaotian Jing sdr_set_field(host->base + tune_reg, 20231ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 20241ede5cb8Syong mao host->hs200_cmd_int_delay); 20256397b7f5SChaotian Jing 20266397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20276397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2028fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 20291ede5cb8Syong mao /* 20301ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20311ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20321ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20331ede5cb8Syong mao */ 20341ede5cb8Syong mao for (j = 0; j < 3; j++) { 20356397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 20361ede5cb8Syong mao if (!cmd_err) { 20374fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 20381ede5cb8Syong mao } else { 20394fe54318SAngeloGioacchino Del Regno rise_delay &= ~BIT(i); 20401ede5cb8Syong mao break; 20411ede5cb8Syong mao } 20421ede5cb8Syong mao } 20436397b7f5SChaotian Jing } 2044ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2045ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 20466b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 20476b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2048ae9c657eSChaotian Jing goto skip_fall; 20496397b7f5SChaotian Jing 20506397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20516397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2052fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 20531ede5cb8Syong mao /* 20541ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20551ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20561ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20571ede5cb8Syong mao */ 20581ede5cb8Syong mao for (j = 0; j < 3; j++) { 20596397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 20601ede5cb8Syong mao if (!cmd_err) { 20614fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 20621ede5cb8Syong mao } else { 20634fe54318SAngeloGioacchino Del Regno fall_delay &= ~BIT(i); 20641ede5cb8Syong mao break; 20651ede5cb8Syong mao } 20661ede5cb8Syong mao } 20676397b7f5SChaotian Jing } 20686397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 20696397b7f5SChaotian Jing 2070ae9c657eSChaotian Jing skip_fall: 20716397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 20721ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 20731ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 20746397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 20756397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20766397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 20776397b7f5SChaotian Jing } else { 20786397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20796397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 20806397b7f5SChaotian Jing } 2081fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2082fd82cc30SChaotian Jing 20832fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 20841ede5cb8Syong mao goto skip_internal; 20856397b7f5SChaotian Jing 20861ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 208739add252SChaotian Jing sdr_set_field(host->base + tune_reg, 20881ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 20891ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20901ede5cb8Syong mao if (!cmd_err) 20914fe54318SAngeloGioacchino Del Regno internal_delay |= BIT(i); 20921ede5cb8Syong mao } 20931ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 20941ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 209539add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 20961ede5cb8Syong mao internal_delay_phase.final_phase); 20971ede5cb8Syong mao skip_internal: 20981ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20991ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 21001ede5cb8Syong mao } 21011ede5cb8Syong mao 21021ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 21031ede5cb8Syong mao { 21041ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 21051ede5cb8Syong mao u32 cmd_delay = 0; 21061ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 21071ede5cb8Syong mao u8 final_delay; 21081ede5cb8Syong mao int cmd_err; 21091ede5cb8Syong mao int i, j; 21101ede5cb8Syong mao 21111ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 21121ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 21138f34e5bdSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 21141ede5cb8Syong mao 21151ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 21161ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 21171ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 21181ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 21191ede5cb8Syong mao host->hs200_cmd_int_delay); 21201ede5cb8Syong mao 21211ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 21221ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 21231ede5cb8Syong mao else 21241ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 21251ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 21261ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 21271ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 21281ede5cb8Syong mao /* 21291ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 21301ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 21311ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 21321ede5cb8Syong mao */ 21331ede5cb8Syong mao for (j = 0; j < 3; j++) { 21341ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 21351ede5cb8Syong mao if (!cmd_err) { 21364fe54318SAngeloGioacchino Del Regno cmd_delay |= BIT(i); 21371ede5cb8Syong mao } else { 21384fe54318SAngeloGioacchino Del Regno cmd_delay &= ~BIT(i); 21391ede5cb8Syong mao break; 21401ede5cb8Syong mao } 21411ede5cb8Syong mao } 21421ede5cb8Syong mao } 21431ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 21441ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 21451ede5cb8Syong mao final_cmd_delay.final_phase); 21461ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 21471ede5cb8Syong mao 21481ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 21496397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 21506397b7f5SChaotian Jing } 21516397b7f5SChaotian Jing 21526397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 21536397b7f5SChaotian Jing { 21546397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 21556397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 2156ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 21576397b7f5SChaotian Jing u8 final_delay, final_maxlen; 21586397b7f5SChaotian Jing int i, ret; 21596397b7f5SChaotian Jing 2160d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2161d17bb71cSChaotian Jing host->latch_ck); 21626397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21636397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21646397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2165fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21666397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21676397b7f5SChaotian Jing if (!ret) 21684fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 21696397b7f5SChaotian Jing } 2170ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2171ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 21721ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 2173ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2174ae9c657eSChaotian Jing goto skip_fall; 21756397b7f5SChaotian Jing 21766397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21776397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21786397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2179fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21806397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21816397b7f5SChaotian Jing if (!ret) 21824fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 21836397b7f5SChaotian Jing } 21846397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 21856397b7f5SChaotian Jing 2186ae9c657eSChaotian Jing skip_fall: 21876397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 21886397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 21896397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21906397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21916397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 21926397b7f5SChaotian Jing } else { 21936397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21946397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21956397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 21966397b7f5SChaotian Jing } 2197fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 21986397b7f5SChaotian Jing 21991ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 22006397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 22016397b7f5SChaotian Jing } 22026397b7f5SChaotian Jing 220386601d0eSChaotian Jing /* 220486601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 220586601d0eSChaotian Jing * together, which can save the tuning time. 220686601d0eSChaotian Jing */ 220786601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 220886601d0eSChaotian Jing { 220986601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 221086601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 221186601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 221286601d0eSChaotian Jing u8 final_delay, final_maxlen; 221386601d0eSChaotian Jing int i, ret; 221486601d0eSChaotian Jing 221586601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 221686601d0eSChaotian Jing host->latch_ck); 221786601d0eSChaotian Jing 221886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 221986601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 222086601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 222186601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2222fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2223fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 222486601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 222586601d0eSChaotian Jing if (!ret) 22264fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 222786601d0eSChaotian Jing } 222886601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 222986601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 223086601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 223186601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 223286601d0eSChaotian Jing goto skip_fall; 223386601d0eSChaotian Jing 223486601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 223586601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 223686601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 223786601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2238fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2239fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 224086601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 224186601d0eSChaotian Jing if (!ret) 22424fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 224386601d0eSChaotian Jing } 224486601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 224586601d0eSChaotian Jing 224686601d0eSChaotian Jing skip_fall: 224786601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 224886601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 224986601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 225086601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 225186601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 225286601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 225386601d0eSChaotian Jing } else { 225486601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 225586601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 225686601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 225786601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 225886601d0eSChaotian Jing } 225986601d0eSChaotian Jing 2260fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2261fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 2262a2e6d1f6SChaotian Jing 226386601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 226486601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 226586601d0eSChaotian Jing } 226686601d0eSChaotian Jing 22676397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 22686397b7f5SChaotian Jing { 22696397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22706397b7f5SChaotian Jing int ret; 227139add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 22726397b7f5SChaotian Jing 227386601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 227486601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 227586601d0eSChaotian Jing if (host->hs400_mode) { 227686601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 227786601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2278fd82cc30SChaotian Jing msdc_set_data_delay(host, 0); 227986601d0eSChaotian Jing } 228086601d0eSChaotian Jing goto tune_done; 228186601d0eSChaotian Jing } 22827f3d5852SChaotian Jing if (host->hs400_mode && 22837f3d5852SChaotian Jing host->dev_comp->hs400_tune) 22841ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 22851ede5cb8Syong mao else 22866397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 22876397b7f5SChaotian Jing if (ret == -EIO) { 22886397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 2289567979fbSUlf Hansson return ret; 22906397b7f5SChaotian Jing } 22915462ff39SChaotian Jing if (host->hs400_mode == false) { 22926397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 22936397b7f5SChaotian Jing if (ret == -EIO) 22946397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 22955462ff39SChaotian Jing } 22966397b7f5SChaotian Jing 229786601d0eSChaotian Jing tune_done: 229886beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 229939add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 23001ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2301a2e6d1f6SChaotian Jing if (host->top_base) { 2302a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = readl(host->top_base + 2303a2e6d1f6SChaotian Jing EMMC_TOP_CONTROL); 2304a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2305a2e6d1f6SChaotian Jing EMMC_TOP_CMD); 2306a2e6d1f6SChaotian Jing } 23076397b7f5SChaotian Jing return ret; 23086397b7f5SChaotian Jing } 23096397b7f5SChaotian Jing 23106397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 23116397b7f5SChaotian Jing { 23126397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 23135462ff39SChaotian Jing host->hs400_mode = true; 23146397b7f5SChaotian Jing 2315a2e6d1f6SChaotian Jing if (host->top_base) 2316a2e6d1f6SChaotian Jing writel(host->hs400_ds_delay, 2317a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2318a2e6d1f6SChaotian Jing else 23196397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 23202fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 23212fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2322c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 2323c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2324c8609b22SChaotian Jing 23256397b7f5SChaotian Jing return 0; 23266397b7f5SChaotian Jing } 23276397b7f5SChaotian Jing 2328c4ac38c6SWenbin Mei static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2329c4ac38c6SWenbin Mei { 2330c4ac38c6SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 2331c4ac38c6SWenbin Mei struct msdc_delay_phase dly1_delay; 2332c4ac38c6SWenbin Mei u32 val, result_dly1 = 0; 2333c4ac38c6SWenbin Mei u8 *ext_csd; 2334c4ac38c6SWenbin Mei int i, ret; 2335c4ac38c6SWenbin Mei 2336c4ac38c6SWenbin Mei if (host->top_base) { 2337c4ac38c6SWenbin Mei sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2338c4ac38c6SWenbin Mei PAD_DS_DLY_SEL); 2339c4ac38c6SWenbin Mei if (host->hs400_ds_dly3) 2340c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2341c4ac38c6SWenbin Mei PAD_DS_DLY3, host->hs400_ds_dly3); 2342c4ac38c6SWenbin Mei } else { 2343c4ac38c6SWenbin Mei sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2344c4ac38c6SWenbin Mei if (host->hs400_ds_dly3) 2345c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2346c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2347c4ac38c6SWenbin Mei } 2348c4ac38c6SWenbin Mei 2349c4ac38c6SWenbin Mei host->hs400_tuning = true; 2350c4ac38c6SWenbin Mei for (i = 0; i < PAD_DELAY_MAX; i++) { 2351c4ac38c6SWenbin Mei if (host->top_base) 2352c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2353c4ac38c6SWenbin Mei PAD_DS_DLY1, i); 2354c4ac38c6SWenbin Mei else 2355c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2356c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY1, i); 2357c4ac38c6SWenbin Mei ret = mmc_get_ext_csd(card, &ext_csd); 2358d594b35dSWenbin Mei if (!ret) { 23594fe54318SAngeloGioacchino Del Regno result_dly1 |= BIT(i); 2360d594b35dSWenbin Mei kfree(ext_csd); 2361d594b35dSWenbin Mei } 2362c4ac38c6SWenbin Mei } 2363c4ac38c6SWenbin Mei host->hs400_tuning = false; 2364c4ac38c6SWenbin Mei 2365c4ac38c6SWenbin Mei dly1_delay = get_best_delay(host, result_dly1); 2366c4ac38c6SWenbin Mei if (dly1_delay.maxlen == 0) { 2367c4ac38c6SWenbin Mei dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2368c4ac38c6SWenbin Mei goto fail; 2369c4ac38c6SWenbin Mei } 2370c4ac38c6SWenbin Mei if (host->top_base) 2371c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2372c4ac38c6SWenbin Mei PAD_DS_DLY1, dly1_delay.final_phase); 2373c4ac38c6SWenbin Mei else 2374c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2375c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2376c4ac38c6SWenbin Mei 2377c4ac38c6SWenbin Mei if (host->top_base) 2378c4ac38c6SWenbin Mei val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2379c4ac38c6SWenbin Mei else 2380c4ac38c6SWenbin Mei val = readl(host->base + PAD_DS_TUNE); 2381c4ac38c6SWenbin Mei 2382f0c88b04SFabien Parent dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); 2383c4ac38c6SWenbin Mei 2384c4ac38c6SWenbin Mei return 0; 2385c4ac38c6SWenbin Mei 2386c4ac38c6SWenbin Mei fail: 2387c4ac38c6SWenbin Mei dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2388c4ac38c6SWenbin Mei return -EIO; 2389c4ac38c6SWenbin Mei } 2390c4ac38c6SWenbin Mei 2391c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 2392c9b5061eSChaotian Jing { 2393c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2394c9b5061eSChaotian Jing 2395c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 2396c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 2397c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 2398c9b5061eSChaotian Jing } 2399c9b5061eSChaotian Jing 24005215b2e9Sjjian zhou static void msdc_ack_sdio_irq(struct mmc_host *mmc) 24015215b2e9Sjjian zhou { 24028a5df8acSjjian zhou unsigned long flags; 24038a5df8acSjjian zhou struct msdc_host *host = mmc_priv(mmc); 24048a5df8acSjjian zhou 24058a5df8acSjjian zhou spin_lock_irqsave(&host->lock, flags); 24068a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 1); 24078a5df8acSjjian zhou spin_unlock_irqrestore(&host->lock, flags); 24085215b2e9Sjjian zhou } 24095215b2e9Sjjian zhou 2410d087bde5SNeilBrown static int msdc_get_cd(struct mmc_host *mmc) 2411d087bde5SNeilBrown { 2412d087bde5SNeilBrown struct msdc_host *host = mmc_priv(mmc); 2413d087bde5SNeilBrown int val; 2414d087bde5SNeilBrown 2415d087bde5SNeilBrown if (mmc->caps & MMC_CAP_NONREMOVABLE) 2416d087bde5SNeilBrown return 1; 2417d087bde5SNeilBrown 2418d087bde5SNeilBrown if (!host->internal_cd) 2419d087bde5SNeilBrown return mmc_gpio_get_cd(mmc); 2420d087bde5SNeilBrown 2421d087bde5SNeilBrown val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2422d087bde5SNeilBrown if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2423d087bde5SNeilBrown return !!val; 2424d087bde5SNeilBrown else 2425d087bde5SNeilBrown return !val; 2426d087bde5SNeilBrown } 2427d087bde5SNeilBrown 242813b4e1e9SWenbin Mei static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 242913b4e1e9SWenbin Mei struct mmc_ios *ios) 243013b4e1e9SWenbin Mei { 243113b4e1e9SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 243213b4e1e9SWenbin Mei 243313b4e1e9SWenbin Mei if (ios->enhanced_strobe) { 243413b4e1e9SWenbin Mei msdc_prepare_hs400_tuning(mmc, ios); 243513b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 243613b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 243713b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 243813b4e1e9SWenbin Mei 243913b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 244013b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 244113b4e1e9SWenbin Mei sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 244213b4e1e9SWenbin Mei } else { 244313b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 244413b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 244513b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 244613b4e1e9SWenbin Mei 244713b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 244813b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 244913b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 245013b4e1e9SWenbin Mei } 245113b4e1e9SWenbin Mei } 245213b4e1e9SWenbin Mei 245388bd652bSChun-Hung Wu static void msdc_cqe_enable(struct mmc_host *mmc) 245488bd652bSChun-Hung Wu { 245588bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 245688bd652bSChun-Hung Wu 245788bd652bSChun-Hung Wu /* enable cmdq irq */ 245888bd652bSChun-Hung Wu writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 245988bd652bSChun-Hung Wu /* enable busy check */ 246088bd652bSChun-Hung Wu sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 246188bd652bSChun-Hung Wu /* default write data / busy timeout 20s */ 246288bd652bSChun-Hung Wu msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 246388bd652bSChun-Hung Wu /* default read data timeout 1s */ 246488bd652bSChun-Hung Wu msdc_set_timeout(host, 1000000000ULL, 0); 246588bd652bSChun-Hung Wu } 246688bd652bSChun-Hung Wu 24677f4bc2e8SWei Yongjun static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 246888bd652bSChun-Hung Wu { 246988bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 247043e5fee3SDerong Liu unsigned int val = 0; 247188bd652bSChun-Hung Wu 247288bd652bSChun-Hung Wu /* disable cmdq irq */ 247388bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 247488bd652bSChun-Hung Wu /* disable busy check */ 247588bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 247688bd652bSChun-Hung Wu 2477cc5d1692SWenbin Mei val = readl(host->base + MSDC_INT); 2478cc5d1692SWenbin Mei writel(val, host->base + MSDC_INT); 2479cc5d1692SWenbin Mei 248088bd652bSChun-Hung Wu if (recovery) { 248188bd652bSChun-Hung Wu sdr_set_field(host->base + MSDC_DMA_CTRL, 248288bd652bSChun-Hung Wu MSDC_DMA_CTRL_STOP, 1); 248389bcd9a6SMengqi Zhang if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, 248489bcd9a6SMengqi Zhang !(val & MSDC_DMA_CTRL_STOP), 1, 3000))) 248589bcd9a6SMengqi Zhang return; 248643e5fee3SDerong Liu if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 248743e5fee3SDerong Liu !(val & MSDC_DMA_CFG_STS), 1, 3000))) 248843e5fee3SDerong Liu return; 248988bd652bSChun-Hung Wu msdc_reset_hw(host); 249088bd652bSChun-Hung Wu } 249188bd652bSChun-Hung Wu } 249288bd652bSChun-Hung Wu 2493e282f204SChun-Hung Wu static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2494e282f204SChun-Hung Wu { 2495e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2496e282f204SChun-Hung Wu u32 reg; 2497e282f204SChun-Hung Wu 2498e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2499e282f204SChun-Hung Wu reg |= CQHCI_ENABLE; 2500e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2501e282f204SChun-Hung Wu } 2502e282f204SChun-Hung Wu 2503e282f204SChun-Hung Wu static void msdc_cqe_post_disable(struct mmc_host *mmc) 2504e282f204SChun-Hung Wu { 2505e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2506e282f204SChun-Hung Wu u32 reg; 2507e282f204SChun-Hung Wu 2508e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2509e282f204SChun-Hung Wu reg &= ~CQHCI_ENABLE; 2510e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2511e282f204SChun-Hung Wu } 2512e282f204SChun-Hung Wu 2513be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 251420848903SChaotian Jing .post_req = msdc_post_req, 251520848903SChaotian Jing .pre_req = msdc_pre_req, 251620848903SChaotian Jing .request = msdc_ops_request, 251720848903SChaotian Jing .set_ios = msdc_ops_set_ios, 25188d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 2519d087bde5SNeilBrown .get_cd = msdc_get_cd, 252013b4e1e9SWenbin Mei .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 25215215b2e9Sjjian zhou .enable_sdio_irq = msdc_enable_sdio_irq, 25225215b2e9Sjjian zhou .ack_sdio_irq = msdc_ack_sdio_irq, 252320848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 252420848903SChaotian Jing .card_busy = msdc_card_busy, 25256397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 25266397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2527c4ac38c6SWenbin Mei .execute_hs400_tuning = msdc_execute_hs400_tuning, 252832f18e59SWolfram Sang .card_hw_reset = msdc_hw_reset, 252920848903SChaotian Jing }; 253020848903SChaotian Jing 253188bd652bSChun-Hung Wu static const struct cqhci_host_ops msdc_cmdq_ops = { 253288bd652bSChun-Hung Wu .enable = msdc_cqe_enable, 253388bd652bSChun-Hung Wu .disable = msdc_cqe_disable, 2534e282f204SChun-Hung Wu .pre_enable = msdc_cqe_pre_enable, 2535e282f204SChun-Hung Wu .post_disable = msdc_cqe_post_disable, 253688bd652bSChun-Hung Wu }; 253788bd652bSChun-Hung Wu 25381ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 25391ede5cb8Syong mao struct msdc_host *host) 25401ede5cb8Syong mao { 2541d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2542d17bb71cSChaotian Jing &host->latch_ck); 2543d17bb71cSChaotian Jing 25441ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 25451ede5cb8Syong mao &host->hs400_ds_delay); 25461ede5cb8Syong mao 2547c4ac38c6SWenbin Mei of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2548c4ac38c6SWenbin Mei &host->hs400_ds_dly3); 2549c4ac38c6SWenbin Mei 25501ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 25511ede5cb8Syong mao &host->hs200_cmd_int_delay); 25521ede5cb8Syong mao 25531ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 25541ede5cb8Syong mao &host->hs400_cmd_int_delay); 25551ede5cb8Syong mao 25561ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 25571ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 25581ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 25591ede5cb8Syong mao else 25601ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 256188bd652bSChun-Hung Wu 256288bd652bSChun-Hung Wu if (of_property_read_bool(pdev->dev.of_node, 256388bd652bSChun-Hung Wu "supports-cqe")) 256488bd652bSChun-Hung Wu host->cqhci = true; 256588bd652bSChun-Hung Wu else 256688bd652bSChun-Hung Wu host->cqhci = false; 25671ede5cb8Syong mao } 25681ede5cb8Syong mao 2569f5eccd94SWenbin Mei static int msdc_of_clock_parse(struct platform_device *pdev, 2570f5eccd94SWenbin Mei struct msdc_host *host) 2571f5eccd94SWenbin Mei { 2572f5eccd94SWenbin Mei int ret; 2573f5eccd94SWenbin Mei 2574f5eccd94SWenbin Mei host->src_clk = devm_clk_get(&pdev->dev, "source"); 2575f5eccd94SWenbin Mei if (IS_ERR(host->src_clk)) 2576f5eccd94SWenbin Mei return PTR_ERR(host->src_clk); 2577f5eccd94SWenbin Mei 2578f5eccd94SWenbin Mei host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2579f5eccd94SWenbin Mei if (IS_ERR(host->h_clk)) 2580f5eccd94SWenbin Mei return PTR_ERR(host->h_clk); 2581f5eccd94SWenbin Mei 2582f5eccd94SWenbin Mei host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2583f5eccd94SWenbin Mei if (IS_ERR(host->bus_clk)) 2584f5eccd94SWenbin Mei host->bus_clk = NULL; 2585f5eccd94SWenbin Mei 2586f5eccd94SWenbin Mei /*source clock control gate is optional clock*/ 2587f5eccd94SWenbin Mei host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2588f5eccd94SWenbin Mei if (IS_ERR(host->src_clk_cg)) 2589996be7b7SAngeloGioacchino Del Regno return PTR_ERR(host->src_clk_cg); 2590f5eccd94SWenbin Mei 2591e5e8b224SAngeloGioacchino Del Regno /* 2592e5e8b224SAngeloGioacchino Del Regno * Fallback for legacy device-trees: src_clk and HCLK use the same 2593e5e8b224SAngeloGioacchino Del Regno * bit to control gating but they are parented to a different mux, 2594e5e8b224SAngeloGioacchino Del Regno * hence if our intention is to gate only the source, required 2595e5e8b224SAngeloGioacchino Del Regno * during a clk mode switch to avoid hw hangs, we need to gate 2596e5e8b224SAngeloGioacchino Del Regno * its parent (specified as a different clock only on new DTs). 2597e5e8b224SAngeloGioacchino Del Regno */ 2598e5e8b224SAngeloGioacchino Del Regno if (!host->src_clk_cg) { 2599e5e8b224SAngeloGioacchino Del Regno host->src_clk_cg = clk_get_parent(host->src_clk); 2600e5e8b224SAngeloGioacchino Del Regno if (IS_ERR(host->src_clk_cg)) 2601e5e8b224SAngeloGioacchino Del Regno return PTR_ERR(host->src_clk_cg); 2602e5e8b224SAngeloGioacchino Del Regno } 2603e5e8b224SAngeloGioacchino Del Regno 2604c61bfb1cSGaosheng Cui /* If present, always enable for this clock gate */ 2605c61bfb1cSGaosheng Cui host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); 2606f5eccd94SWenbin Mei if (IS_ERR(host->sys_clk_cg)) 2607f5eccd94SWenbin Mei host->sys_clk_cg = NULL; 2608f5eccd94SWenbin Mei 2609f5eccd94SWenbin Mei host->bulk_clks[0].id = "pclk_cg"; 2610f5eccd94SWenbin Mei host->bulk_clks[1].id = "axi_cg"; 2611f5eccd94SWenbin Mei host->bulk_clks[2].id = "ahb_cg"; 2612f5eccd94SWenbin Mei ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2613f5eccd94SWenbin Mei host->bulk_clks); 2614f5eccd94SWenbin Mei if (ret) { 2615f5eccd94SWenbin Mei dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2616f5eccd94SWenbin Mei return ret; 2617f5eccd94SWenbin Mei } 2618f5eccd94SWenbin Mei 2619f5eccd94SWenbin Mei return 0; 2620f5eccd94SWenbin Mei } 2621f5eccd94SWenbin Mei 262220848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 262320848903SChaotian Jing { 262420848903SChaotian Jing struct mmc_host *mmc; 262520848903SChaotian Jing struct msdc_host *host; 262620848903SChaotian Jing struct resource *res; 262720848903SChaotian Jing int ret; 262820848903SChaotian Jing 262920848903SChaotian Jing if (!pdev->dev.of_node) { 263020848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 263120848903SChaotian Jing return -EINVAL; 263220848903SChaotian Jing } 2633762d491aSChaotian Jing 263420848903SChaotian Jing /* Allocate MMC host for this device */ 263520848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 263620848903SChaotian Jing if (!mmc) 263720848903SChaotian Jing return -ENOMEM; 263820848903SChaotian Jing 263920848903SChaotian Jing host = mmc_priv(mmc); 264020848903SChaotian Jing ret = mmc_of_parse(mmc); 264120848903SChaotian Jing if (ret) 264220848903SChaotian Jing goto host_free; 264320848903SChaotian Jing 2644bc068d38SYangtao Li host->base = devm_platform_ioremap_resource(pdev, 0); 264520848903SChaotian Jing if (IS_ERR(host->base)) { 264620848903SChaotian Jing ret = PTR_ERR(host->base); 264720848903SChaotian Jing goto host_free; 264820848903SChaotian Jing } 264920848903SChaotian Jing 2650a2e6d1f6SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2651b65be635SFabien Parent if (res) { 2652a2e6d1f6SChaotian Jing host->top_base = devm_ioremap_resource(&pdev->dev, res); 2653a2e6d1f6SChaotian Jing if (IS_ERR(host->top_base)) 2654a2e6d1f6SChaotian Jing host->top_base = NULL; 2655b65be635SFabien Parent } 2656a2e6d1f6SChaotian Jing 265720848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 26582f98ef63SWolfram Sang if (ret) 265920848903SChaotian Jing goto host_free; 266020848903SChaotian Jing 2661f5eccd94SWenbin Mei ret = msdc_of_clock_parse(pdev, host); 2662f5eccd94SWenbin Mei if (ret) 266320848903SChaotian Jing goto host_free; 26643c1a8844SChaotian Jing 2665855d388dSWenbin Mei host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2666855d388dSWenbin Mei "hrst"); 2667bbba85faSZheng Liang if (IS_ERR(host->reset)) { 2668bbba85faSZheng Liang ret = PTR_ERR(host->reset); 2669bbba85faSZheng Liang goto host_free; 2670bbba85faSZheng Liang } 2671855d388dSWenbin Mei 26727b438d03SMengqi Zhang /* only eMMC has crypto property */ 26737b438d03SMengqi Zhang if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { 26747b438d03SMengqi Zhang host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); 26757b438d03SMengqi Zhang if (IS_ERR(host->crypto_clk)) 26767b438d03SMengqi Zhang host->crypto_clk = NULL; 26777b438d03SMengqi Zhang else 26787b438d03SMengqi Zhang mmc->caps2 |= MMC_CAP2_CRYPTO; 26797b438d03SMengqi Zhang } 26807b438d03SMengqi Zhang 268120848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 268220848903SChaotian Jing if (host->irq < 0) { 268320848903SChaotian Jing ret = -EINVAL; 268420848903SChaotian Jing goto host_free; 268520848903SChaotian Jing } 268620848903SChaotian Jing 268720848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 268820848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 268920848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 269020848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 269120848903SChaotian Jing goto host_free; 269220848903SChaotian Jing } 269320848903SChaotian Jing 269420848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 269520848903SChaotian Jing if (IS_ERR(host->pins_default)) { 269620848903SChaotian Jing ret = PTR_ERR(host->pins_default); 269720848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 269820848903SChaotian Jing goto host_free; 269920848903SChaotian Jing } 270020848903SChaotian Jing 270120848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 270220848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 270320848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 270420848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 270520848903SChaotian Jing goto host_free; 270620848903SChaotian Jing } 270720848903SChaotian Jing 2708527f36f5SAxe Yang /* Support for SDIO eint irq ? */ 2709527f36f5SAxe Yang if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { 2710527f36f5SAxe Yang host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup"); 2711527f36f5SAxe Yang if (host->eint_irq > 0) { 2712527f36f5SAxe Yang host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); 2713527f36f5SAxe Yang if (IS_ERR(host->pins_eint)) { 2714527f36f5SAxe Yang dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); 2715527f36f5SAxe Yang host->pins_eint = NULL; 2716527f36f5SAxe Yang } else { 2717527f36f5SAxe Yang device_init_wakeup(&pdev->dev, true); 2718527f36f5SAxe Yang } 2719527f36f5SAxe Yang } 2720527f36f5SAxe Yang } 2721527f36f5SAxe Yang 27221ede5cb8Syong mao msdc_of_property_parse(pdev, host); 27236397b7f5SChaotian Jing 272420848903SChaotian Jing host->dev = &pdev->dev; 2725909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 272620848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 272720848903SChaotian Jing /* Set host parameters to mmc */ 272820848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2729762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 273040ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2731762d491aSChaotian Jing else 2732762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 273320848903SChaotian Jing 2734d087bde5SNeilBrown if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2735d087bde5SNeilBrown !mmc_can_gpio_cd(mmc) && 2736d087bde5SNeilBrown host->dev_comp->use_internal_cd) { 2737d087bde5SNeilBrown /* 2738d087bde5SNeilBrown * Is removable but no GPIO declared, so 2739d087bde5SNeilBrown * use internal functionality. 2740d087bde5SNeilBrown */ 2741d087bde5SNeilBrown host->internal_cd = true; 2742d087bde5SNeilBrown } 2743d087bde5SNeilBrown 27445215b2e9Sjjian zhou if (mmc->caps & MMC_CAP_SDIO_IRQ) 27455215b2e9Sjjian zhou mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 27465215b2e9Sjjian zhou 27471be64c79SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 274888bd652bSChun-Hung Wu if (host->cqhci) 274988bd652bSChun-Hung Wu mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 275020848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 275120848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 27526ef042bdSChaotian Jing if (host->dev_comp->support_64g) 27536ef042bdSChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 27546ef042bdSChaotian Jing else 275520848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 275620848903SChaotian Jing mmc->max_blk_size = 2048; 275720848903SChaotian Jing mmc->max_req_size = 512 * 1024; 275820848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 27592a9bde19SChaotian Jing if (host->dev_comp->support_64g) 27602a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 27612a9bde19SChaotian Jing else 276220848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 276320848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 276420848903SChaotian Jing 2765e8a1ff65SWenbin Mei host->timeout_clks = 3 * 1048576; 2766e8a1ff65SWenbin Mei host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2767e8a1ff65SWenbin Mei 2 * sizeof(struct mt_gpdma_desc), 2768e8a1ff65SWenbin Mei &host->dma.gpd_addr, GFP_KERNEL); 2769e8a1ff65SWenbin Mei host->dma.bd = dma_alloc_coherent(&pdev->dev, 2770e8a1ff65SWenbin Mei MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2771e8a1ff65SWenbin Mei &host->dma.bd_addr, GFP_KERNEL); 2772e8a1ff65SWenbin Mei if (!host->dma.gpd || !host->dma.bd) { 2773e8a1ff65SWenbin Mei ret = -ENOMEM; 2774e8a1ff65SWenbin Mei goto release_mem; 2775e8a1ff65SWenbin Mei } 2776e8a1ff65SWenbin Mei msdc_init_gpd_bd(host, &host->dma); 2777e8a1ff65SWenbin Mei INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2778e8a1ff65SWenbin Mei spin_lock_init(&host->lock); 2779e8a1ff65SWenbin Mei 2780e8a1ff65SWenbin Mei platform_set_drvdata(pdev, mmc); 2781ffaea6ebSAngeloGioacchino Del Regno ret = msdc_ungate_clock(host); 2782ffaea6ebSAngeloGioacchino Del Regno if (ret) { 2783ffaea6ebSAngeloGioacchino Del Regno dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2784ffaea6ebSAngeloGioacchino Del Regno goto release_mem; 2785ffaea6ebSAngeloGioacchino Del Regno } 2786e8a1ff65SWenbin Mei msdc_init_hw(host); 2787e8a1ff65SWenbin Mei 278888bd652bSChun-Hung Wu if (mmc->caps2 & MMC_CAP2_CQE) { 27890caf60c4SAmey Narkhede host->cq_host = devm_kzalloc(mmc->parent, 279088bd652bSChun-Hung Wu sizeof(*host->cq_host), 279188bd652bSChun-Hung Wu GFP_KERNEL); 279288bd652bSChun-Hung Wu if (!host->cq_host) { 279388bd652bSChun-Hung Wu ret = -ENOMEM; 279488bd652bSChun-Hung Wu goto host_free; 279588bd652bSChun-Hung Wu } 279688bd652bSChun-Hung Wu host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 279788bd652bSChun-Hung Wu host->cq_host->mmio = host->base + 0x800; 279888bd652bSChun-Hung Wu host->cq_host->ops = &msdc_cmdq_ops; 279988bd652bSChun-Hung Wu ret = cqhci_init(host->cq_host, mmc, true); 280088bd652bSChun-Hung Wu if (ret) 280188bd652bSChun-Hung Wu goto host_free; 280288bd652bSChun-Hung Wu mmc->max_segs = 128; 280388bd652bSChun-Hung Wu /* cqhci 16bit length */ 280488bd652bSChun-Hung Wu /* 0 size, means 65536 so we don't have to -1 here */ 280588bd652bSChun-Hung Wu mmc->max_seg_size = 64 * 1024; 280688bd652bSChun-Hung Wu } 280788bd652bSChun-Hung Wu 280820848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 280942edb0d5SNeilBrown IRQF_TRIGGER_NONE, pdev->name, host); 281020848903SChaotian Jing if (ret) 281120848903SChaotian Jing goto release; 281220848903SChaotian Jing 28134b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 28144b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 28154b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 28164b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 281720848903SChaotian Jing ret = mmc_add_host(mmc); 28184b8a43e9SChaotian Jing 281920848903SChaotian Jing if (ret) 28204b8a43e9SChaotian Jing goto end; 282120848903SChaotian Jing 282220848903SChaotian Jing return 0; 28234b8a43e9SChaotian Jing end: 28244b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 282520848903SChaotian Jing release: 282620848903SChaotian Jing platform_set_drvdata(pdev, NULL); 282720848903SChaotian Jing msdc_deinit_hw(host); 282820848903SChaotian Jing msdc_gate_clock(host); 282920848903SChaotian Jing release_mem: 283020848903SChaotian Jing if (host->dma.gpd) 283120848903SChaotian Jing dma_free_coherent(&pdev->dev, 283262b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 283320848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 283420848903SChaotian Jing if (host->dma.bd) 283520848903SChaotian Jing dma_free_coherent(&pdev->dev, 283620848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 283720848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 283820848903SChaotian Jing host_free: 283920848903SChaotian Jing mmc_free_host(mmc); 284020848903SChaotian Jing 284120848903SChaotian Jing return ret; 284220848903SChaotian Jing } 284320848903SChaotian Jing 284420848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 284520848903SChaotian Jing { 284620848903SChaotian Jing struct mmc_host *mmc; 284720848903SChaotian Jing struct msdc_host *host; 284820848903SChaotian Jing 284920848903SChaotian Jing mmc = platform_get_drvdata(pdev); 285020848903SChaotian Jing host = mmc_priv(mmc); 285120848903SChaotian Jing 28524b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 28534b8a43e9SChaotian Jing 285420848903SChaotian Jing platform_set_drvdata(pdev, NULL); 28550caf60c4SAmey Narkhede mmc_remove_host(mmc); 285620848903SChaotian Jing msdc_deinit_hw(host); 285720848903SChaotian Jing msdc_gate_clock(host); 285820848903SChaotian Jing 28594b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 28604b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 286120848903SChaotian Jing dma_free_coherent(&pdev->dev, 286216f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 286320848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 286420848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 286520848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 286620848903SChaotian Jing 28670caf60c4SAmey Narkhede mmc_free_host(mmc); 286820848903SChaotian Jing 286920848903SChaotian Jing return 0; 287020848903SChaotian Jing } 287120848903SChaotian Jing 28724b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 28734b8a43e9SChaotian Jing { 287439add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 287539add252SChaotian Jing 28764b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 28774b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 28784b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 28794b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 28804b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 28812fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 28826397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 28831ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 28846397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2885c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2886d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2887a2e6d1f6SChaotian Jing if (host->top_base) { 2888a2e6d1f6SChaotian Jing host->save_para.emmc_top_control = 2889a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 2890a2e6d1f6SChaotian Jing host->save_para.emmc_top_cmd = 2891a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 2892a2e6d1f6SChaotian Jing host->save_para.emmc50_pad_ds_tune = 2893a2e6d1f6SChaotian Jing readl(host->top_base + EMMC50_PAD_DS_TUNE); 2894a2e6d1f6SChaotian Jing } else { 2895a2e6d1f6SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 2896a2e6d1f6SChaotian Jing } 28974b8a43e9SChaotian Jing } 28984b8a43e9SChaotian Jing 28994b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 29004b8a43e9SChaotian Jing { 29010caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 290239add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 290339add252SChaotian Jing 29044b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 29054b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 29064b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 29074b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 29084b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 29092fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 29106397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 29111ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 29126397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2913c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2914d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2915a2e6d1f6SChaotian Jing if (host->top_base) { 2916a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_control, 2917a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 2918a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_cmd, 2919a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 2920a2e6d1f6SChaotian Jing writel(host->save_para.emmc50_pad_ds_tune, 2921a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2922a2e6d1f6SChaotian Jing } else { 2923a2e6d1f6SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 2924a2e6d1f6SChaotian Jing } 29251c81d69dSUlf Hansson 29260caf60c4SAmey Narkhede if (sdio_irq_claimed(mmc)) 29271c81d69dSUlf Hansson __msdc_enable_sdio_irq(host, 1); 29284b8a43e9SChaotian Jing } 29294b8a43e9SChaotian Jing 2930c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_suspend(struct device *dev) 29314b8a43e9SChaotian Jing { 29324b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 29334b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 29344b8a43e9SChaotian Jing 29354b8a43e9SChaotian Jing msdc_save_reg(host); 2936527f36f5SAxe Yang 2937527f36f5SAxe Yang if (sdio_irq_claimed(mmc)) { 2938527f36f5SAxe Yang if (host->pins_eint) { 2939527f36f5SAxe Yang disable_irq(host->irq); 2940527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_eint); 2941527f36f5SAxe Yang } 2942527f36f5SAxe Yang 2943527f36f5SAxe Yang __msdc_enable_sdio_irq(host, 0); 2944527f36f5SAxe Yang } 29454b8a43e9SChaotian Jing msdc_gate_clock(host); 29464b8a43e9SChaotian Jing return 0; 29474b8a43e9SChaotian Jing } 29484b8a43e9SChaotian Jing 2949c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_resume(struct device *dev) 29504b8a43e9SChaotian Jing { 29514b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 29524b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2953ffaea6ebSAngeloGioacchino Del Regno int ret; 29544b8a43e9SChaotian Jing 2955ffaea6ebSAngeloGioacchino Del Regno ret = msdc_ungate_clock(host); 2956ffaea6ebSAngeloGioacchino Del Regno if (ret) 2957ffaea6ebSAngeloGioacchino Del Regno return ret; 2958ffaea6ebSAngeloGioacchino Del Regno 29594b8a43e9SChaotian Jing msdc_restore_reg(host); 2960527f36f5SAxe Yang 2961527f36f5SAxe Yang if (sdio_irq_claimed(mmc) && host->pins_eint) { 2962527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_uhs); 2963527f36f5SAxe Yang enable_irq(host->irq); 2964527f36f5SAxe Yang } 29654b8a43e9SChaotian Jing return 0; 29664b8a43e9SChaotian Jing } 2967c0a2074aSWenbin Mei 2968c0d638a0SArnd Bergmann static int __maybe_unused msdc_suspend(struct device *dev) 2969c0a2074aSWenbin Mei { 2970c0a2074aSWenbin Mei struct mmc_host *mmc = dev_get_drvdata(dev); 2971527f36f5SAxe Yang struct msdc_host *host = mmc_priv(mmc); 2972c0a2074aSWenbin Mei int ret; 2973cc5d1692SWenbin Mei u32 val; 2974c0a2074aSWenbin Mei 2975c0a2074aSWenbin Mei if (mmc->caps2 & MMC_CAP2_CQE) { 2976c0a2074aSWenbin Mei ret = cqhci_suspend(mmc); 2977c0a2074aSWenbin Mei if (ret) 2978c0a2074aSWenbin Mei return ret; 2979cc5d1692SWenbin Mei val = readl(host->base + MSDC_INT); 2980cc5d1692SWenbin Mei writel(val, host->base + MSDC_INT); 2981c0a2074aSWenbin Mei } 2982c0a2074aSWenbin Mei 2983527f36f5SAxe Yang /* 2984527f36f5SAxe Yang * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will 2985527f36f5SAxe Yang * not be marked as 1, pm_runtime_force_resume() will go out directly. 2986527f36f5SAxe Yang */ 2987527f36f5SAxe Yang if (sdio_irq_claimed(mmc) && host->pins_eint) 2988527f36f5SAxe Yang pm_runtime_get_noresume(dev); 2989527f36f5SAxe Yang 2990c0a2074aSWenbin Mei return pm_runtime_force_suspend(dev); 2991c0a2074aSWenbin Mei } 2992c0a2074aSWenbin Mei 2993c0d638a0SArnd Bergmann static int __maybe_unused msdc_resume(struct device *dev) 2994c0a2074aSWenbin Mei { 2995527f36f5SAxe Yang struct mmc_host *mmc = dev_get_drvdata(dev); 2996527f36f5SAxe Yang struct msdc_host *host = mmc_priv(mmc); 2997527f36f5SAxe Yang 2998527f36f5SAxe Yang if (sdio_irq_claimed(mmc) && host->pins_eint) 2999527f36f5SAxe Yang pm_runtime_put_noidle(dev); 3000527f36f5SAxe Yang 3001c0a2074aSWenbin Mei return pm_runtime_force_resume(dev); 3002c0a2074aSWenbin Mei } 30034b8a43e9SChaotian Jing 30044b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 3005c0a2074aSWenbin Mei SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 30064b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 30074b8a43e9SChaotian Jing }; 30084b8a43e9SChaotian Jing 300920848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 301020848903SChaotian Jing .probe = msdc_drv_probe, 301120848903SChaotian Jing .remove = msdc_drv_remove, 301220848903SChaotian Jing .driver = { 301320848903SChaotian Jing .name = "mtk-msdc", 301421b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 301520848903SChaotian Jing .of_match_table = msdc_of_ids, 30164b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 301720848903SChaotian Jing }, 301820848903SChaotian Jing }; 301920848903SChaotian Jing 302020848903SChaotian Jing module_platform_driver(mt_msdc_driver); 302120848903SChaotian Jing MODULE_LICENSE("GPL v2"); 302220848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 3023