120848903SChaotian Jing /* 220848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 320848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 420848903SChaotian Jing * 520848903SChaotian Jing * This program is free software; you can redistribute it and/or modify 620848903SChaotian Jing * it under the terms of the GNU General Public License version 2 as 720848903SChaotian Jing * published by the Free Software Foundation. 820848903SChaotian Jing * 920848903SChaotian Jing * This program is distributed in the hope that it will be useful, 1020848903SChaotian Jing * but WITHOUT ANY WARRANTY; without even the implied warranty of 1120848903SChaotian Jing * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1220848903SChaotian Jing * GNU General Public License for more details. 1320848903SChaotian Jing */ 1420848903SChaotian Jing 1520848903SChaotian Jing #include <linux/module.h> 1620848903SChaotian Jing #include <linux/clk.h> 1720848903SChaotian Jing #include <linux/delay.h> 1820848903SChaotian Jing #include <linux/dma-mapping.h> 1920848903SChaotian Jing #include <linux/ioport.h> 2020848903SChaotian Jing #include <linux/irq.h> 2120848903SChaotian Jing #include <linux/of_address.h> 2220848903SChaotian Jing #include <linux/of_irq.h> 2320848903SChaotian Jing #include <linux/of_gpio.h> 2420848903SChaotian Jing #include <linux/pinctrl/consumer.h> 2520848903SChaotian Jing #include <linux/platform_device.h> 264b8a43e9SChaotian Jing #include <linux/pm.h> 274b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2820848903SChaotian Jing #include <linux/regulator/consumer.h> 296397b7f5SChaotian Jing #include <linux/slab.h> 3020848903SChaotian Jing #include <linux/spinlock.h> 31b8789ec4SUlf Hansson #include <linux/interrupt.h> 3220848903SChaotian Jing 3320848903SChaotian Jing #include <linux/mmc/card.h> 3420848903SChaotian Jing #include <linux/mmc/core.h> 3520848903SChaotian Jing #include <linux/mmc/host.h> 3620848903SChaotian Jing #include <linux/mmc/mmc.h> 3720848903SChaotian Jing #include <linux/mmc/sd.h> 3820848903SChaotian Jing #include <linux/mmc/sdio.h> 398d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 4020848903SChaotian Jing 4120848903SChaotian Jing #define MAX_BD_NUM 1024 4220848903SChaotian Jing 4320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4420848903SChaotian Jing /* Common Definition */ 4520848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4620848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4720848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4820848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4920848903SChaotian Jing 5020848903SChaotian Jing #define MSDC_BURST_64B 0x6 5120848903SChaotian Jing 5220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5320848903SChaotian Jing /* Register Offset */ 5420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5520848903SChaotian Jing #define MSDC_CFG 0x0 5620848903SChaotian Jing #define MSDC_IOCON 0x04 5720848903SChaotian Jing #define MSDC_PS 0x08 5820848903SChaotian Jing #define MSDC_INT 0x0c 5920848903SChaotian Jing #define MSDC_INTEN 0x10 6020848903SChaotian Jing #define MSDC_FIFOCS 0x14 6120848903SChaotian Jing #define SDC_CFG 0x30 6220848903SChaotian Jing #define SDC_CMD 0x34 6320848903SChaotian Jing #define SDC_ARG 0x38 6420848903SChaotian Jing #define SDC_STS 0x3c 6520848903SChaotian Jing #define SDC_RESP0 0x40 6620848903SChaotian Jing #define SDC_RESP1 0x44 6720848903SChaotian Jing #define SDC_RESP2 0x48 6820848903SChaotian Jing #define SDC_RESP3 0x4c 6920848903SChaotian Jing #define SDC_BLK_NUM 0x50 70c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 7120848903SChaotian Jing #define SDC_ACMD_RESP 0x80 7220848903SChaotian Jing #define MSDC_DMA_SA 0x90 7320848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7420848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7520848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7620848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 7720848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 786397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 796397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 8020848903SChaotian Jing 8120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 8220848903SChaotian Jing /* Register Mask */ 8320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 8420848903SChaotian Jing 8520848903SChaotian Jing /* MSDC_CFG mask */ 8620848903SChaotian Jing #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 8720848903SChaotian Jing #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 8820848903SChaotian Jing #define MSDC_CFG_RST (0x1 << 2) /* RW */ 8920848903SChaotian Jing #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 9020848903SChaotian Jing #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 9120848903SChaotian Jing #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 9220848903SChaotian Jing #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 9320848903SChaotian Jing #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 9420848903SChaotian Jing #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 9520848903SChaotian Jing #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 966397b7f5SChaotian Jing #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 9720848903SChaotian Jing 9820848903SChaotian Jing /* MSDC_IOCON mask */ 9920848903SChaotian Jing #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 10020848903SChaotian Jing #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 10120848903SChaotian Jing #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 10220848903SChaotian Jing #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 10320848903SChaotian Jing #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 10420848903SChaotian Jing #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 10520848903SChaotian Jing #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 10620848903SChaotian Jing #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 10720848903SChaotian Jing #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 10820848903SChaotian Jing #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 10920848903SChaotian Jing #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 11020848903SChaotian Jing #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 11120848903SChaotian Jing #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 11220848903SChaotian Jing #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 11320848903SChaotian Jing #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 11420848903SChaotian Jing #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 11520848903SChaotian Jing 11620848903SChaotian Jing /* MSDC_PS mask */ 11720848903SChaotian Jing #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 11820848903SChaotian Jing #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 11920848903SChaotian Jing #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 12020848903SChaotian Jing #define MSDC_PS_DAT (0xff << 16) /* R */ 12120848903SChaotian Jing #define MSDC_PS_CMD (0x1 << 24) /* R */ 12220848903SChaotian Jing #define MSDC_PS_WP (0x1 << 31) /* R */ 12320848903SChaotian Jing 12420848903SChaotian Jing /* MSDC_INT mask */ 12520848903SChaotian Jing #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 12620848903SChaotian Jing #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 12720848903SChaotian Jing #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 12820848903SChaotian Jing #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 12920848903SChaotian Jing #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 13020848903SChaotian Jing #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 13120848903SChaotian Jing #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 13220848903SChaotian Jing #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 13320848903SChaotian Jing #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 13420848903SChaotian Jing #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 13520848903SChaotian Jing #define MSDC_INT_CSTA (0x1 << 11) /* R */ 13620848903SChaotian Jing #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 13720848903SChaotian Jing #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 13820848903SChaotian Jing #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 13920848903SChaotian Jing #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 14020848903SChaotian Jing #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 14120848903SChaotian Jing #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 14220848903SChaotian Jing #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 14320848903SChaotian Jing #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 14420848903SChaotian Jing 14520848903SChaotian Jing /* MSDC_INTEN mask */ 14620848903SChaotian Jing #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 14720848903SChaotian Jing #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 14820848903SChaotian Jing #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 14920848903SChaotian Jing #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 15020848903SChaotian Jing #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 15120848903SChaotian Jing #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 15220848903SChaotian Jing #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 15320848903SChaotian Jing #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 15420848903SChaotian Jing #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 15520848903SChaotian Jing #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 15620848903SChaotian Jing #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 15720848903SChaotian Jing #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 15820848903SChaotian Jing #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 15920848903SChaotian Jing #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 16020848903SChaotian Jing #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 16120848903SChaotian Jing #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 16220848903SChaotian Jing #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 16320848903SChaotian Jing #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 16420848903SChaotian Jing #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 16520848903SChaotian Jing 16620848903SChaotian Jing /* MSDC_FIFOCS mask */ 16720848903SChaotian Jing #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 16820848903SChaotian Jing #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 16920848903SChaotian Jing #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 17020848903SChaotian Jing 17120848903SChaotian Jing /* SDC_CFG mask */ 17220848903SChaotian Jing #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 17320848903SChaotian Jing #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 17420848903SChaotian Jing #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 17520848903SChaotian Jing #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 17620848903SChaotian Jing #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 17720848903SChaotian Jing #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 17820848903SChaotian Jing #define SDC_CFG_DTOC (0xff << 24) /* RW */ 17920848903SChaotian Jing 18020848903SChaotian Jing /* SDC_STS mask */ 18120848903SChaotian Jing #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 18220848903SChaotian Jing #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 18320848903SChaotian Jing #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 18420848903SChaotian Jing 18520848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 18620848903SChaotian Jing #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 18720848903SChaotian Jing #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 18820848903SChaotian Jing #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 18920848903SChaotian Jing #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 19020848903SChaotian Jing #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 19120848903SChaotian Jing #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 19220848903SChaotian Jing 19320848903SChaotian Jing /* MSDC_DMA_CFG mask */ 19420848903SChaotian Jing #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 19520848903SChaotian Jing #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 19620848903SChaotian Jing #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 19720848903SChaotian Jing #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 19820848903SChaotian Jing #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 19920848903SChaotian Jing 20020848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 20120848903SChaotian Jing #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 20220848903SChaotian Jing #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 20320848903SChaotian Jing #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 20420848903SChaotian Jing #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 20520848903SChaotian Jing #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 20620848903SChaotian Jing #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 20720848903SChaotian Jing #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 20820848903SChaotian Jing #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 20920848903SChaotian Jing #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 21020848903SChaotian Jing #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 21120848903SChaotian Jing #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 21220848903SChaotian Jing #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 21320848903SChaotian Jing 2146397b7f5SChaotian Jing #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 2156397b7f5SChaotian Jing #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 2166397b7f5SChaotian Jing 2176397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 2186397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 2196397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 2206397b7f5SChaotian Jing 2216397b7f5SChaotian Jing #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 2226397b7f5SChaotian Jing #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 2236397b7f5SChaotian Jing #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 2246397b7f5SChaotian Jing 22520848903SChaotian Jing #define REQ_CMD_EIO (0x1 << 0) 22620848903SChaotian Jing #define REQ_CMD_TMO (0x1 << 1) 22720848903SChaotian Jing #define REQ_DAT_ERR (0x1 << 2) 22820848903SChaotian Jing #define REQ_STOP_EIO (0x1 << 3) 22920848903SChaotian Jing #define REQ_STOP_TMO (0x1 << 4) 23020848903SChaotian Jing #define REQ_CMD_BUSY (0x1 << 5) 23120848903SChaotian Jing 23220848903SChaotian Jing #define MSDC_PREPARE_FLAG (0x1 << 0) 23320848903SChaotian Jing #define MSDC_ASYNC_FLAG (0x1 << 1) 23420848903SChaotian Jing #define MSDC_MMAP_FLAG (0x1 << 2) 23520848903SChaotian Jing 2364b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 23720848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 23820848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 23920848903SChaotian Jing 2406397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 24120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 24220848903SChaotian Jing /* Descriptor Structure */ 24320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 24420848903SChaotian Jing struct mt_gpdma_desc { 24520848903SChaotian Jing u32 gpd_info; 24620848903SChaotian Jing #define GPDMA_DESC_HWO (0x1 << 0) 24720848903SChaotian Jing #define GPDMA_DESC_BDP (0x1 << 1) 24820848903SChaotian Jing #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 24920848903SChaotian Jing #define GPDMA_DESC_INT (0x1 << 16) 25020848903SChaotian Jing u32 next; 25120848903SChaotian Jing u32 ptr; 25220848903SChaotian Jing u32 gpd_data_len; 25320848903SChaotian Jing #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 25420848903SChaotian Jing #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 25520848903SChaotian Jing u32 arg; 25620848903SChaotian Jing u32 blknum; 25720848903SChaotian Jing u32 cmd; 25820848903SChaotian Jing }; 25920848903SChaotian Jing 26020848903SChaotian Jing struct mt_bdma_desc { 26120848903SChaotian Jing u32 bd_info; 26220848903SChaotian Jing #define BDMA_DESC_EOL (0x1 << 0) 26320848903SChaotian Jing #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 26420848903SChaotian Jing #define BDMA_DESC_BLKPAD (0x1 << 17) 26520848903SChaotian Jing #define BDMA_DESC_DWPAD (0x1 << 18) 26620848903SChaotian Jing u32 next; 26720848903SChaotian Jing u32 ptr; 26820848903SChaotian Jing u32 bd_data_len; 26920848903SChaotian Jing #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 27020848903SChaotian Jing }; 27120848903SChaotian Jing 27220848903SChaotian Jing struct msdc_dma { 27320848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 27420848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 27520848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 27620848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 27720848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 27820848903SChaotian Jing }; 27920848903SChaotian Jing 2804b8a43e9SChaotian Jing struct msdc_save_para { 2814b8a43e9SChaotian Jing u32 msdc_cfg; 2824b8a43e9SChaotian Jing u32 iocon; 2834b8a43e9SChaotian Jing u32 sdc_cfg; 2844b8a43e9SChaotian Jing u32 pad_tune; 2854b8a43e9SChaotian Jing u32 patch_bit0; 2864b8a43e9SChaotian Jing u32 patch_bit1; 2876397b7f5SChaotian Jing u32 pad_ds_tune; 2886397b7f5SChaotian Jing u32 emmc50_cfg0; 2896397b7f5SChaotian Jing }; 2906397b7f5SChaotian Jing 29186beac37SChaotian Jing struct msdc_tune_para { 29286beac37SChaotian Jing u32 iocon; 29386beac37SChaotian Jing u32 pad_tune; 29486beac37SChaotian Jing }; 29586beac37SChaotian Jing 2966397b7f5SChaotian Jing struct msdc_delay_phase { 2976397b7f5SChaotian Jing u8 maxlen; 2986397b7f5SChaotian Jing u8 start; 2996397b7f5SChaotian Jing u8 final_phase; 3004b8a43e9SChaotian Jing }; 3014b8a43e9SChaotian Jing 30220848903SChaotian Jing struct msdc_host { 30320848903SChaotian Jing struct device *dev; 30420848903SChaotian Jing struct mmc_host *mmc; /* mmc structure */ 30520848903SChaotian Jing int cmd_rsp; 30620848903SChaotian Jing 30720848903SChaotian Jing spinlock_t lock; 30820848903SChaotian Jing struct mmc_request *mrq; 30920848903SChaotian Jing struct mmc_command *cmd; 31020848903SChaotian Jing struct mmc_data *data; 31120848903SChaotian Jing int error; 31220848903SChaotian Jing 31320848903SChaotian Jing void __iomem *base; /* host base address */ 31420848903SChaotian Jing 31520848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 31620848903SChaotian Jing u64 dma_mask; 31720848903SChaotian Jing 31820848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 31920848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 32020848903SChaotian Jing 32120848903SChaotian Jing struct pinctrl *pinctrl; 32220848903SChaotian Jing struct pinctrl_state *pins_default; 32320848903SChaotian Jing struct pinctrl_state *pins_uhs; 32420848903SChaotian Jing struct delayed_work req_timeout; 32520848903SChaotian Jing int irq; /* host interrupt */ 32620848903SChaotian Jing 32720848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 32820848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 32920848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 33020848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 33120848903SChaotian Jing u32 sclk; /* SD/MS bus clock frequency */ 3326e622947SChaotian Jing unsigned char timing; 33320848903SChaotian Jing bool vqmmc_enabled; 3346397b7f5SChaotian Jing u32 hs400_ds_delay; 3355462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 3364b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 33786beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 33886beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 33920848903SChaotian Jing }; 34020848903SChaotian Jing 34120848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 34220848903SChaotian Jing { 34320848903SChaotian Jing u32 val = readl(reg); 34420848903SChaotian Jing 34520848903SChaotian Jing val |= bs; 34620848903SChaotian Jing writel(val, reg); 34720848903SChaotian Jing } 34820848903SChaotian Jing 34920848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 35020848903SChaotian Jing { 35120848903SChaotian Jing u32 val = readl(reg); 35220848903SChaotian Jing 35320848903SChaotian Jing val &= ~bs; 35420848903SChaotian Jing writel(val, reg); 35520848903SChaotian Jing } 35620848903SChaotian Jing 35720848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 35820848903SChaotian Jing { 35920848903SChaotian Jing unsigned int tv = readl(reg); 36020848903SChaotian Jing 36120848903SChaotian Jing tv &= ~field; 36220848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 36320848903SChaotian Jing writel(tv, reg); 36420848903SChaotian Jing } 36520848903SChaotian Jing 36620848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 36720848903SChaotian Jing { 36820848903SChaotian Jing unsigned int tv = readl(reg); 36920848903SChaotian Jing 37020848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 37120848903SChaotian Jing } 37220848903SChaotian Jing 37320848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 37420848903SChaotian Jing { 37520848903SChaotian Jing u32 val; 37620848903SChaotian Jing 37720848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 37820848903SChaotian Jing while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 37920848903SChaotian Jing cpu_relax(); 38020848903SChaotian Jing 38120848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 38220848903SChaotian Jing while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 38320848903SChaotian Jing cpu_relax(); 38420848903SChaotian Jing 38520848903SChaotian Jing val = readl(host->base + MSDC_INT); 38620848903SChaotian Jing writel(val, host->base + MSDC_INT); 38720848903SChaotian Jing } 38820848903SChaotian Jing 38920848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 39020848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 39120848903SChaotian Jing 392726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 393726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 394726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 395726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 39620848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 39720848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 39820848903SChaotian Jing 39920848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 40020848903SChaotian Jing { 40120848903SChaotian Jing u32 i, sum = 0; 40220848903SChaotian Jing 40320848903SChaotian Jing for (i = 0; i < len; i++) 40420848903SChaotian Jing sum += buf[i]; 40520848903SChaotian Jing return 0xff - (u8) sum; 40620848903SChaotian Jing } 40720848903SChaotian Jing 40820848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 40920848903SChaotian Jing struct mmc_data *data) 41020848903SChaotian Jing { 41120848903SChaotian Jing unsigned int j, dma_len; 41220848903SChaotian Jing dma_addr_t dma_address; 41320848903SChaotian Jing u32 dma_ctrl; 41420848903SChaotian Jing struct scatterlist *sg; 41520848903SChaotian Jing struct mt_gpdma_desc *gpd; 41620848903SChaotian Jing struct mt_bdma_desc *bd; 41720848903SChaotian Jing 41820848903SChaotian Jing sg = data->sg; 41920848903SChaotian Jing 42020848903SChaotian Jing gpd = dma->gpd; 42120848903SChaotian Jing bd = dma->bd; 42220848903SChaotian Jing 42320848903SChaotian Jing /* modify gpd */ 42420848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 42520848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 42620848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 42720848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 42820848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 42920848903SChaotian Jing 43020848903SChaotian Jing /* modify bd */ 43120848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 43220848903SChaotian Jing dma_address = sg_dma_address(sg); 43320848903SChaotian Jing dma_len = sg_dma_len(sg); 43420848903SChaotian Jing 43520848903SChaotian Jing /* init bd */ 43620848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 43720848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 43820848903SChaotian Jing bd[j].ptr = (u32)dma_address; 43920848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 44020848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 44120848903SChaotian Jing 44220848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 44320848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 44420848903SChaotian Jing else 44520848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 44620848903SChaotian Jing 44720848903SChaotian Jing /* checksume need to clear first */ 44820848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 44920848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 45020848903SChaotian Jing } 45120848903SChaotian Jing 45220848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 45320848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 45420848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 45520848903SChaotian Jing dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 45620848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 45720848903SChaotian Jing writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 45820848903SChaotian Jing } 45920848903SChaotian Jing 46020848903SChaotian Jing static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 46120848903SChaotian Jing { 46220848903SChaotian Jing struct mmc_data *data = mrq->data; 46320848903SChaotian Jing 46420848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 46520848903SChaotian Jing bool read = (data->flags & MMC_DATA_READ) != 0; 46620848903SChaotian Jing 46720848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 46820848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 46920848903SChaotian Jing read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 47020848903SChaotian Jing } 47120848903SChaotian Jing } 47220848903SChaotian Jing 47320848903SChaotian Jing static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 47420848903SChaotian Jing { 47520848903SChaotian Jing struct mmc_data *data = mrq->data; 47620848903SChaotian Jing 47720848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 47820848903SChaotian Jing return; 47920848903SChaotian Jing 48020848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 48120848903SChaotian Jing bool read = (data->flags & MMC_DATA_READ) != 0; 48220848903SChaotian Jing 48320848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 48420848903SChaotian Jing read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 48520848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 48620848903SChaotian Jing } 48720848903SChaotian Jing } 48820848903SChaotian Jing 48920848903SChaotian Jing /* clock control primitives */ 49020848903SChaotian Jing static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 49120848903SChaotian Jing { 49220848903SChaotian Jing u32 timeout, clk_ns; 49320848903SChaotian Jing u32 mode = 0; 49420848903SChaotian Jing 49520848903SChaotian Jing host->timeout_ns = ns; 49620848903SChaotian Jing host->timeout_clks = clks; 49720848903SChaotian Jing if (host->sclk == 0) { 49820848903SChaotian Jing timeout = 0; 49920848903SChaotian Jing } else { 50020848903SChaotian Jing clk_ns = 1000000000UL / host->sclk; 50120848903SChaotian Jing timeout = (ns + clk_ns - 1) / clk_ns + clks; 50220848903SChaotian Jing /* in 1048576 sclk cycle unit */ 50320848903SChaotian Jing timeout = (timeout + (0x1 << 20) - 1) >> 20; 50420848903SChaotian Jing sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 50520848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 50620848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 50720848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 50820848903SChaotian Jing timeout = timeout > 255 ? 255 : timeout; 50920848903SChaotian Jing } 51020848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 51120848903SChaotian Jing } 51220848903SChaotian Jing 51320848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 51420848903SChaotian Jing { 51520848903SChaotian Jing clk_disable_unprepare(host->src_clk); 51620848903SChaotian Jing clk_disable_unprepare(host->h_clk); 51720848903SChaotian Jing } 51820848903SChaotian Jing 51920848903SChaotian Jing static void msdc_ungate_clock(struct msdc_host *host) 52020848903SChaotian Jing { 52120848903SChaotian Jing clk_prepare_enable(host->h_clk); 52220848903SChaotian Jing clk_prepare_enable(host->src_clk); 52320848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 52420848903SChaotian Jing cpu_relax(); 52520848903SChaotian Jing } 52620848903SChaotian Jing 5276e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 52820848903SChaotian Jing { 52920848903SChaotian Jing u32 mode; 53020848903SChaotian Jing u32 flags; 53120848903SChaotian Jing u32 div; 53220848903SChaotian Jing u32 sclk; 53320848903SChaotian Jing 53420848903SChaotian Jing if (!hz) { 53520848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 53620848903SChaotian Jing host->mclk = 0; 53720848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 53820848903SChaotian Jing return; 53920848903SChaotian Jing } 54020848903SChaotian Jing 54120848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 54220848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 5436397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 5446e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 5456397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 5466397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 5476397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 5486397b7f5SChaotian Jing mode = 0x3; 5496397b7f5SChaotian Jing else 55020848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 5516397b7f5SChaotian Jing 55220848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 55320848903SChaotian Jing div = 0; /* mean div = 1/4 */ 55420848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 55520848903SChaotian Jing } else { 55620848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 55720848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 55820848903SChaotian Jing div = (div >> 1); 55920848903SChaotian Jing } 5606397b7f5SChaotian Jing 5616397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 5626397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 5636397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 5646397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 5656397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 5666397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 5676397b7f5SChaotian Jing } 56820848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 56920848903SChaotian Jing mode = 0x1; /* no divisor */ 57020848903SChaotian Jing div = 0; 57120848903SChaotian Jing sclk = host->src_clk_freq; 57220848903SChaotian Jing } else { 57320848903SChaotian Jing mode = 0x0; /* use divisor */ 57420848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 57520848903SChaotian Jing div = 0; /* mean div = 1/2 */ 57620848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 57720848903SChaotian Jing } else { 57820848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 57920848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 58020848903SChaotian Jing } 58120848903SChaotian Jing } 58220848903SChaotian Jing sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 58320848903SChaotian Jing (mode << 8) | (div % 0xff)); 58420848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 58520848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 58620848903SChaotian Jing cpu_relax(); 58720848903SChaotian Jing host->sclk = sclk; 58820848903SChaotian Jing host->mclk = hz; 5896e622947SChaotian Jing host->timing = timing; 59020848903SChaotian Jing /* need because clk changed. */ 59120848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 59220848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 59320848903SChaotian Jing 59486beac37SChaotian Jing /* 59586beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 59686beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 59786beac37SChaotian Jing */ 59886beac37SChaotian Jing if (host->sclk <= 52000000) { 59986beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 60086beac37SChaotian Jing writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 60186beac37SChaotian Jing } else { 60286beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 60386beac37SChaotian Jing writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 60486beac37SChaotian Jing } 60586beac37SChaotian Jing 6066e622947SChaotian Jing dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 60720848903SChaotian Jing } 60820848903SChaotian Jing 60920848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 61020848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 61120848903SChaotian Jing { 61220848903SChaotian Jing u32 resp; 61320848903SChaotian Jing 61420848903SChaotian Jing switch (mmc_resp_type(cmd)) { 61520848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 61620848903SChaotian Jing case MMC_RSP_R1: 61720848903SChaotian Jing resp = 0x1; 61820848903SChaotian Jing break; 61920848903SChaotian Jing case MMC_RSP_R1B: 62020848903SChaotian Jing resp = 0x7; 62120848903SChaotian Jing break; 62220848903SChaotian Jing case MMC_RSP_R2: 62320848903SChaotian Jing resp = 0x2; 62420848903SChaotian Jing break; 62520848903SChaotian Jing case MMC_RSP_R3: 62620848903SChaotian Jing resp = 0x3; 62720848903SChaotian Jing break; 62820848903SChaotian Jing case MMC_RSP_NONE: 62920848903SChaotian Jing default: 63020848903SChaotian Jing resp = 0x0; 63120848903SChaotian Jing break; 63220848903SChaotian Jing } 63320848903SChaotian Jing 63420848903SChaotian Jing return resp; 63520848903SChaotian Jing } 63620848903SChaotian Jing 63720848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 63820848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 63920848903SChaotian Jing { 64020848903SChaotian Jing /* rawcmd : 64120848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 64220848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 64320848903SChaotian Jing */ 64420848903SChaotian Jing u32 opcode = cmd->opcode; 64520848903SChaotian Jing u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 64620848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 64720848903SChaotian Jing 64820848903SChaotian Jing host->cmd_rsp = resp; 64920848903SChaotian Jing 65020848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 65120848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 65220848903SChaotian Jing rawcmd |= (0x1 << 14); 65320848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 65420848903SChaotian Jing rawcmd |= (0x1 << 30); 65520848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 65620848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 65720848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 65820848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 65920848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 66020848903SChaotian Jing rawcmd |= (0x1 << 11); 66120848903SChaotian Jing 66220848903SChaotian Jing if (cmd->data) { 66320848903SChaotian Jing struct mmc_data *data = cmd->data; 66420848903SChaotian Jing 66520848903SChaotian Jing if (mmc_op_multi(opcode)) { 66620848903SChaotian Jing if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 66720848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 66820848903SChaotian Jing rawcmd |= 0x2 << 28; /* AutoCMD23 */ 66920848903SChaotian Jing } 67020848903SChaotian Jing 67120848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 67220848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 67320848903SChaotian Jing rawcmd |= (0x1 << 13); 67420848903SChaotian Jing if (data->blocks > 1) 67520848903SChaotian Jing rawcmd |= (0x2 << 11); 67620848903SChaotian Jing else 67720848903SChaotian Jing rawcmd |= (0x1 << 11); 67820848903SChaotian Jing /* Always use dma mode */ 67920848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 68020848903SChaotian Jing 68120848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 68220848903SChaotian Jing host->timeout_clks != data->timeout_clks) 68320848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 68420848903SChaotian Jing data->timeout_clks); 68520848903SChaotian Jing 68620848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 68720848903SChaotian Jing } 68820848903SChaotian Jing return rawcmd; 68920848903SChaotian Jing } 69020848903SChaotian Jing 69120848903SChaotian Jing static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 69220848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 69320848903SChaotian Jing { 69420848903SChaotian Jing bool read; 69520848903SChaotian Jing 69620848903SChaotian Jing WARN_ON(host->data); 69720848903SChaotian Jing host->data = data; 69820848903SChaotian Jing read = data->flags & MMC_DATA_READ; 69920848903SChaotian Jing 70020848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 70120848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 70220848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 70320848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 70420848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 70520848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 70620848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 70720848903SChaotian Jing } 70820848903SChaotian Jing 70920848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 71020848903SChaotian Jing struct mmc_command *cmd) 71120848903SChaotian Jing { 71220848903SChaotian Jing u32 *rsp = cmd->resp; 71320848903SChaotian Jing 71420848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 71520848903SChaotian Jing 71620848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 71720848903SChaotian Jing cmd->error = 0; 71820848903SChaotian Jing } else { 71920848903SChaotian Jing msdc_reset_hw(host); 72020848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 72120848903SChaotian Jing cmd->error = -EILSEQ; 72220848903SChaotian Jing host->error |= REQ_STOP_EIO; 72320848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 72420848903SChaotian Jing cmd->error = -ETIMEDOUT; 72520848903SChaotian Jing host->error |= REQ_STOP_TMO; 72620848903SChaotian Jing } 72720848903SChaotian Jing dev_err(host->dev, 72820848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 72920848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 73020848903SChaotian Jing } 73120848903SChaotian Jing return cmd->error; 73220848903SChaotian Jing } 73320848903SChaotian Jing 73420848903SChaotian Jing static void msdc_track_cmd_data(struct msdc_host *host, 73520848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 73620848903SChaotian Jing { 73720848903SChaotian Jing if (host->error) 73820848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 73920848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 74020848903SChaotian Jing } 74120848903SChaotian Jing 74220848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 74320848903SChaotian Jing { 74420848903SChaotian Jing unsigned long flags; 74520848903SChaotian Jing bool ret; 74620848903SChaotian Jing 74720848903SChaotian Jing ret = cancel_delayed_work(&host->req_timeout); 74820848903SChaotian Jing if (!ret) { 74920848903SChaotian Jing /* delay work already running */ 75020848903SChaotian Jing return; 75120848903SChaotian Jing } 75220848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 75320848903SChaotian Jing host->mrq = NULL; 75420848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 75520848903SChaotian Jing 75620848903SChaotian Jing msdc_track_cmd_data(host, mrq->cmd, mrq->data); 75720848903SChaotian Jing if (mrq->data) 75820848903SChaotian Jing msdc_unprepare_data(host, mrq); 75920848903SChaotian Jing mmc_request_done(host->mmc, mrq); 76020848903SChaotian Jing } 76120848903SChaotian Jing 76220848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 76320848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 76420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 76520848903SChaotian Jing { 76620848903SChaotian Jing bool done = false; 76720848903SChaotian Jing bool sbc_error; 76820848903SChaotian Jing unsigned long flags; 76920848903SChaotian Jing u32 *rsp = cmd->resp; 77020848903SChaotian Jing 77120848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 77220848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 77320848903SChaotian Jing | MSDC_INT_ACMDTMO))) 77420848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 77520848903SChaotian Jing 77620848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 77720848903SChaotian Jing 77820848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 77920848903SChaotian Jing | MSDC_INT_RSPCRCERR 78020848903SChaotian Jing | MSDC_INT_CMDTMO))) 78120848903SChaotian Jing return done; 78220848903SChaotian Jing 78320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 78420848903SChaotian Jing done = !host->cmd; 78520848903SChaotian Jing host->cmd = NULL; 78620848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 78720848903SChaotian Jing 78820848903SChaotian Jing if (done) 78920848903SChaotian Jing return true; 79020848903SChaotian Jing 791726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 79220848903SChaotian Jing 79320848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 79420848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 79520848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 79620848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 79720848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 79820848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 79920848903SChaotian Jing } else { 80020848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 80120848903SChaotian Jing } 80220848903SChaotian Jing } 80320848903SChaotian Jing 80420848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 805ddc71387SChaotian Jing if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 806ddc71387SChaotian Jing cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 807ddc71387SChaotian Jing /* 808ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 809ddc71387SChaotian Jing * may have alreay come. 810ddc71387SChaotian Jing */ 81120848903SChaotian Jing msdc_reset_hw(host); 81220848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 81320848903SChaotian Jing cmd->error = -EILSEQ; 81420848903SChaotian Jing host->error |= REQ_CMD_EIO; 81520848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 81620848903SChaotian Jing cmd->error = -ETIMEDOUT; 81720848903SChaotian Jing host->error |= REQ_CMD_TMO; 81820848903SChaotian Jing } 81920848903SChaotian Jing } 82020848903SChaotian Jing if (cmd->error) 82120848903SChaotian Jing dev_dbg(host->dev, 82220848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 82320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 82420848903SChaotian Jing cmd->error); 82520848903SChaotian Jing 82620848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 82720848903SChaotian Jing return true; 82820848903SChaotian Jing } 82920848903SChaotian Jing 83020848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 83120848903SChaotian Jing * is correct before issue a request. but host design do below 83220848903SChaotian Jing * checks recommended. 83320848903SChaotian Jing */ 83420848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 83520848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 83620848903SChaotian Jing { 83720848903SChaotian Jing /* The max busy time we can endure is 20ms */ 83820848903SChaotian Jing unsigned long tmo = jiffies + msecs_to_jiffies(20); 83920848903SChaotian Jing 84020848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 84120848903SChaotian Jing time_before(jiffies, tmo)) 84220848903SChaotian Jing cpu_relax(); 84320848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 84420848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 84520848903SChaotian Jing host->error |= REQ_CMD_BUSY; 84620848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 84720848903SChaotian Jing return false; 84820848903SChaotian Jing } 84920848903SChaotian Jing 85020848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 85120848903SChaotian Jing tmo = jiffies + msecs_to_jiffies(20); 85220848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 85320848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 85420848903SChaotian Jing time_before(jiffies, tmo)) 85520848903SChaotian Jing cpu_relax(); 85620848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 85720848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 85820848903SChaotian Jing host->error |= REQ_CMD_BUSY; 85920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 86020848903SChaotian Jing return false; 86120848903SChaotian Jing } 86220848903SChaotian Jing } 86320848903SChaotian Jing return true; 86420848903SChaotian Jing } 86520848903SChaotian Jing 86620848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 86720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 86820848903SChaotian Jing { 86920848903SChaotian Jing u32 rawcmd; 87020848903SChaotian Jing 87120848903SChaotian Jing WARN_ON(host->cmd); 87220848903SChaotian Jing host->cmd = cmd; 87320848903SChaotian Jing 87420848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 87520848903SChaotian Jing return; 87620848903SChaotian Jing 87720848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 87820848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 87920848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 88020848903SChaotian Jing msdc_reset_hw(host); 88120848903SChaotian Jing } 88220848903SChaotian Jing 88320848903SChaotian Jing cmd->error = 0; 88420848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 88520848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 88620848903SChaotian Jing 887726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 88820848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 88920848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 89020848903SChaotian Jing } 89120848903SChaotian Jing 89220848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 89320848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 89420848903SChaotian Jing { 895ddc71387SChaotian Jing if ((cmd->error && 896ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 897ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 898ddc71387SChaotian Jing cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 899ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 90020848903SChaotian Jing msdc_request_done(host, mrq); 90120848903SChaotian Jing else if (cmd == mrq->sbc) 90220848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 90320848903SChaotian Jing else if (!cmd->data) 90420848903SChaotian Jing msdc_request_done(host, mrq); 90520848903SChaotian Jing else 90620848903SChaotian Jing msdc_start_data(host, mrq, cmd, cmd->data); 90720848903SChaotian Jing } 90820848903SChaotian Jing 90920848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 91020848903SChaotian Jing { 91120848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 91220848903SChaotian Jing 91320848903SChaotian Jing host->error = 0; 91420848903SChaotian Jing WARN_ON(host->mrq); 91520848903SChaotian Jing host->mrq = mrq; 91620848903SChaotian Jing 91720848903SChaotian Jing if (mrq->data) 91820848903SChaotian Jing msdc_prepare_data(host, mrq); 91920848903SChaotian Jing 92020848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 92120848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 92220848903SChaotian Jing * use HW option, otherwise use SW option 92320848903SChaotian Jing */ 92420848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 92520848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 92620848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 92720848903SChaotian Jing else 92820848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 92920848903SChaotian Jing } 93020848903SChaotian Jing 931d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 93220848903SChaotian Jing { 93320848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 93420848903SChaotian Jing struct mmc_data *data = mrq->data; 93520848903SChaotian Jing 93620848903SChaotian Jing if (!data) 93720848903SChaotian Jing return; 93820848903SChaotian Jing 93920848903SChaotian Jing msdc_prepare_data(host, mrq); 94020848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 94120848903SChaotian Jing } 94220848903SChaotian Jing 94320848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 94420848903SChaotian Jing int err) 94520848903SChaotian Jing { 94620848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 94720848903SChaotian Jing struct mmc_data *data; 94820848903SChaotian Jing 94920848903SChaotian Jing data = mrq->data; 95020848903SChaotian Jing if (!data) 95120848903SChaotian Jing return; 95220848903SChaotian Jing if (data->host_cookie) { 95320848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 95420848903SChaotian Jing msdc_unprepare_data(host, mrq); 95520848903SChaotian Jing } 95620848903SChaotian Jing } 95720848903SChaotian Jing 95820848903SChaotian Jing static void msdc_data_xfer_next(struct msdc_host *host, 95920848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 96020848903SChaotian Jing { 96120848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 9626397b7f5SChaotian Jing !mrq->sbc) 96320848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 96420848903SChaotian Jing else 96520848903SChaotian Jing msdc_request_done(host, mrq); 96620848903SChaotian Jing } 96720848903SChaotian Jing 96820848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 96920848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 97020848903SChaotian Jing { 97120848903SChaotian Jing struct mmc_command *stop = data->stop; 97220848903SChaotian Jing unsigned long flags; 97320848903SChaotian Jing bool done; 97420848903SChaotian Jing unsigned int check_data = events & 97520848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 97620848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 97720848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 97820848903SChaotian Jing 97920848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 98020848903SChaotian Jing done = !host->data; 98120848903SChaotian Jing if (check_data) 98220848903SChaotian Jing host->data = NULL; 98320848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 98420848903SChaotian Jing 98520848903SChaotian Jing if (done) 98620848903SChaotian Jing return true; 98720848903SChaotian Jing 98820848903SChaotian Jing if (check_data || (stop && stop->error)) { 98920848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 99020848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 99120848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 99220848903SChaotian Jing 1); 99320848903SChaotian Jing while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 99420848903SChaotian Jing cpu_relax(); 99520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 99620848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 99720848903SChaotian Jing 99820848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 99920848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 100020848903SChaotian Jing } else { 10012066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 100220848903SChaotian Jing msdc_reset_hw(host); 100320848903SChaotian Jing host->error |= REQ_DAT_ERR; 100420848903SChaotian Jing data->bytes_xfered = 0; 100520848903SChaotian Jing 100620848903SChaotian Jing if (events & MSDC_INT_DATTMO) 100720848903SChaotian Jing data->error = -ETIMEDOUT; 10086397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 10096397b7f5SChaotian Jing data->error = -EILSEQ; 101020848903SChaotian Jing 10112066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 101220848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 10132066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 101420848903SChaotian Jing (int)data->error, data->bytes_xfered); 101520848903SChaotian Jing } 101620848903SChaotian Jing 101720848903SChaotian Jing msdc_data_xfer_next(host, mrq, data); 101820848903SChaotian Jing done = true; 101920848903SChaotian Jing } 102020848903SChaotian Jing return done; 102120848903SChaotian Jing } 102220848903SChaotian Jing 102320848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 102420848903SChaotian Jing { 102520848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 102620848903SChaotian Jing 102720848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 102820848903SChaotian Jing 102920848903SChaotian Jing switch (width) { 103020848903SChaotian Jing default: 103120848903SChaotian Jing case MMC_BUS_WIDTH_1: 103220848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 103320848903SChaotian Jing break; 103420848903SChaotian Jing case MMC_BUS_WIDTH_4: 103520848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 103620848903SChaotian Jing break; 103720848903SChaotian Jing case MMC_BUS_WIDTH_8: 103820848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 103920848903SChaotian Jing break; 104020848903SChaotian Jing } 104120848903SChaotian Jing 104220848903SChaotian Jing writel(val, host->base + SDC_CFG); 104320848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 104420848903SChaotian Jing } 104520848903SChaotian Jing 104620848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 104720848903SChaotian Jing { 104820848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 104920848903SChaotian Jing int ret = 0; 105020848903SChaotian Jing 105120848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1052fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1053fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 105420848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 105520848903SChaotian Jing return -EINVAL; 105620848903SChaotian Jing } 105720848903SChaotian Jing 1058fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 105920848903SChaotian Jing if (ret) { 1060fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1061fac49ce5SNicolas Boichat ret, ios->signal_voltage); 106220848903SChaotian Jing } else { 106320848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 106420848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 106520848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 106620848903SChaotian Jing else 106720848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 106820848903SChaotian Jing } 106920848903SChaotian Jing } 107020848903SChaotian Jing return ret; 107120848903SChaotian Jing } 107220848903SChaotian Jing 107320848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 107420848903SChaotian Jing { 107520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 107620848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 107720848903SChaotian Jing 107820848903SChaotian Jing /* check if any pin between dat[0:3] is low */ 107920848903SChaotian Jing if (((status >> 16) & 0xf) != 0xf) 108020848903SChaotian Jing return 1; 108120848903SChaotian Jing 108220848903SChaotian Jing return 0; 108320848903SChaotian Jing } 108420848903SChaotian Jing 108520848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 108620848903SChaotian Jing { 108720848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 108820848903SChaotian Jing req_timeout.work); 108920848903SChaotian Jing 109020848903SChaotian Jing /* simulate HW timeout status */ 109120848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 109220848903SChaotian Jing if (host->mrq) { 109320848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 109420848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 109520848903SChaotian Jing if (host->cmd) { 109620848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 109720848903SChaotian Jing __func__, host->cmd->opcode); 109820848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 109920848903SChaotian Jing host->cmd); 110020848903SChaotian Jing } else if (host->data) { 110120848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 110220848903SChaotian Jing __func__, host->mrq->cmd->opcode, 110320848903SChaotian Jing host->data->blocks); 110420848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 110520848903SChaotian Jing host->data); 110620848903SChaotian Jing } 110720848903SChaotian Jing } 110820848903SChaotian Jing } 110920848903SChaotian Jing 111020848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 111120848903SChaotian Jing { 111220848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 111320848903SChaotian Jing 111420848903SChaotian Jing while (true) { 111520848903SChaotian Jing unsigned long flags; 111620848903SChaotian Jing struct mmc_request *mrq; 111720848903SChaotian Jing struct mmc_command *cmd; 111820848903SChaotian Jing struct mmc_data *data; 111920848903SChaotian Jing u32 events, event_mask; 112020848903SChaotian Jing 112120848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 112220848903SChaotian Jing events = readl(host->base + MSDC_INT); 112320848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 112420848903SChaotian Jing /* clear interrupts */ 112520848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 112620848903SChaotian Jing 112720848903SChaotian Jing mrq = host->mrq; 112820848903SChaotian Jing cmd = host->cmd; 112920848903SChaotian Jing data = host->data; 113020848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 113120848903SChaotian Jing 113220848903SChaotian Jing if (!(events & event_mask)) 113320848903SChaotian Jing break; 113420848903SChaotian Jing 113520848903SChaotian Jing if (!mrq) { 113620848903SChaotian Jing dev_err(host->dev, 113720848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 113820848903SChaotian Jing __func__, events, event_mask); 113920848903SChaotian Jing WARN_ON(1); 114020848903SChaotian Jing break; 114120848903SChaotian Jing } 114220848903SChaotian Jing 114320848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 114420848903SChaotian Jing 114520848903SChaotian Jing if (cmd) 114620848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 114720848903SChaotian Jing else if (data) 114820848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 114920848903SChaotian Jing } 115020848903SChaotian Jing 115120848903SChaotian Jing return IRQ_HANDLED; 115220848903SChaotian Jing } 115320848903SChaotian Jing 115420848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 115520848903SChaotian Jing { 115620848903SChaotian Jing u32 val; 115720848903SChaotian Jing 115820848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 115920848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 116020848903SChaotian Jing 116120848903SChaotian Jing /* Reset */ 116220848903SChaotian Jing msdc_reset_hw(host); 116320848903SChaotian Jing 116420848903SChaotian Jing /* Disable card detection */ 116520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 116620848903SChaotian Jing 116720848903SChaotian Jing /* Disable and clear all interrupts */ 116820848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 116920848903SChaotian Jing val = readl(host->base + MSDC_INT); 117020848903SChaotian Jing writel(val, host->base + MSDC_INT); 117120848903SChaotian Jing 117220848903SChaotian Jing writel(0, host->base + MSDC_PAD_TUNE); 117320848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 11746397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 11756397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 117620848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 117720848903SChaotian Jing writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 11786397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 11796397b7f5SChaotian Jing 118020848903SChaotian Jing /* Configure to enable SDIO mode. 118120848903SChaotian Jing * it's must otherwise sdio cmd5 failed 118220848903SChaotian Jing */ 118320848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 118420848903SChaotian Jing 118520848903SChaotian Jing /* disable detect SDIO device interrupt function */ 118620848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 118720848903SChaotian Jing 118820848903SChaotian Jing /* Configure to default data timeout */ 118920848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 119020848903SChaotian Jing 119186beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 119286beac37SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 119320848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 119420848903SChaotian Jing } 119520848903SChaotian Jing 119620848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 119720848903SChaotian Jing { 119820848903SChaotian Jing u32 val; 119920848903SChaotian Jing /* Disable and clear all interrupts */ 120020848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 120120848903SChaotian Jing 120220848903SChaotian Jing val = readl(host->base + MSDC_INT); 120320848903SChaotian Jing writel(val, host->base + MSDC_INT); 120420848903SChaotian Jing } 120520848903SChaotian Jing 120620848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 120720848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 120820848903SChaotian Jing { 120920848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 121020848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 121120848903SChaotian Jing int i; 121220848903SChaotian Jing 121362b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 121420848903SChaotian Jing 121520848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 121620848903SChaotian Jing gpd->ptr = (u32)dma->bd_addr; /* physical address */ 121762b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 121862b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 121962b0d27aSChaotian Jing */ 122062b0d27aSChaotian Jing gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 122120848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 122220848903SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) 122320848903SChaotian Jing bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 122420848903SChaotian Jing } 122520848903SChaotian Jing 122620848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 122720848903SChaotian Jing { 122820848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 122920848903SChaotian Jing int ret; 123020848903SChaotian Jing 123120848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 123220848903SChaotian Jing 123320848903SChaotian Jing /* Suspend/Resume will do power off/on */ 123420848903SChaotian Jing switch (ios->power_mode) { 123520848903SChaotian Jing case MMC_POWER_UP: 123620848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 12376397b7f5SChaotian Jing msdc_init_hw(host); 123820848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 123920848903SChaotian Jing ios->vdd); 124020848903SChaotian Jing if (ret) { 124120848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1242567979fbSUlf Hansson return; 124320848903SChaotian Jing } 124420848903SChaotian Jing } 124520848903SChaotian Jing break; 124620848903SChaotian Jing case MMC_POWER_ON: 124720848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 124820848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 124920848903SChaotian Jing if (ret) 125020848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 125120848903SChaotian Jing else 125220848903SChaotian Jing host->vqmmc_enabled = true; 125320848903SChaotian Jing } 125420848903SChaotian Jing break; 125520848903SChaotian Jing case MMC_POWER_OFF: 125620848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 125720848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 125820848903SChaotian Jing 125920848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 126020848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 126120848903SChaotian Jing host->vqmmc_enabled = false; 126220848903SChaotian Jing } 126320848903SChaotian Jing break; 126420848903SChaotian Jing default: 126520848903SChaotian Jing break; 126620848903SChaotian Jing } 126720848903SChaotian Jing 12686e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 12696e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 127020848903SChaotian Jing } 127120848903SChaotian Jing 12726397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 12736397b7f5SChaotian Jing { 12746397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 12756397b7f5SChaotian Jing return delay & (1 << bit); 12766397b7f5SChaotian Jing } 12776397b7f5SChaotian Jing 12786397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 12796397b7f5SChaotian Jing { 12806397b7f5SChaotian Jing int i; 12816397b7f5SChaotian Jing 12826397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 12836397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 12846397b7f5SChaotian Jing return i; 12856397b7f5SChaotian Jing } 12866397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 12876397b7f5SChaotian Jing } 12886397b7f5SChaotian Jing 12896397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 12906397b7f5SChaotian Jing { 12916397b7f5SChaotian Jing int start = 0, len = 0; 12926397b7f5SChaotian Jing int start_final = 0, len_final = 0; 12936397b7f5SChaotian Jing u8 final_phase = 0xff; 129462d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 12956397b7f5SChaotian Jing 12966397b7f5SChaotian Jing if (delay == 0) { 12976397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 12986397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 12996397b7f5SChaotian Jing return delay_phase; 13006397b7f5SChaotian Jing } 13016397b7f5SChaotian Jing 13026397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 13036397b7f5SChaotian Jing len = get_delay_len(delay, start); 13046397b7f5SChaotian Jing if (len_final < len) { 13056397b7f5SChaotian Jing start_final = start; 13066397b7f5SChaotian Jing len_final = len; 13076397b7f5SChaotian Jing } 13086397b7f5SChaotian Jing start += len ? len : 1; 13096397b7f5SChaotian Jing if (len >= 8 && start_final < 4) 13106397b7f5SChaotian Jing break; 13116397b7f5SChaotian Jing } 13126397b7f5SChaotian Jing 13136397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 13146397b7f5SChaotian Jing if (start_final == 0) 13156397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 13166397b7f5SChaotian Jing else 13176397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 13186397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 13196397b7f5SChaotian Jing delay, len_final, final_phase); 13206397b7f5SChaotian Jing 13216397b7f5SChaotian Jing delay_phase.maxlen = len_final; 13226397b7f5SChaotian Jing delay_phase.start = start_final; 13236397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 13246397b7f5SChaotian Jing return delay_phase; 13256397b7f5SChaotian Jing } 13266397b7f5SChaotian Jing 13276397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 13286397b7f5SChaotian Jing { 13296397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 13306397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1331ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 13326397b7f5SChaotian Jing u8 final_delay, final_maxlen; 13336397b7f5SChaotian Jing int cmd_err; 13346397b7f5SChaotian Jing int i; 13356397b7f5SChaotian Jing 13366397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 13376397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 13386397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 13396397b7f5SChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 13406397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 13416397b7f5SChaotian Jing if (!cmd_err) 13426397b7f5SChaotian Jing rise_delay |= (1 << i); 13436397b7f5SChaotian Jing } 1344ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1345ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 1346ae9c657eSChaotian Jing if (final_rise_delay.maxlen >= 10 || 1347ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1348ae9c657eSChaotian Jing goto skip_fall; 13496397b7f5SChaotian Jing 13506397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 13516397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 13526397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 13536397b7f5SChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 13546397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 13556397b7f5SChaotian Jing if (!cmd_err) 13566397b7f5SChaotian Jing fall_delay |= (1 << i); 13576397b7f5SChaotian Jing } 13586397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 13596397b7f5SChaotian Jing 1360ae9c657eSChaotian Jing skip_fall: 13616397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 13626397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 13636397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 13646397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 13656397b7f5SChaotian Jing final_rise_delay.final_phase); 13666397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 13676397b7f5SChaotian Jing } else { 13686397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 13696397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 13706397b7f5SChaotian Jing final_fall_delay.final_phase); 13716397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 13726397b7f5SChaotian Jing } 13736397b7f5SChaotian Jing 13746397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 13756397b7f5SChaotian Jing } 13766397b7f5SChaotian Jing 13776397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 13786397b7f5SChaotian Jing { 13796397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 13806397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1381ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 13826397b7f5SChaotian Jing u8 final_delay, final_maxlen; 13836397b7f5SChaotian Jing int i, ret; 13846397b7f5SChaotian Jing 13856397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 13866397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 13876397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 13886397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 13896397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 13906397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 13916397b7f5SChaotian Jing if (!ret) 13926397b7f5SChaotian Jing rise_delay |= (1 << i); 13936397b7f5SChaotian Jing } 1394ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1395ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 1396ae9c657eSChaotian Jing if (final_rise_delay.maxlen >= 10 || 1397ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1398ae9c657eSChaotian Jing goto skip_fall; 13996397b7f5SChaotian Jing 14006397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 14016397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 14026397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 14036397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 14046397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 14056397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 14066397b7f5SChaotian Jing if (!ret) 14076397b7f5SChaotian Jing fall_delay |= (1 << i); 14086397b7f5SChaotian Jing } 14096397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 14106397b7f5SChaotian Jing 1411ae9c657eSChaotian Jing skip_fall: 14126397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 14136397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 14146397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 14156397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 14166397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 14176397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 14186397b7f5SChaotian Jing final_rise_delay.final_phase); 14196397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 14206397b7f5SChaotian Jing } else { 14216397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 14226397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 14236397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 14246397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 14256397b7f5SChaotian Jing final_fall_delay.final_phase); 14266397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 14276397b7f5SChaotian Jing } 14286397b7f5SChaotian Jing 14296397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 14306397b7f5SChaotian Jing } 14316397b7f5SChaotian Jing 14326397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 14336397b7f5SChaotian Jing { 14346397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14356397b7f5SChaotian Jing int ret; 14366397b7f5SChaotian Jing 14376397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 14386397b7f5SChaotian Jing if (ret == -EIO) { 14396397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 1440567979fbSUlf Hansson return ret; 14416397b7f5SChaotian Jing } 14425462ff39SChaotian Jing if (host->hs400_mode == false) { 14436397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 14446397b7f5SChaotian Jing if (ret == -EIO) 14456397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 14465462ff39SChaotian Jing } 14476397b7f5SChaotian Jing 144886beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 144986beac37SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 14506397b7f5SChaotian Jing return ret; 14516397b7f5SChaotian Jing } 14526397b7f5SChaotian Jing 14536397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 14546397b7f5SChaotian Jing { 14556397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14565462ff39SChaotian Jing host->hs400_mode = true; 14576397b7f5SChaotian Jing 14586397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 14596397b7f5SChaotian Jing return 0; 14606397b7f5SChaotian Jing } 14616397b7f5SChaotian Jing 1462c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 1463c9b5061eSChaotian Jing { 1464c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 1465c9b5061eSChaotian Jing 1466c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 1467c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 1468c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 1469c9b5061eSChaotian Jing } 1470c9b5061eSChaotian Jing 147120848903SChaotian Jing static struct mmc_host_ops mt_msdc_ops = { 147220848903SChaotian Jing .post_req = msdc_post_req, 147320848903SChaotian Jing .pre_req = msdc_pre_req, 147420848903SChaotian Jing .request = msdc_ops_request, 147520848903SChaotian Jing .set_ios = msdc_ops_set_ios, 14768d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 147720848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 147820848903SChaotian Jing .card_busy = msdc_card_busy, 14796397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 14806397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1481c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 148220848903SChaotian Jing }; 148320848903SChaotian Jing 148420848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 148520848903SChaotian Jing { 148620848903SChaotian Jing struct mmc_host *mmc; 148720848903SChaotian Jing struct msdc_host *host; 148820848903SChaotian Jing struct resource *res; 148920848903SChaotian Jing int ret; 149020848903SChaotian Jing 149120848903SChaotian Jing if (!pdev->dev.of_node) { 149220848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 149320848903SChaotian Jing return -EINVAL; 149420848903SChaotian Jing } 149520848903SChaotian Jing /* Allocate MMC host for this device */ 149620848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 149720848903SChaotian Jing if (!mmc) 149820848903SChaotian Jing return -ENOMEM; 149920848903SChaotian Jing 150020848903SChaotian Jing host = mmc_priv(mmc); 150120848903SChaotian Jing ret = mmc_of_parse(mmc); 150220848903SChaotian Jing if (ret) 150320848903SChaotian Jing goto host_free; 150420848903SChaotian Jing 150520848903SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 150620848903SChaotian Jing host->base = devm_ioremap_resource(&pdev->dev, res); 150720848903SChaotian Jing if (IS_ERR(host->base)) { 150820848903SChaotian Jing ret = PTR_ERR(host->base); 150920848903SChaotian Jing goto host_free; 151020848903SChaotian Jing } 151120848903SChaotian Jing 151220848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 151320848903SChaotian Jing if (ret == -EPROBE_DEFER) 151420848903SChaotian Jing goto host_free; 151520848903SChaotian Jing 151620848903SChaotian Jing host->src_clk = devm_clk_get(&pdev->dev, "source"); 151720848903SChaotian Jing if (IS_ERR(host->src_clk)) { 151820848903SChaotian Jing ret = PTR_ERR(host->src_clk); 151920848903SChaotian Jing goto host_free; 152020848903SChaotian Jing } 152120848903SChaotian Jing 152220848903SChaotian Jing host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 152320848903SChaotian Jing if (IS_ERR(host->h_clk)) { 152420848903SChaotian Jing ret = PTR_ERR(host->h_clk); 152520848903SChaotian Jing goto host_free; 152620848903SChaotian Jing } 152720848903SChaotian Jing 152820848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 152920848903SChaotian Jing if (host->irq < 0) { 153020848903SChaotian Jing ret = -EINVAL; 153120848903SChaotian Jing goto host_free; 153220848903SChaotian Jing } 153320848903SChaotian Jing 153420848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 153520848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 153620848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 153720848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 153820848903SChaotian Jing goto host_free; 153920848903SChaotian Jing } 154020848903SChaotian Jing 154120848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 154220848903SChaotian Jing if (IS_ERR(host->pins_default)) { 154320848903SChaotian Jing ret = PTR_ERR(host->pins_default); 154420848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 154520848903SChaotian Jing goto host_free; 154620848903SChaotian Jing } 154720848903SChaotian Jing 154820848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 154920848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 155020848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 155120848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 155220848903SChaotian Jing goto host_free; 155320848903SChaotian Jing } 155420848903SChaotian Jing 15556397b7f5SChaotian Jing if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 15566397b7f5SChaotian Jing &host->hs400_ds_delay)) 15576397b7f5SChaotian Jing dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n", 15586397b7f5SChaotian Jing host->hs400_ds_delay); 15596397b7f5SChaotian Jing 156020848903SChaotian Jing host->dev = &pdev->dev; 156120848903SChaotian Jing host->mmc = mmc; 156220848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 156320848903SChaotian Jing /* Set host parameters to mmc */ 156420848903SChaotian Jing mmc->ops = &mt_msdc_ops; 156520848903SChaotian Jing mmc->f_min = host->src_clk_freq / (4 * 255); 156620848903SChaotian Jing 156720848903SChaotian Jing mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 156820848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 156920848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 157020848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 157120848903SChaotian Jing mmc->max_blk_size = 2048; 157220848903SChaotian Jing mmc->max_req_size = 512 * 1024; 157320848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 157420848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 157520848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 157620848903SChaotian Jing 157720848903SChaotian Jing host->timeout_clks = 3 * 1048576; 157820848903SChaotian Jing host->dma.gpd = dma_alloc_coherent(&pdev->dev, 157962b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 158020848903SChaotian Jing &host->dma.gpd_addr, GFP_KERNEL); 158120848903SChaotian Jing host->dma.bd = dma_alloc_coherent(&pdev->dev, 158220848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 158320848903SChaotian Jing &host->dma.bd_addr, GFP_KERNEL); 158420848903SChaotian Jing if (!host->dma.gpd || !host->dma.bd) { 158520848903SChaotian Jing ret = -ENOMEM; 158620848903SChaotian Jing goto release_mem; 158720848903SChaotian Jing } 158820848903SChaotian Jing msdc_init_gpd_bd(host, &host->dma); 158920848903SChaotian Jing INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 159020848903SChaotian Jing spin_lock_init(&host->lock); 159120848903SChaotian Jing 159220848903SChaotian Jing platform_set_drvdata(pdev, mmc); 159320848903SChaotian Jing msdc_ungate_clock(host); 159420848903SChaotian Jing msdc_init_hw(host); 159520848903SChaotian Jing 159620848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 159720848903SChaotian Jing IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 159820848903SChaotian Jing if (ret) 159920848903SChaotian Jing goto release; 160020848903SChaotian Jing 16014b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 16024b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 16034b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 16044b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 160520848903SChaotian Jing ret = mmc_add_host(mmc); 16064b8a43e9SChaotian Jing 160720848903SChaotian Jing if (ret) 16084b8a43e9SChaotian Jing goto end; 160920848903SChaotian Jing 161020848903SChaotian Jing return 0; 16114b8a43e9SChaotian Jing end: 16124b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 161320848903SChaotian Jing release: 161420848903SChaotian Jing platform_set_drvdata(pdev, NULL); 161520848903SChaotian Jing msdc_deinit_hw(host); 161620848903SChaotian Jing msdc_gate_clock(host); 161720848903SChaotian Jing release_mem: 161820848903SChaotian Jing if (host->dma.gpd) 161920848903SChaotian Jing dma_free_coherent(&pdev->dev, 162062b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 162120848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 162220848903SChaotian Jing if (host->dma.bd) 162320848903SChaotian Jing dma_free_coherent(&pdev->dev, 162420848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 162520848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 162620848903SChaotian Jing host_free: 162720848903SChaotian Jing mmc_free_host(mmc); 162820848903SChaotian Jing 162920848903SChaotian Jing return ret; 163020848903SChaotian Jing } 163120848903SChaotian Jing 163220848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 163320848903SChaotian Jing { 163420848903SChaotian Jing struct mmc_host *mmc; 163520848903SChaotian Jing struct msdc_host *host; 163620848903SChaotian Jing 163720848903SChaotian Jing mmc = platform_get_drvdata(pdev); 163820848903SChaotian Jing host = mmc_priv(mmc); 163920848903SChaotian Jing 16404b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 16414b8a43e9SChaotian Jing 164220848903SChaotian Jing platform_set_drvdata(pdev, NULL); 164320848903SChaotian Jing mmc_remove_host(host->mmc); 164420848903SChaotian Jing msdc_deinit_hw(host); 164520848903SChaotian Jing msdc_gate_clock(host); 164620848903SChaotian Jing 16474b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 16484b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 164920848903SChaotian Jing dma_free_coherent(&pdev->dev, 165020848903SChaotian Jing sizeof(struct mt_gpdma_desc), 165120848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 165220848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 165320848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 165420848903SChaotian Jing 165520848903SChaotian Jing mmc_free_host(host->mmc); 165620848903SChaotian Jing 165720848903SChaotian Jing return 0; 165820848903SChaotian Jing } 165920848903SChaotian Jing 16604b8a43e9SChaotian Jing #ifdef CONFIG_PM 16614b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 16624b8a43e9SChaotian Jing { 16634b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 16644b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 16654b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 16664b8a43e9SChaotian Jing host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 16674b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 16684b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 16696397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 16706397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 16714b8a43e9SChaotian Jing } 16724b8a43e9SChaotian Jing 16734b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 16744b8a43e9SChaotian Jing { 16754b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 16764b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 16774b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 16784b8a43e9SChaotian Jing writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 16794b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 16804b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 16816397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 16826397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 16834b8a43e9SChaotian Jing } 16844b8a43e9SChaotian Jing 16854b8a43e9SChaotian Jing static int msdc_runtime_suspend(struct device *dev) 16864b8a43e9SChaotian Jing { 16874b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 16884b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 16894b8a43e9SChaotian Jing 16904b8a43e9SChaotian Jing msdc_save_reg(host); 16914b8a43e9SChaotian Jing msdc_gate_clock(host); 16924b8a43e9SChaotian Jing return 0; 16934b8a43e9SChaotian Jing } 16944b8a43e9SChaotian Jing 16954b8a43e9SChaotian Jing static int msdc_runtime_resume(struct device *dev) 16964b8a43e9SChaotian Jing { 16974b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 16984b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 16994b8a43e9SChaotian Jing 17004b8a43e9SChaotian Jing msdc_ungate_clock(host); 17014b8a43e9SChaotian Jing msdc_restore_reg(host); 17024b8a43e9SChaotian Jing return 0; 17034b8a43e9SChaotian Jing } 17044b8a43e9SChaotian Jing #endif 17054b8a43e9SChaotian Jing 17064b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 17074b8a43e9SChaotian Jing SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 17084b8a43e9SChaotian Jing pm_runtime_force_resume) 17094b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 17104b8a43e9SChaotian Jing }; 17114b8a43e9SChaotian Jing 171220848903SChaotian Jing static const struct of_device_id msdc_of_ids[] = { 171320848903SChaotian Jing { .compatible = "mediatek,mt8135-mmc", }, 171420848903SChaotian Jing {} 171520848903SChaotian Jing }; 17169cb02eefSJavier Martinez Canillas MODULE_DEVICE_TABLE(of, msdc_of_ids); 171720848903SChaotian Jing 171820848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 171920848903SChaotian Jing .probe = msdc_drv_probe, 172020848903SChaotian Jing .remove = msdc_drv_remove, 172120848903SChaotian Jing .driver = { 172220848903SChaotian Jing .name = "mtk-msdc", 172320848903SChaotian Jing .of_match_table = msdc_of_ids, 17244b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 172520848903SChaotian Jing }, 172620848903SChaotian Jing }; 172720848903SChaotian Jing 172820848903SChaotian Jing module_platform_driver(mt_msdc_driver); 172920848903SChaotian Jing MODULE_LICENSE("GPL v2"); 173020848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1731