11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 220848903SChaotian Jing /* 320848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 420848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 520848903SChaotian Jing */ 620848903SChaotian Jing 720848903SChaotian Jing #include <linux/module.h> 820848903SChaotian Jing #include <linux/clk.h> 920848903SChaotian Jing #include <linux/delay.h> 1020848903SChaotian Jing #include <linux/dma-mapping.h> 1120848903SChaotian Jing #include <linux/ioport.h> 1220848903SChaotian Jing #include <linux/irq.h> 1320848903SChaotian Jing #include <linux/of_address.h> 14909b3456SRyder Lee #include <linux/of_device.h> 1520848903SChaotian Jing #include <linux/of_irq.h> 1620848903SChaotian Jing #include <linux/of_gpio.h> 1720848903SChaotian Jing #include <linux/pinctrl/consumer.h> 1820848903SChaotian Jing #include <linux/platform_device.h> 194b8a43e9SChaotian Jing #include <linux/pm.h> 204b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2120848903SChaotian Jing #include <linux/regulator/consumer.h> 226397b7f5SChaotian Jing #include <linux/slab.h> 2320848903SChaotian Jing #include <linux/spinlock.h> 24b8789ec4SUlf Hansson #include <linux/interrupt.h> 2520848903SChaotian Jing 2620848903SChaotian Jing #include <linux/mmc/card.h> 2720848903SChaotian Jing #include <linux/mmc/core.h> 2820848903SChaotian Jing #include <linux/mmc/host.h> 2920848903SChaotian Jing #include <linux/mmc/mmc.h> 3020848903SChaotian Jing #include <linux/mmc/sd.h> 3120848903SChaotian Jing #include <linux/mmc/sdio.h> 328d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 3320848903SChaotian Jing 3420848903SChaotian Jing #define MAX_BD_NUM 1024 3520848903SChaotian Jing 3620848903SChaotian Jing /*--------------------------------------------------------------------------*/ 3720848903SChaotian Jing /* Common Definition */ 3820848903SChaotian Jing /*--------------------------------------------------------------------------*/ 3920848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4020848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4120848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4220848903SChaotian Jing 4320848903SChaotian Jing #define MSDC_BURST_64B 0x6 4420848903SChaotian Jing 4520848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4620848903SChaotian Jing /* Register Offset */ 4720848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4820848903SChaotian Jing #define MSDC_CFG 0x0 4920848903SChaotian Jing #define MSDC_IOCON 0x04 5020848903SChaotian Jing #define MSDC_PS 0x08 5120848903SChaotian Jing #define MSDC_INT 0x0c 5220848903SChaotian Jing #define MSDC_INTEN 0x10 5320848903SChaotian Jing #define MSDC_FIFOCS 0x14 5420848903SChaotian Jing #define SDC_CFG 0x30 5520848903SChaotian Jing #define SDC_CMD 0x34 5620848903SChaotian Jing #define SDC_ARG 0x38 5720848903SChaotian Jing #define SDC_STS 0x3c 5820848903SChaotian Jing #define SDC_RESP0 0x40 5920848903SChaotian Jing #define SDC_RESP1 0x44 6020848903SChaotian Jing #define SDC_RESP2 0x48 6120848903SChaotian Jing #define SDC_RESP3 0x4c 6220848903SChaotian Jing #define SDC_BLK_NUM 0x50 63d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 64c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 6520848903SChaotian Jing #define SDC_ACMD_RESP 0x80 662a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 6720848903SChaotian Jing #define MSDC_DMA_SA 0x90 6820848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 6920848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7020848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7120848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 722fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 7320848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 7439add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 756397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 761ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 776397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 78c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 79d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 8020848903SChaotian Jing 8120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 82a2e6d1f6SChaotian Jing /* Top Pad Register Offset */ 83a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 84a2e6d1f6SChaotian Jing #define EMMC_TOP_CONTROL 0x00 85a2e6d1f6SChaotian Jing #define EMMC_TOP_CMD 0x04 86a2e6d1f6SChaotian Jing #define EMMC50_PAD_DS_TUNE 0x0c 87a2e6d1f6SChaotian Jing 88a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 8920848903SChaotian Jing /* Register Mask */ 9020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 9120848903SChaotian Jing 9220848903SChaotian Jing /* MSDC_CFG mask */ 9320848903SChaotian Jing #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 9420848903SChaotian Jing #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 9520848903SChaotian Jing #define MSDC_CFG_RST (0x1 << 2) /* RW */ 9620848903SChaotian Jing #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 9720848903SChaotian Jing #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 9820848903SChaotian Jing #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 9920848903SChaotian Jing #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 10020848903SChaotian Jing #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 10120848903SChaotian Jing #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 10220848903SChaotian Jing #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 1036397b7f5SChaotian Jing #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 104762d491aSChaotian Jing #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 105762d491aSChaotian Jing #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 106762d491aSChaotian Jing #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 10720848903SChaotian Jing 10820848903SChaotian Jing /* MSDC_IOCON mask */ 10920848903SChaotian Jing #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 11020848903SChaotian Jing #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 11120848903SChaotian Jing #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 11220848903SChaotian Jing #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 11320848903SChaotian Jing #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 11420848903SChaotian Jing #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 11520848903SChaotian Jing #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 11620848903SChaotian Jing #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 11720848903SChaotian Jing #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 11820848903SChaotian Jing #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 11920848903SChaotian Jing #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 12020848903SChaotian Jing #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 12120848903SChaotian Jing #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 12220848903SChaotian Jing #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 12320848903SChaotian Jing #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 12420848903SChaotian Jing #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 12520848903SChaotian Jing 12620848903SChaotian Jing /* MSDC_PS mask */ 12720848903SChaotian Jing #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 12820848903SChaotian Jing #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 12920848903SChaotian Jing #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 13020848903SChaotian Jing #define MSDC_PS_DAT (0xff << 16) /* R */ 13120848903SChaotian Jing #define MSDC_PS_CMD (0x1 << 24) /* R */ 13220848903SChaotian Jing #define MSDC_PS_WP (0x1 << 31) /* R */ 13320848903SChaotian Jing 13420848903SChaotian Jing /* MSDC_INT mask */ 13520848903SChaotian Jing #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 13620848903SChaotian Jing #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 13720848903SChaotian Jing #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 13820848903SChaotian Jing #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 13920848903SChaotian Jing #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 14020848903SChaotian Jing #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 14120848903SChaotian Jing #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 14220848903SChaotian Jing #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 14320848903SChaotian Jing #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 14420848903SChaotian Jing #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 14520848903SChaotian Jing #define MSDC_INT_CSTA (0x1 << 11) /* R */ 14620848903SChaotian Jing #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 14720848903SChaotian Jing #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 14820848903SChaotian Jing #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 14920848903SChaotian Jing #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 15020848903SChaotian Jing #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 15120848903SChaotian Jing #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 15220848903SChaotian Jing #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 15320848903SChaotian Jing #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 15420848903SChaotian Jing 15520848903SChaotian Jing /* MSDC_INTEN mask */ 15620848903SChaotian Jing #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 15720848903SChaotian Jing #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 15820848903SChaotian Jing #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 15920848903SChaotian Jing #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 16020848903SChaotian Jing #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 16120848903SChaotian Jing #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 16220848903SChaotian Jing #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 16320848903SChaotian Jing #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 16420848903SChaotian Jing #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 16520848903SChaotian Jing #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 16620848903SChaotian Jing #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 16720848903SChaotian Jing #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 16820848903SChaotian Jing #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 16920848903SChaotian Jing #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 17020848903SChaotian Jing #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 17120848903SChaotian Jing #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 17220848903SChaotian Jing #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 17320848903SChaotian Jing #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 17420848903SChaotian Jing #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 17520848903SChaotian Jing 17620848903SChaotian Jing /* MSDC_FIFOCS mask */ 17720848903SChaotian Jing #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 17820848903SChaotian Jing #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 17920848903SChaotian Jing #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 18020848903SChaotian Jing 18120848903SChaotian Jing /* SDC_CFG mask */ 18220848903SChaotian Jing #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 18320848903SChaotian Jing #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 18420848903SChaotian Jing #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 18520848903SChaotian Jing #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 18620848903SChaotian Jing #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 18720848903SChaotian Jing #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 18820848903SChaotian Jing #define SDC_CFG_DTOC (0xff << 24) /* RW */ 18920848903SChaotian Jing 19020848903SChaotian Jing /* SDC_STS mask */ 19120848903SChaotian Jing #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 19220848903SChaotian Jing #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 19320848903SChaotian Jing #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 19420848903SChaotian Jing 19526c71a13Syong mao #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 196d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 197d9dcbfc8SChaotian Jing #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 198d9dcbfc8SChaotian Jing 1992a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2002a9bde19SChaotian Jing #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 2012a9bde19SChaotian Jing 20220848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 20320848903SChaotian Jing #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 20420848903SChaotian Jing #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 20520848903SChaotian Jing #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 20620848903SChaotian Jing #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 20720848903SChaotian Jing #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 20820848903SChaotian Jing #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 20920848903SChaotian Jing 21020848903SChaotian Jing /* MSDC_DMA_CFG mask */ 21120848903SChaotian Jing #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 21220848903SChaotian Jing #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 21320848903SChaotian Jing #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 21420848903SChaotian Jing #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 21520848903SChaotian Jing #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 21620848903SChaotian Jing 21720848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 21820848903SChaotian Jing #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 21920848903SChaotian Jing #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 22020848903SChaotian Jing #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 22120848903SChaotian Jing #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 22220848903SChaotian Jing #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 22320848903SChaotian Jing #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 22420848903SChaotian Jing #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 22520848903SChaotian Jing #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 22620848903SChaotian Jing #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 22720848903SChaotian Jing #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 22820848903SChaotian Jing #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 22920848903SChaotian Jing #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 23020848903SChaotian Jing 2318f34e5bdSChaotian Jing #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 232d9dcbfc8SChaotian Jing #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 233d9dcbfc8SChaotian Jing 2342fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 2352fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 2362a9bde19SChaotian Jing #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 2372fea5819SChaotian Jing #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 2382fea5819SChaotian Jing #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 2392fea5819SChaotian Jing #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 2402fea5819SChaotian Jing 2411ede5cb8Syong mao #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 2426397b7f5SChaotian Jing #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 2436397b7f5SChaotian Jing #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 2441ede5cb8Syong mao #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 2451ede5cb8Syong mao #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 2462fea5819SChaotian Jing #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 2472fea5819SChaotian Jing #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 2482fea5819SChaotian Jing #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 2496397b7f5SChaotian Jing 2506397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 2516397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 2526397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 2536397b7f5SChaotian Jing 2541ede5cb8Syong mao #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 2551ede5cb8Syong mao 2566397b7f5SChaotian Jing #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 2576397b7f5SChaotian Jing #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 2586397b7f5SChaotian Jing #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 2596397b7f5SChaotian Jing 260c8609b22SChaotian Jing #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 261c8609b22SChaotian Jing 262d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 263d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 264d9dcbfc8SChaotian Jing 265a2e6d1f6SChaotian Jing /* EMMC_TOP_CONTROL mask */ 266a2e6d1f6SChaotian Jing #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 267a2e6d1f6SChaotian Jing #define DELAY_EN (0x1 << 1) /* RW */ 268a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 269a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 270a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 271a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 272a2e6d1f6SChaotian Jing #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 273a2e6d1f6SChaotian Jing #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 274a2e6d1f6SChaotian Jing 275a2e6d1f6SChaotian Jing /* EMMC_TOP_CMD mask */ 276a2e6d1f6SChaotian Jing #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 277a2e6d1f6SChaotian Jing #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 278a2e6d1f6SChaotian Jing #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 279a2e6d1f6SChaotian Jing #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 280a2e6d1f6SChaotian Jing #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 281a2e6d1f6SChaotian Jing 28220848903SChaotian Jing #define REQ_CMD_EIO (0x1 << 0) 28320848903SChaotian Jing #define REQ_CMD_TMO (0x1 << 1) 28420848903SChaotian Jing #define REQ_DAT_ERR (0x1 << 2) 28520848903SChaotian Jing #define REQ_STOP_EIO (0x1 << 3) 28620848903SChaotian Jing #define REQ_STOP_TMO (0x1 << 4) 28720848903SChaotian Jing #define REQ_CMD_BUSY (0x1 << 5) 28820848903SChaotian Jing 28920848903SChaotian Jing #define MSDC_PREPARE_FLAG (0x1 << 0) 29020848903SChaotian Jing #define MSDC_ASYNC_FLAG (0x1 << 1) 29120848903SChaotian Jing #define MSDC_MMAP_FLAG (0x1 << 2) 29220848903SChaotian Jing 2934b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 29420848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 29520848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 29620848903SChaotian Jing 297d087bde5SNeilBrown #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 298d087bde5SNeilBrown 2996397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 30020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 30120848903SChaotian Jing /* Descriptor Structure */ 30220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 30320848903SChaotian Jing struct mt_gpdma_desc { 30420848903SChaotian Jing u32 gpd_info; 30520848903SChaotian Jing #define GPDMA_DESC_HWO (0x1 << 0) 30620848903SChaotian Jing #define GPDMA_DESC_BDP (0x1 << 1) 30720848903SChaotian Jing #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 30820848903SChaotian Jing #define GPDMA_DESC_INT (0x1 << 16) 3092a9bde19SChaotian Jing #define GPDMA_DESC_NEXT_H4 (0xf << 24) 3102a9bde19SChaotian Jing #define GPDMA_DESC_PTR_H4 (0xf << 28) 31120848903SChaotian Jing u32 next; 31220848903SChaotian Jing u32 ptr; 31320848903SChaotian Jing u32 gpd_data_len; 31420848903SChaotian Jing #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 31520848903SChaotian Jing #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 31620848903SChaotian Jing u32 arg; 31720848903SChaotian Jing u32 blknum; 31820848903SChaotian Jing u32 cmd; 31920848903SChaotian Jing }; 32020848903SChaotian Jing 32120848903SChaotian Jing struct mt_bdma_desc { 32220848903SChaotian Jing u32 bd_info; 32320848903SChaotian Jing #define BDMA_DESC_EOL (0x1 << 0) 32420848903SChaotian Jing #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 32520848903SChaotian Jing #define BDMA_DESC_BLKPAD (0x1 << 17) 32620848903SChaotian Jing #define BDMA_DESC_DWPAD (0x1 << 18) 3272a9bde19SChaotian Jing #define BDMA_DESC_NEXT_H4 (0xf << 24) 3282a9bde19SChaotian Jing #define BDMA_DESC_PTR_H4 (0xf << 28) 32920848903SChaotian Jing u32 next; 33020848903SChaotian Jing u32 ptr; 33120848903SChaotian Jing u32 bd_data_len; 33220848903SChaotian Jing #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 3336ef042bdSChaotian Jing #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 33420848903SChaotian Jing }; 33520848903SChaotian Jing 33620848903SChaotian Jing struct msdc_dma { 33720848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 33820848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 33920848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 34020848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 34120848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 34220848903SChaotian Jing }; 34320848903SChaotian Jing 3444b8a43e9SChaotian Jing struct msdc_save_para { 3454b8a43e9SChaotian Jing u32 msdc_cfg; 3464b8a43e9SChaotian Jing u32 iocon; 3474b8a43e9SChaotian Jing u32 sdc_cfg; 3484b8a43e9SChaotian Jing u32 pad_tune; 3494b8a43e9SChaotian Jing u32 patch_bit0; 3504b8a43e9SChaotian Jing u32 patch_bit1; 3512fea5819SChaotian Jing u32 patch_bit2; 3526397b7f5SChaotian Jing u32 pad_ds_tune; 3531ede5cb8Syong mao u32 pad_cmd_tune; 3546397b7f5SChaotian Jing u32 emmc50_cfg0; 355c8609b22SChaotian Jing u32 emmc50_cfg3; 356d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 357a2e6d1f6SChaotian Jing u32 emmc_top_control; 358a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 359a2e6d1f6SChaotian Jing u32 emmc50_pad_ds_tune; 3606397b7f5SChaotian Jing }; 3616397b7f5SChaotian Jing 362762d491aSChaotian Jing struct mtk_mmc_compatible { 363762d491aSChaotian Jing u8 clk_div_bits; 3647f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 36539add252SChaotian Jing u32 pad_tune_reg; 3662fea5819SChaotian Jing bool async_fifo; 3672fea5819SChaotian Jing bool data_tune; 368acde28c4SChaotian Jing bool busy_check; 369d9dcbfc8SChaotian Jing bool stop_clk_fix; 370d9dcbfc8SChaotian Jing bool enhance_rx; 3712a9bde19SChaotian Jing bool support_64g; 372d087bde5SNeilBrown bool use_internal_cd; 373762d491aSChaotian Jing }; 374762d491aSChaotian Jing 37586beac37SChaotian Jing struct msdc_tune_para { 37686beac37SChaotian Jing u32 iocon; 37786beac37SChaotian Jing u32 pad_tune; 3781ede5cb8Syong mao u32 pad_cmd_tune; 379a2e6d1f6SChaotian Jing u32 emmc_top_control; 380a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 38186beac37SChaotian Jing }; 38286beac37SChaotian Jing 3836397b7f5SChaotian Jing struct msdc_delay_phase { 3846397b7f5SChaotian Jing u8 maxlen; 3856397b7f5SChaotian Jing u8 start; 3866397b7f5SChaotian Jing u8 final_phase; 3874b8a43e9SChaotian Jing }; 3884b8a43e9SChaotian Jing 38920848903SChaotian Jing struct msdc_host { 39020848903SChaotian Jing struct device *dev; 391762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 39220848903SChaotian Jing struct mmc_host *mmc; /* mmc structure */ 39320848903SChaotian Jing int cmd_rsp; 39420848903SChaotian Jing 39520848903SChaotian Jing spinlock_t lock; 39620848903SChaotian Jing struct mmc_request *mrq; 39720848903SChaotian Jing struct mmc_command *cmd; 39820848903SChaotian Jing struct mmc_data *data; 39920848903SChaotian Jing int error; 40020848903SChaotian Jing 40120848903SChaotian Jing void __iomem *base; /* host base address */ 402a2e6d1f6SChaotian Jing void __iomem *top_base; /* host top register base address */ 40320848903SChaotian Jing 40420848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 40520848903SChaotian Jing u64 dma_mask; 40620848903SChaotian Jing 40720848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 40820848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 40920848903SChaotian Jing 41020848903SChaotian Jing struct pinctrl *pinctrl; 41120848903SChaotian Jing struct pinctrl_state *pins_default; 41220848903SChaotian Jing struct pinctrl_state *pins_uhs; 41320848903SChaotian Jing struct delayed_work req_timeout; 41420848903SChaotian Jing int irq; /* host interrupt */ 41520848903SChaotian Jing 41620848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 41720848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 418258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 4193c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 42020848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 42120848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 4226e622947SChaotian Jing unsigned char timing; 42320848903SChaotian Jing bool vqmmc_enabled; 424d17bb71cSChaotian Jing u32 latch_ck; 4256397b7f5SChaotian Jing u32 hs400_ds_delay; 4261ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 4271ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4281ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4291ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4305462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 431d087bde5SNeilBrown bool internal_cd; /* Use internal card-detect logic */ 4324b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 43386beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 43486beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 43520848903SChaotian Jing }; 43620848903SChaotian Jing 437762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 438762d491aSChaotian Jing .clk_div_bits = 8, 4397f3d5852SChaotian Jing .hs400_tune = false, 44039add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4412fea5819SChaotian Jing .async_fifo = false, 4422fea5819SChaotian Jing .data_tune = false, 443acde28c4SChaotian Jing .busy_check = false, 444d9dcbfc8SChaotian Jing .stop_clk_fix = false, 445d9dcbfc8SChaotian Jing .enhance_rx = false, 4462a9bde19SChaotian Jing .support_64g = false, 447762d491aSChaotian Jing }; 448762d491aSChaotian Jing 449762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 450762d491aSChaotian Jing .clk_div_bits = 8, 4517f3d5852SChaotian Jing .hs400_tune = true, 45239add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4532fea5819SChaotian Jing .async_fifo = false, 4542fea5819SChaotian Jing .data_tune = false, 455acde28c4SChaotian Jing .busy_check = false, 456d9dcbfc8SChaotian Jing .stop_clk_fix = false, 457d9dcbfc8SChaotian Jing .enhance_rx = false, 4582a9bde19SChaotian Jing .support_64g = false, 459762d491aSChaotian Jing }; 460762d491aSChaotian Jing 461a2e6d1f6SChaotian Jing static const struct mtk_mmc_compatible mt8183_compat = { 462a2e6d1f6SChaotian Jing .clk_div_bits = 12, 463a2e6d1f6SChaotian Jing .hs400_tune = false, 464a2e6d1f6SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 465a2e6d1f6SChaotian Jing .async_fifo = true, 466a2e6d1f6SChaotian Jing .data_tune = true, 467a2e6d1f6SChaotian Jing .busy_check = true, 468a2e6d1f6SChaotian Jing .stop_clk_fix = true, 469a2e6d1f6SChaotian Jing .enhance_rx = true, 470a2e6d1f6SChaotian Jing .support_64g = true, 471a2e6d1f6SChaotian Jing }; 472a2e6d1f6SChaotian Jing 473762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2701_compat = { 474762d491aSChaotian Jing .clk_div_bits = 12, 4757f3d5852SChaotian Jing .hs400_tune = false, 47639add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 4772fea5819SChaotian Jing .async_fifo = true, 4782fea5819SChaotian Jing .data_tune = true, 479acde28c4SChaotian Jing .busy_check = false, 480d9dcbfc8SChaotian Jing .stop_clk_fix = false, 481d9dcbfc8SChaotian Jing .enhance_rx = false, 4822a9bde19SChaotian Jing .support_64g = false, 483762d491aSChaotian Jing }; 484762d491aSChaotian Jing 485762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2712_compat = { 486762d491aSChaotian Jing .clk_div_bits = 12, 4877f3d5852SChaotian Jing .hs400_tune = false, 48839add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 4892fea5819SChaotian Jing .async_fifo = true, 4902fea5819SChaotian Jing .data_tune = true, 491acde28c4SChaotian Jing .busy_check = true, 492d9dcbfc8SChaotian Jing .stop_clk_fix = true, 493d9dcbfc8SChaotian Jing .enhance_rx = true, 4942a9bde19SChaotian Jing .support_64g = true, 495762d491aSChaotian Jing }; 496762d491aSChaotian Jing 497966580adSSean Wang static const struct mtk_mmc_compatible mt7622_compat = { 498966580adSSean Wang .clk_div_bits = 12, 499966580adSSean Wang .hs400_tune = false, 500966580adSSean Wang .pad_tune_reg = MSDC_PAD_TUNE0, 501966580adSSean Wang .async_fifo = true, 502966580adSSean Wang .data_tune = true, 503966580adSSean Wang .busy_check = true, 504966580adSSean Wang .stop_clk_fix = true, 505966580adSSean Wang .enhance_rx = true, 5062a9bde19SChaotian Jing .support_64g = false, 507966580adSSean Wang }; 508966580adSSean Wang 50989822b73SFabien Parent static const struct mtk_mmc_compatible mt8516_compat = { 51089822b73SFabien Parent .clk_div_bits = 12, 51189822b73SFabien Parent .hs400_tune = false, 51289822b73SFabien Parent .pad_tune_reg = MSDC_PAD_TUNE0, 51389822b73SFabien Parent .async_fifo = true, 51489822b73SFabien Parent .data_tune = true, 51589822b73SFabien Parent .busy_check = true, 51689822b73SFabien Parent .stop_clk_fix = true, 51789822b73SFabien Parent }; 51889822b73SFabien Parent 519afb7c791SNeilBrown static const struct mtk_mmc_compatible mt7620_compat = { 520afb7c791SNeilBrown .clk_div_bits = 8, 521afb7c791SNeilBrown .hs400_tune = false, 522afb7c791SNeilBrown .pad_tune_reg = MSDC_PAD_TUNE, 523afb7c791SNeilBrown .async_fifo = false, 524afb7c791SNeilBrown .data_tune = false, 525afb7c791SNeilBrown .busy_check = false, 526afb7c791SNeilBrown .stop_clk_fix = false, 527afb7c791SNeilBrown .enhance_rx = false, 528d087bde5SNeilBrown .use_internal_cd = true, 529afb7c791SNeilBrown }; 530afb7c791SNeilBrown 531762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 532762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 533762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 534a2e6d1f6SChaotian Jing { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 535762d491aSChaotian Jing { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 536762d491aSChaotian Jing { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 537966580adSSean Wang { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 53889822b73SFabien Parent { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 539afb7c791SNeilBrown { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 540762d491aSChaotian Jing {} 541762d491aSChaotian Jing }; 542762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 543762d491aSChaotian Jing 54420848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 54520848903SChaotian Jing { 54620848903SChaotian Jing u32 val = readl(reg); 54720848903SChaotian Jing 54820848903SChaotian Jing val |= bs; 54920848903SChaotian Jing writel(val, reg); 55020848903SChaotian Jing } 55120848903SChaotian Jing 55220848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 55320848903SChaotian Jing { 55420848903SChaotian Jing u32 val = readl(reg); 55520848903SChaotian Jing 55620848903SChaotian Jing val &= ~bs; 55720848903SChaotian Jing writel(val, reg); 55820848903SChaotian Jing } 55920848903SChaotian Jing 56020848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 56120848903SChaotian Jing { 56220848903SChaotian Jing unsigned int tv = readl(reg); 56320848903SChaotian Jing 56420848903SChaotian Jing tv &= ~field; 56520848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 56620848903SChaotian Jing writel(tv, reg); 56720848903SChaotian Jing } 56820848903SChaotian Jing 56920848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 57020848903SChaotian Jing { 57120848903SChaotian Jing unsigned int tv = readl(reg); 57220848903SChaotian Jing 57320848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 57420848903SChaotian Jing } 57520848903SChaotian Jing 57620848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 57720848903SChaotian Jing { 57820848903SChaotian Jing u32 val; 57920848903SChaotian Jing 58020848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 58120848903SChaotian Jing while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 58220848903SChaotian Jing cpu_relax(); 58320848903SChaotian Jing 58420848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 58520848903SChaotian Jing while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 58620848903SChaotian Jing cpu_relax(); 58720848903SChaotian Jing 58820848903SChaotian Jing val = readl(host->base + MSDC_INT); 58920848903SChaotian Jing writel(val, host->base + MSDC_INT); 59020848903SChaotian Jing } 59120848903SChaotian Jing 59220848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 59320848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 59420848903SChaotian Jing 595726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 596726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 597726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 598726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 59920848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 60020848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 60120848903SChaotian Jing 60220848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 60320848903SChaotian Jing { 60420848903SChaotian Jing u32 i, sum = 0; 60520848903SChaotian Jing 60620848903SChaotian Jing for (i = 0; i < len; i++) 60720848903SChaotian Jing sum += buf[i]; 60820848903SChaotian Jing return 0xff - (u8) sum; 60920848903SChaotian Jing } 61020848903SChaotian Jing 61120848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 61220848903SChaotian Jing struct mmc_data *data) 61320848903SChaotian Jing { 61420848903SChaotian Jing unsigned int j, dma_len; 61520848903SChaotian Jing dma_addr_t dma_address; 61620848903SChaotian Jing u32 dma_ctrl; 61720848903SChaotian Jing struct scatterlist *sg; 61820848903SChaotian Jing struct mt_gpdma_desc *gpd; 61920848903SChaotian Jing struct mt_bdma_desc *bd; 62020848903SChaotian Jing 62120848903SChaotian Jing sg = data->sg; 62220848903SChaotian Jing 62320848903SChaotian Jing gpd = dma->gpd; 62420848903SChaotian Jing bd = dma->bd; 62520848903SChaotian Jing 62620848903SChaotian Jing /* modify gpd */ 62720848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 62820848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 62920848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 63020848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 63120848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 63220848903SChaotian Jing 63320848903SChaotian Jing /* modify bd */ 63420848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 63520848903SChaotian Jing dma_address = sg_dma_address(sg); 63620848903SChaotian Jing dma_len = sg_dma_len(sg); 63720848903SChaotian Jing 63820848903SChaotian Jing /* init bd */ 63920848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 64020848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 6412a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 6422a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 6432a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 6442a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 6452a9bde19SChaotian Jing << 28; 6462a9bde19SChaotian Jing } 6476ef042bdSChaotian Jing 6486ef042bdSChaotian Jing if (host->dev_comp->support_64g) { 6496ef042bdSChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 6506ef042bdSChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 6516ef042bdSChaotian Jing } else { 65220848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 65320848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 6546ef042bdSChaotian Jing } 65520848903SChaotian Jing 65620848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 65720848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 65820848903SChaotian Jing else 65920848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 66020848903SChaotian Jing 66120848903SChaotian Jing /* checksume need to clear first */ 66220848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 66320848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 66420848903SChaotian Jing } 66520848903SChaotian Jing 66620848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 66720848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 66820848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 66920848903SChaotian Jing dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 67020848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 6712a9bde19SChaotian Jing if (host->dev_comp->support_64g) 6722a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 6732a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 6742a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 67520848903SChaotian Jing } 67620848903SChaotian Jing 67720848903SChaotian Jing static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 67820848903SChaotian Jing { 67920848903SChaotian Jing struct mmc_data *data = mrq->data; 68020848903SChaotian Jing 68120848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 68220848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 68320848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 684feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 68520848903SChaotian Jing } 68620848903SChaotian Jing } 68720848903SChaotian Jing 68820848903SChaotian Jing static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 68920848903SChaotian Jing { 69020848903SChaotian Jing struct mmc_data *data = mrq->data; 69120848903SChaotian Jing 69220848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 69320848903SChaotian Jing return; 69420848903SChaotian Jing 69520848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 69620848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 697feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 69820848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 69920848903SChaotian Jing } 70020848903SChaotian Jing } 70120848903SChaotian Jing 70220848903SChaotian Jing /* clock control primitives */ 70320848903SChaotian Jing static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 70420848903SChaotian Jing { 70520848903SChaotian Jing u32 timeout, clk_ns; 70620848903SChaotian Jing u32 mode = 0; 70720848903SChaotian Jing 70820848903SChaotian Jing host->timeout_ns = ns; 70920848903SChaotian Jing host->timeout_clks = clks; 71056f6cbbeSChaotian Jing if (host->mmc->actual_clock == 0) { 71120848903SChaotian Jing timeout = 0; 71220848903SChaotian Jing } else { 71356f6cbbeSChaotian Jing clk_ns = 1000000000UL / host->mmc->actual_clock; 71420848903SChaotian Jing timeout = (ns + clk_ns - 1) / clk_ns + clks; 71520848903SChaotian Jing /* in 1048576 sclk cycle unit */ 71620848903SChaotian Jing timeout = (timeout + (0x1 << 20) - 1) >> 20; 717762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 718762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 719762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 720762d491aSChaotian Jing else 721762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 722762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 72320848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 72420848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 72520848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 72620848903SChaotian Jing timeout = timeout > 255 ? 255 : timeout; 72720848903SChaotian Jing } 72820848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 72920848903SChaotian Jing } 73020848903SChaotian Jing 73120848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 73220848903SChaotian Jing { 7333c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 73420848903SChaotian Jing clk_disable_unprepare(host->src_clk); 735258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 73620848903SChaotian Jing clk_disable_unprepare(host->h_clk); 73720848903SChaotian Jing } 73820848903SChaotian Jing 73920848903SChaotian Jing static void msdc_ungate_clock(struct msdc_host *host) 74020848903SChaotian Jing { 74120848903SChaotian Jing clk_prepare_enable(host->h_clk); 742258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 74320848903SChaotian Jing clk_prepare_enable(host->src_clk); 7443c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 74520848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 74620848903SChaotian Jing cpu_relax(); 74720848903SChaotian Jing } 74820848903SChaotian Jing 7496e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 75020848903SChaotian Jing { 75120848903SChaotian Jing u32 mode; 75220848903SChaotian Jing u32 flags; 75320848903SChaotian Jing u32 div; 75420848903SChaotian Jing u32 sclk; 75539add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 75620848903SChaotian Jing 75720848903SChaotian Jing if (!hz) { 75820848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 75920848903SChaotian Jing host->mclk = 0; 76056f6cbbeSChaotian Jing host->mmc->actual_clock = 0; 76120848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 76220848903SChaotian Jing return; 76320848903SChaotian Jing } 76420848903SChaotian Jing 76520848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 76620848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 767762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 7686397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 769762d491aSChaotian Jing else 770762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 771762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 7726e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 7736397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 7746397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 7756397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 7766397b7f5SChaotian Jing mode = 0x3; 7776397b7f5SChaotian Jing else 77820848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 7796397b7f5SChaotian Jing 78020848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 78120848903SChaotian Jing div = 0; /* mean div = 1/4 */ 78220848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 78320848903SChaotian Jing } else { 78420848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 78520848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 78620848903SChaotian Jing div = (div >> 1); 78720848903SChaotian Jing } 7886397b7f5SChaotian Jing 7896397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 7906397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 791762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 7926397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 7936397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 794762d491aSChaotian Jing else 795762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 796762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 7976397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 7986397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 7996397b7f5SChaotian Jing } 80020848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 80120848903SChaotian Jing mode = 0x1; /* no divisor */ 80220848903SChaotian Jing div = 0; 80320848903SChaotian Jing sclk = host->src_clk_freq; 80420848903SChaotian Jing } else { 80520848903SChaotian Jing mode = 0x0; /* use divisor */ 80620848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 80720848903SChaotian Jing div = 0; /* mean div = 1/2 */ 80820848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 80920848903SChaotian Jing } else { 81020848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 81120848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 81220848903SChaotian Jing } 81320848903SChaotian Jing } 8143c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 8153c1a8844SChaotian Jing /* 8163c1a8844SChaotian Jing * As src_clk/HCLK use the same bit to gate/ungate, 8173c1a8844SChaotian Jing * So if want to only gate src_clk, need gate its parent(mux). 8183c1a8844SChaotian Jing */ 8193c1a8844SChaotian Jing if (host->src_clk_cg) 8203c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 8213c1a8844SChaotian Jing else 8223c1a8844SChaotian Jing clk_disable_unprepare(clk_get_parent(host->src_clk)); 823762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 824762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 825762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 82640ceda09Syong mao (mode << 8) | div); 827762d491aSChaotian Jing else 828762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 829762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 830762d491aSChaotian Jing (mode << 12) | div); 8313c1a8844SChaotian Jing if (host->src_clk_cg) 8323c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 8333c1a8844SChaotian Jing else 8343c1a8844SChaotian Jing clk_prepare_enable(clk_get_parent(host->src_clk)); 835762d491aSChaotian Jing 83620848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 83720848903SChaotian Jing cpu_relax(); 8383c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 83956f6cbbeSChaotian Jing host->mmc->actual_clock = sclk; 84020848903SChaotian Jing host->mclk = hz; 8416e622947SChaotian Jing host->timing = timing; 84220848903SChaotian Jing /* need because clk changed. */ 84320848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 84420848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 84520848903SChaotian Jing 84686beac37SChaotian Jing /* 84786beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 84886beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 84986beac37SChaotian Jing */ 85056f6cbbeSChaotian Jing if (host->mmc->actual_clock <= 52000000) { 85186beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 852a2e6d1f6SChaotian Jing if (host->top_base) { 853a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_control, 854a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 855a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_cmd, 856a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 857a2e6d1f6SChaotian Jing } else { 858a2e6d1f6SChaotian Jing writel(host->def_tune_para.pad_tune, 859a2e6d1f6SChaotian Jing host->base + tune_reg); 860a2e6d1f6SChaotian Jing } 86186beac37SChaotian Jing } else { 86286beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 8631ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 8641ede5cb8Syong mao host->base + PAD_CMD_TUNE); 865a2e6d1f6SChaotian Jing if (host->top_base) { 866a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_control, 867a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 868a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_cmd, 869a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 870a2e6d1f6SChaotian Jing } else { 871a2e6d1f6SChaotian Jing writel(host->saved_tune_para.pad_tune, 872a2e6d1f6SChaotian Jing host->base + tune_reg); 873a2e6d1f6SChaotian Jing } 87486beac37SChaotian Jing } 87586beac37SChaotian Jing 8767f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 8777f3d5852SChaotian Jing host->dev_comp->hs400_tune) 8783751e008SChaotian Jing sdr_set_field(host->base + tune_reg, 8791ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 8801ede5cb8Syong mao host->hs400_cmd_int_delay); 88156f6cbbeSChaotian Jing dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 88256f6cbbeSChaotian Jing timing); 88320848903SChaotian Jing } 88420848903SChaotian Jing 88520848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 88620848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 88720848903SChaotian Jing { 88820848903SChaotian Jing u32 resp; 88920848903SChaotian Jing 89020848903SChaotian Jing switch (mmc_resp_type(cmd)) { 89120848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 89220848903SChaotian Jing case MMC_RSP_R1: 89320848903SChaotian Jing resp = 0x1; 89420848903SChaotian Jing break; 89520848903SChaotian Jing case MMC_RSP_R1B: 89620848903SChaotian Jing resp = 0x7; 89720848903SChaotian Jing break; 89820848903SChaotian Jing case MMC_RSP_R2: 89920848903SChaotian Jing resp = 0x2; 90020848903SChaotian Jing break; 90120848903SChaotian Jing case MMC_RSP_R3: 90220848903SChaotian Jing resp = 0x3; 90320848903SChaotian Jing break; 90420848903SChaotian Jing case MMC_RSP_NONE: 90520848903SChaotian Jing default: 90620848903SChaotian Jing resp = 0x0; 90720848903SChaotian Jing break; 90820848903SChaotian Jing } 90920848903SChaotian Jing 91020848903SChaotian Jing return resp; 91120848903SChaotian Jing } 91220848903SChaotian Jing 91320848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 91420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 91520848903SChaotian Jing { 91620848903SChaotian Jing /* rawcmd : 91720848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 91820848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 91920848903SChaotian Jing */ 92020848903SChaotian Jing u32 opcode = cmd->opcode; 92120848903SChaotian Jing u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 92220848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 92320848903SChaotian Jing 92420848903SChaotian Jing host->cmd_rsp = resp; 92520848903SChaotian Jing 92620848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 92720848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 92820848903SChaotian Jing rawcmd |= (0x1 << 14); 92920848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 93020848903SChaotian Jing rawcmd |= (0x1 << 30); 93120848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 93220848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 93320848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 93420848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 93520848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 93620848903SChaotian Jing rawcmd |= (0x1 << 11); 93720848903SChaotian Jing 93820848903SChaotian Jing if (cmd->data) { 93920848903SChaotian Jing struct mmc_data *data = cmd->data; 94020848903SChaotian Jing 94120848903SChaotian Jing if (mmc_op_multi(opcode)) { 94220848903SChaotian Jing if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 94320848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 94420848903SChaotian Jing rawcmd |= 0x2 << 28; /* AutoCMD23 */ 94520848903SChaotian Jing } 94620848903SChaotian Jing 94720848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 94820848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 94920848903SChaotian Jing rawcmd |= (0x1 << 13); 95020848903SChaotian Jing if (data->blocks > 1) 95120848903SChaotian Jing rawcmd |= (0x2 << 11); 95220848903SChaotian Jing else 95320848903SChaotian Jing rawcmd |= (0x1 << 11); 95420848903SChaotian Jing /* Always use dma mode */ 95520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 95620848903SChaotian Jing 95720848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 95820848903SChaotian Jing host->timeout_clks != data->timeout_clks) 95920848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 96020848903SChaotian Jing data->timeout_clks); 96120848903SChaotian Jing 96220848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 96320848903SChaotian Jing } 96420848903SChaotian Jing return rawcmd; 96520848903SChaotian Jing } 96620848903SChaotian Jing 96720848903SChaotian Jing static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 96820848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 96920848903SChaotian Jing { 97020848903SChaotian Jing bool read; 97120848903SChaotian Jing 97220848903SChaotian Jing WARN_ON(host->data); 97320848903SChaotian Jing host->data = data; 97420848903SChaotian Jing read = data->flags & MMC_DATA_READ; 97520848903SChaotian Jing 97620848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 97720848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 97820848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 97920848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 98020848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 98120848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 98220848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 98320848903SChaotian Jing } 98420848903SChaotian Jing 98520848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 98620848903SChaotian Jing struct mmc_command *cmd) 98720848903SChaotian Jing { 98820848903SChaotian Jing u32 *rsp = cmd->resp; 98920848903SChaotian Jing 99020848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 99120848903SChaotian Jing 99220848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 99320848903SChaotian Jing cmd->error = 0; 99420848903SChaotian Jing } else { 99520848903SChaotian Jing msdc_reset_hw(host); 99620848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 99720848903SChaotian Jing cmd->error = -EILSEQ; 99820848903SChaotian Jing host->error |= REQ_STOP_EIO; 99920848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 100020848903SChaotian Jing cmd->error = -ETIMEDOUT; 100120848903SChaotian Jing host->error |= REQ_STOP_TMO; 100220848903SChaotian Jing } 100320848903SChaotian Jing dev_err(host->dev, 100420848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 100520848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 100620848903SChaotian Jing } 100720848903SChaotian Jing return cmd->error; 100820848903SChaotian Jing } 100920848903SChaotian Jing 101020848903SChaotian Jing static void msdc_track_cmd_data(struct msdc_host *host, 101120848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 101220848903SChaotian Jing { 101320848903SChaotian Jing if (host->error) 101420848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 101520848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 101620848903SChaotian Jing } 101720848903SChaotian Jing 101820848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 101920848903SChaotian Jing { 102020848903SChaotian Jing unsigned long flags; 102120848903SChaotian Jing bool ret; 102220848903SChaotian Jing 102320848903SChaotian Jing ret = cancel_delayed_work(&host->req_timeout); 102420848903SChaotian Jing if (!ret) { 102520848903SChaotian Jing /* delay work already running */ 102620848903SChaotian Jing return; 102720848903SChaotian Jing } 102820848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 102920848903SChaotian Jing host->mrq = NULL; 103020848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 103120848903SChaotian Jing 103220848903SChaotian Jing msdc_track_cmd_data(host, mrq->cmd, mrq->data); 103320848903SChaotian Jing if (mrq->data) 103420848903SChaotian Jing msdc_unprepare_data(host, mrq); 103520314ce3Sjjian zhou if (host->error) 103620314ce3Sjjian zhou msdc_reset_hw(host); 103720848903SChaotian Jing mmc_request_done(host->mmc, mrq); 103820848903SChaotian Jing } 103920848903SChaotian Jing 104020848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 104120848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 104220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 104320848903SChaotian Jing { 104420848903SChaotian Jing bool done = false; 104520848903SChaotian Jing bool sbc_error; 104620848903SChaotian Jing unsigned long flags; 104720848903SChaotian Jing u32 *rsp = cmd->resp; 104820848903SChaotian Jing 104920848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 105020848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 105120848903SChaotian Jing | MSDC_INT_ACMDTMO))) 105220848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 105320848903SChaotian Jing 105420848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 105520848903SChaotian Jing 105620848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 105720848903SChaotian Jing | MSDC_INT_RSPCRCERR 105820848903SChaotian Jing | MSDC_INT_CMDTMO))) 105920848903SChaotian Jing return done; 106020848903SChaotian Jing 106120848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 106220848903SChaotian Jing done = !host->cmd; 106320848903SChaotian Jing host->cmd = NULL; 106420848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 106520848903SChaotian Jing 106620848903SChaotian Jing if (done) 106720848903SChaotian Jing return true; 106820848903SChaotian Jing 1069726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 107020848903SChaotian Jing 107120848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 107220848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 107320848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 107420848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 107520848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 107620848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 107720848903SChaotian Jing } else { 107820848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 107920848903SChaotian Jing } 108020848903SChaotian Jing } 108120848903SChaotian Jing 108220848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1083da6e0f70SChaotian Jing if (events & MSDC_INT_CMDTMO || 1084da6e0f70SChaotian Jing (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1085da6e0f70SChaotian Jing cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1086ddc71387SChaotian Jing /* 1087ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 1088da6e0f70SChaotian Jing * may have alreay come when cmd19/cmd21 gets response 1089da6e0f70SChaotian Jing * CRC error. 1090ddc71387SChaotian Jing */ 109120848903SChaotian Jing msdc_reset_hw(host); 109220848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 109320848903SChaotian Jing cmd->error = -EILSEQ; 109420848903SChaotian Jing host->error |= REQ_CMD_EIO; 109520848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 109620848903SChaotian Jing cmd->error = -ETIMEDOUT; 109720848903SChaotian Jing host->error |= REQ_CMD_TMO; 109820848903SChaotian Jing } 109920848903SChaotian Jing } 110020848903SChaotian Jing if (cmd->error) 110120848903SChaotian Jing dev_dbg(host->dev, 110220848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 110320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 110420848903SChaotian Jing cmd->error); 110520848903SChaotian Jing 110620848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 110720848903SChaotian Jing return true; 110820848903SChaotian Jing } 110920848903SChaotian Jing 111020848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 111120848903SChaotian Jing * is correct before issue a request. but host design do below 111220848903SChaotian Jing * checks recommended. 111320848903SChaotian Jing */ 111420848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 111520848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 111620848903SChaotian Jing { 111720848903SChaotian Jing /* The max busy time we can endure is 20ms */ 111820848903SChaotian Jing unsigned long tmo = jiffies + msecs_to_jiffies(20); 111920848903SChaotian Jing 112020848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 112120848903SChaotian Jing time_before(jiffies, tmo)) 112220848903SChaotian Jing cpu_relax(); 112320848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 112420848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 112520848903SChaotian Jing host->error |= REQ_CMD_BUSY; 112620848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 112720848903SChaotian Jing return false; 112820848903SChaotian Jing } 112920848903SChaotian Jing 113020848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 113120848903SChaotian Jing tmo = jiffies + msecs_to_jiffies(20); 113220848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 113320848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 113420848903SChaotian Jing time_before(jiffies, tmo)) 113520848903SChaotian Jing cpu_relax(); 113620848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 113720848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 113820848903SChaotian Jing host->error |= REQ_CMD_BUSY; 113920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 114020848903SChaotian Jing return false; 114120848903SChaotian Jing } 114220848903SChaotian Jing } 114320848903SChaotian Jing return true; 114420848903SChaotian Jing } 114520848903SChaotian Jing 114620848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 114720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 114820848903SChaotian Jing { 114920848903SChaotian Jing u32 rawcmd; 11505215b2e9Sjjian zhou unsigned long flags; 115120848903SChaotian Jing 115220848903SChaotian Jing WARN_ON(host->cmd); 115320848903SChaotian Jing host->cmd = cmd; 115420848903SChaotian Jing 1155f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 115620848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 115720848903SChaotian Jing return; 115820848903SChaotian Jing 115920848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 116020848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 116120848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 116220848903SChaotian Jing msdc_reset_hw(host); 116320848903SChaotian Jing } 116420848903SChaotian Jing 116520848903SChaotian Jing cmd->error = 0; 116620848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 116720848903SChaotian Jing 11685215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 1169726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 11705215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 11715215b2e9Sjjian zhou 117220848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 117320848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 117420848903SChaotian Jing } 117520848903SChaotian Jing 117620848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 117720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 117820848903SChaotian Jing { 1179ddc71387SChaotian Jing if ((cmd->error && 1180ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1181ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1182ddc71387SChaotian Jing cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1183ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 118420848903SChaotian Jing msdc_request_done(host, mrq); 118520848903SChaotian Jing else if (cmd == mrq->sbc) 118620848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 118720848903SChaotian Jing else if (!cmd->data) 118820848903SChaotian Jing msdc_request_done(host, mrq); 118920848903SChaotian Jing else 119020848903SChaotian Jing msdc_start_data(host, mrq, cmd, cmd->data); 119120848903SChaotian Jing } 119220848903SChaotian Jing 119320848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 119420848903SChaotian Jing { 119520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 119620848903SChaotian Jing 119720848903SChaotian Jing host->error = 0; 119820848903SChaotian Jing WARN_ON(host->mrq); 119920848903SChaotian Jing host->mrq = mrq; 120020848903SChaotian Jing 120120848903SChaotian Jing if (mrq->data) 120220848903SChaotian Jing msdc_prepare_data(host, mrq); 120320848903SChaotian Jing 120420848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 120520848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 120620848903SChaotian Jing * use HW option, otherwise use SW option 120720848903SChaotian Jing */ 120820848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 120920848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 121020848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 121120848903SChaotian Jing else 121220848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 121320848903SChaotian Jing } 121420848903SChaotian Jing 1215d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 121620848903SChaotian Jing { 121720848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 121820848903SChaotian Jing struct mmc_data *data = mrq->data; 121920848903SChaotian Jing 122020848903SChaotian Jing if (!data) 122120848903SChaotian Jing return; 122220848903SChaotian Jing 122320848903SChaotian Jing msdc_prepare_data(host, mrq); 122420848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 122520848903SChaotian Jing } 122620848903SChaotian Jing 122720848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 122820848903SChaotian Jing int err) 122920848903SChaotian Jing { 123020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 123120848903SChaotian Jing struct mmc_data *data; 123220848903SChaotian Jing 123320848903SChaotian Jing data = mrq->data; 123420848903SChaotian Jing if (!data) 123520848903SChaotian Jing return; 123620848903SChaotian Jing if (data->host_cookie) { 123720848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 123820848903SChaotian Jing msdc_unprepare_data(host, mrq); 123920848903SChaotian Jing } 124020848903SChaotian Jing } 124120848903SChaotian Jing 124220848903SChaotian Jing static void msdc_data_xfer_next(struct msdc_host *host, 124320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 124420848903SChaotian Jing { 124520848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 12466397b7f5SChaotian Jing !mrq->sbc) 124720848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 124820848903SChaotian Jing else 124920848903SChaotian Jing msdc_request_done(host, mrq); 125020848903SChaotian Jing } 125120848903SChaotian Jing 125220848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 125320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 125420848903SChaotian Jing { 125520848903SChaotian Jing struct mmc_command *stop = data->stop; 125620848903SChaotian Jing unsigned long flags; 125720848903SChaotian Jing bool done; 125820848903SChaotian Jing unsigned int check_data = events & 125920848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 126020848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 126120848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 126220848903SChaotian Jing 126320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 126420848903SChaotian Jing done = !host->data; 126520848903SChaotian Jing if (check_data) 126620848903SChaotian Jing host->data = NULL; 126720848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 126820848903SChaotian Jing 126920848903SChaotian Jing if (done) 127020848903SChaotian Jing return true; 127120848903SChaotian Jing 127220848903SChaotian Jing if (check_data || (stop && stop->error)) { 127320848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 127420848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 127520848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 127620848903SChaotian Jing 1); 127720848903SChaotian Jing while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 127820848903SChaotian Jing cpu_relax(); 127920848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 128020848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 128120848903SChaotian Jing 128220848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 128320848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 128420848903SChaotian Jing } else { 12852066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 128620848903SChaotian Jing msdc_reset_hw(host); 128720848903SChaotian Jing host->error |= REQ_DAT_ERR; 128820848903SChaotian Jing data->bytes_xfered = 0; 128920848903SChaotian Jing 129020848903SChaotian Jing if (events & MSDC_INT_DATTMO) 129120848903SChaotian Jing data->error = -ETIMEDOUT; 12926397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 12936397b7f5SChaotian Jing data->error = -EILSEQ; 129420848903SChaotian Jing 12952066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 129620848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 12972066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 129820848903SChaotian Jing (int)data->error, data->bytes_xfered); 129920848903SChaotian Jing } 130020848903SChaotian Jing 130120848903SChaotian Jing msdc_data_xfer_next(host, mrq, data); 130220848903SChaotian Jing done = true; 130320848903SChaotian Jing } 130420848903SChaotian Jing return done; 130520848903SChaotian Jing } 130620848903SChaotian Jing 130720848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 130820848903SChaotian Jing { 130920848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 131020848903SChaotian Jing 131120848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 131220848903SChaotian Jing 131320848903SChaotian Jing switch (width) { 131420848903SChaotian Jing default: 131520848903SChaotian Jing case MMC_BUS_WIDTH_1: 131620848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 131720848903SChaotian Jing break; 131820848903SChaotian Jing case MMC_BUS_WIDTH_4: 131920848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 132020848903SChaotian Jing break; 132120848903SChaotian Jing case MMC_BUS_WIDTH_8: 132220848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 132320848903SChaotian Jing break; 132420848903SChaotian Jing } 132520848903SChaotian Jing 132620848903SChaotian Jing writel(val, host->base + SDC_CFG); 132720848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 132820848903SChaotian Jing } 132920848903SChaotian Jing 133020848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 133120848903SChaotian Jing { 133220848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 133320848903SChaotian Jing int ret = 0; 133420848903SChaotian Jing 133520848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1336fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1337fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 133820848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 133920848903SChaotian Jing return -EINVAL; 134020848903SChaotian Jing } 134120848903SChaotian Jing 1342fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 134320848903SChaotian Jing if (ret) { 1344fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1345fac49ce5SNicolas Boichat ret, ios->signal_voltage); 134620848903SChaotian Jing } else { 134720848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 134820848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 134920848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 135020848903SChaotian Jing else 135120848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 135220848903SChaotian Jing } 135320848903SChaotian Jing } 135420848903SChaotian Jing return ret; 135520848903SChaotian Jing } 135620848903SChaotian Jing 135720848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 135820848903SChaotian Jing { 135920848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 136020848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 136120848903SChaotian Jing 13623bc702edSyong mao /* only check if data0 is low */ 13633bc702edSyong mao return !(status & BIT(16)); 136420848903SChaotian Jing } 136520848903SChaotian Jing 136620848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 136720848903SChaotian Jing { 136820848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 136920848903SChaotian Jing req_timeout.work); 137020848903SChaotian Jing 137120848903SChaotian Jing /* simulate HW timeout status */ 137220848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 137320848903SChaotian Jing if (host->mrq) { 137420848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 137520848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 137620848903SChaotian Jing if (host->cmd) { 137720848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 137820848903SChaotian Jing __func__, host->cmd->opcode); 137920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 138020848903SChaotian Jing host->cmd); 138120848903SChaotian Jing } else if (host->data) { 138220848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 138320848903SChaotian Jing __func__, host->mrq->cmd->opcode, 138420848903SChaotian Jing host->data->blocks); 138520848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 138620848903SChaotian Jing host->data); 138720848903SChaotian Jing } 138820848903SChaotian Jing } 138920848903SChaotian Jing } 139020848903SChaotian Jing 13918a5df8acSjjian zhou static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 13928a5df8acSjjian zhou { 13938a5df8acSjjian zhou if (enb) { 13948a5df8acSjjian zhou sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 13958a5df8acSjjian zhou sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 13968a5df8acSjjian zhou } else { 13978a5df8acSjjian zhou sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 13988a5df8acSjjian zhou sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 13998a5df8acSjjian zhou } 14008a5df8acSjjian zhou } 14018a5df8acSjjian zhou 14028a5df8acSjjian zhou static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 14035215b2e9Sjjian zhou { 14045215b2e9Sjjian zhou unsigned long flags; 14055215b2e9Sjjian zhou struct msdc_host *host = mmc_priv(mmc); 14065215b2e9Sjjian zhou 14075215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 14088a5df8acSjjian zhou __msdc_enable_sdio_irq(host, enb); 14095215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 14105215b2e9Sjjian zhou 14115215b2e9Sjjian zhou if (enb) 14125215b2e9Sjjian zhou pm_runtime_get_noresume(host->dev); 14135215b2e9Sjjian zhou else 14145215b2e9Sjjian zhou pm_runtime_put_noidle(host->dev); 14155215b2e9Sjjian zhou } 14165215b2e9Sjjian zhou 141720848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 141820848903SChaotian Jing { 141920848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 142020848903SChaotian Jing 142120848903SChaotian Jing while (true) { 142220848903SChaotian Jing unsigned long flags; 142320848903SChaotian Jing struct mmc_request *mrq; 142420848903SChaotian Jing struct mmc_command *cmd; 142520848903SChaotian Jing struct mmc_data *data; 142620848903SChaotian Jing u32 events, event_mask; 142720848903SChaotian Jing 142820848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 142920848903SChaotian Jing events = readl(host->base + MSDC_INT); 143020848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 14318a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 14328a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 0); 143320848903SChaotian Jing /* clear interrupts */ 143420848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 143520848903SChaotian Jing 143620848903SChaotian Jing mrq = host->mrq; 143720848903SChaotian Jing cmd = host->cmd; 143820848903SChaotian Jing data = host->data; 143920848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 144020848903SChaotian Jing 14418a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 14425215b2e9Sjjian zhou sdio_signal_irq(host->mmc); 14435215b2e9Sjjian zhou 1444d087bde5SNeilBrown if ((events & event_mask) & MSDC_INT_CDSC) { 1445d087bde5SNeilBrown if (host->internal_cd) 1446d087bde5SNeilBrown mmc_detect_change(host->mmc, msecs_to_jiffies(20)); 1447d087bde5SNeilBrown events &= ~MSDC_INT_CDSC; 1448d087bde5SNeilBrown } 1449d087bde5SNeilBrown 14505215b2e9Sjjian zhou if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 145120848903SChaotian Jing break; 145220848903SChaotian Jing 145320848903SChaotian Jing if (!mrq) { 145420848903SChaotian Jing dev_err(host->dev, 145520848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 145620848903SChaotian Jing __func__, events, event_mask); 145720848903SChaotian Jing WARN_ON(1); 145820848903SChaotian Jing break; 145920848903SChaotian Jing } 146020848903SChaotian Jing 146120848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 146220848903SChaotian Jing 146320848903SChaotian Jing if (cmd) 146420848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 146520848903SChaotian Jing else if (data) 146620848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 146720848903SChaotian Jing } 146820848903SChaotian Jing 146920848903SChaotian Jing return IRQ_HANDLED; 147020848903SChaotian Jing } 147120848903SChaotian Jing 147220848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 147320848903SChaotian Jing { 147420848903SChaotian Jing u32 val; 147539add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 147620848903SChaotian Jing 147720848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 147820848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 147920848903SChaotian Jing 148020848903SChaotian Jing /* Reset */ 148120848903SChaotian Jing msdc_reset_hw(host); 148220848903SChaotian Jing 148320848903SChaotian Jing /* Disable and clear all interrupts */ 148420848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 148520848903SChaotian Jing val = readl(host->base + MSDC_INT); 148620848903SChaotian Jing writel(val, host->base + MSDC_INT); 148720848903SChaotian Jing 1488d087bde5SNeilBrown /* Configure card detection */ 1489d087bde5SNeilBrown if (host->internal_cd) { 1490d087bde5SNeilBrown sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1491d087bde5SNeilBrown DEFAULT_DEBOUNCE); 1492d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1493d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1494d087bde5SNeilBrown sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1495d087bde5SNeilBrown } else { 1496d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1497d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1498d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1499d087bde5SNeilBrown } 1500d087bde5SNeilBrown 1501a2e6d1f6SChaotian Jing if (host->top_base) { 1502a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CONTROL); 1503a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CMD); 1504a2e6d1f6SChaotian Jing } else { 150539add252SChaotian Jing writel(0, host->base + tune_reg); 1506a2e6d1f6SChaotian Jing } 150720848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 15086397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 15096397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 151020848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 15112fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 15126397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1513d9dcbfc8SChaotian Jing 1514d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1515d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1516d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1517d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1518d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1519d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1520d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1521d9dcbfc8SChaotian Jing } 1522d9dcbfc8SChaotian Jing 1523acde28c4SChaotian Jing if (host->dev_comp->busy_check) 1524acde28c4SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1525d9dcbfc8SChaotian Jing 15262fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 15272fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 15282fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1529d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1530a2e6d1f6SChaotian Jing if (host->top_base) 1531a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1532a2e6d1f6SChaotian Jing SDC_RX_ENH_EN); 1533a2e6d1f6SChaotian Jing else 1534d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1535d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1536d9dcbfc8SChaotian Jing } else { 15372fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 15382fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 15392fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 15402fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1541d9dcbfc8SChaotian Jing } 15422fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 15432fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 15442fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 15452fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 15462fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 15472fea5819SChaotian Jing } 15482fea5819SChaotian Jing 15492a9bde19SChaotian Jing if (host->dev_comp->support_64g) 15502a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 15512a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 15522fea5819SChaotian Jing if (host->dev_comp->data_tune) { 1553a2e6d1f6SChaotian Jing if (host->top_base) { 1554a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1555a2e6d1f6SChaotian Jing PAD_DAT_RD_RXDLY_SEL); 1556a2e6d1f6SChaotian Jing sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1557a2e6d1f6SChaotian Jing DATA_K_VALUE_SEL); 1558a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1559a2e6d1f6SChaotian Jing PAD_CMD_RD_RXDLY_SEL); 1560a2e6d1f6SChaotian Jing } else { 15612fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 1562a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RD_SEL | 1563a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_CMD_SEL); 1564a2e6d1f6SChaotian Jing } 15652fea5819SChaotian Jing } else { 15662fea5819SChaotian Jing /* choose clock tune */ 1567a2e6d1f6SChaotian Jing if (host->top_base) 1568a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1569a2e6d1f6SChaotian Jing PAD_RXDLY_SEL); 1570a2e6d1f6SChaotian Jing else 1571a2e6d1f6SChaotian Jing sdr_set_bits(host->base + tune_reg, 1572a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RXDLYSEL); 15732fea5819SChaotian Jing } 15746397b7f5SChaotian Jing 157520848903SChaotian Jing /* Configure to enable SDIO mode. 157620848903SChaotian Jing * it's must otherwise sdio cmd5 failed 157720848903SChaotian Jing */ 157820848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 157920848903SChaotian Jing 15805215b2e9Sjjian zhou /* Config SDIO device detect interrupt function */ 158120848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 158226c71a13Syong mao sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 158320848903SChaotian Jing 158420848903SChaotian Jing /* Configure to default data timeout */ 158520848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 158620848903SChaotian Jing 158786beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 15882fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1589a2e6d1f6SChaotian Jing if (host->top_base) { 1590a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_control = 1591a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1592a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_cmd = 1593a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1594a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = 1595a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1596a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = 1597a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1598a2e6d1f6SChaotian Jing } else { 1599a2e6d1f6SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 16002fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1601a2e6d1f6SChaotian Jing } 160220848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 160320848903SChaotian Jing } 160420848903SChaotian Jing 160520848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 160620848903SChaotian Jing { 160720848903SChaotian Jing u32 val; 1608d087bde5SNeilBrown 1609d087bde5SNeilBrown if (host->internal_cd) { 1610d087bde5SNeilBrown /* Disabled card-detect */ 1611d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1612d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1613d087bde5SNeilBrown } 1614d087bde5SNeilBrown 161520848903SChaotian Jing /* Disable and clear all interrupts */ 161620848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 161720848903SChaotian Jing 161820848903SChaotian Jing val = readl(host->base + MSDC_INT); 161920848903SChaotian Jing writel(val, host->base + MSDC_INT); 162020848903SChaotian Jing } 162120848903SChaotian Jing 162220848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 162320848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 162420848903SChaotian Jing { 162520848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 162620848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 16272a9bde19SChaotian Jing dma_addr_t dma_addr; 162820848903SChaotian Jing int i; 162920848903SChaotian Jing 163062b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 163120848903SChaotian Jing 16322a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 163320848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 163462b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 163562b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 163662b0d27aSChaotian Jing */ 16372a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 16382a9bde19SChaotian Jing if (host->dev_comp->support_64g) 16392a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 16402a9bde19SChaotian Jing 16412a9bde19SChaotian Jing dma_addr = dma->bd_addr; 16422a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 16432a9bde19SChaotian Jing if (host->dev_comp->support_64g) 16442a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 16452a9bde19SChaotian Jing 164620848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 16472a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 16482a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 16492a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 16502a9bde19SChaotian Jing if (host->dev_comp->support_64g) 16512a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 16522a9bde19SChaotian Jing } 165320848903SChaotian Jing } 165420848903SChaotian Jing 165520848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 165620848903SChaotian Jing { 165720848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 165820848903SChaotian Jing int ret; 165920848903SChaotian Jing 166020848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 166120848903SChaotian Jing 166220848903SChaotian Jing /* Suspend/Resume will do power off/on */ 166320848903SChaotian Jing switch (ios->power_mode) { 166420848903SChaotian Jing case MMC_POWER_UP: 166520848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 16666397b7f5SChaotian Jing msdc_init_hw(host); 166720848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 166820848903SChaotian Jing ios->vdd); 166920848903SChaotian Jing if (ret) { 167020848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1671567979fbSUlf Hansson return; 167220848903SChaotian Jing } 167320848903SChaotian Jing } 167420848903SChaotian Jing break; 167520848903SChaotian Jing case MMC_POWER_ON: 167620848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 167720848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 167820848903SChaotian Jing if (ret) 167920848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 168020848903SChaotian Jing else 168120848903SChaotian Jing host->vqmmc_enabled = true; 168220848903SChaotian Jing } 168320848903SChaotian Jing break; 168420848903SChaotian Jing case MMC_POWER_OFF: 168520848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 168620848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 168720848903SChaotian Jing 168820848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 168920848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 169020848903SChaotian Jing host->vqmmc_enabled = false; 169120848903SChaotian Jing } 169220848903SChaotian Jing break; 169320848903SChaotian Jing default: 169420848903SChaotian Jing break; 169520848903SChaotian Jing } 169620848903SChaotian Jing 16976e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 16986e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 169920848903SChaotian Jing } 170020848903SChaotian Jing 17016397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 17026397b7f5SChaotian Jing { 17036397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 17046397b7f5SChaotian Jing return delay & (1 << bit); 17056397b7f5SChaotian Jing } 17066397b7f5SChaotian Jing 17076397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 17086397b7f5SChaotian Jing { 17096397b7f5SChaotian Jing int i; 17106397b7f5SChaotian Jing 17116397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 17126397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 17136397b7f5SChaotian Jing return i; 17146397b7f5SChaotian Jing } 17156397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 17166397b7f5SChaotian Jing } 17176397b7f5SChaotian Jing 17186397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 17196397b7f5SChaotian Jing { 17206397b7f5SChaotian Jing int start = 0, len = 0; 17216397b7f5SChaotian Jing int start_final = 0, len_final = 0; 17226397b7f5SChaotian Jing u8 final_phase = 0xff; 172362d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 17246397b7f5SChaotian Jing 17256397b7f5SChaotian Jing if (delay == 0) { 17266397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 17276397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 17286397b7f5SChaotian Jing return delay_phase; 17296397b7f5SChaotian Jing } 17306397b7f5SChaotian Jing 17316397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 17326397b7f5SChaotian Jing len = get_delay_len(delay, start); 17336397b7f5SChaotian Jing if (len_final < len) { 17346397b7f5SChaotian Jing start_final = start; 17356397b7f5SChaotian Jing len_final = len; 17366397b7f5SChaotian Jing } 17376397b7f5SChaotian Jing start += len ? len : 1; 17381ede5cb8Syong mao if (len >= 12 && start_final < 4) 17396397b7f5SChaotian Jing break; 17406397b7f5SChaotian Jing } 17416397b7f5SChaotian Jing 17426397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 17436397b7f5SChaotian Jing if (start_final == 0) 17446397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 17456397b7f5SChaotian Jing else 17466397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 17476397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 17486397b7f5SChaotian Jing delay, len_final, final_phase); 17496397b7f5SChaotian Jing 17506397b7f5SChaotian Jing delay_phase.maxlen = len_final; 17516397b7f5SChaotian Jing delay_phase.start = start_final; 17526397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 17536397b7f5SChaotian Jing return delay_phase; 17546397b7f5SChaotian Jing } 17556397b7f5SChaotian Jing 1756fd82cc30SChaotian Jing static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1757fd82cc30SChaotian Jing { 1758fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1759fd82cc30SChaotian Jing 1760fd82cc30SChaotian Jing if (host->top_base) 1761fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1762fd82cc30SChaotian Jing value); 1763fd82cc30SChaotian Jing else 1764fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1765fd82cc30SChaotian Jing value); 1766fd82cc30SChaotian Jing } 1767fd82cc30SChaotian Jing 1768fd82cc30SChaotian Jing static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1769fd82cc30SChaotian Jing { 1770fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1771fd82cc30SChaotian Jing 1772fd82cc30SChaotian Jing if (host->top_base) 1773fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1774fd82cc30SChaotian Jing PAD_DAT_RD_RXDLY, value); 1775fd82cc30SChaotian Jing else 1776fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1777fd82cc30SChaotian Jing value); 1778fd82cc30SChaotian Jing } 1779fd82cc30SChaotian Jing 17806397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 17816397b7f5SChaotian Jing { 17826397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 17836397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1784ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 17851ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 17866397b7f5SChaotian Jing u8 final_delay, final_maxlen; 17871ede5cb8Syong mao u32 internal_delay = 0; 178839add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 17896397b7f5SChaotian Jing int cmd_err; 17901ede5cb8Syong mao int i, j; 17911ede5cb8Syong mao 17921ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 17931ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 179439add252SChaotian Jing sdr_set_field(host->base + tune_reg, 17951ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 17961ede5cb8Syong mao host->hs200_cmd_int_delay); 17976397b7f5SChaotian Jing 17986397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 17996397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1800fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 18011ede5cb8Syong mao /* 18021ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 18031ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 18041ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 18051ede5cb8Syong mao */ 18061ede5cb8Syong mao for (j = 0; j < 3; j++) { 18076397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 18081ede5cb8Syong mao if (!cmd_err) { 18096397b7f5SChaotian Jing rise_delay |= (1 << i); 18101ede5cb8Syong mao } else { 18111ede5cb8Syong mao rise_delay &= ~(1 << i); 18121ede5cb8Syong mao break; 18131ede5cb8Syong mao } 18141ede5cb8Syong mao } 18156397b7f5SChaotian Jing } 1816ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1817ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 18186b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 18196b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1820ae9c657eSChaotian Jing goto skip_fall; 18216397b7f5SChaotian Jing 18226397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 18236397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 1824fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 18251ede5cb8Syong mao /* 18261ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 18271ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 18281ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 18291ede5cb8Syong mao */ 18301ede5cb8Syong mao for (j = 0; j < 3; j++) { 18316397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 18321ede5cb8Syong mao if (!cmd_err) { 18336397b7f5SChaotian Jing fall_delay |= (1 << i); 18341ede5cb8Syong mao } else { 18351ede5cb8Syong mao fall_delay &= ~(1 << i); 18361ede5cb8Syong mao break; 18371ede5cb8Syong mao } 18381ede5cb8Syong mao } 18396397b7f5SChaotian Jing } 18406397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 18416397b7f5SChaotian Jing 1842ae9c657eSChaotian Jing skip_fall: 18436397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 18441ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 18451ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 18466397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 18476397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 18486397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 18496397b7f5SChaotian Jing } else { 18506397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 18516397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 18526397b7f5SChaotian Jing } 1853fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 1854fd82cc30SChaotian Jing 18552fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 18561ede5cb8Syong mao goto skip_internal; 18576397b7f5SChaotian Jing 18581ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 185939add252SChaotian Jing sdr_set_field(host->base + tune_reg, 18601ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 18611ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 18621ede5cb8Syong mao if (!cmd_err) 18631ede5cb8Syong mao internal_delay |= (1 << i); 18641ede5cb8Syong mao } 18651ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 18661ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 186739add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 18681ede5cb8Syong mao internal_delay_phase.final_phase); 18691ede5cb8Syong mao skip_internal: 18701ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 18711ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 18721ede5cb8Syong mao } 18731ede5cb8Syong mao 18741ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 18751ede5cb8Syong mao { 18761ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 18771ede5cb8Syong mao u32 cmd_delay = 0; 18781ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 18791ede5cb8Syong mao u8 final_delay; 18801ede5cb8Syong mao int cmd_err; 18811ede5cb8Syong mao int i, j; 18821ede5cb8Syong mao 18831ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 18841ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 18858f34e5bdSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 18861ede5cb8Syong mao 18871ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 18881ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 18891ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 18901ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 18911ede5cb8Syong mao host->hs200_cmd_int_delay); 18921ede5cb8Syong mao 18931ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 18941ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 18951ede5cb8Syong mao else 18961ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 18971ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 18981ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 18991ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 19001ede5cb8Syong mao /* 19011ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19021ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19031ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19041ede5cb8Syong mao */ 19051ede5cb8Syong mao for (j = 0; j < 3; j++) { 19061ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 19071ede5cb8Syong mao if (!cmd_err) { 19081ede5cb8Syong mao cmd_delay |= (1 << i); 19091ede5cb8Syong mao } else { 19101ede5cb8Syong mao cmd_delay &= ~(1 << i); 19111ede5cb8Syong mao break; 19121ede5cb8Syong mao } 19131ede5cb8Syong mao } 19141ede5cb8Syong mao } 19151ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 19161ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 19171ede5cb8Syong mao final_cmd_delay.final_phase); 19181ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 19191ede5cb8Syong mao 19201ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 19216397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 19226397b7f5SChaotian Jing } 19236397b7f5SChaotian Jing 19246397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 19256397b7f5SChaotian Jing { 19266397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 19276397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1928ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 19296397b7f5SChaotian Jing u8 final_delay, final_maxlen; 19306397b7f5SChaotian Jing int i, ret; 19316397b7f5SChaotian Jing 1932d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1933d17bb71cSChaotian Jing host->latch_ck); 19346397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 19356397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 19366397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1937fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 19386397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 19396397b7f5SChaotian Jing if (!ret) 19406397b7f5SChaotian Jing rise_delay |= (1 << i); 19416397b7f5SChaotian Jing } 1942ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1943ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 19441ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 1945ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1946ae9c657eSChaotian Jing goto skip_fall; 19476397b7f5SChaotian Jing 19486397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 19496397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 19506397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 1951fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 19526397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 19536397b7f5SChaotian Jing if (!ret) 19546397b7f5SChaotian Jing fall_delay |= (1 << i); 19556397b7f5SChaotian Jing } 19566397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 19576397b7f5SChaotian Jing 1958ae9c657eSChaotian Jing skip_fall: 19596397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 19606397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 19616397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 19626397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 19636397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 19646397b7f5SChaotian Jing } else { 19656397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 19666397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 19676397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 19686397b7f5SChaotian Jing } 1969fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 19706397b7f5SChaotian Jing 19711ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 19726397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 19736397b7f5SChaotian Jing } 19746397b7f5SChaotian Jing 197586601d0eSChaotian Jing /* 197686601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 197786601d0eSChaotian Jing * together, which can save the tuning time. 197886601d0eSChaotian Jing */ 197986601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 198086601d0eSChaotian Jing { 198186601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 198286601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 198386601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 198486601d0eSChaotian Jing u8 final_delay, final_maxlen; 198586601d0eSChaotian Jing int i, ret; 198686601d0eSChaotian Jing 198786601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 198886601d0eSChaotian Jing host->latch_ck); 198986601d0eSChaotian Jing 199086601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 199186601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 199286601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 199386601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1994fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 1995fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 199686601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 199786601d0eSChaotian Jing if (!ret) 199886601d0eSChaotian Jing rise_delay |= (1 << i); 199986601d0eSChaotian Jing } 200086601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 200186601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 200286601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 200386601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 200486601d0eSChaotian Jing goto skip_fall; 200586601d0eSChaotian Jing 200686601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 200786601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 200886601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 200986601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2010fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2011fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 201286601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 201386601d0eSChaotian Jing if (!ret) 201486601d0eSChaotian Jing fall_delay |= (1 << i); 201586601d0eSChaotian Jing } 201686601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 201786601d0eSChaotian Jing 201886601d0eSChaotian Jing skip_fall: 201986601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 202086601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 202186601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 202286601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 202386601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 202486601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 202586601d0eSChaotian Jing } else { 202686601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 202786601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 202886601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 202986601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 203086601d0eSChaotian Jing } 203186601d0eSChaotian Jing 2032fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2033fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 2034a2e6d1f6SChaotian Jing 203586601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 203686601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 203786601d0eSChaotian Jing } 203886601d0eSChaotian Jing 20396397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 20406397b7f5SChaotian Jing { 20416397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 20426397b7f5SChaotian Jing int ret; 204339add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 20446397b7f5SChaotian Jing 204586601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 204686601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 204786601d0eSChaotian Jing if (host->hs400_mode) { 204886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 204986601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2050fd82cc30SChaotian Jing msdc_set_data_delay(host, 0); 205186601d0eSChaotian Jing } 205286601d0eSChaotian Jing goto tune_done; 205386601d0eSChaotian Jing } 20547f3d5852SChaotian Jing if (host->hs400_mode && 20557f3d5852SChaotian Jing host->dev_comp->hs400_tune) 20561ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 20571ede5cb8Syong mao else 20586397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 20596397b7f5SChaotian Jing if (ret == -EIO) { 20606397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 2061567979fbSUlf Hansson return ret; 20626397b7f5SChaotian Jing } 20635462ff39SChaotian Jing if (host->hs400_mode == false) { 20646397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 20656397b7f5SChaotian Jing if (ret == -EIO) 20666397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 20675462ff39SChaotian Jing } 20686397b7f5SChaotian Jing 206986601d0eSChaotian Jing tune_done: 207086beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 207139add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 20721ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2073a2e6d1f6SChaotian Jing if (host->top_base) { 2074a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = readl(host->top_base + 2075a2e6d1f6SChaotian Jing EMMC_TOP_CONTROL); 2076a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2077a2e6d1f6SChaotian Jing EMMC_TOP_CMD); 2078a2e6d1f6SChaotian Jing } 20796397b7f5SChaotian Jing return ret; 20806397b7f5SChaotian Jing } 20816397b7f5SChaotian Jing 20826397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 20836397b7f5SChaotian Jing { 20846397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 20855462ff39SChaotian Jing host->hs400_mode = true; 20866397b7f5SChaotian Jing 2087a2e6d1f6SChaotian Jing if (host->top_base) 2088a2e6d1f6SChaotian Jing writel(host->hs400_ds_delay, 2089a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2090a2e6d1f6SChaotian Jing else 20916397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 20922fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 20932fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2094c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 2095c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2096c8609b22SChaotian Jing 20976397b7f5SChaotian Jing return 0; 20986397b7f5SChaotian Jing } 20996397b7f5SChaotian Jing 2100c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 2101c9b5061eSChaotian Jing { 2102c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2103c9b5061eSChaotian Jing 2104c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 2105c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 2106c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 2107c9b5061eSChaotian Jing } 2108c9b5061eSChaotian Jing 21095215b2e9Sjjian zhou static void msdc_ack_sdio_irq(struct mmc_host *mmc) 21105215b2e9Sjjian zhou { 21118a5df8acSjjian zhou unsigned long flags; 21128a5df8acSjjian zhou struct msdc_host *host = mmc_priv(mmc); 21138a5df8acSjjian zhou 21148a5df8acSjjian zhou spin_lock_irqsave(&host->lock, flags); 21158a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 1); 21168a5df8acSjjian zhou spin_unlock_irqrestore(&host->lock, flags); 21175215b2e9Sjjian zhou } 21185215b2e9Sjjian zhou 2119d087bde5SNeilBrown static int msdc_get_cd(struct mmc_host *mmc) 2120d087bde5SNeilBrown { 2121d087bde5SNeilBrown struct msdc_host *host = mmc_priv(mmc); 2122d087bde5SNeilBrown int val; 2123d087bde5SNeilBrown 2124d087bde5SNeilBrown if (mmc->caps & MMC_CAP_NONREMOVABLE) 2125d087bde5SNeilBrown return 1; 2126d087bde5SNeilBrown 2127d087bde5SNeilBrown if (!host->internal_cd) 2128d087bde5SNeilBrown return mmc_gpio_get_cd(mmc); 2129d087bde5SNeilBrown 2130d087bde5SNeilBrown val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2131d087bde5SNeilBrown if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2132d087bde5SNeilBrown return !!val; 2133d087bde5SNeilBrown else 2134d087bde5SNeilBrown return !val; 2135d087bde5SNeilBrown } 2136d087bde5SNeilBrown 2137be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 213820848903SChaotian Jing .post_req = msdc_post_req, 213920848903SChaotian Jing .pre_req = msdc_pre_req, 214020848903SChaotian Jing .request = msdc_ops_request, 214120848903SChaotian Jing .set_ios = msdc_ops_set_ios, 21428d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 2143d087bde5SNeilBrown .get_cd = msdc_get_cd, 21445215b2e9Sjjian zhou .enable_sdio_irq = msdc_enable_sdio_irq, 21455215b2e9Sjjian zhou .ack_sdio_irq = msdc_ack_sdio_irq, 214620848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 214720848903SChaotian Jing .card_busy = msdc_card_busy, 21486397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 21496397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2150c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 215120848903SChaotian Jing }; 215220848903SChaotian Jing 21531ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 21541ede5cb8Syong mao struct msdc_host *host) 21551ede5cb8Syong mao { 2156d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2157d17bb71cSChaotian Jing &host->latch_ck); 2158d17bb71cSChaotian Jing 21591ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 21601ede5cb8Syong mao &host->hs400_ds_delay); 21611ede5cb8Syong mao 21621ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 21631ede5cb8Syong mao &host->hs200_cmd_int_delay); 21641ede5cb8Syong mao 21651ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 21661ede5cb8Syong mao &host->hs400_cmd_int_delay); 21671ede5cb8Syong mao 21681ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 21691ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 21701ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 21711ede5cb8Syong mao else 21721ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 21731ede5cb8Syong mao } 21741ede5cb8Syong mao 217520848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 217620848903SChaotian Jing { 217720848903SChaotian Jing struct mmc_host *mmc; 217820848903SChaotian Jing struct msdc_host *host; 217920848903SChaotian Jing struct resource *res; 218020848903SChaotian Jing int ret; 218120848903SChaotian Jing 218220848903SChaotian Jing if (!pdev->dev.of_node) { 218320848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 218420848903SChaotian Jing return -EINVAL; 218520848903SChaotian Jing } 2186762d491aSChaotian Jing 218720848903SChaotian Jing /* Allocate MMC host for this device */ 218820848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 218920848903SChaotian Jing if (!mmc) 219020848903SChaotian Jing return -ENOMEM; 219120848903SChaotian Jing 219220848903SChaotian Jing host = mmc_priv(mmc); 219320848903SChaotian Jing ret = mmc_of_parse(mmc); 219420848903SChaotian Jing if (ret) 219520848903SChaotian Jing goto host_free; 219620848903SChaotian Jing 219720848903SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 219820848903SChaotian Jing host->base = devm_ioremap_resource(&pdev->dev, res); 219920848903SChaotian Jing if (IS_ERR(host->base)) { 220020848903SChaotian Jing ret = PTR_ERR(host->base); 220120848903SChaotian Jing goto host_free; 220220848903SChaotian Jing } 220320848903SChaotian Jing 2204a2e6d1f6SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2205b65be635SFabien Parent if (res) { 2206a2e6d1f6SChaotian Jing host->top_base = devm_ioremap_resource(&pdev->dev, res); 2207a2e6d1f6SChaotian Jing if (IS_ERR(host->top_base)) 2208a2e6d1f6SChaotian Jing host->top_base = NULL; 2209b65be635SFabien Parent } 2210a2e6d1f6SChaotian Jing 221120848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 22122f98ef63SWolfram Sang if (ret) 221320848903SChaotian Jing goto host_free; 221420848903SChaotian Jing 221520848903SChaotian Jing host->src_clk = devm_clk_get(&pdev->dev, "source"); 221620848903SChaotian Jing if (IS_ERR(host->src_clk)) { 221720848903SChaotian Jing ret = PTR_ERR(host->src_clk); 221820848903SChaotian Jing goto host_free; 221920848903SChaotian Jing } 222020848903SChaotian Jing 222120848903SChaotian Jing host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 222220848903SChaotian Jing if (IS_ERR(host->h_clk)) { 222320848903SChaotian Jing ret = PTR_ERR(host->h_clk); 222420848903SChaotian Jing goto host_free; 222520848903SChaotian Jing } 222620848903SChaotian Jing 2227258bac4aSChaotian Jing host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2228258bac4aSChaotian Jing if (IS_ERR(host->bus_clk)) 2229258bac4aSChaotian Jing host->bus_clk = NULL; 22303c1a8844SChaotian Jing /*source clock control gate is optional clock*/ 22313c1a8844SChaotian Jing host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 22323c1a8844SChaotian Jing if (IS_ERR(host->src_clk_cg)) 22333c1a8844SChaotian Jing host->src_clk_cg = NULL; 22343c1a8844SChaotian Jing 223520848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 223620848903SChaotian Jing if (host->irq < 0) { 223720848903SChaotian Jing ret = -EINVAL; 223820848903SChaotian Jing goto host_free; 223920848903SChaotian Jing } 224020848903SChaotian Jing 224120848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 224220848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 224320848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 224420848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 224520848903SChaotian Jing goto host_free; 224620848903SChaotian Jing } 224720848903SChaotian Jing 224820848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 224920848903SChaotian Jing if (IS_ERR(host->pins_default)) { 225020848903SChaotian Jing ret = PTR_ERR(host->pins_default); 225120848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 225220848903SChaotian Jing goto host_free; 225320848903SChaotian Jing } 225420848903SChaotian Jing 225520848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 225620848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 225720848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 225820848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 225920848903SChaotian Jing goto host_free; 226020848903SChaotian Jing } 226120848903SChaotian Jing 22621ede5cb8Syong mao msdc_of_property_parse(pdev, host); 22636397b7f5SChaotian Jing 226420848903SChaotian Jing host->dev = &pdev->dev; 2265909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 226620848903SChaotian Jing host->mmc = mmc; 226720848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 226820848903SChaotian Jing /* Set host parameters to mmc */ 226920848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2270762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 227140ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2272762d491aSChaotian Jing else 2273762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 227420848903SChaotian Jing 2275d087bde5SNeilBrown if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2276d087bde5SNeilBrown !mmc_can_gpio_cd(mmc) && 2277d087bde5SNeilBrown host->dev_comp->use_internal_cd) { 2278d087bde5SNeilBrown /* 2279d087bde5SNeilBrown * Is removable but no GPIO declared, so 2280d087bde5SNeilBrown * use internal functionality. 2281d087bde5SNeilBrown */ 2282d087bde5SNeilBrown host->internal_cd = true; 2283d087bde5SNeilBrown } 2284d087bde5SNeilBrown 22855215b2e9Sjjian zhou if (mmc->caps & MMC_CAP_SDIO_IRQ) 22865215b2e9Sjjian zhou mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 22875215b2e9Sjjian zhou 228820848903SChaotian Jing mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 228920848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 229020848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 22916ef042bdSChaotian Jing if (host->dev_comp->support_64g) 22926ef042bdSChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 22936ef042bdSChaotian Jing else 229420848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 229520848903SChaotian Jing mmc->max_blk_size = 2048; 229620848903SChaotian Jing mmc->max_req_size = 512 * 1024; 229720848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 22982a9bde19SChaotian Jing if (host->dev_comp->support_64g) 22992a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 23002a9bde19SChaotian Jing else 230120848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 230220848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 230320848903SChaotian Jing 230420848903SChaotian Jing host->timeout_clks = 3 * 1048576; 230520848903SChaotian Jing host->dma.gpd = dma_alloc_coherent(&pdev->dev, 230662b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 230720848903SChaotian Jing &host->dma.gpd_addr, GFP_KERNEL); 230820848903SChaotian Jing host->dma.bd = dma_alloc_coherent(&pdev->dev, 230920848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 231020848903SChaotian Jing &host->dma.bd_addr, GFP_KERNEL); 231120848903SChaotian Jing if (!host->dma.gpd || !host->dma.bd) { 231220848903SChaotian Jing ret = -ENOMEM; 231320848903SChaotian Jing goto release_mem; 231420848903SChaotian Jing } 231520848903SChaotian Jing msdc_init_gpd_bd(host, &host->dma); 231620848903SChaotian Jing INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 231720848903SChaotian Jing spin_lock_init(&host->lock); 231820848903SChaotian Jing 231920848903SChaotian Jing platform_set_drvdata(pdev, mmc); 232020848903SChaotian Jing msdc_ungate_clock(host); 232120848903SChaotian Jing msdc_init_hw(host); 232220848903SChaotian Jing 232320848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 232442edb0d5SNeilBrown IRQF_TRIGGER_NONE, pdev->name, host); 232520848903SChaotian Jing if (ret) 232620848903SChaotian Jing goto release; 232720848903SChaotian Jing 23284b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 23294b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 23304b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 23314b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 233220848903SChaotian Jing ret = mmc_add_host(mmc); 23334b8a43e9SChaotian Jing 233420848903SChaotian Jing if (ret) 23354b8a43e9SChaotian Jing goto end; 233620848903SChaotian Jing 233720848903SChaotian Jing return 0; 23384b8a43e9SChaotian Jing end: 23394b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 234020848903SChaotian Jing release: 234120848903SChaotian Jing platform_set_drvdata(pdev, NULL); 234220848903SChaotian Jing msdc_deinit_hw(host); 234320848903SChaotian Jing msdc_gate_clock(host); 234420848903SChaotian Jing release_mem: 234520848903SChaotian Jing if (host->dma.gpd) 234620848903SChaotian Jing dma_free_coherent(&pdev->dev, 234762b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 234820848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 234920848903SChaotian Jing if (host->dma.bd) 235020848903SChaotian Jing dma_free_coherent(&pdev->dev, 235120848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 235220848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 235320848903SChaotian Jing host_free: 235420848903SChaotian Jing mmc_free_host(mmc); 235520848903SChaotian Jing 235620848903SChaotian Jing return ret; 235720848903SChaotian Jing } 235820848903SChaotian Jing 235920848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 236020848903SChaotian Jing { 236120848903SChaotian Jing struct mmc_host *mmc; 236220848903SChaotian Jing struct msdc_host *host; 236320848903SChaotian Jing 236420848903SChaotian Jing mmc = platform_get_drvdata(pdev); 236520848903SChaotian Jing host = mmc_priv(mmc); 236620848903SChaotian Jing 23674b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 23684b8a43e9SChaotian Jing 236920848903SChaotian Jing platform_set_drvdata(pdev, NULL); 237020848903SChaotian Jing mmc_remove_host(host->mmc); 237120848903SChaotian Jing msdc_deinit_hw(host); 237220848903SChaotian Jing msdc_gate_clock(host); 237320848903SChaotian Jing 23744b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 23754b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 237620848903SChaotian Jing dma_free_coherent(&pdev->dev, 237716f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 237820848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 237920848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 238020848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 238120848903SChaotian Jing 238220848903SChaotian Jing mmc_free_host(host->mmc); 238320848903SChaotian Jing 238420848903SChaotian Jing return 0; 238520848903SChaotian Jing } 238620848903SChaotian Jing 23874b8a43e9SChaotian Jing #ifdef CONFIG_PM 23884b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 23894b8a43e9SChaotian Jing { 239039add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 239139add252SChaotian Jing 23924b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 23934b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 23944b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 23954b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 23964b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 23972fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 23986397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 23991ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 24006397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2401c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2402d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2403a2e6d1f6SChaotian Jing if (host->top_base) { 2404a2e6d1f6SChaotian Jing host->save_para.emmc_top_control = 2405a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 2406a2e6d1f6SChaotian Jing host->save_para.emmc_top_cmd = 2407a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 2408a2e6d1f6SChaotian Jing host->save_para.emmc50_pad_ds_tune = 2409a2e6d1f6SChaotian Jing readl(host->top_base + EMMC50_PAD_DS_TUNE); 2410a2e6d1f6SChaotian Jing } else { 2411a2e6d1f6SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 2412a2e6d1f6SChaotian Jing } 24134b8a43e9SChaotian Jing } 24144b8a43e9SChaotian Jing 24154b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 24164b8a43e9SChaotian Jing { 241739add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 241839add252SChaotian Jing 24194b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 24204b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 24214b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 24224b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 24234b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 24242fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 24256397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 24261ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 24276397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2428c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2429d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2430a2e6d1f6SChaotian Jing if (host->top_base) { 2431a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_control, 2432a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 2433a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_cmd, 2434a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 2435a2e6d1f6SChaotian Jing writel(host->save_para.emmc50_pad_ds_tune, 2436a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2437a2e6d1f6SChaotian Jing } else { 2438a2e6d1f6SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 2439a2e6d1f6SChaotian Jing } 24401c81d69dSUlf Hansson 24411c81d69dSUlf Hansson if (sdio_irq_claimed(host->mmc)) 24421c81d69dSUlf Hansson __msdc_enable_sdio_irq(host, 1); 24434b8a43e9SChaotian Jing } 24444b8a43e9SChaotian Jing 24454b8a43e9SChaotian Jing static int msdc_runtime_suspend(struct device *dev) 24464b8a43e9SChaotian Jing { 24474b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 24484b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 24494b8a43e9SChaotian Jing 24504b8a43e9SChaotian Jing msdc_save_reg(host); 24514b8a43e9SChaotian Jing msdc_gate_clock(host); 24524b8a43e9SChaotian Jing return 0; 24534b8a43e9SChaotian Jing } 24544b8a43e9SChaotian Jing 24554b8a43e9SChaotian Jing static int msdc_runtime_resume(struct device *dev) 24564b8a43e9SChaotian Jing { 24574b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 24584b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 24594b8a43e9SChaotian Jing 24604b8a43e9SChaotian Jing msdc_ungate_clock(host); 24614b8a43e9SChaotian Jing msdc_restore_reg(host); 24624b8a43e9SChaotian Jing return 0; 24634b8a43e9SChaotian Jing } 24644b8a43e9SChaotian Jing #endif 24654b8a43e9SChaotian Jing 24664b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 24674b8a43e9SChaotian Jing SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 24684b8a43e9SChaotian Jing pm_runtime_force_resume) 24694b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 24704b8a43e9SChaotian Jing }; 24714b8a43e9SChaotian Jing 247220848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 247320848903SChaotian Jing .probe = msdc_drv_probe, 247420848903SChaotian Jing .remove = msdc_drv_remove, 247520848903SChaotian Jing .driver = { 247620848903SChaotian Jing .name = "mtk-msdc", 247720848903SChaotian Jing .of_match_table = msdc_of_ids, 24784b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 247920848903SChaotian Jing }, 248020848903SChaotian Jing }; 248120848903SChaotian Jing 248220848903SChaotian Jing module_platform_driver(mt_msdc_driver); 248320848903SChaotian Jing MODULE_LICENSE("GPL v2"); 248420848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2485