120848903SChaotian Jing /* 220848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 320848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 420848903SChaotian Jing * 520848903SChaotian Jing * This program is free software; you can redistribute it and/or modify 620848903SChaotian Jing * it under the terms of the GNU General Public License version 2 as 720848903SChaotian Jing * published by the Free Software Foundation. 820848903SChaotian Jing * 920848903SChaotian Jing * This program is distributed in the hope that it will be useful, 1020848903SChaotian Jing * but WITHOUT ANY WARRANTY; without even the implied warranty of 1120848903SChaotian Jing * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1220848903SChaotian Jing * GNU General Public License for more details. 1320848903SChaotian Jing */ 1420848903SChaotian Jing 1520848903SChaotian Jing #include <linux/module.h> 1620848903SChaotian Jing #include <linux/clk.h> 1720848903SChaotian Jing #include <linux/delay.h> 1820848903SChaotian Jing #include <linux/dma-mapping.h> 1920848903SChaotian Jing #include <linux/ioport.h> 2020848903SChaotian Jing #include <linux/irq.h> 2120848903SChaotian Jing #include <linux/of_address.h> 22909b3456SRyder Lee #include <linux/of_device.h> 2320848903SChaotian Jing #include <linux/of_irq.h> 2420848903SChaotian Jing #include <linux/of_gpio.h> 2520848903SChaotian Jing #include <linux/pinctrl/consumer.h> 2620848903SChaotian Jing #include <linux/platform_device.h> 274b8a43e9SChaotian Jing #include <linux/pm.h> 284b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2920848903SChaotian Jing #include <linux/regulator/consumer.h> 306397b7f5SChaotian Jing #include <linux/slab.h> 3120848903SChaotian Jing #include <linux/spinlock.h> 32b8789ec4SUlf Hansson #include <linux/interrupt.h> 3320848903SChaotian Jing 3420848903SChaotian Jing #include <linux/mmc/card.h> 3520848903SChaotian Jing #include <linux/mmc/core.h> 3620848903SChaotian Jing #include <linux/mmc/host.h> 3720848903SChaotian Jing #include <linux/mmc/mmc.h> 3820848903SChaotian Jing #include <linux/mmc/sd.h> 3920848903SChaotian Jing #include <linux/mmc/sdio.h> 408d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 4120848903SChaotian Jing 4220848903SChaotian Jing #define MAX_BD_NUM 1024 4320848903SChaotian Jing 4420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4520848903SChaotian Jing /* Common Definition */ 4620848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4720848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4820848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4920848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 5020848903SChaotian Jing 5120848903SChaotian Jing #define MSDC_BURST_64B 0x6 5220848903SChaotian Jing 5320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5420848903SChaotian Jing /* Register Offset */ 5520848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5620848903SChaotian Jing #define MSDC_CFG 0x0 5720848903SChaotian Jing #define MSDC_IOCON 0x04 5820848903SChaotian Jing #define MSDC_PS 0x08 5920848903SChaotian Jing #define MSDC_INT 0x0c 6020848903SChaotian Jing #define MSDC_INTEN 0x10 6120848903SChaotian Jing #define MSDC_FIFOCS 0x14 6220848903SChaotian Jing #define SDC_CFG 0x30 6320848903SChaotian Jing #define SDC_CMD 0x34 6420848903SChaotian Jing #define SDC_ARG 0x38 6520848903SChaotian Jing #define SDC_STS 0x3c 6620848903SChaotian Jing #define SDC_RESP0 0x40 6720848903SChaotian Jing #define SDC_RESP1 0x44 6820848903SChaotian Jing #define SDC_RESP2 0x48 6920848903SChaotian Jing #define SDC_RESP3 0x4c 7020848903SChaotian Jing #define SDC_BLK_NUM 0x50 71d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 72c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 7320848903SChaotian Jing #define SDC_ACMD_RESP 0x80 742a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 7520848903SChaotian Jing #define MSDC_DMA_SA 0x90 7620848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7720848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7820848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7920848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 802fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 8120848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 8239add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 836397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 841ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 856397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 86c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 87d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 8820848903SChaotian Jing 8920848903SChaotian Jing /*--------------------------------------------------------------------------*/ 9020848903SChaotian Jing /* Register Mask */ 9120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 9220848903SChaotian Jing 9320848903SChaotian Jing /* MSDC_CFG mask */ 9420848903SChaotian Jing #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 9520848903SChaotian Jing #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 9620848903SChaotian Jing #define MSDC_CFG_RST (0x1 << 2) /* RW */ 9720848903SChaotian Jing #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 9820848903SChaotian Jing #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 9920848903SChaotian Jing #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 10020848903SChaotian Jing #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 10120848903SChaotian Jing #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 10220848903SChaotian Jing #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 10320848903SChaotian Jing #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 1046397b7f5SChaotian Jing #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 105762d491aSChaotian Jing #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 106762d491aSChaotian Jing #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 107762d491aSChaotian Jing #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 10820848903SChaotian Jing 10920848903SChaotian Jing /* MSDC_IOCON mask */ 11020848903SChaotian Jing #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 11120848903SChaotian Jing #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 11220848903SChaotian Jing #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 11320848903SChaotian Jing #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 11420848903SChaotian Jing #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 11520848903SChaotian Jing #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 11620848903SChaotian Jing #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 11720848903SChaotian Jing #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 11820848903SChaotian Jing #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 11920848903SChaotian Jing #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 12020848903SChaotian Jing #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 12120848903SChaotian Jing #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 12220848903SChaotian Jing #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 12320848903SChaotian Jing #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 12420848903SChaotian Jing #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 12520848903SChaotian Jing #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 12620848903SChaotian Jing 12720848903SChaotian Jing /* MSDC_PS mask */ 12820848903SChaotian Jing #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 12920848903SChaotian Jing #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 13020848903SChaotian Jing #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 13120848903SChaotian Jing #define MSDC_PS_DAT (0xff << 16) /* R */ 13220848903SChaotian Jing #define MSDC_PS_CMD (0x1 << 24) /* R */ 13320848903SChaotian Jing #define MSDC_PS_WP (0x1 << 31) /* R */ 13420848903SChaotian Jing 13520848903SChaotian Jing /* MSDC_INT mask */ 13620848903SChaotian Jing #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 13720848903SChaotian Jing #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 13820848903SChaotian Jing #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 13920848903SChaotian Jing #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 14020848903SChaotian Jing #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 14120848903SChaotian Jing #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 14220848903SChaotian Jing #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 14320848903SChaotian Jing #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 14420848903SChaotian Jing #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 14520848903SChaotian Jing #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 14620848903SChaotian Jing #define MSDC_INT_CSTA (0x1 << 11) /* R */ 14720848903SChaotian Jing #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 14820848903SChaotian Jing #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 14920848903SChaotian Jing #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 15020848903SChaotian Jing #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 15120848903SChaotian Jing #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 15220848903SChaotian Jing #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 15320848903SChaotian Jing #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 15420848903SChaotian Jing #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 15520848903SChaotian Jing 15620848903SChaotian Jing /* MSDC_INTEN mask */ 15720848903SChaotian Jing #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 15820848903SChaotian Jing #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 15920848903SChaotian Jing #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 16020848903SChaotian Jing #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 16120848903SChaotian Jing #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 16220848903SChaotian Jing #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 16320848903SChaotian Jing #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 16420848903SChaotian Jing #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 16520848903SChaotian Jing #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 16620848903SChaotian Jing #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 16720848903SChaotian Jing #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 16820848903SChaotian Jing #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 16920848903SChaotian Jing #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 17020848903SChaotian Jing #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 17120848903SChaotian Jing #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 17220848903SChaotian Jing #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 17320848903SChaotian Jing #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 17420848903SChaotian Jing #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 17520848903SChaotian Jing #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 17620848903SChaotian Jing 17720848903SChaotian Jing /* MSDC_FIFOCS mask */ 17820848903SChaotian Jing #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 17920848903SChaotian Jing #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 18020848903SChaotian Jing #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 18120848903SChaotian Jing 18220848903SChaotian Jing /* SDC_CFG mask */ 18320848903SChaotian Jing #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 18420848903SChaotian Jing #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 18520848903SChaotian Jing #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 18620848903SChaotian Jing #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 18720848903SChaotian Jing #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 18820848903SChaotian Jing #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 18920848903SChaotian Jing #define SDC_CFG_DTOC (0xff << 24) /* RW */ 19020848903SChaotian Jing 19120848903SChaotian Jing /* SDC_STS mask */ 19220848903SChaotian Jing #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 19320848903SChaotian Jing #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 19420848903SChaotian Jing #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 19520848903SChaotian Jing 196d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 197d9dcbfc8SChaotian Jing #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 198d9dcbfc8SChaotian Jing 1992a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2002a9bde19SChaotian Jing #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 2012a9bde19SChaotian Jing 20220848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 20320848903SChaotian Jing #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 20420848903SChaotian Jing #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 20520848903SChaotian Jing #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 20620848903SChaotian Jing #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 20720848903SChaotian Jing #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 20820848903SChaotian Jing #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 20920848903SChaotian Jing 21020848903SChaotian Jing /* MSDC_DMA_CFG mask */ 21120848903SChaotian Jing #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 21220848903SChaotian Jing #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 21320848903SChaotian Jing #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 21420848903SChaotian Jing #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 21520848903SChaotian Jing #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 21620848903SChaotian Jing 21720848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 21820848903SChaotian Jing #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 21920848903SChaotian Jing #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 22020848903SChaotian Jing #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 22120848903SChaotian Jing #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 22220848903SChaotian Jing #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 22320848903SChaotian Jing #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 22420848903SChaotian Jing #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 22520848903SChaotian Jing #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 22620848903SChaotian Jing #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 22720848903SChaotian Jing #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 22820848903SChaotian Jing #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 22920848903SChaotian Jing #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 23020848903SChaotian Jing 231d9dcbfc8SChaotian Jing #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 232d9dcbfc8SChaotian Jing 2332fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 2342fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 2352a9bde19SChaotian Jing #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 2362fea5819SChaotian Jing #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 2372fea5819SChaotian Jing #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 2382fea5819SChaotian Jing #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 2392fea5819SChaotian Jing 2401ede5cb8Syong mao #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 2416397b7f5SChaotian Jing #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 2426397b7f5SChaotian Jing #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 2431ede5cb8Syong mao #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 2441ede5cb8Syong mao #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 2452fea5819SChaotian Jing #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 2462fea5819SChaotian Jing #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 2472fea5819SChaotian Jing #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 2486397b7f5SChaotian Jing 2496397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 2506397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 2516397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 2526397b7f5SChaotian Jing 2531ede5cb8Syong mao #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 2541ede5cb8Syong mao 2556397b7f5SChaotian Jing #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 2566397b7f5SChaotian Jing #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 2576397b7f5SChaotian Jing #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 2586397b7f5SChaotian Jing 259c8609b22SChaotian Jing #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 260c8609b22SChaotian Jing 261d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 262d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 263d9dcbfc8SChaotian Jing 26420848903SChaotian Jing #define REQ_CMD_EIO (0x1 << 0) 26520848903SChaotian Jing #define REQ_CMD_TMO (0x1 << 1) 26620848903SChaotian Jing #define REQ_DAT_ERR (0x1 << 2) 26720848903SChaotian Jing #define REQ_STOP_EIO (0x1 << 3) 26820848903SChaotian Jing #define REQ_STOP_TMO (0x1 << 4) 26920848903SChaotian Jing #define REQ_CMD_BUSY (0x1 << 5) 27020848903SChaotian Jing 27120848903SChaotian Jing #define MSDC_PREPARE_FLAG (0x1 << 0) 27220848903SChaotian Jing #define MSDC_ASYNC_FLAG (0x1 << 1) 27320848903SChaotian Jing #define MSDC_MMAP_FLAG (0x1 << 2) 27420848903SChaotian Jing 2754b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 27620848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 27720848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 27820848903SChaotian Jing 2796397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 28020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 28120848903SChaotian Jing /* Descriptor Structure */ 28220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 28320848903SChaotian Jing struct mt_gpdma_desc { 28420848903SChaotian Jing u32 gpd_info; 28520848903SChaotian Jing #define GPDMA_DESC_HWO (0x1 << 0) 28620848903SChaotian Jing #define GPDMA_DESC_BDP (0x1 << 1) 28720848903SChaotian Jing #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 28820848903SChaotian Jing #define GPDMA_DESC_INT (0x1 << 16) 2892a9bde19SChaotian Jing #define GPDMA_DESC_NEXT_H4 (0xf << 24) 2902a9bde19SChaotian Jing #define GPDMA_DESC_PTR_H4 (0xf << 28) 29120848903SChaotian Jing u32 next; 29220848903SChaotian Jing u32 ptr; 29320848903SChaotian Jing u32 gpd_data_len; 29420848903SChaotian Jing #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 29520848903SChaotian Jing #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 29620848903SChaotian Jing u32 arg; 29720848903SChaotian Jing u32 blknum; 29820848903SChaotian Jing u32 cmd; 29920848903SChaotian Jing }; 30020848903SChaotian Jing 30120848903SChaotian Jing struct mt_bdma_desc { 30220848903SChaotian Jing u32 bd_info; 30320848903SChaotian Jing #define BDMA_DESC_EOL (0x1 << 0) 30420848903SChaotian Jing #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 30520848903SChaotian Jing #define BDMA_DESC_BLKPAD (0x1 << 17) 30620848903SChaotian Jing #define BDMA_DESC_DWPAD (0x1 << 18) 3072a9bde19SChaotian Jing #define BDMA_DESC_NEXT_H4 (0xf << 24) 3082a9bde19SChaotian Jing #define BDMA_DESC_PTR_H4 (0xf << 28) 30920848903SChaotian Jing u32 next; 31020848903SChaotian Jing u32 ptr; 31120848903SChaotian Jing u32 bd_data_len; 31220848903SChaotian Jing #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 31320848903SChaotian Jing }; 31420848903SChaotian Jing 31520848903SChaotian Jing struct msdc_dma { 31620848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 31720848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 31820848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 31920848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 32020848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 32120848903SChaotian Jing }; 32220848903SChaotian Jing 3234b8a43e9SChaotian Jing struct msdc_save_para { 3244b8a43e9SChaotian Jing u32 msdc_cfg; 3254b8a43e9SChaotian Jing u32 iocon; 3264b8a43e9SChaotian Jing u32 sdc_cfg; 3274b8a43e9SChaotian Jing u32 pad_tune; 3284b8a43e9SChaotian Jing u32 patch_bit0; 3294b8a43e9SChaotian Jing u32 patch_bit1; 3302fea5819SChaotian Jing u32 patch_bit2; 3316397b7f5SChaotian Jing u32 pad_ds_tune; 3321ede5cb8Syong mao u32 pad_cmd_tune; 3336397b7f5SChaotian Jing u32 emmc50_cfg0; 334c8609b22SChaotian Jing u32 emmc50_cfg3; 335d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 3366397b7f5SChaotian Jing }; 3376397b7f5SChaotian Jing 338762d491aSChaotian Jing struct mtk_mmc_compatible { 339762d491aSChaotian Jing u8 clk_div_bits; 3407f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 34139add252SChaotian Jing u32 pad_tune_reg; 3422fea5819SChaotian Jing bool async_fifo; 3432fea5819SChaotian Jing bool data_tune; 344acde28c4SChaotian Jing bool busy_check; 345d9dcbfc8SChaotian Jing bool stop_clk_fix; 346d9dcbfc8SChaotian Jing bool enhance_rx; 3472a9bde19SChaotian Jing bool support_64g; 348762d491aSChaotian Jing }; 349762d491aSChaotian Jing 35086beac37SChaotian Jing struct msdc_tune_para { 35186beac37SChaotian Jing u32 iocon; 35286beac37SChaotian Jing u32 pad_tune; 3531ede5cb8Syong mao u32 pad_cmd_tune; 35486beac37SChaotian Jing }; 35586beac37SChaotian Jing 3566397b7f5SChaotian Jing struct msdc_delay_phase { 3576397b7f5SChaotian Jing u8 maxlen; 3586397b7f5SChaotian Jing u8 start; 3596397b7f5SChaotian Jing u8 final_phase; 3604b8a43e9SChaotian Jing }; 3614b8a43e9SChaotian Jing 36220848903SChaotian Jing struct msdc_host { 36320848903SChaotian Jing struct device *dev; 364762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 36520848903SChaotian Jing struct mmc_host *mmc; /* mmc structure */ 36620848903SChaotian Jing int cmd_rsp; 36720848903SChaotian Jing 36820848903SChaotian Jing spinlock_t lock; 36920848903SChaotian Jing struct mmc_request *mrq; 37020848903SChaotian Jing struct mmc_command *cmd; 37120848903SChaotian Jing struct mmc_data *data; 37220848903SChaotian Jing int error; 37320848903SChaotian Jing 37420848903SChaotian Jing void __iomem *base; /* host base address */ 37520848903SChaotian Jing 37620848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 37720848903SChaotian Jing u64 dma_mask; 37820848903SChaotian Jing 37920848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 38020848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 38120848903SChaotian Jing 38220848903SChaotian Jing struct pinctrl *pinctrl; 38320848903SChaotian Jing struct pinctrl_state *pins_default; 38420848903SChaotian Jing struct pinctrl_state *pins_uhs; 38520848903SChaotian Jing struct delayed_work req_timeout; 38620848903SChaotian Jing int irq; /* host interrupt */ 38720848903SChaotian Jing 38820848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 38920848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 390258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 3913c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 39220848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 39320848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 3946e622947SChaotian Jing unsigned char timing; 39520848903SChaotian Jing bool vqmmc_enabled; 396d17bb71cSChaotian Jing u32 latch_ck; 3976397b7f5SChaotian Jing u32 hs400_ds_delay; 3981ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 3991ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4001ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4011ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4025462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 4034b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 40486beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 40586beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 40620848903SChaotian Jing }; 40720848903SChaotian Jing 408762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 409762d491aSChaotian Jing .clk_div_bits = 8, 4107f3d5852SChaotian Jing .hs400_tune = false, 41139add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4122fea5819SChaotian Jing .async_fifo = false, 4132fea5819SChaotian Jing .data_tune = false, 414acde28c4SChaotian Jing .busy_check = false, 415d9dcbfc8SChaotian Jing .stop_clk_fix = false, 416d9dcbfc8SChaotian Jing .enhance_rx = false, 4172a9bde19SChaotian Jing .support_64g = false, 418762d491aSChaotian Jing }; 419762d491aSChaotian Jing 420762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 421762d491aSChaotian Jing .clk_div_bits = 8, 4227f3d5852SChaotian Jing .hs400_tune = true, 42339add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4242fea5819SChaotian Jing .async_fifo = false, 4252fea5819SChaotian Jing .data_tune = false, 426acde28c4SChaotian Jing .busy_check = false, 427d9dcbfc8SChaotian Jing .stop_clk_fix = false, 428d9dcbfc8SChaotian Jing .enhance_rx = false, 4292a9bde19SChaotian Jing .support_64g = false, 430762d491aSChaotian Jing }; 431762d491aSChaotian Jing 432762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2701_compat = { 433762d491aSChaotian Jing .clk_div_bits = 12, 4347f3d5852SChaotian Jing .hs400_tune = false, 43539add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 4362fea5819SChaotian Jing .async_fifo = true, 4372fea5819SChaotian Jing .data_tune = true, 438acde28c4SChaotian Jing .busy_check = false, 439d9dcbfc8SChaotian Jing .stop_clk_fix = false, 440d9dcbfc8SChaotian Jing .enhance_rx = false, 4412a9bde19SChaotian Jing .support_64g = false, 442762d491aSChaotian Jing }; 443762d491aSChaotian Jing 444762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2712_compat = { 445762d491aSChaotian Jing .clk_div_bits = 12, 4467f3d5852SChaotian Jing .hs400_tune = false, 44739add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 4482fea5819SChaotian Jing .async_fifo = true, 4492fea5819SChaotian Jing .data_tune = true, 450acde28c4SChaotian Jing .busy_check = true, 451d9dcbfc8SChaotian Jing .stop_clk_fix = true, 452d9dcbfc8SChaotian Jing .enhance_rx = true, 4532a9bde19SChaotian Jing .support_64g = true, 454762d491aSChaotian Jing }; 455762d491aSChaotian Jing 456966580adSSean Wang static const struct mtk_mmc_compatible mt7622_compat = { 457966580adSSean Wang .clk_div_bits = 12, 458966580adSSean Wang .hs400_tune = false, 459966580adSSean Wang .pad_tune_reg = MSDC_PAD_TUNE0, 460966580adSSean Wang .async_fifo = true, 461966580adSSean Wang .data_tune = true, 462966580adSSean Wang .busy_check = true, 463966580adSSean Wang .stop_clk_fix = true, 464966580adSSean Wang .enhance_rx = true, 4652a9bde19SChaotian Jing .support_64g = false, 466966580adSSean Wang }; 467966580adSSean Wang 468762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 469762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 470762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 471762d491aSChaotian Jing { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 472762d491aSChaotian Jing { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 473966580adSSean Wang { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 474762d491aSChaotian Jing {} 475762d491aSChaotian Jing }; 476762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 477762d491aSChaotian Jing 47820848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 47920848903SChaotian Jing { 48020848903SChaotian Jing u32 val = readl(reg); 48120848903SChaotian Jing 48220848903SChaotian Jing val |= bs; 48320848903SChaotian Jing writel(val, reg); 48420848903SChaotian Jing } 48520848903SChaotian Jing 48620848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 48720848903SChaotian Jing { 48820848903SChaotian Jing u32 val = readl(reg); 48920848903SChaotian Jing 49020848903SChaotian Jing val &= ~bs; 49120848903SChaotian Jing writel(val, reg); 49220848903SChaotian Jing } 49320848903SChaotian Jing 49420848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 49520848903SChaotian Jing { 49620848903SChaotian Jing unsigned int tv = readl(reg); 49720848903SChaotian Jing 49820848903SChaotian Jing tv &= ~field; 49920848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 50020848903SChaotian Jing writel(tv, reg); 50120848903SChaotian Jing } 50220848903SChaotian Jing 50320848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 50420848903SChaotian Jing { 50520848903SChaotian Jing unsigned int tv = readl(reg); 50620848903SChaotian Jing 50720848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 50820848903SChaotian Jing } 50920848903SChaotian Jing 51020848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 51120848903SChaotian Jing { 51220848903SChaotian Jing u32 val; 51320848903SChaotian Jing 51420848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 51520848903SChaotian Jing while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 51620848903SChaotian Jing cpu_relax(); 51720848903SChaotian Jing 51820848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 51920848903SChaotian Jing while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 52020848903SChaotian Jing cpu_relax(); 52120848903SChaotian Jing 52220848903SChaotian Jing val = readl(host->base + MSDC_INT); 52320848903SChaotian Jing writel(val, host->base + MSDC_INT); 52420848903SChaotian Jing } 52520848903SChaotian Jing 52620848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 52720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 52820848903SChaotian Jing 529726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 530726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 531726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 532726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 53320848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 53420848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 53520848903SChaotian Jing 53620848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 53720848903SChaotian Jing { 53820848903SChaotian Jing u32 i, sum = 0; 53920848903SChaotian Jing 54020848903SChaotian Jing for (i = 0; i < len; i++) 54120848903SChaotian Jing sum += buf[i]; 54220848903SChaotian Jing return 0xff - (u8) sum; 54320848903SChaotian Jing } 54420848903SChaotian Jing 54520848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 54620848903SChaotian Jing struct mmc_data *data) 54720848903SChaotian Jing { 54820848903SChaotian Jing unsigned int j, dma_len; 54920848903SChaotian Jing dma_addr_t dma_address; 55020848903SChaotian Jing u32 dma_ctrl; 55120848903SChaotian Jing struct scatterlist *sg; 55220848903SChaotian Jing struct mt_gpdma_desc *gpd; 55320848903SChaotian Jing struct mt_bdma_desc *bd; 55420848903SChaotian Jing 55520848903SChaotian Jing sg = data->sg; 55620848903SChaotian Jing 55720848903SChaotian Jing gpd = dma->gpd; 55820848903SChaotian Jing bd = dma->bd; 55920848903SChaotian Jing 56020848903SChaotian Jing /* modify gpd */ 56120848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 56220848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 56320848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 56420848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 56520848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 56620848903SChaotian Jing 56720848903SChaotian Jing /* modify bd */ 56820848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 56920848903SChaotian Jing dma_address = sg_dma_address(sg); 57020848903SChaotian Jing dma_len = sg_dma_len(sg); 57120848903SChaotian Jing 57220848903SChaotian Jing /* init bd */ 57320848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 57420848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 5752a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 5762a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 5772a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 5782a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 5792a9bde19SChaotian Jing << 28; 5802a9bde19SChaotian Jing } 58120848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 58220848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 58320848903SChaotian Jing 58420848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 58520848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 58620848903SChaotian Jing else 58720848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 58820848903SChaotian Jing 58920848903SChaotian Jing /* checksume need to clear first */ 59020848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 59120848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 59220848903SChaotian Jing } 59320848903SChaotian Jing 59420848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 59520848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 59620848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 59720848903SChaotian Jing dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 59820848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 5992a9bde19SChaotian Jing if (host->dev_comp->support_64g) 6002a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 6012a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 6022a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 60320848903SChaotian Jing } 60420848903SChaotian Jing 60520848903SChaotian Jing static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 60620848903SChaotian Jing { 60720848903SChaotian Jing struct mmc_data *data = mrq->data; 60820848903SChaotian Jing 60920848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 61020848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 61120848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 612feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 61320848903SChaotian Jing } 61420848903SChaotian Jing } 61520848903SChaotian Jing 61620848903SChaotian Jing static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 61720848903SChaotian Jing { 61820848903SChaotian Jing struct mmc_data *data = mrq->data; 61920848903SChaotian Jing 62020848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 62120848903SChaotian Jing return; 62220848903SChaotian Jing 62320848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 62420848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 625feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 62620848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 62720848903SChaotian Jing } 62820848903SChaotian Jing } 62920848903SChaotian Jing 63020848903SChaotian Jing /* clock control primitives */ 63120848903SChaotian Jing static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 63220848903SChaotian Jing { 63320848903SChaotian Jing u32 timeout, clk_ns; 63420848903SChaotian Jing u32 mode = 0; 63520848903SChaotian Jing 63620848903SChaotian Jing host->timeout_ns = ns; 63720848903SChaotian Jing host->timeout_clks = clks; 63856f6cbbeSChaotian Jing if (host->mmc->actual_clock == 0) { 63920848903SChaotian Jing timeout = 0; 64020848903SChaotian Jing } else { 64156f6cbbeSChaotian Jing clk_ns = 1000000000UL / host->mmc->actual_clock; 64220848903SChaotian Jing timeout = (ns + clk_ns - 1) / clk_ns + clks; 64320848903SChaotian Jing /* in 1048576 sclk cycle unit */ 64420848903SChaotian Jing timeout = (timeout + (0x1 << 20) - 1) >> 20; 645762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 646762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 647762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 648762d491aSChaotian Jing else 649762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 650762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 65120848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 65220848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 65320848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 65420848903SChaotian Jing timeout = timeout > 255 ? 255 : timeout; 65520848903SChaotian Jing } 65620848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 65720848903SChaotian Jing } 65820848903SChaotian Jing 65920848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 66020848903SChaotian Jing { 6613c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 66220848903SChaotian Jing clk_disable_unprepare(host->src_clk); 663258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 66420848903SChaotian Jing clk_disable_unprepare(host->h_clk); 66520848903SChaotian Jing } 66620848903SChaotian Jing 66720848903SChaotian Jing static void msdc_ungate_clock(struct msdc_host *host) 66820848903SChaotian Jing { 66920848903SChaotian Jing clk_prepare_enable(host->h_clk); 670258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 67120848903SChaotian Jing clk_prepare_enable(host->src_clk); 6723c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 67320848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 67420848903SChaotian Jing cpu_relax(); 67520848903SChaotian Jing } 67620848903SChaotian Jing 6776e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 67820848903SChaotian Jing { 67920848903SChaotian Jing u32 mode; 68020848903SChaotian Jing u32 flags; 68120848903SChaotian Jing u32 div; 68220848903SChaotian Jing u32 sclk; 68339add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 68420848903SChaotian Jing 68520848903SChaotian Jing if (!hz) { 68620848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 68720848903SChaotian Jing host->mclk = 0; 68856f6cbbeSChaotian Jing host->mmc->actual_clock = 0; 68920848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 69020848903SChaotian Jing return; 69120848903SChaotian Jing } 69220848903SChaotian Jing 69320848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 69420848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 695762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 6966397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 697762d491aSChaotian Jing else 698762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 699762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 7006e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 7016397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 7026397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 7036397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 7046397b7f5SChaotian Jing mode = 0x3; 7056397b7f5SChaotian Jing else 70620848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 7076397b7f5SChaotian Jing 70820848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 70920848903SChaotian Jing div = 0; /* mean div = 1/4 */ 71020848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 71120848903SChaotian Jing } else { 71220848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 71320848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 71420848903SChaotian Jing div = (div >> 1); 71520848903SChaotian Jing } 7166397b7f5SChaotian Jing 7176397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 7186397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 719762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 7206397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 7216397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 722762d491aSChaotian Jing else 723762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 724762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 7256397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 7266397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 7276397b7f5SChaotian Jing } 72820848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 72920848903SChaotian Jing mode = 0x1; /* no divisor */ 73020848903SChaotian Jing div = 0; 73120848903SChaotian Jing sclk = host->src_clk_freq; 73220848903SChaotian Jing } else { 73320848903SChaotian Jing mode = 0x0; /* use divisor */ 73420848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 73520848903SChaotian Jing div = 0; /* mean div = 1/2 */ 73620848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 73720848903SChaotian Jing } else { 73820848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 73920848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 74020848903SChaotian Jing } 74120848903SChaotian Jing } 7423c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 7433c1a8844SChaotian Jing /* 7443c1a8844SChaotian Jing * As src_clk/HCLK use the same bit to gate/ungate, 7453c1a8844SChaotian Jing * So if want to only gate src_clk, need gate its parent(mux). 7463c1a8844SChaotian Jing */ 7473c1a8844SChaotian Jing if (host->src_clk_cg) 7483c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 7493c1a8844SChaotian Jing else 7503c1a8844SChaotian Jing clk_disable_unprepare(clk_get_parent(host->src_clk)); 751762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 752762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 753762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 75440ceda09Syong mao (mode << 8) | div); 755762d491aSChaotian Jing else 756762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 757762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 758762d491aSChaotian Jing (mode << 12) | div); 7593c1a8844SChaotian Jing if (host->src_clk_cg) 7603c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 7613c1a8844SChaotian Jing else 7623c1a8844SChaotian Jing clk_prepare_enable(clk_get_parent(host->src_clk)); 763762d491aSChaotian Jing 76420848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 76520848903SChaotian Jing cpu_relax(); 7663c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 76756f6cbbeSChaotian Jing host->mmc->actual_clock = sclk; 76820848903SChaotian Jing host->mclk = hz; 7696e622947SChaotian Jing host->timing = timing; 77020848903SChaotian Jing /* need because clk changed. */ 77120848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 77220848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 77320848903SChaotian Jing 77486beac37SChaotian Jing /* 77586beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 77686beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 77786beac37SChaotian Jing */ 77856f6cbbeSChaotian Jing if (host->mmc->actual_clock <= 52000000) { 77986beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 78039add252SChaotian Jing writel(host->def_tune_para.pad_tune, host->base + tune_reg); 78186beac37SChaotian Jing } else { 78286beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 78339add252SChaotian Jing writel(host->saved_tune_para.pad_tune, host->base + tune_reg); 7841ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 7851ede5cb8Syong mao host->base + PAD_CMD_TUNE); 78686beac37SChaotian Jing } 78786beac37SChaotian Jing 7887f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 7897f3d5852SChaotian Jing host->dev_comp->hs400_tune) 7901ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 7911ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 7921ede5cb8Syong mao host->hs400_cmd_int_delay); 79356f6cbbeSChaotian Jing dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 79456f6cbbeSChaotian Jing timing); 79520848903SChaotian Jing } 79620848903SChaotian Jing 79720848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 79820848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 79920848903SChaotian Jing { 80020848903SChaotian Jing u32 resp; 80120848903SChaotian Jing 80220848903SChaotian Jing switch (mmc_resp_type(cmd)) { 80320848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 80420848903SChaotian Jing case MMC_RSP_R1: 80520848903SChaotian Jing resp = 0x1; 80620848903SChaotian Jing break; 80720848903SChaotian Jing case MMC_RSP_R1B: 80820848903SChaotian Jing resp = 0x7; 80920848903SChaotian Jing break; 81020848903SChaotian Jing case MMC_RSP_R2: 81120848903SChaotian Jing resp = 0x2; 81220848903SChaotian Jing break; 81320848903SChaotian Jing case MMC_RSP_R3: 81420848903SChaotian Jing resp = 0x3; 81520848903SChaotian Jing break; 81620848903SChaotian Jing case MMC_RSP_NONE: 81720848903SChaotian Jing default: 81820848903SChaotian Jing resp = 0x0; 81920848903SChaotian Jing break; 82020848903SChaotian Jing } 82120848903SChaotian Jing 82220848903SChaotian Jing return resp; 82320848903SChaotian Jing } 82420848903SChaotian Jing 82520848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 82620848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 82720848903SChaotian Jing { 82820848903SChaotian Jing /* rawcmd : 82920848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 83020848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 83120848903SChaotian Jing */ 83220848903SChaotian Jing u32 opcode = cmd->opcode; 83320848903SChaotian Jing u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 83420848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 83520848903SChaotian Jing 83620848903SChaotian Jing host->cmd_rsp = resp; 83720848903SChaotian Jing 83820848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 83920848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 84020848903SChaotian Jing rawcmd |= (0x1 << 14); 84120848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 84220848903SChaotian Jing rawcmd |= (0x1 << 30); 84320848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 84420848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 84520848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 84620848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 84720848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 84820848903SChaotian Jing rawcmd |= (0x1 << 11); 84920848903SChaotian Jing 85020848903SChaotian Jing if (cmd->data) { 85120848903SChaotian Jing struct mmc_data *data = cmd->data; 85220848903SChaotian Jing 85320848903SChaotian Jing if (mmc_op_multi(opcode)) { 85420848903SChaotian Jing if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 85520848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 85620848903SChaotian Jing rawcmd |= 0x2 << 28; /* AutoCMD23 */ 85720848903SChaotian Jing } 85820848903SChaotian Jing 85920848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 86020848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 86120848903SChaotian Jing rawcmd |= (0x1 << 13); 86220848903SChaotian Jing if (data->blocks > 1) 86320848903SChaotian Jing rawcmd |= (0x2 << 11); 86420848903SChaotian Jing else 86520848903SChaotian Jing rawcmd |= (0x1 << 11); 86620848903SChaotian Jing /* Always use dma mode */ 86720848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 86820848903SChaotian Jing 86920848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 87020848903SChaotian Jing host->timeout_clks != data->timeout_clks) 87120848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 87220848903SChaotian Jing data->timeout_clks); 87320848903SChaotian Jing 87420848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 87520848903SChaotian Jing } 87620848903SChaotian Jing return rawcmd; 87720848903SChaotian Jing } 87820848903SChaotian Jing 87920848903SChaotian Jing static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 88020848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 88120848903SChaotian Jing { 88220848903SChaotian Jing bool read; 88320848903SChaotian Jing 88420848903SChaotian Jing WARN_ON(host->data); 88520848903SChaotian Jing host->data = data; 88620848903SChaotian Jing read = data->flags & MMC_DATA_READ; 88720848903SChaotian Jing 88820848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 88920848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 89020848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 89120848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 89220848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 89320848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 89420848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 89520848903SChaotian Jing } 89620848903SChaotian Jing 89720848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 89820848903SChaotian Jing struct mmc_command *cmd) 89920848903SChaotian Jing { 90020848903SChaotian Jing u32 *rsp = cmd->resp; 90120848903SChaotian Jing 90220848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 90320848903SChaotian Jing 90420848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 90520848903SChaotian Jing cmd->error = 0; 90620848903SChaotian Jing } else { 90720848903SChaotian Jing msdc_reset_hw(host); 90820848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 90920848903SChaotian Jing cmd->error = -EILSEQ; 91020848903SChaotian Jing host->error |= REQ_STOP_EIO; 91120848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 91220848903SChaotian Jing cmd->error = -ETIMEDOUT; 91320848903SChaotian Jing host->error |= REQ_STOP_TMO; 91420848903SChaotian Jing } 91520848903SChaotian Jing dev_err(host->dev, 91620848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 91720848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 91820848903SChaotian Jing } 91920848903SChaotian Jing return cmd->error; 92020848903SChaotian Jing } 92120848903SChaotian Jing 92220848903SChaotian Jing static void msdc_track_cmd_data(struct msdc_host *host, 92320848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 92420848903SChaotian Jing { 92520848903SChaotian Jing if (host->error) 92620848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 92720848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 92820848903SChaotian Jing } 92920848903SChaotian Jing 93020848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 93120848903SChaotian Jing { 93220848903SChaotian Jing unsigned long flags; 93320848903SChaotian Jing bool ret; 93420848903SChaotian Jing 93520848903SChaotian Jing ret = cancel_delayed_work(&host->req_timeout); 93620848903SChaotian Jing if (!ret) { 93720848903SChaotian Jing /* delay work already running */ 93820848903SChaotian Jing return; 93920848903SChaotian Jing } 94020848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 94120848903SChaotian Jing host->mrq = NULL; 94220848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 94320848903SChaotian Jing 94420848903SChaotian Jing msdc_track_cmd_data(host, mrq->cmd, mrq->data); 94520848903SChaotian Jing if (mrq->data) 94620848903SChaotian Jing msdc_unprepare_data(host, mrq); 94720848903SChaotian Jing mmc_request_done(host->mmc, mrq); 94820848903SChaotian Jing } 94920848903SChaotian Jing 95020848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 95120848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 95220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 95320848903SChaotian Jing { 95420848903SChaotian Jing bool done = false; 95520848903SChaotian Jing bool sbc_error; 95620848903SChaotian Jing unsigned long flags; 95720848903SChaotian Jing u32 *rsp = cmd->resp; 95820848903SChaotian Jing 95920848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 96020848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 96120848903SChaotian Jing | MSDC_INT_ACMDTMO))) 96220848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 96320848903SChaotian Jing 96420848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 96520848903SChaotian Jing 96620848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 96720848903SChaotian Jing | MSDC_INT_RSPCRCERR 96820848903SChaotian Jing | MSDC_INT_CMDTMO))) 96920848903SChaotian Jing return done; 97020848903SChaotian Jing 97120848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 97220848903SChaotian Jing done = !host->cmd; 97320848903SChaotian Jing host->cmd = NULL; 97420848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 97520848903SChaotian Jing 97620848903SChaotian Jing if (done) 97720848903SChaotian Jing return true; 97820848903SChaotian Jing 979726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 98020848903SChaotian Jing 98120848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 98220848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 98320848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 98420848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 98520848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 98620848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 98720848903SChaotian Jing } else { 98820848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 98920848903SChaotian Jing } 99020848903SChaotian Jing } 99120848903SChaotian Jing 99220848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 993ddc71387SChaotian Jing if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 994ddc71387SChaotian Jing cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 995ddc71387SChaotian Jing /* 996ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 997ddc71387SChaotian Jing * may have alreay come. 998ddc71387SChaotian Jing */ 99920848903SChaotian Jing msdc_reset_hw(host); 100020848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 100120848903SChaotian Jing cmd->error = -EILSEQ; 100220848903SChaotian Jing host->error |= REQ_CMD_EIO; 100320848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 100420848903SChaotian Jing cmd->error = -ETIMEDOUT; 100520848903SChaotian Jing host->error |= REQ_CMD_TMO; 100620848903SChaotian Jing } 100720848903SChaotian Jing } 100820848903SChaotian Jing if (cmd->error) 100920848903SChaotian Jing dev_dbg(host->dev, 101020848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 101120848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 101220848903SChaotian Jing cmd->error); 101320848903SChaotian Jing 101420848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 101520848903SChaotian Jing return true; 101620848903SChaotian Jing } 101720848903SChaotian Jing 101820848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 101920848903SChaotian Jing * is correct before issue a request. but host design do below 102020848903SChaotian Jing * checks recommended. 102120848903SChaotian Jing */ 102220848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 102320848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 102420848903SChaotian Jing { 102520848903SChaotian Jing /* The max busy time we can endure is 20ms */ 102620848903SChaotian Jing unsigned long tmo = jiffies + msecs_to_jiffies(20); 102720848903SChaotian Jing 102820848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 102920848903SChaotian Jing time_before(jiffies, tmo)) 103020848903SChaotian Jing cpu_relax(); 103120848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 103220848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 103320848903SChaotian Jing host->error |= REQ_CMD_BUSY; 103420848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 103520848903SChaotian Jing return false; 103620848903SChaotian Jing } 103720848903SChaotian Jing 103820848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 103920848903SChaotian Jing tmo = jiffies + msecs_to_jiffies(20); 104020848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 104120848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 104220848903SChaotian Jing time_before(jiffies, tmo)) 104320848903SChaotian Jing cpu_relax(); 104420848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 104520848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 104620848903SChaotian Jing host->error |= REQ_CMD_BUSY; 104720848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 104820848903SChaotian Jing return false; 104920848903SChaotian Jing } 105020848903SChaotian Jing } 105120848903SChaotian Jing return true; 105220848903SChaotian Jing } 105320848903SChaotian Jing 105420848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 105520848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 105620848903SChaotian Jing { 105720848903SChaotian Jing u32 rawcmd; 105820848903SChaotian Jing 105920848903SChaotian Jing WARN_ON(host->cmd); 106020848903SChaotian Jing host->cmd = cmd; 106120848903SChaotian Jing 1062f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 106320848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 106420848903SChaotian Jing return; 106520848903SChaotian Jing 106620848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 106720848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 106820848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 106920848903SChaotian Jing msdc_reset_hw(host); 107020848903SChaotian Jing } 107120848903SChaotian Jing 107220848903SChaotian Jing cmd->error = 0; 107320848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 107420848903SChaotian Jing 1075726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 107620848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 107720848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 107820848903SChaotian Jing } 107920848903SChaotian Jing 108020848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 108120848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 108220848903SChaotian Jing { 1083ddc71387SChaotian Jing if ((cmd->error && 1084ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1085ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1086ddc71387SChaotian Jing cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1087ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 108820848903SChaotian Jing msdc_request_done(host, mrq); 108920848903SChaotian Jing else if (cmd == mrq->sbc) 109020848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 109120848903SChaotian Jing else if (!cmd->data) 109220848903SChaotian Jing msdc_request_done(host, mrq); 109320848903SChaotian Jing else 109420848903SChaotian Jing msdc_start_data(host, mrq, cmd, cmd->data); 109520848903SChaotian Jing } 109620848903SChaotian Jing 109720848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 109820848903SChaotian Jing { 109920848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 110020848903SChaotian Jing 110120848903SChaotian Jing host->error = 0; 110220848903SChaotian Jing WARN_ON(host->mrq); 110320848903SChaotian Jing host->mrq = mrq; 110420848903SChaotian Jing 110520848903SChaotian Jing if (mrq->data) 110620848903SChaotian Jing msdc_prepare_data(host, mrq); 110720848903SChaotian Jing 110820848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 110920848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 111020848903SChaotian Jing * use HW option, otherwise use SW option 111120848903SChaotian Jing */ 111220848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 111320848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 111420848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 111520848903SChaotian Jing else 111620848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 111720848903SChaotian Jing } 111820848903SChaotian Jing 1119d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 112020848903SChaotian Jing { 112120848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 112220848903SChaotian Jing struct mmc_data *data = mrq->data; 112320848903SChaotian Jing 112420848903SChaotian Jing if (!data) 112520848903SChaotian Jing return; 112620848903SChaotian Jing 112720848903SChaotian Jing msdc_prepare_data(host, mrq); 112820848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 112920848903SChaotian Jing } 113020848903SChaotian Jing 113120848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 113220848903SChaotian Jing int err) 113320848903SChaotian Jing { 113420848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 113520848903SChaotian Jing struct mmc_data *data; 113620848903SChaotian Jing 113720848903SChaotian Jing data = mrq->data; 113820848903SChaotian Jing if (!data) 113920848903SChaotian Jing return; 114020848903SChaotian Jing if (data->host_cookie) { 114120848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 114220848903SChaotian Jing msdc_unprepare_data(host, mrq); 114320848903SChaotian Jing } 114420848903SChaotian Jing } 114520848903SChaotian Jing 114620848903SChaotian Jing static void msdc_data_xfer_next(struct msdc_host *host, 114720848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 114820848903SChaotian Jing { 114920848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 11506397b7f5SChaotian Jing !mrq->sbc) 115120848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 115220848903SChaotian Jing else 115320848903SChaotian Jing msdc_request_done(host, mrq); 115420848903SChaotian Jing } 115520848903SChaotian Jing 115620848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 115720848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 115820848903SChaotian Jing { 115920848903SChaotian Jing struct mmc_command *stop = data->stop; 116020848903SChaotian Jing unsigned long flags; 116120848903SChaotian Jing bool done; 116220848903SChaotian Jing unsigned int check_data = events & 116320848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 116420848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 116520848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 116620848903SChaotian Jing 116720848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 116820848903SChaotian Jing done = !host->data; 116920848903SChaotian Jing if (check_data) 117020848903SChaotian Jing host->data = NULL; 117120848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 117220848903SChaotian Jing 117320848903SChaotian Jing if (done) 117420848903SChaotian Jing return true; 117520848903SChaotian Jing 117620848903SChaotian Jing if (check_data || (stop && stop->error)) { 117720848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 117820848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 117920848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 118020848903SChaotian Jing 1); 118120848903SChaotian Jing while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 118220848903SChaotian Jing cpu_relax(); 118320848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 118420848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 118520848903SChaotian Jing 118620848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 118720848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 118820848903SChaotian Jing } else { 11892066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 119020848903SChaotian Jing msdc_reset_hw(host); 119120848903SChaotian Jing host->error |= REQ_DAT_ERR; 119220848903SChaotian Jing data->bytes_xfered = 0; 119320848903SChaotian Jing 119420848903SChaotian Jing if (events & MSDC_INT_DATTMO) 119520848903SChaotian Jing data->error = -ETIMEDOUT; 11966397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 11976397b7f5SChaotian Jing data->error = -EILSEQ; 119820848903SChaotian Jing 11992066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 120020848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 12012066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 120220848903SChaotian Jing (int)data->error, data->bytes_xfered); 120320848903SChaotian Jing } 120420848903SChaotian Jing 120520848903SChaotian Jing msdc_data_xfer_next(host, mrq, data); 120620848903SChaotian Jing done = true; 120720848903SChaotian Jing } 120820848903SChaotian Jing return done; 120920848903SChaotian Jing } 121020848903SChaotian Jing 121120848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 121220848903SChaotian Jing { 121320848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 121420848903SChaotian Jing 121520848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 121620848903SChaotian Jing 121720848903SChaotian Jing switch (width) { 121820848903SChaotian Jing default: 121920848903SChaotian Jing case MMC_BUS_WIDTH_1: 122020848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 122120848903SChaotian Jing break; 122220848903SChaotian Jing case MMC_BUS_WIDTH_4: 122320848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 122420848903SChaotian Jing break; 122520848903SChaotian Jing case MMC_BUS_WIDTH_8: 122620848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 122720848903SChaotian Jing break; 122820848903SChaotian Jing } 122920848903SChaotian Jing 123020848903SChaotian Jing writel(val, host->base + SDC_CFG); 123120848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 123220848903SChaotian Jing } 123320848903SChaotian Jing 123420848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 123520848903SChaotian Jing { 123620848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 123720848903SChaotian Jing int ret = 0; 123820848903SChaotian Jing 123920848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1240fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1241fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 124220848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 124320848903SChaotian Jing return -EINVAL; 124420848903SChaotian Jing } 124520848903SChaotian Jing 1246fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 124720848903SChaotian Jing if (ret) { 1248fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1249fac49ce5SNicolas Boichat ret, ios->signal_voltage); 125020848903SChaotian Jing } else { 125120848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 125220848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 125320848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 125420848903SChaotian Jing else 125520848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 125620848903SChaotian Jing } 125720848903SChaotian Jing } 125820848903SChaotian Jing return ret; 125920848903SChaotian Jing } 126020848903SChaotian Jing 126120848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 126220848903SChaotian Jing { 126320848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 126420848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 126520848903SChaotian Jing 12663bc702edSyong mao /* only check if data0 is low */ 12673bc702edSyong mao return !(status & BIT(16)); 126820848903SChaotian Jing } 126920848903SChaotian Jing 127020848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 127120848903SChaotian Jing { 127220848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 127320848903SChaotian Jing req_timeout.work); 127420848903SChaotian Jing 127520848903SChaotian Jing /* simulate HW timeout status */ 127620848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 127720848903SChaotian Jing if (host->mrq) { 127820848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 127920848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 128020848903SChaotian Jing if (host->cmd) { 128120848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 128220848903SChaotian Jing __func__, host->cmd->opcode); 128320848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 128420848903SChaotian Jing host->cmd); 128520848903SChaotian Jing } else if (host->data) { 128620848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 128720848903SChaotian Jing __func__, host->mrq->cmd->opcode, 128820848903SChaotian Jing host->data->blocks); 128920848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 129020848903SChaotian Jing host->data); 129120848903SChaotian Jing } 129220848903SChaotian Jing } 129320848903SChaotian Jing } 129420848903SChaotian Jing 129520848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 129620848903SChaotian Jing { 129720848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 129820848903SChaotian Jing 129920848903SChaotian Jing while (true) { 130020848903SChaotian Jing unsigned long flags; 130120848903SChaotian Jing struct mmc_request *mrq; 130220848903SChaotian Jing struct mmc_command *cmd; 130320848903SChaotian Jing struct mmc_data *data; 130420848903SChaotian Jing u32 events, event_mask; 130520848903SChaotian Jing 130620848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 130720848903SChaotian Jing events = readl(host->base + MSDC_INT); 130820848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 130920848903SChaotian Jing /* clear interrupts */ 131020848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 131120848903SChaotian Jing 131220848903SChaotian Jing mrq = host->mrq; 131320848903SChaotian Jing cmd = host->cmd; 131420848903SChaotian Jing data = host->data; 131520848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 131620848903SChaotian Jing 131720848903SChaotian Jing if (!(events & event_mask)) 131820848903SChaotian Jing break; 131920848903SChaotian Jing 132020848903SChaotian Jing if (!mrq) { 132120848903SChaotian Jing dev_err(host->dev, 132220848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 132320848903SChaotian Jing __func__, events, event_mask); 132420848903SChaotian Jing WARN_ON(1); 132520848903SChaotian Jing break; 132620848903SChaotian Jing } 132720848903SChaotian Jing 132820848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 132920848903SChaotian Jing 133020848903SChaotian Jing if (cmd) 133120848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 133220848903SChaotian Jing else if (data) 133320848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 133420848903SChaotian Jing } 133520848903SChaotian Jing 133620848903SChaotian Jing return IRQ_HANDLED; 133720848903SChaotian Jing } 133820848903SChaotian Jing 133920848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 134020848903SChaotian Jing { 134120848903SChaotian Jing u32 val; 134239add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 134320848903SChaotian Jing 134420848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 134520848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 134620848903SChaotian Jing 134720848903SChaotian Jing /* Reset */ 134820848903SChaotian Jing msdc_reset_hw(host); 134920848903SChaotian Jing 135020848903SChaotian Jing /* Disable card detection */ 135120848903SChaotian Jing sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 135220848903SChaotian Jing 135320848903SChaotian Jing /* Disable and clear all interrupts */ 135420848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 135520848903SChaotian Jing val = readl(host->base + MSDC_INT); 135620848903SChaotian Jing writel(val, host->base + MSDC_INT); 135720848903SChaotian Jing 135839add252SChaotian Jing writel(0, host->base + tune_reg); 135920848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 13606397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 13616397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 136220848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 13632fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 13646397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1365d9dcbfc8SChaotian Jing 1366d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1367d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1368d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1369d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1370d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1371d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1372d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1373d9dcbfc8SChaotian Jing } 1374d9dcbfc8SChaotian Jing 1375acde28c4SChaotian Jing if (host->dev_comp->busy_check) 1376acde28c4SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1377d9dcbfc8SChaotian Jing 13782fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 13792fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 13802fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1381d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1382d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1383d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1384d9dcbfc8SChaotian Jing } else { 13852fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 13862fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 13872fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 13882fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1389d9dcbfc8SChaotian Jing } 13902fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 13912fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 13922fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 13932fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 13942fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 13952fea5819SChaotian Jing } 13962fea5819SChaotian Jing 13972a9bde19SChaotian Jing if (host->dev_comp->support_64g) 13982a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 13992a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 14002fea5819SChaotian Jing if (host->dev_comp->data_tune) { 14012fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 14022fea5819SChaotian Jing MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); 14032fea5819SChaotian Jing } else { 14042fea5819SChaotian Jing /* choose clock tune */ 14052fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL); 14062fea5819SChaotian Jing } 14076397b7f5SChaotian Jing 140820848903SChaotian Jing /* Configure to enable SDIO mode. 140920848903SChaotian Jing * it's must otherwise sdio cmd5 failed 141020848903SChaotian Jing */ 141120848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 141220848903SChaotian Jing 141320848903SChaotian Jing /* disable detect SDIO device interrupt function */ 141420848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 141520848903SChaotian Jing 141620848903SChaotian Jing /* Configure to default data timeout */ 141720848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 141820848903SChaotian Jing 141986beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 142039add252SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 14212fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 14222fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 142320848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 142420848903SChaotian Jing } 142520848903SChaotian Jing 142620848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 142720848903SChaotian Jing { 142820848903SChaotian Jing u32 val; 142920848903SChaotian Jing /* Disable and clear all interrupts */ 143020848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 143120848903SChaotian Jing 143220848903SChaotian Jing val = readl(host->base + MSDC_INT); 143320848903SChaotian Jing writel(val, host->base + MSDC_INT); 143420848903SChaotian Jing } 143520848903SChaotian Jing 143620848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 143720848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 143820848903SChaotian Jing { 143920848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 144020848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 14412a9bde19SChaotian Jing dma_addr_t dma_addr; 144220848903SChaotian Jing int i; 144320848903SChaotian Jing 144462b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 144520848903SChaotian Jing 14462a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 144720848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 144862b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 144962b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 145062b0d27aSChaotian Jing */ 14512a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 14522a9bde19SChaotian Jing if (host->dev_comp->support_64g) 14532a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 14542a9bde19SChaotian Jing 14552a9bde19SChaotian Jing dma_addr = dma->bd_addr; 14562a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 14572a9bde19SChaotian Jing if (host->dev_comp->support_64g) 14582a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 14592a9bde19SChaotian Jing 146020848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 14612a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 14622a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 14632a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 14642a9bde19SChaotian Jing if (host->dev_comp->support_64g) 14652a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 14662a9bde19SChaotian Jing } 146720848903SChaotian Jing } 146820848903SChaotian Jing 146920848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 147020848903SChaotian Jing { 147120848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 147220848903SChaotian Jing int ret; 147320848903SChaotian Jing 147420848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 147520848903SChaotian Jing 147620848903SChaotian Jing /* Suspend/Resume will do power off/on */ 147720848903SChaotian Jing switch (ios->power_mode) { 147820848903SChaotian Jing case MMC_POWER_UP: 147920848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 14806397b7f5SChaotian Jing msdc_init_hw(host); 148120848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 148220848903SChaotian Jing ios->vdd); 148320848903SChaotian Jing if (ret) { 148420848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1485567979fbSUlf Hansson return; 148620848903SChaotian Jing } 148720848903SChaotian Jing } 148820848903SChaotian Jing break; 148920848903SChaotian Jing case MMC_POWER_ON: 149020848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 149120848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 149220848903SChaotian Jing if (ret) 149320848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 149420848903SChaotian Jing else 149520848903SChaotian Jing host->vqmmc_enabled = true; 149620848903SChaotian Jing } 149720848903SChaotian Jing break; 149820848903SChaotian Jing case MMC_POWER_OFF: 149920848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 150020848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 150120848903SChaotian Jing 150220848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 150320848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 150420848903SChaotian Jing host->vqmmc_enabled = false; 150520848903SChaotian Jing } 150620848903SChaotian Jing break; 150720848903SChaotian Jing default: 150820848903SChaotian Jing break; 150920848903SChaotian Jing } 151020848903SChaotian Jing 15116e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 15126e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 151320848903SChaotian Jing } 151420848903SChaotian Jing 15156397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 15166397b7f5SChaotian Jing { 15176397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 15186397b7f5SChaotian Jing return delay & (1 << bit); 15196397b7f5SChaotian Jing } 15206397b7f5SChaotian Jing 15216397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 15226397b7f5SChaotian Jing { 15236397b7f5SChaotian Jing int i; 15246397b7f5SChaotian Jing 15256397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 15266397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 15276397b7f5SChaotian Jing return i; 15286397b7f5SChaotian Jing } 15296397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 15306397b7f5SChaotian Jing } 15316397b7f5SChaotian Jing 15326397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 15336397b7f5SChaotian Jing { 15346397b7f5SChaotian Jing int start = 0, len = 0; 15356397b7f5SChaotian Jing int start_final = 0, len_final = 0; 15366397b7f5SChaotian Jing u8 final_phase = 0xff; 153762d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 15386397b7f5SChaotian Jing 15396397b7f5SChaotian Jing if (delay == 0) { 15406397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 15416397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 15426397b7f5SChaotian Jing return delay_phase; 15436397b7f5SChaotian Jing } 15446397b7f5SChaotian Jing 15456397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 15466397b7f5SChaotian Jing len = get_delay_len(delay, start); 15476397b7f5SChaotian Jing if (len_final < len) { 15486397b7f5SChaotian Jing start_final = start; 15496397b7f5SChaotian Jing len_final = len; 15506397b7f5SChaotian Jing } 15516397b7f5SChaotian Jing start += len ? len : 1; 15521ede5cb8Syong mao if (len >= 12 && start_final < 4) 15536397b7f5SChaotian Jing break; 15546397b7f5SChaotian Jing } 15556397b7f5SChaotian Jing 15566397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 15576397b7f5SChaotian Jing if (start_final == 0) 15586397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 15596397b7f5SChaotian Jing else 15606397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 15616397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 15626397b7f5SChaotian Jing delay, len_final, final_phase); 15636397b7f5SChaotian Jing 15646397b7f5SChaotian Jing delay_phase.maxlen = len_final; 15656397b7f5SChaotian Jing delay_phase.start = start_final; 15666397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 15676397b7f5SChaotian Jing return delay_phase; 15686397b7f5SChaotian Jing } 15696397b7f5SChaotian Jing 15706397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 15716397b7f5SChaotian Jing { 15726397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 15736397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1574ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 15751ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 15766397b7f5SChaotian Jing u8 final_delay, final_maxlen; 15771ede5cb8Syong mao u32 internal_delay = 0; 157839add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 15796397b7f5SChaotian Jing int cmd_err; 15801ede5cb8Syong mao int i, j; 15811ede5cb8Syong mao 15821ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 15831ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 158439add252SChaotian Jing sdr_set_field(host->base + tune_reg, 15851ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 15861ede5cb8Syong mao host->hs200_cmd_int_delay); 15876397b7f5SChaotian Jing 15886397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 15896397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 159039add252SChaotian Jing sdr_set_field(host->base + tune_reg, 15916397b7f5SChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 15921ede5cb8Syong mao /* 15931ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 15941ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 15951ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 15961ede5cb8Syong mao */ 15971ede5cb8Syong mao for (j = 0; j < 3; j++) { 15986397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 15991ede5cb8Syong mao if (!cmd_err) { 16006397b7f5SChaotian Jing rise_delay |= (1 << i); 16011ede5cb8Syong mao } else { 16021ede5cb8Syong mao rise_delay &= ~(1 << i); 16031ede5cb8Syong mao break; 16041ede5cb8Syong mao } 16051ede5cb8Syong mao } 16066397b7f5SChaotian Jing } 1607ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1608ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 16096b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 16106b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1611ae9c657eSChaotian Jing goto skip_fall; 16126397b7f5SChaotian Jing 16136397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 16146397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 161539add252SChaotian Jing sdr_set_field(host->base + tune_reg, 16166397b7f5SChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 16171ede5cb8Syong mao /* 16181ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 16191ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 16201ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 16211ede5cb8Syong mao */ 16221ede5cb8Syong mao for (j = 0; j < 3; j++) { 16236397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 16241ede5cb8Syong mao if (!cmd_err) { 16256397b7f5SChaotian Jing fall_delay |= (1 << i); 16261ede5cb8Syong mao } else { 16271ede5cb8Syong mao fall_delay &= ~(1 << i); 16281ede5cb8Syong mao break; 16291ede5cb8Syong mao } 16301ede5cb8Syong mao } 16316397b7f5SChaotian Jing } 16326397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 16336397b7f5SChaotian Jing 1634ae9c657eSChaotian Jing skip_fall: 16356397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 16361ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 16371ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 16386397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 16396397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 164039add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 16416397b7f5SChaotian Jing final_rise_delay.final_phase); 16426397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 16436397b7f5SChaotian Jing } else { 16446397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 164539add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 16466397b7f5SChaotian Jing final_fall_delay.final_phase); 16476397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 16486397b7f5SChaotian Jing } 16492fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 16501ede5cb8Syong mao goto skip_internal; 16516397b7f5SChaotian Jing 16521ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 165339add252SChaotian Jing sdr_set_field(host->base + tune_reg, 16541ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 16551ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 16561ede5cb8Syong mao if (!cmd_err) 16571ede5cb8Syong mao internal_delay |= (1 << i); 16581ede5cb8Syong mao } 16591ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 16601ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 166139add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 16621ede5cb8Syong mao internal_delay_phase.final_phase); 16631ede5cb8Syong mao skip_internal: 16641ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 16651ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 16661ede5cb8Syong mao } 16671ede5cb8Syong mao 16681ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 16691ede5cb8Syong mao { 16701ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 16711ede5cb8Syong mao u32 cmd_delay = 0; 16721ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 16731ede5cb8Syong mao u8 final_delay; 16741ede5cb8Syong mao int cmd_err; 16751ede5cb8Syong mao int i, j; 16761ede5cb8Syong mao 16771ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 16781ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 16791ede5cb8Syong mao 16801ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 16811ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 16821ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 16831ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 16841ede5cb8Syong mao host->hs200_cmd_int_delay); 16851ede5cb8Syong mao 16861ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 16871ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 16881ede5cb8Syong mao else 16891ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 16901ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 16911ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 16921ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 16931ede5cb8Syong mao /* 16941ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 16951ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 16961ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 16971ede5cb8Syong mao */ 16981ede5cb8Syong mao for (j = 0; j < 3; j++) { 16991ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 17001ede5cb8Syong mao if (!cmd_err) { 17011ede5cb8Syong mao cmd_delay |= (1 << i); 17021ede5cb8Syong mao } else { 17031ede5cb8Syong mao cmd_delay &= ~(1 << i); 17041ede5cb8Syong mao break; 17051ede5cb8Syong mao } 17061ede5cb8Syong mao } 17071ede5cb8Syong mao } 17081ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 17091ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 17101ede5cb8Syong mao final_cmd_delay.final_phase); 17111ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 17121ede5cb8Syong mao 17131ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 17146397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 17156397b7f5SChaotian Jing } 17166397b7f5SChaotian Jing 17176397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 17186397b7f5SChaotian Jing { 17196397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 17206397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1721ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 17226397b7f5SChaotian Jing u8 final_delay, final_maxlen; 172339add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 17246397b7f5SChaotian Jing int i, ret; 17256397b7f5SChaotian Jing 1726d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1727d17bb71cSChaotian Jing host->latch_ck); 17286397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 17296397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 17306397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 173139add252SChaotian Jing sdr_set_field(host->base + tune_reg, 17326397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 17336397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 17346397b7f5SChaotian Jing if (!ret) 17356397b7f5SChaotian Jing rise_delay |= (1 << i); 17366397b7f5SChaotian Jing } 1737ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1738ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 17391ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 1740ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1741ae9c657eSChaotian Jing goto skip_fall; 17426397b7f5SChaotian Jing 17436397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 17446397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 17456397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 174639add252SChaotian Jing sdr_set_field(host->base + tune_reg, 17476397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 17486397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 17496397b7f5SChaotian Jing if (!ret) 17506397b7f5SChaotian Jing fall_delay |= (1 << i); 17516397b7f5SChaotian Jing } 17526397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 17536397b7f5SChaotian Jing 1754ae9c657eSChaotian Jing skip_fall: 17556397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 17566397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 17576397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 17586397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 175939add252SChaotian Jing sdr_set_field(host->base + tune_reg, 17606397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 17616397b7f5SChaotian Jing final_rise_delay.final_phase); 17626397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 17636397b7f5SChaotian Jing } else { 17646397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 17656397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 176639add252SChaotian Jing sdr_set_field(host->base + tune_reg, 17676397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 17686397b7f5SChaotian Jing final_fall_delay.final_phase); 17696397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 17706397b7f5SChaotian Jing } 17716397b7f5SChaotian Jing 17721ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 17736397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 17746397b7f5SChaotian Jing } 17756397b7f5SChaotian Jing 177686601d0eSChaotian Jing /* 177786601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 177886601d0eSChaotian Jing * together, which can save the tuning time. 177986601d0eSChaotian Jing */ 178086601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 178186601d0eSChaotian Jing { 178286601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 178386601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 178486601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 178586601d0eSChaotian Jing u8 final_delay, final_maxlen; 178686601d0eSChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 178786601d0eSChaotian Jing int i, ret; 178886601d0eSChaotian Jing 178986601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 179086601d0eSChaotian Jing host->latch_ck); 179186601d0eSChaotian Jing 179286601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 179386601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 179486601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 179586601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 179686601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 179786601d0eSChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 179886601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 179986601d0eSChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 180086601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 180186601d0eSChaotian Jing if (!ret) 180286601d0eSChaotian Jing rise_delay |= (1 << i); 180386601d0eSChaotian Jing } 180486601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 180586601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 180686601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 180786601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 180886601d0eSChaotian Jing goto skip_fall; 180986601d0eSChaotian Jing 181086601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 181186601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 181286601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 181386601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 181486601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 181586601d0eSChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 181686601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 181786601d0eSChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 181886601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 181986601d0eSChaotian Jing if (!ret) 182086601d0eSChaotian Jing fall_delay |= (1 << i); 182186601d0eSChaotian Jing } 182286601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 182386601d0eSChaotian Jing 182486601d0eSChaotian Jing skip_fall: 182586601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 182686601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 182786601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 182886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 182986601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 183086601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 183186601d0eSChaotian Jing final_rise_delay.final_phase); 183286601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 183386601d0eSChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 183486601d0eSChaotian Jing final_rise_delay.final_phase); 183586601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 183686601d0eSChaotian Jing } else { 183786601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 183886601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 183986601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 184086601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 184186601d0eSChaotian Jing final_fall_delay.final_phase); 184286601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 184386601d0eSChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 184486601d0eSChaotian Jing final_fall_delay.final_phase); 184586601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 184686601d0eSChaotian Jing } 184786601d0eSChaotian Jing 184886601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 184986601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 185086601d0eSChaotian Jing } 185186601d0eSChaotian Jing 18526397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 18536397b7f5SChaotian Jing { 18546397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 18556397b7f5SChaotian Jing int ret; 185639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 18576397b7f5SChaotian Jing 185886601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 185986601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 186086601d0eSChaotian Jing if (host->hs400_mode) { 186186601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 186286601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 186386601d0eSChaotian Jing sdr_set_field(host->base + tune_reg, 186486601d0eSChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 0); 186586601d0eSChaotian Jing } 186686601d0eSChaotian Jing goto tune_done; 186786601d0eSChaotian Jing } 18687f3d5852SChaotian Jing if (host->hs400_mode && 18697f3d5852SChaotian Jing host->dev_comp->hs400_tune) 18701ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 18711ede5cb8Syong mao else 18726397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 18736397b7f5SChaotian Jing if (ret == -EIO) { 18746397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 1875567979fbSUlf Hansson return ret; 18766397b7f5SChaotian Jing } 18775462ff39SChaotian Jing if (host->hs400_mode == false) { 18786397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 18796397b7f5SChaotian Jing if (ret == -EIO) 18806397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 18815462ff39SChaotian Jing } 18826397b7f5SChaotian Jing 188386601d0eSChaotian Jing tune_done: 188486beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 188539add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 18861ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 18876397b7f5SChaotian Jing return ret; 18886397b7f5SChaotian Jing } 18896397b7f5SChaotian Jing 18906397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 18916397b7f5SChaotian Jing { 18926397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 18935462ff39SChaotian Jing host->hs400_mode = true; 18946397b7f5SChaotian Jing 18956397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 18962fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 18972fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 1898c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 1899c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 1900c8609b22SChaotian Jing 19016397b7f5SChaotian Jing return 0; 19026397b7f5SChaotian Jing } 19036397b7f5SChaotian Jing 1904c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 1905c9b5061eSChaotian Jing { 1906c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 1907c9b5061eSChaotian Jing 1908c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 1909c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 1910c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 1911c9b5061eSChaotian Jing } 1912c9b5061eSChaotian Jing 1913be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 191420848903SChaotian Jing .post_req = msdc_post_req, 191520848903SChaotian Jing .pre_req = msdc_pre_req, 191620848903SChaotian Jing .request = msdc_ops_request, 191720848903SChaotian Jing .set_ios = msdc_ops_set_ios, 19188d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 1919c7b16deeSChaotian Jing .get_cd = mmc_gpio_get_cd, 192020848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 192120848903SChaotian Jing .card_busy = msdc_card_busy, 19226397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 19236397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1924c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 192520848903SChaotian Jing }; 192620848903SChaotian Jing 19271ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 19281ede5cb8Syong mao struct msdc_host *host) 19291ede5cb8Syong mao { 1930d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 1931d17bb71cSChaotian Jing &host->latch_ck); 1932d17bb71cSChaotian Jing 19331ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 19341ede5cb8Syong mao &host->hs400_ds_delay); 19351ede5cb8Syong mao 19361ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 19371ede5cb8Syong mao &host->hs200_cmd_int_delay); 19381ede5cb8Syong mao 19391ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 19401ede5cb8Syong mao &host->hs400_cmd_int_delay); 19411ede5cb8Syong mao 19421ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 19431ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 19441ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 19451ede5cb8Syong mao else 19461ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 19471ede5cb8Syong mao } 19481ede5cb8Syong mao 194920848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 195020848903SChaotian Jing { 195120848903SChaotian Jing struct mmc_host *mmc; 195220848903SChaotian Jing struct msdc_host *host; 195320848903SChaotian Jing struct resource *res; 195420848903SChaotian Jing int ret; 195520848903SChaotian Jing 195620848903SChaotian Jing if (!pdev->dev.of_node) { 195720848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 195820848903SChaotian Jing return -EINVAL; 195920848903SChaotian Jing } 1960762d491aSChaotian Jing 196120848903SChaotian Jing /* Allocate MMC host for this device */ 196220848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 196320848903SChaotian Jing if (!mmc) 196420848903SChaotian Jing return -ENOMEM; 196520848903SChaotian Jing 196620848903SChaotian Jing host = mmc_priv(mmc); 196720848903SChaotian Jing ret = mmc_of_parse(mmc); 196820848903SChaotian Jing if (ret) 196920848903SChaotian Jing goto host_free; 197020848903SChaotian Jing 197120848903SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 197220848903SChaotian Jing host->base = devm_ioremap_resource(&pdev->dev, res); 197320848903SChaotian Jing if (IS_ERR(host->base)) { 197420848903SChaotian Jing ret = PTR_ERR(host->base); 197520848903SChaotian Jing goto host_free; 197620848903SChaotian Jing } 197720848903SChaotian Jing 197820848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 19792f98ef63SWolfram Sang if (ret) 198020848903SChaotian Jing goto host_free; 198120848903SChaotian Jing 198220848903SChaotian Jing host->src_clk = devm_clk_get(&pdev->dev, "source"); 198320848903SChaotian Jing if (IS_ERR(host->src_clk)) { 198420848903SChaotian Jing ret = PTR_ERR(host->src_clk); 198520848903SChaotian Jing goto host_free; 198620848903SChaotian Jing } 198720848903SChaotian Jing 198820848903SChaotian Jing host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 198920848903SChaotian Jing if (IS_ERR(host->h_clk)) { 199020848903SChaotian Jing ret = PTR_ERR(host->h_clk); 199120848903SChaotian Jing goto host_free; 199220848903SChaotian Jing } 199320848903SChaotian Jing 1994258bac4aSChaotian Jing host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 1995258bac4aSChaotian Jing if (IS_ERR(host->bus_clk)) 1996258bac4aSChaotian Jing host->bus_clk = NULL; 19973c1a8844SChaotian Jing /*source clock control gate is optional clock*/ 19983c1a8844SChaotian Jing host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 19993c1a8844SChaotian Jing if (IS_ERR(host->src_clk_cg)) 20003c1a8844SChaotian Jing host->src_clk_cg = NULL; 20013c1a8844SChaotian Jing 200220848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 200320848903SChaotian Jing if (host->irq < 0) { 200420848903SChaotian Jing ret = -EINVAL; 200520848903SChaotian Jing goto host_free; 200620848903SChaotian Jing } 200720848903SChaotian Jing 200820848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 200920848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 201020848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 201120848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 201220848903SChaotian Jing goto host_free; 201320848903SChaotian Jing } 201420848903SChaotian Jing 201520848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 201620848903SChaotian Jing if (IS_ERR(host->pins_default)) { 201720848903SChaotian Jing ret = PTR_ERR(host->pins_default); 201820848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 201920848903SChaotian Jing goto host_free; 202020848903SChaotian Jing } 202120848903SChaotian Jing 202220848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 202320848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 202420848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 202520848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 202620848903SChaotian Jing goto host_free; 202720848903SChaotian Jing } 202820848903SChaotian Jing 20291ede5cb8Syong mao msdc_of_property_parse(pdev, host); 20306397b7f5SChaotian Jing 203120848903SChaotian Jing host->dev = &pdev->dev; 2032909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 203320848903SChaotian Jing host->mmc = mmc; 203420848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 203520848903SChaotian Jing /* Set host parameters to mmc */ 203620848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2037762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 203840ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2039762d491aSChaotian Jing else 2040762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 204120848903SChaotian Jing 204220848903SChaotian Jing mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 204320848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 204420848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 204520848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 204620848903SChaotian Jing mmc->max_blk_size = 2048; 204720848903SChaotian Jing mmc->max_req_size = 512 * 1024; 204820848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 20492a9bde19SChaotian Jing if (host->dev_comp->support_64g) 20502a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 20512a9bde19SChaotian Jing else 205220848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 205320848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 205420848903SChaotian Jing 205520848903SChaotian Jing host->timeout_clks = 3 * 1048576; 205620848903SChaotian Jing host->dma.gpd = dma_alloc_coherent(&pdev->dev, 205762b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 205820848903SChaotian Jing &host->dma.gpd_addr, GFP_KERNEL); 205920848903SChaotian Jing host->dma.bd = dma_alloc_coherent(&pdev->dev, 206020848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 206120848903SChaotian Jing &host->dma.bd_addr, GFP_KERNEL); 206220848903SChaotian Jing if (!host->dma.gpd || !host->dma.bd) { 206320848903SChaotian Jing ret = -ENOMEM; 206420848903SChaotian Jing goto release_mem; 206520848903SChaotian Jing } 206620848903SChaotian Jing msdc_init_gpd_bd(host, &host->dma); 206720848903SChaotian Jing INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 206820848903SChaotian Jing spin_lock_init(&host->lock); 206920848903SChaotian Jing 207020848903SChaotian Jing platform_set_drvdata(pdev, mmc); 207120848903SChaotian Jing msdc_ungate_clock(host); 207220848903SChaotian Jing msdc_init_hw(host); 207320848903SChaotian Jing 207420848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 207520848903SChaotian Jing IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 207620848903SChaotian Jing if (ret) 207720848903SChaotian Jing goto release; 207820848903SChaotian Jing 20794b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 20804b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 20814b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 20824b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 208320848903SChaotian Jing ret = mmc_add_host(mmc); 20844b8a43e9SChaotian Jing 208520848903SChaotian Jing if (ret) 20864b8a43e9SChaotian Jing goto end; 208720848903SChaotian Jing 208820848903SChaotian Jing return 0; 20894b8a43e9SChaotian Jing end: 20904b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 209120848903SChaotian Jing release: 209220848903SChaotian Jing platform_set_drvdata(pdev, NULL); 209320848903SChaotian Jing msdc_deinit_hw(host); 209420848903SChaotian Jing msdc_gate_clock(host); 209520848903SChaotian Jing release_mem: 209620848903SChaotian Jing if (host->dma.gpd) 209720848903SChaotian Jing dma_free_coherent(&pdev->dev, 209862b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 209920848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 210020848903SChaotian Jing if (host->dma.bd) 210120848903SChaotian Jing dma_free_coherent(&pdev->dev, 210220848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 210320848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 210420848903SChaotian Jing host_free: 210520848903SChaotian Jing mmc_free_host(mmc); 210620848903SChaotian Jing 210720848903SChaotian Jing return ret; 210820848903SChaotian Jing } 210920848903SChaotian Jing 211020848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 211120848903SChaotian Jing { 211220848903SChaotian Jing struct mmc_host *mmc; 211320848903SChaotian Jing struct msdc_host *host; 211420848903SChaotian Jing 211520848903SChaotian Jing mmc = platform_get_drvdata(pdev); 211620848903SChaotian Jing host = mmc_priv(mmc); 211720848903SChaotian Jing 21184b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 21194b8a43e9SChaotian Jing 212020848903SChaotian Jing platform_set_drvdata(pdev, NULL); 212120848903SChaotian Jing mmc_remove_host(host->mmc); 212220848903SChaotian Jing msdc_deinit_hw(host); 212320848903SChaotian Jing msdc_gate_clock(host); 212420848903SChaotian Jing 21254b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 21264b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 212720848903SChaotian Jing dma_free_coherent(&pdev->dev, 212816f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 212920848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 213020848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 213120848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 213220848903SChaotian Jing 213320848903SChaotian Jing mmc_free_host(host->mmc); 213420848903SChaotian Jing 213520848903SChaotian Jing return 0; 213620848903SChaotian Jing } 213720848903SChaotian Jing 21384b8a43e9SChaotian Jing #ifdef CONFIG_PM 21394b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 21404b8a43e9SChaotian Jing { 214139add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 214239add252SChaotian Jing 21434b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 21444b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 21454b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 214639add252SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 21474b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 21484b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 21492fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 21506397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 21511ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 21526397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2153c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2154d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 21554b8a43e9SChaotian Jing } 21564b8a43e9SChaotian Jing 21574b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 21584b8a43e9SChaotian Jing { 215939add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 216039add252SChaotian Jing 21614b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 21624b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 21634b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 216439add252SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 21654b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 21664b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 21672fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 21686397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 21691ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 21706397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2171c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2172d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 21734b8a43e9SChaotian Jing } 21744b8a43e9SChaotian Jing 21754b8a43e9SChaotian Jing static int msdc_runtime_suspend(struct device *dev) 21764b8a43e9SChaotian Jing { 21774b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 21784b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 21794b8a43e9SChaotian Jing 21804b8a43e9SChaotian Jing msdc_save_reg(host); 21814b8a43e9SChaotian Jing msdc_gate_clock(host); 21824b8a43e9SChaotian Jing return 0; 21834b8a43e9SChaotian Jing } 21844b8a43e9SChaotian Jing 21854b8a43e9SChaotian Jing static int msdc_runtime_resume(struct device *dev) 21864b8a43e9SChaotian Jing { 21874b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 21884b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 21894b8a43e9SChaotian Jing 21904b8a43e9SChaotian Jing msdc_ungate_clock(host); 21914b8a43e9SChaotian Jing msdc_restore_reg(host); 21924b8a43e9SChaotian Jing return 0; 21934b8a43e9SChaotian Jing } 21944b8a43e9SChaotian Jing #endif 21954b8a43e9SChaotian Jing 21964b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 21974b8a43e9SChaotian Jing SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 21984b8a43e9SChaotian Jing pm_runtime_force_resume) 21994b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 22004b8a43e9SChaotian Jing }; 22014b8a43e9SChaotian Jing 220220848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 220320848903SChaotian Jing .probe = msdc_drv_probe, 220420848903SChaotian Jing .remove = msdc_drv_remove, 220520848903SChaotian Jing .driver = { 220620848903SChaotian Jing .name = "mtk-msdc", 220720848903SChaotian Jing .of_match_table = msdc_of_ids, 22084b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 220920848903SChaotian Jing }, 221020848903SChaotian Jing }; 221120848903SChaotian Jing 221220848903SChaotian Jing module_platform_driver(mt_msdc_driver); 221320848903SChaotian Jing MODULE_LICENSE("GPL v2"); 221420848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2215