11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 220848903SChaotian Jing /* 3*527f36f5SAxe Yang * Copyright (c) 2014-2015, 2022 MediaTek Inc. 420848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 520848903SChaotian Jing */ 620848903SChaotian Jing 720848903SChaotian Jing #include <linux/module.h> 84fe54318SAngeloGioacchino Del Regno #include <linux/bitops.h> 920848903SChaotian Jing #include <linux/clk.h> 1020848903SChaotian Jing #include <linux/delay.h> 1120848903SChaotian Jing #include <linux/dma-mapping.h> 1243e5fee3SDerong Liu #include <linux/iopoll.h> 1320848903SChaotian Jing #include <linux/ioport.h> 1420848903SChaotian Jing #include <linux/irq.h> 1520848903SChaotian Jing #include <linux/of_address.h> 16909b3456SRyder Lee #include <linux/of_device.h> 1720848903SChaotian Jing #include <linux/of_irq.h> 1820848903SChaotian Jing #include <linux/of_gpio.h> 1920848903SChaotian Jing #include <linux/pinctrl/consumer.h> 2020848903SChaotian Jing #include <linux/platform_device.h> 214b8a43e9SChaotian Jing #include <linux/pm.h> 224b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 23*527f36f5SAxe Yang #include <linux/pm_wakeirq.h> 2420848903SChaotian Jing #include <linux/regulator/consumer.h> 256397b7f5SChaotian Jing #include <linux/slab.h> 2620848903SChaotian Jing #include <linux/spinlock.h> 27b8789ec4SUlf Hansson #include <linux/interrupt.h> 28855d388dSWenbin Mei #include <linux/reset.h> 2920848903SChaotian Jing 3020848903SChaotian Jing #include <linux/mmc/card.h> 3120848903SChaotian Jing #include <linux/mmc/core.h> 3220848903SChaotian Jing #include <linux/mmc/host.h> 3320848903SChaotian Jing #include <linux/mmc/mmc.h> 3420848903SChaotian Jing #include <linux/mmc/sd.h> 3520848903SChaotian Jing #include <linux/mmc/sdio.h> 368d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 3720848903SChaotian Jing 3888bd652bSChun-Hung Wu #include "cqhci.h" 3988bd652bSChun-Hung Wu 4020848903SChaotian Jing #define MAX_BD_NUM 1024 41f5eccd94SWenbin Mei #define MSDC_NR_CLOCKS 3 4220848903SChaotian Jing 4320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4420848903SChaotian Jing /* Common Definition */ 4520848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4620848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4720848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4820848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4920848903SChaotian Jing 5020848903SChaotian Jing #define MSDC_BURST_64B 0x6 5120848903SChaotian Jing 5220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5320848903SChaotian Jing /* Register Offset */ 5420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5520848903SChaotian Jing #define MSDC_CFG 0x0 5620848903SChaotian Jing #define MSDC_IOCON 0x04 5720848903SChaotian Jing #define MSDC_PS 0x08 5820848903SChaotian Jing #define MSDC_INT 0x0c 5920848903SChaotian Jing #define MSDC_INTEN 0x10 6020848903SChaotian Jing #define MSDC_FIFOCS 0x14 6120848903SChaotian Jing #define SDC_CFG 0x30 6220848903SChaotian Jing #define SDC_CMD 0x34 6320848903SChaotian Jing #define SDC_ARG 0x38 6420848903SChaotian Jing #define SDC_STS 0x3c 6520848903SChaotian Jing #define SDC_RESP0 0x40 6620848903SChaotian Jing #define SDC_RESP1 0x44 6720848903SChaotian Jing #define SDC_RESP2 0x48 6820848903SChaotian Jing #define SDC_RESP3 0x4c 6920848903SChaotian Jing #define SDC_BLK_NUM 0x50 70d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 71c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 7220848903SChaotian Jing #define SDC_ACMD_RESP 0x80 732a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 7420848903SChaotian Jing #define MSDC_DMA_SA 0x90 7520848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7620848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7720848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7820848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 792fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 8020848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 8139add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 826397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 831ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 8413b4e1e9SWenbin Mei #define EMMC51_CFG0 0x204 856397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 8613b4e1e9SWenbin Mei #define EMMC50_CFG1 0x20c 87c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 88d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 8913b4e1e9SWenbin Mei #define CQHCI_SETTING 0x7fc 9020848903SChaotian Jing 9120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 92a2e6d1f6SChaotian Jing /* Top Pad Register Offset */ 93a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 94a2e6d1f6SChaotian Jing #define EMMC_TOP_CONTROL 0x00 95a2e6d1f6SChaotian Jing #define EMMC_TOP_CMD 0x04 96a2e6d1f6SChaotian Jing #define EMMC50_PAD_DS_TUNE 0x0c 97a2e6d1f6SChaotian Jing 98a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 9920848903SChaotian Jing /* Register Mask */ 10020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 10120848903SChaotian Jing 10220848903SChaotian Jing /* MSDC_CFG mask */ 1034fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_MODE BIT(0) /* RW */ 1044fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKPDN BIT(1) /* RW */ 1054fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_RST BIT(2) /* RW */ 1064fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_PIO BIT(3) /* RW */ 1074fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 1084fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 1094fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_BV18PSS BIT(6) /* R */ 1104fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKSTB BIT(7) /* R */ 1114fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 1124fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 1134fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 1144fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 1154fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 1164fe54318SAngeloGioacchino Del Regno #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 11720848903SChaotian Jing 11820848903SChaotian Jing /* MSDC_IOCON mask */ 1194fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 1204fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_RSPL BIT(1) /* RW */ 1214fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DSPL BIT(2) /* RW */ 1224fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 1234fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 1244fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 1254fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 1264fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 1274fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 1284fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 1294fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 1304fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 1314fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 1324fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 1334fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 1344fe54318SAngeloGioacchino Del Regno #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 13520848903SChaotian Jing 13620848903SChaotian Jing /* MSDC_PS mask */ 1374fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDEN BIT(0) /* RW */ 1384fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDSTS BIT(1) /* R */ 1394fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 1404fe54318SAngeloGioacchino Del Regno #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 1414fe54318SAngeloGioacchino Del Regno #define MSDC_PS_DATA1 BIT(17) /* R */ 1424fe54318SAngeloGioacchino Del Regno #define MSDC_PS_CMD BIT(24) /* R */ 1434fe54318SAngeloGioacchino Del Regno #define MSDC_PS_WP BIT(31) /* R */ 14420848903SChaotian Jing 14520848903SChaotian Jing /* MSDC_INT mask */ 1464fe54318SAngeloGioacchino Del Regno #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 1474fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CDSC BIT(1) /* W1C */ 1484fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 1494fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 1504fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 1514fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 1524fe54318SAngeloGioacchino Del Regno #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 1534fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 1544fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 1554fe54318SAngeloGioacchino Del Regno #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 1564fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CSTA BIT(11) /* R */ 1574fe54318SAngeloGioacchino Del Regno #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 1584fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 1594fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DATTMO BIT(14) /* W1C */ 1604fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 1614fe54318SAngeloGioacchino Del Regno #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 1624fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 1634fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 1644fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 1654fe54318SAngeloGioacchino Del Regno #define MSDC_INT_CMDQ BIT(28) /* W1C */ 16620848903SChaotian Jing 16720848903SChaotian Jing /* MSDC_INTEN mask */ 1684fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 1694fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CDSC BIT(1) /* RW */ 1704fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 1714fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 1724fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 1734fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 1744fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 1754fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 1764fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 1774fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 1784fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_CSTA BIT(11) /* RW */ 1794fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 1804fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 1814fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 1824fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 1834fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 1844fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 1854fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 1864fe54318SAngeloGioacchino Del Regno #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 18720848903SChaotian Jing 18820848903SChaotian Jing /* MSDC_FIFOCS mask */ 1894fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 1904fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 1914fe54318SAngeloGioacchino Del Regno #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 19220848903SChaotian Jing 19320848903SChaotian Jing /* SDC_CFG mask */ 1944fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 1954fe54318SAngeloGioacchino Del Regno #define SDC_CFG_INSWKUP BIT(1) /* RW */ 1964fe54318SAngeloGioacchino Del Regno #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 1974fe54318SAngeloGioacchino Del Regno #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 1984fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIO BIT(19) /* RW */ 1994fe54318SAngeloGioacchino Del Regno #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 2004fe54318SAngeloGioacchino Del Regno #define SDC_CFG_INTATGAP BIT(21) /* RW */ 2014fe54318SAngeloGioacchino Del Regno #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 20220848903SChaotian Jing 20320848903SChaotian Jing /* SDC_STS mask */ 2044fe54318SAngeloGioacchino Del Regno #define SDC_STS_SDCBUSY BIT(0) /* RW */ 2054fe54318SAngeloGioacchino Del Regno #define SDC_STS_CMDBUSY BIT(1) /* RW */ 2064fe54318SAngeloGioacchino Del Regno #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 20720848903SChaotian Jing 2084fe54318SAngeloGioacchino Del Regno #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 209d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 2104fe54318SAngeloGioacchino Del Regno #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 211d9dcbfc8SChaotian Jing 2122a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2134fe54318SAngeloGioacchino Del Regno #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 2142a9bde19SChaotian Jing 21520848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 2164fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_START BIT(0) /* W */ 2174fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 2184fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 2194fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 2204fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 2214fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 22220848903SChaotian Jing 22320848903SChaotian Jing /* MSDC_DMA_CFG mask */ 2244fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_STS BIT(0) /* R */ 2254fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 2264fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 2274fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 2284fe54318SAngeloGioacchino Del Regno #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 22920848903SChaotian Jing 23020848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 2314fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 2324fe54318SAngeloGioacchino Del Regno #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 2334fe54318SAngeloGioacchino Del Regno #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 2344fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 2354fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 2364fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 2374fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 2384fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 2394fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 2404fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 2414fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 2424fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 24320848903SChaotian Jing 2444fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 2454fe54318SAngeloGioacchino Del Regno #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 2464fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 247d9dcbfc8SChaotian Jing 2484fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 2494fe54318SAngeloGioacchino Del Regno #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 2504fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 2514fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 2524fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 2534fe54318SAngeloGioacchino Del Regno #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 2542fea5819SChaotian Jing 2554fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 2564fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 2574fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 2584fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 2594fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 2604fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 2614fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 2624fe54318SAngeloGioacchino Del Regno #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 2636397b7f5SChaotian Jing 2644fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 2654fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 2664fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 2674fe54318SAngeloGioacchino Del Regno #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 2686397b7f5SChaotian Jing 2694fe54318SAngeloGioacchino Del Regno #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 2701ede5cb8Syong mao 27113b4e1e9SWenbin Mei /* EMMC51_CFG0 mask */ 2724fe54318SAngeloGioacchino Del Regno #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 27313b4e1e9SWenbin Mei 2744fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 2754fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 2764fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 2774fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 27813b4e1e9SWenbin Mei 27913b4e1e9SWenbin Mei /* EMMC50_CFG1 mask */ 2804fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 2816397b7f5SChaotian Jing 2824fe54318SAngeloGioacchino Del Regno #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 283c8609b22SChaotian Jing 2844fe54318SAngeloGioacchino Del Regno #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 2854fe54318SAngeloGioacchino Del Regno #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 286d9dcbfc8SChaotian Jing 28713b4e1e9SWenbin Mei /* CQHCI_SETTING */ 2884fe54318SAngeloGioacchino Del Regno #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 2894fe54318SAngeloGioacchino Del Regno #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 29013b4e1e9SWenbin Mei 291a2e6d1f6SChaotian Jing /* EMMC_TOP_CONTROL mask */ 2924fe54318SAngeloGioacchino Del Regno #define PAD_RXDLY_SEL BIT(0) /* RW */ 2934fe54318SAngeloGioacchino Del Regno #define DELAY_EN BIT(1) /* RW */ 2944fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 2954fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 2964fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 2974fe54318SAngeloGioacchino Del Regno #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 2984fe54318SAngeloGioacchino Del Regno #define DATA_K_VALUE_SEL BIT(14) /* RW */ 2994fe54318SAngeloGioacchino Del Regno #define SDC_RX_ENH_EN BIT(15) /* TW */ 300a2e6d1f6SChaotian Jing 301a2e6d1f6SChaotian Jing /* EMMC_TOP_CMD mask */ 3024fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 3034fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 3044fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 3054fe54318SAngeloGioacchino Del Regno #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 3064fe54318SAngeloGioacchino Del Regno #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 307a2e6d1f6SChaotian Jing 308c4ac38c6SWenbin Mei /* EMMC50_PAD_DS_TUNE mask */ 3094fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY_SEL BIT(16) /* RW */ 3104fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 3114fe54318SAngeloGioacchino Del Regno #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 312c4ac38c6SWenbin Mei 3134fe54318SAngeloGioacchino Del Regno #define REQ_CMD_EIO BIT(0) 3144fe54318SAngeloGioacchino Del Regno #define REQ_CMD_TMO BIT(1) 3154fe54318SAngeloGioacchino Del Regno #define REQ_DAT_ERR BIT(2) 3164fe54318SAngeloGioacchino Del Regno #define REQ_STOP_EIO BIT(3) 3174fe54318SAngeloGioacchino Del Regno #define REQ_STOP_TMO BIT(4) 3184fe54318SAngeloGioacchino Del Regno #define REQ_CMD_BUSY BIT(5) 31920848903SChaotian Jing 3204fe54318SAngeloGioacchino Del Regno #define MSDC_PREPARE_FLAG BIT(0) 3214fe54318SAngeloGioacchino Del Regno #define MSDC_ASYNC_FLAG BIT(1) 3224fe54318SAngeloGioacchino Del Regno #define MSDC_MMAP_FLAG BIT(2) 32320848903SChaotian Jing 3244b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 32520848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 32620848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 32720848903SChaotian Jing 328d087bde5SNeilBrown #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 329d087bde5SNeilBrown 3306397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 33120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 33220848903SChaotian Jing /* Descriptor Structure */ 33320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 33420848903SChaotian Jing struct mt_gpdma_desc { 33520848903SChaotian Jing u32 gpd_info; 3364fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_HWO BIT(0) 3374fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_BDP BIT(1) 3384fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 3394fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_INT BIT(16) 3404fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 3414fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 34220848903SChaotian Jing u32 next; 34320848903SChaotian Jing u32 ptr; 34420848903SChaotian Jing u32 gpd_data_len; 3454fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 3464fe54318SAngeloGioacchino Del Regno #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 34720848903SChaotian Jing u32 arg; 34820848903SChaotian Jing u32 blknum; 34920848903SChaotian Jing u32 cmd; 35020848903SChaotian Jing }; 35120848903SChaotian Jing 35220848903SChaotian Jing struct mt_bdma_desc { 35320848903SChaotian Jing u32 bd_info; 3544fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_EOL BIT(0) 3554fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 3564fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BLKPAD BIT(17) 3574fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_DWPAD BIT(18) 3584fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 3594fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 36020848903SChaotian Jing u32 next; 36120848903SChaotian Jing u32 ptr; 36220848903SChaotian Jing u32 bd_data_len; 3634fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BUFLEN GENMASK(15, 0) 3644fe54318SAngeloGioacchino Del Regno #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 36520848903SChaotian Jing }; 36620848903SChaotian Jing 36720848903SChaotian Jing struct msdc_dma { 36820848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 36920848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 37020848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 37120848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 37220848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 37320848903SChaotian Jing }; 37420848903SChaotian Jing 3754b8a43e9SChaotian Jing struct msdc_save_para { 3764b8a43e9SChaotian Jing u32 msdc_cfg; 3774b8a43e9SChaotian Jing u32 iocon; 3784b8a43e9SChaotian Jing u32 sdc_cfg; 3794b8a43e9SChaotian Jing u32 pad_tune; 3804b8a43e9SChaotian Jing u32 patch_bit0; 3814b8a43e9SChaotian Jing u32 patch_bit1; 3822fea5819SChaotian Jing u32 patch_bit2; 3836397b7f5SChaotian Jing u32 pad_ds_tune; 3841ede5cb8Syong mao u32 pad_cmd_tune; 3856397b7f5SChaotian Jing u32 emmc50_cfg0; 386c8609b22SChaotian Jing u32 emmc50_cfg3; 387d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 388a2e6d1f6SChaotian Jing u32 emmc_top_control; 389a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 390a2e6d1f6SChaotian Jing u32 emmc50_pad_ds_tune; 3916397b7f5SChaotian Jing }; 3926397b7f5SChaotian Jing 393762d491aSChaotian Jing struct mtk_mmc_compatible { 394762d491aSChaotian Jing u8 clk_div_bits; 3959e2582e5Syong mao bool recheck_sdio_irq; 3967f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 39739add252SChaotian Jing u32 pad_tune_reg; 3982fea5819SChaotian Jing bool async_fifo; 3992fea5819SChaotian Jing bool data_tune; 400acde28c4SChaotian Jing bool busy_check; 401d9dcbfc8SChaotian Jing bool stop_clk_fix; 402d9dcbfc8SChaotian Jing bool enhance_rx; 4032a9bde19SChaotian Jing bool support_64g; 404d087bde5SNeilBrown bool use_internal_cd; 405762d491aSChaotian Jing }; 406762d491aSChaotian Jing 40786beac37SChaotian Jing struct msdc_tune_para { 40886beac37SChaotian Jing u32 iocon; 40986beac37SChaotian Jing u32 pad_tune; 4101ede5cb8Syong mao u32 pad_cmd_tune; 411a2e6d1f6SChaotian Jing u32 emmc_top_control; 412a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 41386beac37SChaotian Jing }; 41486beac37SChaotian Jing 4156397b7f5SChaotian Jing struct msdc_delay_phase { 4166397b7f5SChaotian Jing u8 maxlen; 4176397b7f5SChaotian Jing u8 start; 4186397b7f5SChaotian Jing u8 final_phase; 4194b8a43e9SChaotian Jing }; 4204b8a43e9SChaotian Jing 42120848903SChaotian Jing struct msdc_host { 42220848903SChaotian Jing struct device *dev; 423762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 42420848903SChaotian Jing int cmd_rsp; 42520848903SChaotian Jing 42620848903SChaotian Jing spinlock_t lock; 42720848903SChaotian Jing struct mmc_request *mrq; 42820848903SChaotian Jing struct mmc_command *cmd; 42920848903SChaotian Jing struct mmc_data *data; 43020848903SChaotian Jing int error; 43120848903SChaotian Jing 43220848903SChaotian Jing void __iomem *base; /* host base address */ 433a2e6d1f6SChaotian Jing void __iomem *top_base; /* host top register base address */ 43420848903SChaotian Jing 43520848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 43620848903SChaotian Jing u64 dma_mask; 43720848903SChaotian Jing 43820848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 43920848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 44020848903SChaotian Jing 44120848903SChaotian Jing struct pinctrl *pinctrl; 44220848903SChaotian Jing struct pinctrl_state *pins_default; 44320848903SChaotian Jing struct pinctrl_state *pins_uhs; 444*527f36f5SAxe Yang struct pinctrl_state *pins_eint; 44520848903SChaotian Jing struct delayed_work req_timeout; 44620848903SChaotian Jing int irq; /* host interrupt */ 447*527f36f5SAxe Yang int eint_irq; /* interrupt from sdio device for waking up system */ 448855d388dSWenbin Mei struct reset_control *reset; 44920848903SChaotian Jing 45020848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 45120848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 452258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 4533c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 454f5eccd94SWenbin Mei struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 455f5eccd94SWenbin Mei struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 45620848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 45720848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 4586e622947SChaotian Jing unsigned char timing; 45920848903SChaotian Jing bool vqmmc_enabled; 460d17bb71cSChaotian Jing u32 latch_ck; 4616397b7f5SChaotian Jing u32 hs400_ds_delay; 462c4ac38c6SWenbin Mei u32 hs400_ds_dly3; 4631ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 4641ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4651ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4661ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4675462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 468c4ac38c6SWenbin Mei bool hs400_tuning; /* hs400 mode online tuning */ 469d087bde5SNeilBrown bool internal_cd; /* Use internal card-detect logic */ 47088bd652bSChun-Hung Wu bool cqhci; /* support eMMC hw cmdq */ 4714b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 47286beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 47386beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 47488bd652bSChun-Hung Wu struct cqhci_host *cq_host; 47520848903SChaotian Jing }; 47620848903SChaotian Jing 477762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 478762d491aSChaotian Jing .clk_div_bits = 8, 479903a72ecSyong mao .recheck_sdio_irq = true, 4807f3d5852SChaotian Jing .hs400_tune = false, 48139add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4822fea5819SChaotian Jing .async_fifo = false, 4832fea5819SChaotian Jing .data_tune = false, 484acde28c4SChaotian Jing .busy_check = false, 485d9dcbfc8SChaotian Jing .stop_clk_fix = false, 486d9dcbfc8SChaotian Jing .enhance_rx = false, 4872a9bde19SChaotian Jing .support_64g = false, 488762d491aSChaotian Jing }; 489762d491aSChaotian Jing 490762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 491762d491aSChaotian Jing .clk_div_bits = 8, 4929e2582e5Syong mao .recheck_sdio_irq = true, 4937f3d5852SChaotian Jing .hs400_tune = true, 49439add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4952fea5819SChaotian Jing .async_fifo = false, 4962fea5819SChaotian Jing .data_tune = false, 497acde28c4SChaotian Jing .busy_check = false, 498d9dcbfc8SChaotian Jing .stop_clk_fix = false, 499d9dcbfc8SChaotian Jing .enhance_rx = false, 5002a9bde19SChaotian Jing .support_64g = false, 501762d491aSChaotian Jing }; 502762d491aSChaotian Jing 503a2e6d1f6SChaotian Jing static const struct mtk_mmc_compatible mt8183_compat = { 504a2e6d1f6SChaotian Jing .clk_div_bits = 12, 5059e2582e5Syong mao .recheck_sdio_irq = false, 506a2e6d1f6SChaotian Jing .hs400_tune = false, 507a2e6d1f6SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 508a2e6d1f6SChaotian Jing .async_fifo = true, 509a2e6d1f6SChaotian Jing .data_tune = true, 510a2e6d1f6SChaotian Jing .busy_check = true, 511a2e6d1f6SChaotian Jing .stop_clk_fix = true, 512a2e6d1f6SChaotian Jing .enhance_rx = true, 513a2e6d1f6SChaotian Jing .support_64g = true, 514a2e6d1f6SChaotian Jing }; 515a2e6d1f6SChaotian Jing 516762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2701_compat = { 517762d491aSChaotian Jing .clk_div_bits = 12, 518903a72ecSyong mao .recheck_sdio_irq = true, 5197f3d5852SChaotian Jing .hs400_tune = false, 52039add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5212fea5819SChaotian Jing .async_fifo = true, 5222fea5819SChaotian Jing .data_tune = true, 523acde28c4SChaotian Jing .busy_check = false, 524d9dcbfc8SChaotian Jing .stop_clk_fix = false, 525d9dcbfc8SChaotian Jing .enhance_rx = false, 5262a9bde19SChaotian Jing .support_64g = false, 527762d491aSChaotian Jing }; 528762d491aSChaotian Jing 529762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2712_compat = { 530762d491aSChaotian Jing .clk_div_bits = 12, 5319e2582e5Syong mao .recheck_sdio_irq = false, 5327f3d5852SChaotian Jing .hs400_tune = false, 53339add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5342fea5819SChaotian Jing .async_fifo = true, 5352fea5819SChaotian Jing .data_tune = true, 536acde28c4SChaotian Jing .busy_check = true, 537d9dcbfc8SChaotian Jing .stop_clk_fix = true, 538d9dcbfc8SChaotian Jing .enhance_rx = true, 5392a9bde19SChaotian Jing .support_64g = true, 540762d491aSChaotian Jing }; 541762d491aSChaotian Jing 542966580adSSean Wang static const struct mtk_mmc_compatible mt7622_compat = { 543966580adSSean Wang .clk_div_bits = 12, 544903a72ecSyong mao .recheck_sdio_irq = true, 545966580adSSean Wang .hs400_tune = false, 546966580adSSean Wang .pad_tune_reg = MSDC_PAD_TUNE0, 547966580adSSean Wang .async_fifo = true, 548966580adSSean Wang .data_tune = true, 549966580adSSean Wang .busy_check = true, 550966580adSSean Wang .stop_clk_fix = true, 551966580adSSean Wang .enhance_rx = true, 5522a9bde19SChaotian Jing .support_64g = false, 553966580adSSean Wang }; 554966580adSSean Wang 55589822b73SFabien Parent static const struct mtk_mmc_compatible mt8516_compat = { 55689822b73SFabien Parent .clk_div_bits = 12, 557903a72ecSyong mao .recheck_sdio_irq = true, 55889822b73SFabien Parent .hs400_tune = false, 55989822b73SFabien Parent .pad_tune_reg = MSDC_PAD_TUNE0, 56089822b73SFabien Parent .async_fifo = true, 56189822b73SFabien Parent .data_tune = true, 56289822b73SFabien Parent .busy_check = true, 56389822b73SFabien Parent .stop_clk_fix = true, 56489822b73SFabien Parent }; 56589822b73SFabien Parent 566afb7c791SNeilBrown static const struct mtk_mmc_compatible mt7620_compat = { 567afb7c791SNeilBrown .clk_div_bits = 8, 568903a72ecSyong mao .recheck_sdio_irq = true, 569afb7c791SNeilBrown .hs400_tune = false, 570afb7c791SNeilBrown .pad_tune_reg = MSDC_PAD_TUNE, 571afb7c791SNeilBrown .async_fifo = false, 572afb7c791SNeilBrown .data_tune = false, 573afb7c791SNeilBrown .busy_check = false, 574afb7c791SNeilBrown .stop_clk_fix = false, 575afb7c791SNeilBrown .enhance_rx = false, 576d087bde5SNeilBrown .use_internal_cd = true, 577afb7c791SNeilBrown }; 578afb7c791SNeilBrown 5797d176b0eSChun-Hung Wu static const struct mtk_mmc_compatible mt6779_compat = { 5807d176b0eSChun-Hung Wu .clk_div_bits = 12, 581903a72ecSyong mao .recheck_sdio_irq = false, 5827d176b0eSChun-Hung Wu .hs400_tune = false, 5837d176b0eSChun-Hung Wu .pad_tune_reg = MSDC_PAD_TUNE0, 5847d176b0eSChun-Hung Wu .async_fifo = true, 5857d176b0eSChun-Hung Wu .data_tune = true, 5867d176b0eSChun-Hung Wu .busy_check = true, 5877d176b0eSChun-Hung Wu .stop_clk_fix = true, 5887d176b0eSChun-Hung Wu .enhance_rx = true, 5897d176b0eSChun-Hung Wu .support_64g = true, 5907d176b0eSChun-Hung Wu }; 5917d176b0eSChun-Hung Wu 592762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 593762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 594762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 595a2e6d1f6SChaotian Jing { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 596762d491aSChaotian Jing { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 597762d491aSChaotian Jing { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 598966580adSSean Wang { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 59989822b73SFabien Parent { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 600afb7c791SNeilBrown { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 6017d176b0eSChun-Hung Wu { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 602762d491aSChaotian Jing {} 603762d491aSChaotian Jing }; 604762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 605762d491aSChaotian Jing 60620848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 60720848903SChaotian Jing { 60820848903SChaotian Jing u32 val = readl(reg); 60920848903SChaotian Jing 61020848903SChaotian Jing val |= bs; 61120848903SChaotian Jing writel(val, reg); 61220848903SChaotian Jing } 61320848903SChaotian Jing 61420848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 61520848903SChaotian Jing { 61620848903SChaotian Jing u32 val = readl(reg); 61720848903SChaotian Jing 61820848903SChaotian Jing val &= ~bs; 61920848903SChaotian Jing writel(val, reg); 62020848903SChaotian Jing } 62120848903SChaotian Jing 62220848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 62320848903SChaotian Jing { 62420848903SChaotian Jing unsigned int tv = readl(reg); 62520848903SChaotian Jing 62620848903SChaotian Jing tv &= ~field; 62720848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 62820848903SChaotian Jing writel(tv, reg); 62920848903SChaotian Jing } 63020848903SChaotian Jing 63120848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 63220848903SChaotian Jing { 63320848903SChaotian Jing unsigned int tv = readl(reg); 63420848903SChaotian Jing 63520848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 63620848903SChaotian Jing } 63720848903SChaotian Jing 63820848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 63920848903SChaotian Jing { 64020848903SChaotian Jing u32 val; 64120848903SChaotian Jing 64220848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 643ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 64420848903SChaotian Jing 64520848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 646ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_FIFOCS, val, 647ffaea6ebSAngeloGioacchino Del Regno !(val & MSDC_FIFOCS_CLR), 0, 0); 64820848903SChaotian Jing 64920848903SChaotian Jing val = readl(host->base + MSDC_INT); 65020848903SChaotian Jing writel(val, host->base + MSDC_INT); 65120848903SChaotian Jing } 65220848903SChaotian Jing 65320848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 65420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 6559e2582e5Syong mao static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 65620848903SChaotian Jing 657726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 658726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 659726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 660726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 66120848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 66220848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 66320848903SChaotian Jing 66420848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 66520848903SChaotian Jing { 66620848903SChaotian Jing u32 i, sum = 0; 66720848903SChaotian Jing 66820848903SChaotian Jing for (i = 0; i < len; i++) 66920848903SChaotian Jing sum += buf[i]; 67020848903SChaotian Jing return 0xff - (u8) sum; 67120848903SChaotian Jing } 67220848903SChaotian Jing 67320848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 67420848903SChaotian Jing struct mmc_data *data) 67520848903SChaotian Jing { 67620848903SChaotian Jing unsigned int j, dma_len; 67720848903SChaotian Jing dma_addr_t dma_address; 67820848903SChaotian Jing u32 dma_ctrl; 67920848903SChaotian Jing struct scatterlist *sg; 68020848903SChaotian Jing struct mt_gpdma_desc *gpd; 68120848903SChaotian Jing struct mt_bdma_desc *bd; 68220848903SChaotian Jing 68320848903SChaotian Jing sg = data->sg; 68420848903SChaotian Jing 68520848903SChaotian Jing gpd = dma->gpd; 68620848903SChaotian Jing bd = dma->bd; 68720848903SChaotian Jing 68820848903SChaotian Jing /* modify gpd */ 68920848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 69020848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 69120848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 69220848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 69320848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 69420848903SChaotian Jing 69520848903SChaotian Jing /* modify bd */ 69620848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 69720848903SChaotian Jing dma_address = sg_dma_address(sg); 69820848903SChaotian Jing dma_len = sg_dma_len(sg); 69920848903SChaotian Jing 70020848903SChaotian Jing /* init bd */ 70120848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 70220848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 7032a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 7042a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 7052a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 7062a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 7072a9bde19SChaotian Jing << 28; 7082a9bde19SChaotian Jing } 7096ef042bdSChaotian Jing 7106ef042bdSChaotian Jing if (host->dev_comp->support_64g) { 7116ef042bdSChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 7126ef042bdSChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 7136ef042bdSChaotian Jing } else { 71420848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 71520848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 7166ef042bdSChaotian Jing } 71720848903SChaotian Jing 71820848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 71920848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 72020848903SChaotian Jing else 72120848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 72220848903SChaotian Jing 72320848903SChaotian Jing /* checksume need to clear first */ 72420848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 72520848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 72620848903SChaotian Jing } 72720848903SChaotian Jing 72820848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 72920848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 73020848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 7314fe54318SAngeloGioacchino Del Regno dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 73220848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 7332a9bde19SChaotian Jing if (host->dev_comp->support_64g) 7342a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 7352a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 7362a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 73720848903SChaotian Jing } 73820848903SChaotian Jing 73915107135SYue Hu static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 74020848903SChaotian Jing { 74120848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 74220848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 74320848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 744feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 74520848903SChaotian Jing } 74620848903SChaotian Jing } 74720848903SChaotian Jing 74815107135SYue Hu static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 74920848903SChaotian Jing { 75020848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 75120848903SChaotian Jing return; 75220848903SChaotian Jing 75320848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 75420848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 755feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 75620848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 75720848903SChaotian Jing } 75820848903SChaotian Jing } 75920848903SChaotian Jing 760557011b6SChun-Hung Wu static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 76120848903SChaotian Jing { 7620caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 763557011b6SChun-Hung Wu u64 timeout, clk_ns; 76420848903SChaotian Jing u32 mode = 0; 76520848903SChaotian Jing 7660caf60c4SAmey Narkhede if (mmc->actual_clock == 0) { 76720848903SChaotian Jing timeout = 0; 76820848903SChaotian Jing } else { 769557011b6SChun-Hung Wu clk_ns = 1000000000ULL; 7700caf60c4SAmey Narkhede do_div(clk_ns, mmc->actual_clock); 771557011b6SChun-Hung Wu timeout = ns + clk_ns - 1; 772557011b6SChun-Hung Wu do_div(timeout, clk_ns); 773557011b6SChun-Hung Wu timeout += clks; 77420848903SChaotian Jing /* in 1048576 sclk cycle unit */ 7754fe54318SAngeloGioacchino Del Regno timeout = DIV_ROUND_UP(timeout, BIT(20)); 776762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 777762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 778762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 779762d491aSChaotian Jing else 780762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 781762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 78220848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 78320848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 78420848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 78520848903SChaotian Jing } 786557011b6SChun-Hung Wu return timeout; 787557011b6SChun-Hung Wu } 788557011b6SChun-Hung Wu 789557011b6SChun-Hung Wu /* clock control primitives */ 790557011b6SChun-Hung Wu static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 791557011b6SChun-Hung Wu { 792557011b6SChun-Hung Wu u64 timeout; 793557011b6SChun-Hung Wu 794557011b6SChun-Hung Wu host->timeout_ns = ns; 795557011b6SChun-Hung Wu host->timeout_clks = clks; 796557011b6SChun-Hung Wu 797557011b6SChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 798557011b6SChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 799557011b6SChun-Hung Wu (u32)(timeout > 255 ? 255 : timeout)); 80020848903SChaotian Jing } 80120848903SChaotian Jing 80288bd652bSChun-Hung Wu static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 80388bd652bSChun-Hung Wu { 80488bd652bSChun-Hung Wu u64 timeout; 80588bd652bSChun-Hung Wu 80688bd652bSChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 80788bd652bSChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 80888bd652bSChun-Hung Wu (u32)(timeout > 8191 ? 8191 : timeout)); 80988bd652bSChun-Hung Wu } 81088bd652bSChun-Hung Wu 81120848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 81220848903SChaotian Jing { 813f5eccd94SWenbin Mei clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 8143c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 81520848903SChaotian Jing clk_disable_unprepare(host->src_clk); 816258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 81720848903SChaotian Jing clk_disable_unprepare(host->h_clk); 81820848903SChaotian Jing } 81920848903SChaotian Jing 820ffaea6ebSAngeloGioacchino Del Regno static int msdc_ungate_clock(struct msdc_host *host) 82120848903SChaotian Jing { 822ffaea6ebSAngeloGioacchino Del Regno u32 val; 823f5eccd94SWenbin Mei int ret; 824f5eccd94SWenbin Mei 82520848903SChaotian Jing clk_prepare_enable(host->h_clk); 826258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 82720848903SChaotian Jing clk_prepare_enable(host->src_clk); 8283c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 829f5eccd94SWenbin Mei ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 830f5eccd94SWenbin Mei if (ret) { 831f5eccd94SWenbin Mei dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 832ffaea6ebSAngeloGioacchino Del Regno return ret; 833f5eccd94SWenbin Mei } 834f5eccd94SWenbin Mei 835ffaea6ebSAngeloGioacchino Del Regno return readl_poll_timeout(host->base + MSDC_CFG, val, 836ffaea6ebSAngeloGioacchino Del Regno (val & MSDC_CFG_CKSTB), 1, 20000); 83720848903SChaotian Jing } 83820848903SChaotian Jing 8396e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 84020848903SChaotian Jing { 8410caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 84220848903SChaotian Jing u32 mode; 84320848903SChaotian Jing u32 flags; 84420848903SChaotian Jing u32 div; 84520848903SChaotian Jing u32 sclk; 84639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 847ffaea6ebSAngeloGioacchino Del Regno u32 val; 84820848903SChaotian Jing 84920848903SChaotian Jing if (!hz) { 85020848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 85120848903SChaotian Jing host->mclk = 0; 8520caf60c4SAmey Narkhede mmc->actual_clock = 0; 85320848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 85420848903SChaotian Jing return; 85520848903SChaotian Jing } 85620848903SChaotian Jing 85720848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 85820848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 859762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8606397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 861762d491aSChaotian Jing else 862762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 863762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8646e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 8656397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 8666397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 8676397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 8686397b7f5SChaotian Jing mode = 0x3; 8696397b7f5SChaotian Jing else 87020848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 8716397b7f5SChaotian Jing 87220848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 87320848903SChaotian Jing div = 0; /* mean div = 1/4 */ 87420848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 87520848903SChaotian Jing } else { 87620848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 87720848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 87820848903SChaotian Jing div = (div >> 1); 87920848903SChaotian Jing } 8806397b7f5SChaotian Jing 8816397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 8826397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 883762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8846397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 8856397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 886762d491aSChaotian Jing else 887762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 888762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8896397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 8906397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 8916397b7f5SChaotian Jing } 89220848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 89320848903SChaotian Jing mode = 0x1; /* no divisor */ 89420848903SChaotian Jing div = 0; 89520848903SChaotian Jing sclk = host->src_clk_freq; 89620848903SChaotian Jing } else { 89720848903SChaotian Jing mode = 0x0; /* use divisor */ 89820848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 89920848903SChaotian Jing div = 0; /* mean div = 1/2 */ 90020848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 90120848903SChaotian Jing } else { 90220848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 90320848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 90420848903SChaotian Jing } 90520848903SChaotian Jing } 9063c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 907e5e8b224SAngeloGioacchino Del Regno 9083c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 909762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 910762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 911762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 91240ceda09Syong mao (mode << 8) | div); 913762d491aSChaotian Jing else 914762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 915762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 916762d491aSChaotian Jing (mode << 12) | div); 917762d491aSChaotian Jing 918e5e8b224SAngeloGioacchino Del Regno clk_prepare_enable(host->src_clk_cg); 919ffaea6ebSAngeloGioacchino Del Regno readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 9203c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 9210caf60c4SAmey Narkhede mmc->actual_clock = sclk; 92220848903SChaotian Jing host->mclk = hz; 9236e622947SChaotian Jing host->timing = timing; 92420848903SChaotian Jing /* need because clk changed. */ 92520848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 92620848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 92720848903SChaotian Jing 92886beac37SChaotian Jing /* 92986beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 93086beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 93186beac37SChaotian Jing */ 9320caf60c4SAmey Narkhede if (mmc->actual_clock <= 52000000) { 93386beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 934a2e6d1f6SChaotian Jing if (host->top_base) { 935a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_control, 936a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 937a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_cmd, 938a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 939a2e6d1f6SChaotian Jing } else { 940a2e6d1f6SChaotian Jing writel(host->def_tune_para.pad_tune, 941a2e6d1f6SChaotian Jing host->base + tune_reg); 942a2e6d1f6SChaotian Jing } 94386beac37SChaotian Jing } else { 94486beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 9451ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 9461ede5cb8Syong mao host->base + PAD_CMD_TUNE); 947a2e6d1f6SChaotian Jing if (host->top_base) { 948a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_control, 949a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 950a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_cmd, 951a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 952a2e6d1f6SChaotian Jing } else { 953a2e6d1f6SChaotian Jing writel(host->saved_tune_para.pad_tune, 954a2e6d1f6SChaotian Jing host->base + tune_reg); 955a2e6d1f6SChaotian Jing } 95686beac37SChaotian Jing } 95786beac37SChaotian Jing 9587f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 9597f3d5852SChaotian Jing host->dev_comp->hs400_tune) 9603751e008SChaotian Jing sdr_set_field(host->base + tune_reg, 9611ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 9621ede5cb8Syong mao host->hs400_cmd_int_delay); 9630caf60c4SAmey Narkhede dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 96456f6cbbeSChaotian Jing timing); 96520848903SChaotian Jing } 96620848903SChaotian Jing 96720848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 968961e40f7SChanWoo Lee struct mmc_command *cmd) 96920848903SChaotian Jing { 97020848903SChaotian Jing u32 resp; 97120848903SChaotian Jing 97220848903SChaotian Jing switch (mmc_resp_type(cmd)) { 97320848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 97420848903SChaotian Jing case MMC_RSP_R1: 97520848903SChaotian Jing resp = 0x1; 97620848903SChaotian Jing break; 97720848903SChaotian Jing case MMC_RSP_R1B: 97820848903SChaotian Jing resp = 0x7; 97920848903SChaotian Jing break; 98020848903SChaotian Jing case MMC_RSP_R2: 98120848903SChaotian Jing resp = 0x2; 98220848903SChaotian Jing break; 98320848903SChaotian Jing case MMC_RSP_R3: 98420848903SChaotian Jing resp = 0x3; 98520848903SChaotian Jing break; 98620848903SChaotian Jing case MMC_RSP_NONE: 98720848903SChaotian Jing default: 98820848903SChaotian Jing resp = 0x0; 98920848903SChaotian Jing break; 99020848903SChaotian Jing } 99120848903SChaotian Jing 99220848903SChaotian Jing return resp; 99320848903SChaotian Jing } 99420848903SChaotian Jing 99520848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 99620848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 99720848903SChaotian Jing { 9980caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 99920848903SChaotian Jing /* rawcmd : 100020848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 100120848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 100220848903SChaotian Jing */ 100320848903SChaotian Jing u32 opcode = cmd->opcode; 1004961e40f7SChanWoo Lee u32 resp = msdc_cmd_find_resp(host, cmd); 100520848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 100620848903SChaotian Jing 100720848903SChaotian Jing host->cmd_rsp = resp; 100820848903SChaotian Jing 100920848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 101020848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 10114fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(14); 101220848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 10134fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(30); 101420848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 101520848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 101620848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 101720848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 101820848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 10194fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(11); 102020848903SChaotian Jing 102120848903SChaotian Jing if (cmd->data) { 102220848903SChaotian Jing struct mmc_data *data = cmd->data; 102320848903SChaotian Jing 102420848903SChaotian Jing if (mmc_op_multi(opcode)) { 10250caf60c4SAmey Narkhede if (mmc_card_mmc(mmc->card) && mrq->sbc && 102620848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 10274fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(29); /* AutoCMD23 */ 102820848903SChaotian Jing } 102920848903SChaotian Jing 103020848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 103120848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 10324fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(13); 103320848903SChaotian Jing if (data->blocks > 1) 10344fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(12); 103520848903SChaotian Jing else 10364fe54318SAngeloGioacchino Del Regno rawcmd |= BIT(11); 103720848903SChaotian Jing /* Always use dma mode */ 103820848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 103920848903SChaotian Jing 104020848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 104120848903SChaotian Jing host->timeout_clks != data->timeout_clks) 104220848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 104320848903SChaotian Jing data->timeout_clks); 104420848903SChaotian Jing 104520848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 104620848903SChaotian Jing } 104720848903SChaotian Jing return rawcmd; 104820848903SChaotian Jing } 104920848903SChaotian Jing 1050d74179b8SChanWoo Lee static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1051d74179b8SChanWoo Lee struct mmc_data *data) 105220848903SChaotian Jing { 105320848903SChaotian Jing bool read; 105420848903SChaotian Jing 105520848903SChaotian Jing WARN_ON(host->data); 105620848903SChaotian Jing host->data = data; 105720848903SChaotian Jing read = data->flags & MMC_DATA_READ; 105820848903SChaotian Jing 105920848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 106020848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 106120848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 106220848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 106320848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 106420848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 106520848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 106620848903SChaotian Jing } 106720848903SChaotian Jing 106820848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 106920848903SChaotian Jing struct mmc_command *cmd) 107020848903SChaotian Jing { 107120848903SChaotian Jing u32 *rsp = cmd->resp; 107220848903SChaotian Jing 107320848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 107420848903SChaotian Jing 107520848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 107620848903SChaotian Jing cmd->error = 0; 107720848903SChaotian Jing } else { 107820848903SChaotian Jing msdc_reset_hw(host); 107920848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 108020848903SChaotian Jing cmd->error = -EILSEQ; 108120848903SChaotian Jing host->error |= REQ_STOP_EIO; 108220848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 108320848903SChaotian Jing cmd->error = -ETIMEDOUT; 108420848903SChaotian Jing host->error |= REQ_STOP_TMO; 108520848903SChaotian Jing } 108620848903SChaotian Jing dev_err(host->dev, 108720848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 108820848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 108920848903SChaotian Jing } 109020848903SChaotian Jing return cmd->error; 109120848903SChaotian Jing } 109220848903SChaotian Jing 10936ec5a7b7SLee Jones /* 10949e2582e5Syong mao * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 10959e2582e5Syong mao * 10969e2582e5Syong mao * Host controller may lost interrupt in some special case. 10979e2582e5Syong mao * Add SDIO irq recheck mechanism to make sure all interrupts 10989e2582e5Syong mao * can be processed immediately 10999e2582e5Syong mao */ 11009e2582e5Syong mao static void msdc_recheck_sdio_irq(struct msdc_host *host) 11019e2582e5Syong mao { 11020caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 11039e2582e5Syong mao u32 reg_int, reg_inten, reg_ps; 11049e2582e5Syong mao 11050caf60c4SAmey Narkhede if (mmc->caps & MMC_CAP_SDIO_IRQ) { 11069e2582e5Syong mao reg_inten = readl(host->base + MSDC_INTEN); 11079e2582e5Syong mao if (reg_inten & MSDC_INTEN_SDIOIRQ) { 11089e2582e5Syong mao reg_int = readl(host->base + MSDC_INT); 11099e2582e5Syong mao reg_ps = readl(host->base + MSDC_PS); 11109e2582e5Syong mao if (!(reg_int & MSDC_INT_SDIOIRQ || 11119e2582e5Syong mao reg_ps & MSDC_PS_DATA1)) { 11129e2582e5Syong mao __msdc_enable_sdio_irq(host, 0); 11130caf60c4SAmey Narkhede sdio_signal_irq(mmc); 11149e2582e5Syong mao } 11159e2582e5Syong mao } 11169e2582e5Syong mao } 11179e2582e5Syong mao } 11189e2582e5Syong mao 1119d74179b8SChanWoo Lee static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 112020848903SChaotian Jing { 112120848903SChaotian Jing if (host->error) 112220848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 112320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 112420848903SChaotian Jing } 112520848903SChaotian Jing 112620848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 112720848903SChaotian Jing { 112820848903SChaotian Jing unsigned long flags; 112920848903SChaotian Jing 11300354ca6eSChaotian Jing /* 11310354ca6eSChaotian Jing * No need check the return value of cancel_delayed_work, as only ONE 11320354ca6eSChaotian Jing * path will go here! 11330354ca6eSChaotian Jing */ 11340354ca6eSChaotian Jing cancel_delayed_work(&host->req_timeout); 11350354ca6eSChaotian Jing 113620848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 113720848903SChaotian Jing host->mrq = NULL; 113820848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 113920848903SChaotian Jing 1140d74179b8SChanWoo Lee msdc_track_cmd_data(host, mrq->cmd); 114120848903SChaotian Jing if (mrq->data) 114215107135SYue Hu msdc_unprepare_data(host, mrq->data); 114320314ce3Sjjian zhou if (host->error) 114420314ce3Sjjian zhou msdc_reset_hw(host); 11450caf60c4SAmey Narkhede mmc_request_done(mmc_from_priv(host), mrq); 11469e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 11479e2582e5Syong mao msdc_recheck_sdio_irq(host); 114820848903SChaotian Jing } 114920848903SChaotian Jing 115020848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 115120848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 115220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 115320848903SChaotian Jing { 115420848903SChaotian Jing bool done = false; 115520848903SChaotian Jing bool sbc_error; 115620848903SChaotian Jing unsigned long flags; 11570354ca6eSChaotian Jing u32 *rsp; 115820848903SChaotian Jing 115920848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 116020848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 116120848903SChaotian Jing | MSDC_INT_ACMDTMO))) 116220848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 116320848903SChaotian Jing 116420848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 116520848903SChaotian Jing 116620848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 116720848903SChaotian Jing | MSDC_INT_RSPCRCERR 116820848903SChaotian Jing | MSDC_INT_CMDTMO))) 116920848903SChaotian Jing return done; 117020848903SChaotian Jing 117120848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 117220848903SChaotian Jing done = !host->cmd; 117320848903SChaotian Jing host->cmd = NULL; 117420848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 117520848903SChaotian Jing 117620848903SChaotian Jing if (done) 117720848903SChaotian Jing return true; 11780354ca6eSChaotian Jing rsp = cmd->resp; 117920848903SChaotian Jing 1180726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 118120848903SChaotian Jing 118220848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 118320848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 118420848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 118520848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 118620848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 118720848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 118820848903SChaotian Jing } else { 118920848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 119020848903SChaotian Jing } 119120848903SChaotian Jing } 119220848903SChaotian Jing 119320848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1194da6e0f70SChaotian Jing if (events & MSDC_INT_CMDTMO || 1195da6e0f70SChaotian Jing (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1196c4ac38c6SWenbin Mei cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1197c4ac38c6SWenbin Mei !host->hs400_tuning)) 1198ddc71387SChaotian Jing /* 1199ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 1200da6e0f70SChaotian Jing * may have alreay come when cmd19/cmd21 gets response 1201da6e0f70SChaotian Jing * CRC error. 1202ddc71387SChaotian Jing */ 120320848903SChaotian Jing msdc_reset_hw(host); 120420848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 120520848903SChaotian Jing cmd->error = -EILSEQ; 120620848903SChaotian Jing host->error |= REQ_CMD_EIO; 120720848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 120820848903SChaotian Jing cmd->error = -ETIMEDOUT; 120920848903SChaotian Jing host->error |= REQ_CMD_TMO; 121020848903SChaotian Jing } 121120848903SChaotian Jing } 121220848903SChaotian Jing if (cmd->error) 121320848903SChaotian Jing dev_dbg(host->dev, 121420848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 121520848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 121620848903SChaotian Jing cmd->error); 121720848903SChaotian Jing 121820848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 121920848903SChaotian Jing return true; 122020848903SChaotian Jing } 122120848903SChaotian Jing 122220848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 122320848903SChaotian Jing * is correct before issue a request. but host design do below 122420848903SChaotian Jing * checks recommended. 122520848903SChaotian Jing */ 122620848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 122720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 122820848903SChaotian Jing { 1229ffaea6ebSAngeloGioacchino Del Regno u32 val; 1230ffaea6ebSAngeloGioacchino Del Regno int ret; 123120848903SChaotian Jing 1232ffaea6ebSAngeloGioacchino Del Regno /* The max busy time we can endure is 20ms */ 1233ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1234ffaea6ebSAngeloGioacchino Del Regno !(val & SDC_STS_CMDBUSY), 1, 20000); 1235ffaea6ebSAngeloGioacchino Del Regno if (ret) { 123620848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 123720848903SChaotian Jing host->error |= REQ_CMD_BUSY; 123820848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 123920848903SChaotian Jing return false; 124020848903SChaotian Jing } 124120848903SChaotian Jing 124220848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 124320848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 1244ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1245ffaea6ebSAngeloGioacchino Del Regno !(val & SDC_STS_SDCBUSY), 1, 20000); 1246ffaea6ebSAngeloGioacchino Del Regno if (ret) { 124720848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 124820848903SChaotian Jing host->error |= REQ_CMD_BUSY; 124920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 125020848903SChaotian Jing return false; 125120848903SChaotian Jing } 125220848903SChaotian Jing } 125320848903SChaotian Jing return true; 125420848903SChaotian Jing } 125520848903SChaotian Jing 125620848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 125720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 125820848903SChaotian Jing { 125920848903SChaotian Jing u32 rawcmd; 12605215b2e9Sjjian zhou unsigned long flags; 126120848903SChaotian Jing 126220848903SChaotian Jing WARN_ON(host->cmd); 126320848903SChaotian Jing host->cmd = cmd; 126420848903SChaotian Jing 1265f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 126620848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 126720848903SChaotian Jing return; 126820848903SChaotian Jing 126920848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 127020848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 127120848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 127220848903SChaotian Jing msdc_reset_hw(host); 127320848903SChaotian Jing } 127420848903SChaotian Jing 127520848903SChaotian Jing cmd->error = 0; 127620848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 127720848903SChaotian Jing 12785215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 1279726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 12805215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 12815215b2e9Sjjian zhou 128220848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 128320848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 128420848903SChaotian Jing } 128520848903SChaotian Jing 128620848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 128720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 128820848903SChaotian Jing { 1289ddc71387SChaotian Jing if ((cmd->error && 1290ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1291ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1292c4ac38c6SWenbin Mei cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1293c4ac38c6SWenbin Mei host->hs400_tuning))) || 1294ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 129520848903SChaotian Jing msdc_request_done(host, mrq); 129620848903SChaotian Jing else if (cmd == mrq->sbc) 129720848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 129820848903SChaotian Jing else if (!cmd->data) 129920848903SChaotian Jing msdc_request_done(host, mrq); 130020848903SChaotian Jing else 1301d74179b8SChanWoo Lee msdc_start_data(host, cmd, cmd->data); 130220848903SChaotian Jing } 130320848903SChaotian Jing 130420848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 130520848903SChaotian Jing { 130620848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 130720848903SChaotian Jing 130820848903SChaotian Jing host->error = 0; 130920848903SChaotian Jing WARN_ON(host->mrq); 131020848903SChaotian Jing host->mrq = mrq; 131120848903SChaotian Jing 131220848903SChaotian Jing if (mrq->data) 131315107135SYue Hu msdc_prepare_data(host, mrq->data); 131420848903SChaotian Jing 131520848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 131620848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 131720848903SChaotian Jing * use HW option, otherwise use SW option 131820848903SChaotian Jing */ 131920848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 132020848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 132120848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 132220848903SChaotian Jing else 132320848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 132420848903SChaotian Jing } 132520848903SChaotian Jing 1326d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 132720848903SChaotian Jing { 132820848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 132920848903SChaotian Jing struct mmc_data *data = mrq->data; 133020848903SChaotian Jing 133120848903SChaotian Jing if (!data) 133220848903SChaotian Jing return; 133320848903SChaotian Jing 133415107135SYue Hu msdc_prepare_data(host, data); 133520848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 133620848903SChaotian Jing } 133720848903SChaotian Jing 133820848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 133920848903SChaotian Jing int err) 134020848903SChaotian Jing { 134120848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 134215107135SYue Hu struct mmc_data *data = mrq->data; 134320848903SChaotian Jing 134420848903SChaotian Jing if (!data) 134520848903SChaotian Jing return; 134615107135SYue Hu 134720848903SChaotian Jing if (data->host_cookie) { 134820848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 134915107135SYue Hu msdc_unprepare_data(host, data); 135020848903SChaotian Jing } 135120848903SChaotian Jing } 135220848903SChaotian Jing 1353f0ed43edSYue Hu static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 135420848903SChaotian Jing { 135520848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 13566397b7f5SChaotian Jing !mrq->sbc) 135720848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 135820848903SChaotian Jing else 135920848903SChaotian Jing msdc_request_done(host, mrq); 136020848903SChaotian Jing } 136120848903SChaotian Jing 136289bcd9a6SMengqi Zhang static void msdc_data_xfer_done(struct msdc_host *host, u32 events, 136320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 136420848903SChaotian Jing { 13650354ca6eSChaotian Jing struct mmc_command *stop; 136620848903SChaotian Jing unsigned long flags; 136720848903SChaotian Jing bool done; 136820848903SChaotian Jing unsigned int check_data = events & 136920848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 137020848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 137120848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 1372ffaea6ebSAngeloGioacchino Del Regno u32 val; 1373ffaea6ebSAngeloGioacchino Del Regno int ret; 137420848903SChaotian Jing 137520848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 137620848903SChaotian Jing done = !host->data; 137720848903SChaotian Jing if (check_data) 137820848903SChaotian Jing host->data = NULL; 137920848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 138020848903SChaotian Jing 138120848903SChaotian Jing if (done) 138289bcd9a6SMengqi Zhang return; 13830354ca6eSChaotian Jing stop = data->stop; 138420848903SChaotian Jing 138520848903SChaotian Jing if (check_data || (stop && stop->error)) { 138620848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 138720848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 138820848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 138920848903SChaotian Jing 1); 1390ffaea6ebSAngeloGioacchino Del Regno 139189bcd9a6SMengqi Zhang ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, 139289bcd9a6SMengqi Zhang !(val & MSDC_DMA_CTRL_STOP), 1, 20000); 139389bcd9a6SMengqi Zhang if (ret) 139489bcd9a6SMengqi Zhang dev_dbg(host->dev, "DMA stop timed out\n"); 139589bcd9a6SMengqi Zhang 1396ffaea6ebSAngeloGioacchino Del Regno ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1397ffaea6ebSAngeloGioacchino Del Regno !(val & MSDC_DMA_CFG_STS), 1, 20000); 139889bcd9a6SMengqi Zhang if (ret) 139989bcd9a6SMengqi Zhang dev_dbg(host->dev, "DMA inactive timed out\n"); 1400ffaea6ebSAngeloGioacchino Del Regno 140120848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 140220848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 140320848903SChaotian Jing 140420848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 140520848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 140620848903SChaotian Jing } else { 14072066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 140820848903SChaotian Jing msdc_reset_hw(host); 140920848903SChaotian Jing host->error |= REQ_DAT_ERR; 141020848903SChaotian Jing data->bytes_xfered = 0; 141120848903SChaotian Jing 141220848903SChaotian Jing if (events & MSDC_INT_DATTMO) 141320848903SChaotian Jing data->error = -ETIMEDOUT; 14146397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 14156397b7f5SChaotian Jing data->error = -EILSEQ; 141620848903SChaotian Jing 14172066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 141820848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 14192066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 142020848903SChaotian Jing (int)data->error, data->bytes_xfered); 142120848903SChaotian Jing } 142220848903SChaotian Jing 1423f0ed43edSYue Hu msdc_data_xfer_next(host, mrq); 142420848903SChaotian Jing } 142520848903SChaotian Jing } 142620848903SChaotian Jing 142720848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 142820848903SChaotian Jing { 142920848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 143020848903SChaotian Jing 143120848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 143220848903SChaotian Jing 143320848903SChaotian Jing switch (width) { 143420848903SChaotian Jing default: 143520848903SChaotian Jing case MMC_BUS_WIDTH_1: 143620848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 143720848903SChaotian Jing break; 143820848903SChaotian Jing case MMC_BUS_WIDTH_4: 143920848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 144020848903SChaotian Jing break; 144120848903SChaotian Jing case MMC_BUS_WIDTH_8: 144220848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 144320848903SChaotian Jing break; 144420848903SChaotian Jing } 144520848903SChaotian Jing 144620848903SChaotian Jing writel(val, host->base + SDC_CFG); 144720848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 144820848903SChaotian Jing } 144920848903SChaotian Jing 145020848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 145120848903SChaotian Jing { 145220848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14539cbe0fc8SMarek Vasut int ret; 145420848903SChaotian Jing 145520848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1456fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1457fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 145820848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 145920848903SChaotian Jing return -EINVAL; 146020848903SChaotian Jing } 146120848903SChaotian Jing 1462fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 14639cbe0fc8SMarek Vasut if (ret < 0) { 1464fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1465fac49ce5SNicolas Boichat ret, ios->signal_voltage); 14669cbe0fc8SMarek Vasut return ret; 14679cbe0fc8SMarek Vasut } 14689cbe0fc8SMarek Vasut 146920848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 147020848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 147120848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 147220848903SChaotian Jing else 147320848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 147420848903SChaotian Jing } 14759cbe0fc8SMarek Vasut return 0; 147620848903SChaotian Jing } 147720848903SChaotian Jing 147820848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 147920848903SChaotian Jing { 148020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 148120848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 148220848903SChaotian Jing 14833bc702edSyong mao /* only check if data0 is low */ 14843bc702edSyong mao return !(status & BIT(16)); 148520848903SChaotian Jing } 148620848903SChaotian Jing 148720848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 148820848903SChaotian Jing { 148920848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 149020848903SChaotian Jing req_timeout.work); 149120848903SChaotian Jing 149220848903SChaotian Jing /* simulate HW timeout status */ 149320848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 149420848903SChaotian Jing if (host->mrq) { 149520848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 149620848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 149720848903SChaotian Jing if (host->cmd) { 149820848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 149920848903SChaotian Jing __func__, host->cmd->opcode); 150020848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 150120848903SChaotian Jing host->cmd); 150220848903SChaotian Jing } else if (host->data) { 150320848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 150420848903SChaotian Jing __func__, host->mrq->cmd->opcode, 150520848903SChaotian Jing host->data->blocks); 150620848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 150720848903SChaotian Jing host->data); 150820848903SChaotian Jing } 150920848903SChaotian Jing } 151020848903SChaotian Jing } 151120848903SChaotian Jing 15128a5df8acSjjian zhou static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 15138a5df8acSjjian zhou { 15148a5df8acSjjian zhou if (enb) { 15158a5df8acSjjian zhou sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15168a5df8acSjjian zhou sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15179e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 15189e2582e5Syong mao msdc_recheck_sdio_irq(host); 15198a5df8acSjjian zhou } else { 15208a5df8acSjjian zhou sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15218a5df8acSjjian zhou sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15228a5df8acSjjian zhou } 15238a5df8acSjjian zhou } 15248a5df8acSjjian zhou 15258a5df8acSjjian zhou static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 15265215b2e9Sjjian zhou { 15275215b2e9Sjjian zhou struct msdc_host *host = mmc_priv(mmc); 1528*527f36f5SAxe Yang unsigned long flags; 1529*527f36f5SAxe Yang int ret; 15305215b2e9Sjjian zhou 15315215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 15328a5df8acSjjian zhou __msdc_enable_sdio_irq(host, enb); 15335215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 15345215b2e9Sjjian zhou 1535*527f36f5SAxe Yang if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { 1536*527f36f5SAxe Yang if (enb) { 1537*527f36f5SAxe Yang /* 1538*527f36f5SAxe Yang * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to 1539*527f36f5SAxe Yang * GPIO mode. We need to restore it to SDIO DAT1 mode after that. 1540*527f36f5SAxe Yang * Since the current pinstate is pins_uhs, to ensure pinctrl select take 1541*527f36f5SAxe Yang * affect successfully, we change the pinstate to pins_eint firstly. 1542*527f36f5SAxe Yang */ 1543*527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_eint); 1544*527f36f5SAxe Yang ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); 1545*527f36f5SAxe Yang 1546*527f36f5SAxe Yang if (ret) { 1547*527f36f5SAxe Yang dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); 1548*527f36f5SAxe Yang host->pins_eint = NULL; 15495215b2e9Sjjian zhou pm_runtime_get_noresume(host->dev); 1550*527f36f5SAxe Yang } else { 1551*527f36f5SAxe Yang dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); 1552*527f36f5SAxe Yang } 1553*527f36f5SAxe Yang 1554*527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_uhs); 1555*527f36f5SAxe Yang } else { 1556*527f36f5SAxe Yang dev_pm_clear_wake_irq(host->dev); 1557*527f36f5SAxe Yang } 1558*527f36f5SAxe Yang } else { 1559*527f36f5SAxe Yang if (enb) { 1560*527f36f5SAxe Yang /* Ensure host->pins_eint is NULL */ 1561*527f36f5SAxe Yang host->pins_eint = NULL; 1562*527f36f5SAxe Yang pm_runtime_get_noresume(host->dev); 1563*527f36f5SAxe Yang } else { 15645215b2e9Sjjian zhou pm_runtime_put_noidle(host->dev); 15655215b2e9Sjjian zhou } 1566*527f36f5SAxe Yang } 1567*527f36f5SAxe Yang } 15685215b2e9Sjjian zhou 156988bd652bSChun-Hung Wu static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 157088bd652bSChun-Hung Wu { 15710caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 157288bd652bSChun-Hung Wu int cmd_err = 0, dat_err = 0; 157388bd652bSChun-Hung Wu 157488bd652bSChun-Hung Wu if (intsts & MSDC_INT_RSPCRCERR) { 157588bd652bSChun-Hung Wu cmd_err = -EILSEQ; 157688bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD CRC ERR", __func__); 157788bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_CMDTMO) { 157888bd652bSChun-Hung Wu cmd_err = -ETIMEDOUT; 157988bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 158088bd652bSChun-Hung Wu } 158188bd652bSChun-Hung Wu 158288bd652bSChun-Hung Wu if (intsts & MSDC_INT_DATCRCERR) { 158388bd652bSChun-Hung Wu dat_err = -EILSEQ; 158488bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA CRC ERR", __func__); 158588bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_DATTMO) { 158688bd652bSChun-Hung Wu dat_err = -ETIMEDOUT; 158788bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 158888bd652bSChun-Hung Wu } 158988bd652bSChun-Hung Wu 159088bd652bSChun-Hung Wu if (cmd_err || dat_err) { 159188bd652bSChun-Hung Wu dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 159288bd652bSChun-Hung Wu cmd_err, dat_err, intsts); 159388bd652bSChun-Hung Wu } 159488bd652bSChun-Hung Wu 15950caf60c4SAmey Narkhede return cqhci_irq(mmc, 0, cmd_err, dat_err); 159688bd652bSChun-Hung Wu } 159788bd652bSChun-Hung Wu 159820848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 159920848903SChaotian Jing { 160020848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 16010caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 160220848903SChaotian Jing 160320848903SChaotian Jing while (true) { 160420848903SChaotian Jing struct mmc_request *mrq; 160520848903SChaotian Jing struct mmc_command *cmd; 160620848903SChaotian Jing struct mmc_data *data; 160720848903SChaotian Jing u32 events, event_mask; 160820848903SChaotian Jing 16099baf7c5eSTian Tao spin_lock(&host->lock); 161020848903SChaotian Jing events = readl(host->base + MSDC_INT); 161120848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 16128a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 16138a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 0); 161420848903SChaotian Jing /* clear interrupts */ 161520848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 161620848903SChaotian Jing 161720848903SChaotian Jing mrq = host->mrq; 161820848903SChaotian Jing cmd = host->cmd; 161920848903SChaotian Jing data = host->data; 16209baf7c5eSTian Tao spin_unlock(&host->lock); 162120848903SChaotian Jing 16228a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 16230caf60c4SAmey Narkhede sdio_signal_irq(mmc); 16245215b2e9Sjjian zhou 1625d087bde5SNeilBrown if ((events & event_mask) & MSDC_INT_CDSC) { 1626d087bde5SNeilBrown if (host->internal_cd) 16270caf60c4SAmey Narkhede mmc_detect_change(mmc, msecs_to_jiffies(20)); 1628d087bde5SNeilBrown events &= ~MSDC_INT_CDSC; 1629d087bde5SNeilBrown } 1630d087bde5SNeilBrown 16315215b2e9Sjjian zhou if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 163220848903SChaotian Jing break; 163320848903SChaotian Jing 16340caf60c4SAmey Narkhede if ((mmc->caps2 & MMC_CAP2_CQE) && 163588bd652bSChun-Hung Wu (events & MSDC_INT_CMDQ)) { 163688bd652bSChun-Hung Wu msdc_cmdq_irq(host, events); 163788bd652bSChun-Hung Wu /* clear interrupts */ 163888bd652bSChun-Hung Wu writel(events, host->base + MSDC_INT); 163988bd652bSChun-Hung Wu return IRQ_HANDLED; 164088bd652bSChun-Hung Wu } 164188bd652bSChun-Hung Wu 164220848903SChaotian Jing if (!mrq) { 164320848903SChaotian Jing dev_err(host->dev, 164420848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 164520848903SChaotian Jing __func__, events, event_mask); 164620848903SChaotian Jing WARN_ON(1); 164720848903SChaotian Jing break; 164820848903SChaotian Jing } 164920848903SChaotian Jing 165020848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 165120848903SChaotian Jing 165220848903SChaotian Jing if (cmd) 165320848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 165420848903SChaotian Jing else if (data) 165520848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 165620848903SChaotian Jing } 165720848903SChaotian Jing 165820848903SChaotian Jing return IRQ_HANDLED; 165920848903SChaotian Jing } 166020848903SChaotian Jing 166120848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 166220848903SChaotian Jing { 166320848903SChaotian Jing u32 val; 166439add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 166583b27217SAngeloGioacchino Del Regno struct mmc_host *mmc = mmc_from_priv(host); 166620848903SChaotian Jing 1667855d388dSWenbin Mei if (host->reset) { 1668855d388dSWenbin Mei reset_control_assert(host->reset); 1669855d388dSWenbin Mei usleep_range(10, 50); 1670855d388dSWenbin Mei reset_control_deassert(host->reset); 1671855d388dSWenbin Mei } 1672855d388dSWenbin Mei 167320848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 167420848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 167520848903SChaotian Jing 167620848903SChaotian Jing /* Reset */ 167720848903SChaotian Jing msdc_reset_hw(host); 167820848903SChaotian Jing 167920848903SChaotian Jing /* Disable and clear all interrupts */ 168020848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 168120848903SChaotian Jing val = readl(host->base + MSDC_INT); 168220848903SChaotian Jing writel(val, host->base + MSDC_INT); 168320848903SChaotian Jing 1684d087bde5SNeilBrown /* Configure card detection */ 1685d087bde5SNeilBrown if (host->internal_cd) { 1686d087bde5SNeilBrown sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1687d087bde5SNeilBrown DEFAULT_DEBOUNCE); 1688d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1689d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1690d087bde5SNeilBrown sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1691d087bde5SNeilBrown } else { 1692d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1693d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1694d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1695d087bde5SNeilBrown } 1696d087bde5SNeilBrown 1697a2e6d1f6SChaotian Jing if (host->top_base) { 1698a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CONTROL); 1699a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CMD); 1700a2e6d1f6SChaotian Jing } else { 170139add252SChaotian Jing writel(0, host->base + tune_reg); 1702a2e6d1f6SChaotian Jing } 170320848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 17046397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 17056397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 170620848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 17072fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 17086397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1709d9dcbfc8SChaotian Jing 1710d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1711d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1712d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1713d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1714d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1715d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1716d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1717d9dcbfc8SChaotian Jing } 1718d9dcbfc8SChaotian Jing 1719acde28c4SChaotian Jing if (host->dev_comp->busy_check) 17204fe54318SAngeloGioacchino Del Regno sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1721d9dcbfc8SChaotian Jing 17222fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 17232fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17242fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1725d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1726a2e6d1f6SChaotian Jing if (host->top_base) 1727a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1728a2e6d1f6SChaotian Jing SDC_RX_ENH_EN); 1729a2e6d1f6SChaotian Jing else 1730d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1731d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1732d9dcbfc8SChaotian Jing } else { 17332fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17342fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 17352fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 17362fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1737d9dcbfc8SChaotian Jing } 17382fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 17392fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 17402fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 17412fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17422fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 17432fea5819SChaotian Jing } 17442fea5819SChaotian Jing 17452a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17462a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17472a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 17482fea5819SChaotian Jing if (host->dev_comp->data_tune) { 1749a2e6d1f6SChaotian Jing if (host->top_base) { 1750a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1751a2e6d1f6SChaotian Jing PAD_DAT_RD_RXDLY_SEL); 1752a2e6d1f6SChaotian Jing sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1753a2e6d1f6SChaotian Jing DATA_K_VALUE_SEL); 1754a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1755a2e6d1f6SChaotian Jing PAD_CMD_RD_RXDLY_SEL); 1756a2e6d1f6SChaotian Jing } else { 17572fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 1758a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RD_SEL | 1759a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_CMD_SEL); 1760a2e6d1f6SChaotian Jing } 17612fea5819SChaotian Jing } else { 17622fea5819SChaotian Jing /* choose clock tune */ 1763a2e6d1f6SChaotian Jing if (host->top_base) 1764a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1765a2e6d1f6SChaotian Jing PAD_RXDLY_SEL); 1766a2e6d1f6SChaotian Jing else 1767a2e6d1f6SChaotian Jing sdr_set_bits(host->base + tune_reg, 1768a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RXDLYSEL); 17692fea5819SChaotian Jing } 17706397b7f5SChaotian Jing 177183b27217SAngeloGioacchino Del Regno if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 177283b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 177383b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 177483b27217SAngeloGioacchino Del Regno sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 177583b27217SAngeloGioacchino Del Regno } else { 177683b27217SAngeloGioacchino Del Regno /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 177720848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 177820848903SChaotian Jing 17795215b2e9Sjjian zhou /* Config SDIO device detect interrupt function */ 178020848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 178126c71a13Syong mao sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 178283b27217SAngeloGioacchino Del Regno } 178320848903SChaotian Jing 178420848903SChaotian Jing /* Configure to default data timeout */ 178520848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 178620848903SChaotian Jing 178786beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 17882fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1789a2e6d1f6SChaotian Jing if (host->top_base) { 1790a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_control = 1791a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1792a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_cmd = 1793a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1794a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = 1795a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1796a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = 1797a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1798a2e6d1f6SChaotian Jing } else { 1799a2e6d1f6SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 18002fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1801a2e6d1f6SChaotian Jing } 180220848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 180320848903SChaotian Jing } 180420848903SChaotian Jing 180520848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 180620848903SChaotian Jing { 180720848903SChaotian Jing u32 val; 1808d087bde5SNeilBrown 1809d087bde5SNeilBrown if (host->internal_cd) { 1810d087bde5SNeilBrown /* Disabled card-detect */ 1811d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1812d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1813d087bde5SNeilBrown } 1814d087bde5SNeilBrown 181520848903SChaotian Jing /* Disable and clear all interrupts */ 181620848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 181720848903SChaotian Jing 181820848903SChaotian Jing val = readl(host->base + MSDC_INT); 181920848903SChaotian Jing writel(val, host->base + MSDC_INT); 182020848903SChaotian Jing } 182120848903SChaotian Jing 182220848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 182320848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 182420848903SChaotian Jing { 182520848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 182620848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 18272a9bde19SChaotian Jing dma_addr_t dma_addr; 182820848903SChaotian Jing int i; 182920848903SChaotian Jing 183062b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 183120848903SChaotian Jing 18322a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 183320848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 183462b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 183562b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 183662b0d27aSChaotian Jing */ 18372a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 18382a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18392a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18402a9bde19SChaotian Jing 18412a9bde19SChaotian Jing dma_addr = dma->bd_addr; 18422a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 18432a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18442a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 18452a9bde19SChaotian Jing 184620848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 18472a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 18482a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 18492a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 18502a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18512a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18522a9bde19SChaotian Jing } 185320848903SChaotian Jing } 185420848903SChaotian Jing 185520848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 185620848903SChaotian Jing { 185720848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 185820848903SChaotian Jing int ret; 185920848903SChaotian Jing 186020848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 186120848903SChaotian Jing 186220848903SChaotian Jing /* Suspend/Resume will do power off/on */ 186320848903SChaotian Jing switch (ios->power_mode) { 186420848903SChaotian Jing case MMC_POWER_UP: 186520848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 18666397b7f5SChaotian Jing msdc_init_hw(host); 186720848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 186820848903SChaotian Jing ios->vdd); 186920848903SChaotian Jing if (ret) { 187020848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1871567979fbSUlf Hansson return; 187220848903SChaotian Jing } 187320848903SChaotian Jing } 187420848903SChaotian Jing break; 187520848903SChaotian Jing case MMC_POWER_ON: 187620848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 187720848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 187820848903SChaotian Jing if (ret) 187920848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 188020848903SChaotian Jing else 188120848903SChaotian Jing host->vqmmc_enabled = true; 188220848903SChaotian Jing } 188320848903SChaotian Jing break; 188420848903SChaotian Jing case MMC_POWER_OFF: 188520848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 188620848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 188720848903SChaotian Jing 188820848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 188920848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 189020848903SChaotian Jing host->vqmmc_enabled = false; 189120848903SChaotian Jing } 189220848903SChaotian Jing break; 189320848903SChaotian Jing default: 189420848903SChaotian Jing break; 189520848903SChaotian Jing } 189620848903SChaotian Jing 18976e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 18986e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 189920848903SChaotian Jing } 190020848903SChaotian Jing 19016397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 19026397b7f5SChaotian Jing { 19036397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 19044fe54318SAngeloGioacchino Del Regno return delay & BIT(bit); 19056397b7f5SChaotian Jing } 19066397b7f5SChaotian Jing 19076397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 19086397b7f5SChaotian Jing { 19096397b7f5SChaotian Jing int i; 19106397b7f5SChaotian Jing 19116397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 19126397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 19136397b7f5SChaotian Jing return i; 19146397b7f5SChaotian Jing } 19156397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 19166397b7f5SChaotian Jing } 19176397b7f5SChaotian Jing 19186397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 19196397b7f5SChaotian Jing { 19206397b7f5SChaotian Jing int start = 0, len = 0; 19216397b7f5SChaotian Jing int start_final = 0, len_final = 0; 19226397b7f5SChaotian Jing u8 final_phase = 0xff; 192362d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 19246397b7f5SChaotian Jing 19256397b7f5SChaotian Jing if (delay == 0) { 19266397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 19276397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 19286397b7f5SChaotian Jing return delay_phase; 19296397b7f5SChaotian Jing } 19306397b7f5SChaotian Jing 19316397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 19326397b7f5SChaotian Jing len = get_delay_len(delay, start); 19336397b7f5SChaotian Jing if (len_final < len) { 19346397b7f5SChaotian Jing start_final = start; 19356397b7f5SChaotian Jing len_final = len; 19366397b7f5SChaotian Jing } 19376397b7f5SChaotian Jing start += len ? len : 1; 19381ede5cb8Syong mao if (len >= 12 && start_final < 4) 19396397b7f5SChaotian Jing break; 19406397b7f5SChaotian Jing } 19416397b7f5SChaotian Jing 19426397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 19436397b7f5SChaotian Jing if (start_final == 0) 19446397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 19456397b7f5SChaotian Jing else 19466397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 194733106d78SAlexandre Bailon dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 19486397b7f5SChaotian Jing delay, len_final, final_phase); 19496397b7f5SChaotian Jing 19506397b7f5SChaotian Jing delay_phase.maxlen = len_final; 19516397b7f5SChaotian Jing delay_phase.start = start_final; 19526397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 19536397b7f5SChaotian Jing return delay_phase; 19546397b7f5SChaotian Jing } 19556397b7f5SChaotian Jing 1956fd82cc30SChaotian Jing static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1957fd82cc30SChaotian Jing { 1958fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1959fd82cc30SChaotian Jing 1960fd82cc30SChaotian Jing if (host->top_base) 1961fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1962fd82cc30SChaotian Jing value); 1963fd82cc30SChaotian Jing else 1964fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1965fd82cc30SChaotian Jing value); 1966fd82cc30SChaotian Jing } 1967fd82cc30SChaotian Jing 1968fd82cc30SChaotian Jing static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1969fd82cc30SChaotian Jing { 1970fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1971fd82cc30SChaotian Jing 1972fd82cc30SChaotian Jing if (host->top_base) 1973fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1974fd82cc30SChaotian Jing PAD_DAT_RD_RXDLY, value); 1975fd82cc30SChaotian Jing else 1976fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1977fd82cc30SChaotian Jing value); 1978fd82cc30SChaotian Jing } 1979fd82cc30SChaotian Jing 19806397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 19816397b7f5SChaotian Jing { 19826397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 19836397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1984ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 19851ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 19866397b7f5SChaotian Jing u8 final_delay, final_maxlen; 19871ede5cb8Syong mao u32 internal_delay = 0; 198839add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 19896397b7f5SChaotian Jing int cmd_err; 19901ede5cb8Syong mao int i, j; 19911ede5cb8Syong mao 19921ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 19931ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 199439add252SChaotian Jing sdr_set_field(host->base + tune_reg, 19951ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 19961ede5cb8Syong mao host->hs200_cmd_int_delay); 19976397b7f5SChaotian Jing 19986397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19996397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2000fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 20011ede5cb8Syong mao /* 20021ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20031ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20041ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20051ede5cb8Syong mao */ 20061ede5cb8Syong mao for (j = 0; j < 3; j++) { 20076397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 20081ede5cb8Syong mao if (!cmd_err) { 20094fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 20101ede5cb8Syong mao } else { 20114fe54318SAngeloGioacchino Del Regno rise_delay &= ~BIT(i); 20121ede5cb8Syong mao break; 20131ede5cb8Syong mao } 20141ede5cb8Syong mao } 20156397b7f5SChaotian Jing } 2016ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2017ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 20186b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 20196b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2020ae9c657eSChaotian Jing goto skip_fall; 20216397b7f5SChaotian Jing 20226397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20236397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2024fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 20251ede5cb8Syong mao /* 20261ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20271ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20281ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20291ede5cb8Syong mao */ 20301ede5cb8Syong mao for (j = 0; j < 3; j++) { 20316397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 20321ede5cb8Syong mao if (!cmd_err) { 20334fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 20341ede5cb8Syong mao } else { 20354fe54318SAngeloGioacchino Del Regno fall_delay &= ~BIT(i); 20361ede5cb8Syong mao break; 20371ede5cb8Syong mao } 20381ede5cb8Syong mao } 20396397b7f5SChaotian Jing } 20406397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 20416397b7f5SChaotian Jing 2042ae9c657eSChaotian Jing skip_fall: 20436397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 20441ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 20451ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 20466397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 20476397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20486397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 20496397b7f5SChaotian Jing } else { 20506397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20516397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 20526397b7f5SChaotian Jing } 2053fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2054fd82cc30SChaotian Jing 20552fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 20561ede5cb8Syong mao goto skip_internal; 20576397b7f5SChaotian Jing 20581ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 205939add252SChaotian Jing sdr_set_field(host->base + tune_reg, 20601ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 20611ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20621ede5cb8Syong mao if (!cmd_err) 20634fe54318SAngeloGioacchino Del Regno internal_delay |= BIT(i); 20641ede5cb8Syong mao } 20651ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 20661ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 206739add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 20681ede5cb8Syong mao internal_delay_phase.final_phase); 20691ede5cb8Syong mao skip_internal: 20701ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20711ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 20721ede5cb8Syong mao } 20731ede5cb8Syong mao 20741ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 20751ede5cb8Syong mao { 20761ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 20771ede5cb8Syong mao u32 cmd_delay = 0; 20781ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 20791ede5cb8Syong mao u8 final_delay; 20801ede5cb8Syong mao int cmd_err; 20811ede5cb8Syong mao int i, j; 20821ede5cb8Syong mao 20831ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 20841ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 20858f34e5bdSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 20861ede5cb8Syong mao 20871ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 20881ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 20891ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 20901ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 20911ede5cb8Syong mao host->hs200_cmd_int_delay); 20921ede5cb8Syong mao 20931ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 20941ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20951ede5cb8Syong mao else 20961ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20971ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 20981ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 20991ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 21001ede5cb8Syong mao /* 21011ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 21021ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 21031ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 21041ede5cb8Syong mao */ 21051ede5cb8Syong mao for (j = 0; j < 3; j++) { 21061ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 21071ede5cb8Syong mao if (!cmd_err) { 21084fe54318SAngeloGioacchino Del Regno cmd_delay |= BIT(i); 21091ede5cb8Syong mao } else { 21104fe54318SAngeloGioacchino Del Regno cmd_delay &= ~BIT(i); 21111ede5cb8Syong mao break; 21121ede5cb8Syong mao } 21131ede5cb8Syong mao } 21141ede5cb8Syong mao } 21151ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 21161ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 21171ede5cb8Syong mao final_cmd_delay.final_phase); 21181ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 21191ede5cb8Syong mao 21201ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 21216397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 21226397b7f5SChaotian Jing } 21236397b7f5SChaotian Jing 21246397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 21256397b7f5SChaotian Jing { 21266397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 21276397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 2128ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 21296397b7f5SChaotian Jing u8 final_delay, final_maxlen; 21306397b7f5SChaotian Jing int i, ret; 21316397b7f5SChaotian Jing 2132d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2133d17bb71cSChaotian Jing host->latch_ck); 21346397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21356397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21366397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2137fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21386397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21396397b7f5SChaotian Jing if (!ret) 21404fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 21416397b7f5SChaotian Jing } 2142ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2143ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 21441ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 2145ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2146ae9c657eSChaotian Jing goto skip_fall; 21476397b7f5SChaotian Jing 21486397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21496397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21506397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2151fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21526397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21536397b7f5SChaotian Jing if (!ret) 21544fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 21556397b7f5SChaotian Jing } 21566397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 21576397b7f5SChaotian Jing 2158ae9c657eSChaotian Jing skip_fall: 21596397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 21606397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 21616397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21626397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21636397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 21646397b7f5SChaotian Jing } else { 21656397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21666397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21676397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 21686397b7f5SChaotian Jing } 2169fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 21706397b7f5SChaotian Jing 21711ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 21726397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 21736397b7f5SChaotian Jing } 21746397b7f5SChaotian Jing 217586601d0eSChaotian Jing /* 217686601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 217786601d0eSChaotian Jing * together, which can save the tuning time. 217886601d0eSChaotian Jing */ 217986601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 218086601d0eSChaotian Jing { 218186601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 218286601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 218386601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 218486601d0eSChaotian Jing u8 final_delay, final_maxlen; 218586601d0eSChaotian Jing int i, ret; 218686601d0eSChaotian Jing 218786601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 218886601d0eSChaotian Jing host->latch_ck); 218986601d0eSChaotian Jing 219086601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 219186601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 219286601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 219386601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2194fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2195fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 219686601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 219786601d0eSChaotian Jing if (!ret) 21984fe54318SAngeloGioacchino Del Regno rise_delay |= BIT(i); 219986601d0eSChaotian Jing } 220086601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 220186601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 220286601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 220386601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 220486601d0eSChaotian Jing goto skip_fall; 220586601d0eSChaotian Jing 220686601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 220786601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 220886601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 220986601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2210fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2211fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 221286601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 221386601d0eSChaotian Jing if (!ret) 22144fe54318SAngeloGioacchino Del Regno fall_delay |= BIT(i); 221586601d0eSChaotian Jing } 221686601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 221786601d0eSChaotian Jing 221886601d0eSChaotian Jing skip_fall: 221986601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 222086601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 222186601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 222286601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 222386601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 222486601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 222586601d0eSChaotian Jing } else { 222686601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 222786601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 222886601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 222986601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 223086601d0eSChaotian Jing } 223186601d0eSChaotian Jing 2232fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2233fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 2234a2e6d1f6SChaotian Jing 223586601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 223686601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 223786601d0eSChaotian Jing } 223886601d0eSChaotian Jing 22396397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 22406397b7f5SChaotian Jing { 22416397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22426397b7f5SChaotian Jing int ret; 224339add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 22446397b7f5SChaotian Jing 224586601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 224686601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 224786601d0eSChaotian Jing if (host->hs400_mode) { 224886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 224986601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2250fd82cc30SChaotian Jing msdc_set_data_delay(host, 0); 225186601d0eSChaotian Jing } 225286601d0eSChaotian Jing goto tune_done; 225386601d0eSChaotian Jing } 22547f3d5852SChaotian Jing if (host->hs400_mode && 22557f3d5852SChaotian Jing host->dev_comp->hs400_tune) 22561ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 22571ede5cb8Syong mao else 22586397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 22596397b7f5SChaotian Jing if (ret == -EIO) { 22606397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 2261567979fbSUlf Hansson return ret; 22626397b7f5SChaotian Jing } 22635462ff39SChaotian Jing if (host->hs400_mode == false) { 22646397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 22656397b7f5SChaotian Jing if (ret == -EIO) 22666397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 22675462ff39SChaotian Jing } 22686397b7f5SChaotian Jing 226986601d0eSChaotian Jing tune_done: 227086beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 227139add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 22721ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2273a2e6d1f6SChaotian Jing if (host->top_base) { 2274a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = readl(host->top_base + 2275a2e6d1f6SChaotian Jing EMMC_TOP_CONTROL); 2276a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2277a2e6d1f6SChaotian Jing EMMC_TOP_CMD); 2278a2e6d1f6SChaotian Jing } 22796397b7f5SChaotian Jing return ret; 22806397b7f5SChaotian Jing } 22816397b7f5SChaotian Jing 22826397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 22836397b7f5SChaotian Jing { 22846397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22855462ff39SChaotian Jing host->hs400_mode = true; 22866397b7f5SChaotian Jing 2287a2e6d1f6SChaotian Jing if (host->top_base) 2288a2e6d1f6SChaotian Jing writel(host->hs400_ds_delay, 2289a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2290a2e6d1f6SChaotian Jing else 22916397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 22922fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 22932fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2294c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 2295c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2296c8609b22SChaotian Jing 22976397b7f5SChaotian Jing return 0; 22986397b7f5SChaotian Jing } 22996397b7f5SChaotian Jing 2300c4ac38c6SWenbin Mei static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2301c4ac38c6SWenbin Mei { 2302c4ac38c6SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 2303c4ac38c6SWenbin Mei struct msdc_delay_phase dly1_delay; 2304c4ac38c6SWenbin Mei u32 val, result_dly1 = 0; 2305c4ac38c6SWenbin Mei u8 *ext_csd; 2306c4ac38c6SWenbin Mei int i, ret; 2307c4ac38c6SWenbin Mei 2308c4ac38c6SWenbin Mei if (host->top_base) { 2309c4ac38c6SWenbin Mei sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2310c4ac38c6SWenbin Mei PAD_DS_DLY_SEL); 2311c4ac38c6SWenbin Mei if (host->hs400_ds_dly3) 2312c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2313c4ac38c6SWenbin Mei PAD_DS_DLY3, host->hs400_ds_dly3); 2314c4ac38c6SWenbin Mei } else { 2315c4ac38c6SWenbin Mei sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2316c4ac38c6SWenbin Mei if (host->hs400_ds_dly3) 2317c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2318c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2319c4ac38c6SWenbin Mei } 2320c4ac38c6SWenbin Mei 2321c4ac38c6SWenbin Mei host->hs400_tuning = true; 2322c4ac38c6SWenbin Mei for (i = 0; i < PAD_DELAY_MAX; i++) { 2323c4ac38c6SWenbin Mei if (host->top_base) 2324c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2325c4ac38c6SWenbin Mei PAD_DS_DLY1, i); 2326c4ac38c6SWenbin Mei else 2327c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2328c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY1, i); 2329c4ac38c6SWenbin Mei ret = mmc_get_ext_csd(card, &ext_csd); 2330d594b35dSWenbin Mei if (!ret) { 23314fe54318SAngeloGioacchino Del Regno result_dly1 |= BIT(i); 2332d594b35dSWenbin Mei kfree(ext_csd); 2333d594b35dSWenbin Mei } 2334c4ac38c6SWenbin Mei } 2335c4ac38c6SWenbin Mei host->hs400_tuning = false; 2336c4ac38c6SWenbin Mei 2337c4ac38c6SWenbin Mei dly1_delay = get_best_delay(host, result_dly1); 2338c4ac38c6SWenbin Mei if (dly1_delay.maxlen == 0) { 2339c4ac38c6SWenbin Mei dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2340c4ac38c6SWenbin Mei goto fail; 2341c4ac38c6SWenbin Mei } 2342c4ac38c6SWenbin Mei if (host->top_base) 2343c4ac38c6SWenbin Mei sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2344c4ac38c6SWenbin Mei PAD_DS_DLY1, dly1_delay.final_phase); 2345c4ac38c6SWenbin Mei else 2346c4ac38c6SWenbin Mei sdr_set_field(host->base + PAD_DS_TUNE, 2347c4ac38c6SWenbin Mei PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2348c4ac38c6SWenbin Mei 2349c4ac38c6SWenbin Mei if (host->top_base) 2350c4ac38c6SWenbin Mei val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2351c4ac38c6SWenbin Mei else 2352c4ac38c6SWenbin Mei val = readl(host->base + PAD_DS_TUNE); 2353c4ac38c6SWenbin Mei 2354f0c88b04SFabien Parent dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); 2355c4ac38c6SWenbin Mei 2356c4ac38c6SWenbin Mei return 0; 2357c4ac38c6SWenbin Mei 2358c4ac38c6SWenbin Mei fail: 2359c4ac38c6SWenbin Mei dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2360c4ac38c6SWenbin Mei return -EIO; 2361c4ac38c6SWenbin Mei } 2362c4ac38c6SWenbin Mei 2363c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 2364c9b5061eSChaotian Jing { 2365c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2366c9b5061eSChaotian Jing 2367c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 2368c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 2369c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 2370c9b5061eSChaotian Jing } 2371c9b5061eSChaotian Jing 23725215b2e9Sjjian zhou static void msdc_ack_sdio_irq(struct mmc_host *mmc) 23735215b2e9Sjjian zhou { 23748a5df8acSjjian zhou unsigned long flags; 23758a5df8acSjjian zhou struct msdc_host *host = mmc_priv(mmc); 23768a5df8acSjjian zhou 23778a5df8acSjjian zhou spin_lock_irqsave(&host->lock, flags); 23788a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 1); 23798a5df8acSjjian zhou spin_unlock_irqrestore(&host->lock, flags); 23805215b2e9Sjjian zhou } 23815215b2e9Sjjian zhou 2382d087bde5SNeilBrown static int msdc_get_cd(struct mmc_host *mmc) 2383d087bde5SNeilBrown { 2384d087bde5SNeilBrown struct msdc_host *host = mmc_priv(mmc); 2385d087bde5SNeilBrown int val; 2386d087bde5SNeilBrown 2387d087bde5SNeilBrown if (mmc->caps & MMC_CAP_NONREMOVABLE) 2388d087bde5SNeilBrown return 1; 2389d087bde5SNeilBrown 2390d087bde5SNeilBrown if (!host->internal_cd) 2391d087bde5SNeilBrown return mmc_gpio_get_cd(mmc); 2392d087bde5SNeilBrown 2393d087bde5SNeilBrown val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2394d087bde5SNeilBrown if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2395d087bde5SNeilBrown return !!val; 2396d087bde5SNeilBrown else 2397d087bde5SNeilBrown return !val; 2398d087bde5SNeilBrown } 2399d087bde5SNeilBrown 240013b4e1e9SWenbin Mei static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 240113b4e1e9SWenbin Mei struct mmc_ios *ios) 240213b4e1e9SWenbin Mei { 240313b4e1e9SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 240413b4e1e9SWenbin Mei 240513b4e1e9SWenbin Mei if (ios->enhanced_strobe) { 240613b4e1e9SWenbin Mei msdc_prepare_hs400_tuning(mmc, ios); 240713b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 240813b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 240913b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 241013b4e1e9SWenbin Mei 241113b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 241213b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 241313b4e1e9SWenbin Mei sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 241413b4e1e9SWenbin Mei } else { 241513b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 241613b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 241713b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 241813b4e1e9SWenbin Mei 241913b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 242013b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 242113b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 242213b4e1e9SWenbin Mei } 242313b4e1e9SWenbin Mei } 242413b4e1e9SWenbin Mei 242588bd652bSChun-Hung Wu static void msdc_cqe_enable(struct mmc_host *mmc) 242688bd652bSChun-Hung Wu { 242788bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 242888bd652bSChun-Hung Wu 242988bd652bSChun-Hung Wu /* enable cmdq irq */ 243088bd652bSChun-Hung Wu writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 243188bd652bSChun-Hung Wu /* enable busy check */ 243288bd652bSChun-Hung Wu sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 243388bd652bSChun-Hung Wu /* default write data / busy timeout 20s */ 243488bd652bSChun-Hung Wu msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 243588bd652bSChun-Hung Wu /* default read data timeout 1s */ 243688bd652bSChun-Hung Wu msdc_set_timeout(host, 1000000000ULL, 0); 243788bd652bSChun-Hung Wu } 243888bd652bSChun-Hung Wu 24397f4bc2e8SWei Yongjun static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 244088bd652bSChun-Hung Wu { 244188bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 244243e5fee3SDerong Liu unsigned int val = 0; 244388bd652bSChun-Hung Wu 244488bd652bSChun-Hung Wu /* disable cmdq irq */ 244588bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 244688bd652bSChun-Hung Wu /* disable busy check */ 244788bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 244888bd652bSChun-Hung Wu 244988bd652bSChun-Hung Wu if (recovery) { 245088bd652bSChun-Hung Wu sdr_set_field(host->base + MSDC_DMA_CTRL, 245188bd652bSChun-Hung Wu MSDC_DMA_CTRL_STOP, 1); 245289bcd9a6SMengqi Zhang if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, 245389bcd9a6SMengqi Zhang !(val & MSDC_DMA_CTRL_STOP), 1, 3000))) 245489bcd9a6SMengqi Zhang return; 245543e5fee3SDerong Liu if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 245643e5fee3SDerong Liu !(val & MSDC_DMA_CFG_STS), 1, 3000))) 245743e5fee3SDerong Liu return; 245888bd652bSChun-Hung Wu msdc_reset_hw(host); 245988bd652bSChun-Hung Wu } 246088bd652bSChun-Hung Wu } 246188bd652bSChun-Hung Wu 2462e282f204SChun-Hung Wu static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2463e282f204SChun-Hung Wu { 2464e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2465e282f204SChun-Hung Wu u32 reg; 2466e282f204SChun-Hung Wu 2467e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2468e282f204SChun-Hung Wu reg |= CQHCI_ENABLE; 2469e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2470e282f204SChun-Hung Wu } 2471e282f204SChun-Hung Wu 2472e282f204SChun-Hung Wu static void msdc_cqe_post_disable(struct mmc_host *mmc) 2473e282f204SChun-Hung Wu { 2474e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2475e282f204SChun-Hung Wu u32 reg; 2476e282f204SChun-Hung Wu 2477e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2478e282f204SChun-Hung Wu reg &= ~CQHCI_ENABLE; 2479e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2480e282f204SChun-Hung Wu } 2481e282f204SChun-Hung Wu 2482be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 248320848903SChaotian Jing .post_req = msdc_post_req, 248420848903SChaotian Jing .pre_req = msdc_pre_req, 248520848903SChaotian Jing .request = msdc_ops_request, 248620848903SChaotian Jing .set_ios = msdc_ops_set_ios, 24878d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 2488d087bde5SNeilBrown .get_cd = msdc_get_cd, 248913b4e1e9SWenbin Mei .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 24905215b2e9Sjjian zhou .enable_sdio_irq = msdc_enable_sdio_irq, 24915215b2e9Sjjian zhou .ack_sdio_irq = msdc_ack_sdio_irq, 249220848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 249320848903SChaotian Jing .card_busy = msdc_card_busy, 24946397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 24956397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2496c4ac38c6SWenbin Mei .execute_hs400_tuning = msdc_execute_hs400_tuning, 249732f18e59SWolfram Sang .card_hw_reset = msdc_hw_reset, 249820848903SChaotian Jing }; 249920848903SChaotian Jing 250088bd652bSChun-Hung Wu static const struct cqhci_host_ops msdc_cmdq_ops = { 250188bd652bSChun-Hung Wu .enable = msdc_cqe_enable, 250288bd652bSChun-Hung Wu .disable = msdc_cqe_disable, 2503e282f204SChun-Hung Wu .pre_enable = msdc_cqe_pre_enable, 2504e282f204SChun-Hung Wu .post_disable = msdc_cqe_post_disable, 250588bd652bSChun-Hung Wu }; 250688bd652bSChun-Hung Wu 25071ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 25081ede5cb8Syong mao struct msdc_host *host) 25091ede5cb8Syong mao { 2510d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2511d17bb71cSChaotian Jing &host->latch_ck); 2512d17bb71cSChaotian Jing 25131ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 25141ede5cb8Syong mao &host->hs400_ds_delay); 25151ede5cb8Syong mao 2516c4ac38c6SWenbin Mei of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2517c4ac38c6SWenbin Mei &host->hs400_ds_dly3); 2518c4ac38c6SWenbin Mei 25191ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 25201ede5cb8Syong mao &host->hs200_cmd_int_delay); 25211ede5cb8Syong mao 25221ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 25231ede5cb8Syong mao &host->hs400_cmd_int_delay); 25241ede5cb8Syong mao 25251ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 25261ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 25271ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 25281ede5cb8Syong mao else 25291ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 253088bd652bSChun-Hung Wu 253188bd652bSChun-Hung Wu if (of_property_read_bool(pdev->dev.of_node, 253288bd652bSChun-Hung Wu "supports-cqe")) 253388bd652bSChun-Hung Wu host->cqhci = true; 253488bd652bSChun-Hung Wu else 253588bd652bSChun-Hung Wu host->cqhci = false; 25361ede5cb8Syong mao } 25371ede5cb8Syong mao 2538f5eccd94SWenbin Mei static int msdc_of_clock_parse(struct platform_device *pdev, 2539f5eccd94SWenbin Mei struct msdc_host *host) 2540f5eccd94SWenbin Mei { 2541f5eccd94SWenbin Mei int ret; 2542f5eccd94SWenbin Mei 2543f5eccd94SWenbin Mei host->src_clk = devm_clk_get(&pdev->dev, "source"); 2544f5eccd94SWenbin Mei if (IS_ERR(host->src_clk)) 2545f5eccd94SWenbin Mei return PTR_ERR(host->src_clk); 2546f5eccd94SWenbin Mei 2547f5eccd94SWenbin Mei host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2548f5eccd94SWenbin Mei if (IS_ERR(host->h_clk)) 2549f5eccd94SWenbin Mei return PTR_ERR(host->h_clk); 2550f5eccd94SWenbin Mei 2551f5eccd94SWenbin Mei host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2552f5eccd94SWenbin Mei if (IS_ERR(host->bus_clk)) 2553f5eccd94SWenbin Mei host->bus_clk = NULL; 2554f5eccd94SWenbin Mei 2555f5eccd94SWenbin Mei /*source clock control gate is optional clock*/ 2556f5eccd94SWenbin Mei host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2557f5eccd94SWenbin Mei if (IS_ERR(host->src_clk_cg)) 2558996be7b7SAngeloGioacchino Del Regno return PTR_ERR(host->src_clk_cg); 2559f5eccd94SWenbin Mei 2560e5e8b224SAngeloGioacchino Del Regno /* 2561e5e8b224SAngeloGioacchino Del Regno * Fallback for legacy device-trees: src_clk and HCLK use the same 2562e5e8b224SAngeloGioacchino Del Regno * bit to control gating but they are parented to a different mux, 2563e5e8b224SAngeloGioacchino Del Regno * hence if our intention is to gate only the source, required 2564e5e8b224SAngeloGioacchino Del Regno * during a clk mode switch to avoid hw hangs, we need to gate 2565e5e8b224SAngeloGioacchino Del Regno * its parent (specified as a different clock only on new DTs). 2566e5e8b224SAngeloGioacchino Del Regno */ 2567e5e8b224SAngeloGioacchino Del Regno if (!host->src_clk_cg) { 2568e5e8b224SAngeloGioacchino Del Regno host->src_clk_cg = clk_get_parent(host->src_clk); 2569e5e8b224SAngeloGioacchino Del Regno if (IS_ERR(host->src_clk_cg)) 2570e5e8b224SAngeloGioacchino Del Regno return PTR_ERR(host->src_clk_cg); 2571e5e8b224SAngeloGioacchino Del Regno } 2572e5e8b224SAngeloGioacchino Del Regno 2573f5eccd94SWenbin Mei host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2574f5eccd94SWenbin Mei if (IS_ERR(host->sys_clk_cg)) 2575f5eccd94SWenbin Mei host->sys_clk_cg = NULL; 2576f5eccd94SWenbin Mei 2577f5eccd94SWenbin Mei /* If present, always enable for this clock gate */ 2578f5eccd94SWenbin Mei clk_prepare_enable(host->sys_clk_cg); 2579f5eccd94SWenbin Mei 2580f5eccd94SWenbin Mei host->bulk_clks[0].id = "pclk_cg"; 2581f5eccd94SWenbin Mei host->bulk_clks[1].id = "axi_cg"; 2582f5eccd94SWenbin Mei host->bulk_clks[2].id = "ahb_cg"; 2583f5eccd94SWenbin Mei ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2584f5eccd94SWenbin Mei host->bulk_clks); 2585f5eccd94SWenbin Mei if (ret) { 2586f5eccd94SWenbin Mei dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2587f5eccd94SWenbin Mei return ret; 2588f5eccd94SWenbin Mei } 2589f5eccd94SWenbin Mei 2590f5eccd94SWenbin Mei return 0; 2591f5eccd94SWenbin Mei } 2592f5eccd94SWenbin Mei 259320848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 259420848903SChaotian Jing { 259520848903SChaotian Jing struct mmc_host *mmc; 259620848903SChaotian Jing struct msdc_host *host; 259720848903SChaotian Jing struct resource *res; 259820848903SChaotian Jing int ret; 259920848903SChaotian Jing 260020848903SChaotian Jing if (!pdev->dev.of_node) { 260120848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 260220848903SChaotian Jing return -EINVAL; 260320848903SChaotian Jing } 2604762d491aSChaotian Jing 260520848903SChaotian Jing /* Allocate MMC host for this device */ 260620848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 260720848903SChaotian Jing if (!mmc) 260820848903SChaotian Jing return -ENOMEM; 260920848903SChaotian Jing 261020848903SChaotian Jing host = mmc_priv(mmc); 261120848903SChaotian Jing ret = mmc_of_parse(mmc); 261220848903SChaotian Jing if (ret) 261320848903SChaotian Jing goto host_free; 261420848903SChaotian Jing 2615bc068d38SYangtao Li host->base = devm_platform_ioremap_resource(pdev, 0); 261620848903SChaotian Jing if (IS_ERR(host->base)) { 261720848903SChaotian Jing ret = PTR_ERR(host->base); 261820848903SChaotian Jing goto host_free; 261920848903SChaotian Jing } 262020848903SChaotian Jing 2621a2e6d1f6SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2622b65be635SFabien Parent if (res) { 2623a2e6d1f6SChaotian Jing host->top_base = devm_ioremap_resource(&pdev->dev, res); 2624a2e6d1f6SChaotian Jing if (IS_ERR(host->top_base)) 2625a2e6d1f6SChaotian Jing host->top_base = NULL; 2626b65be635SFabien Parent } 2627a2e6d1f6SChaotian Jing 262820848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 26292f98ef63SWolfram Sang if (ret) 263020848903SChaotian Jing goto host_free; 263120848903SChaotian Jing 2632f5eccd94SWenbin Mei ret = msdc_of_clock_parse(pdev, host); 2633f5eccd94SWenbin Mei if (ret) 263420848903SChaotian Jing goto host_free; 26353c1a8844SChaotian Jing 2636855d388dSWenbin Mei host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2637855d388dSWenbin Mei "hrst"); 2638bbba85faSZheng Liang if (IS_ERR(host->reset)) { 2639bbba85faSZheng Liang ret = PTR_ERR(host->reset); 2640bbba85faSZheng Liang goto host_free; 2641bbba85faSZheng Liang } 2642855d388dSWenbin Mei 264320848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 264420848903SChaotian Jing if (host->irq < 0) { 264520848903SChaotian Jing ret = -EINVAL; 264620848903SChaotian Jing goto host_free; 264720848903SChaotian Jing } 264820848903SChaotian Jing 264920848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 265020848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 265120848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 265220848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 265320848903SChaotian Jing goto host_free; 265420848903SChaotian Jing } 265520848903SChaotian Jing 265620848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 265720848903SChaotian Jing if (IS_ERR(host->pins_default)) { 265820848903SChaotian Jing ret = PTR_ERR(host->pins_default); 265920848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 266020848903SChaotian Jing goto host_free; 266120848903SChaotian Jing } 266220848903SChaotian Jing 266320848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 266420848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 266520848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 266620848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 266720848903SChaotian Jing goto host_free; 266820848903SChaotian Jing } 266920848903SChaotian Jing 2670*527f36f5SAxe Yang /* Support for SDIO eint irq ? */ 2671*527f36f5SAxe Yang if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { 2672*527f36f5SAxe Yang host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup"); 2673*527f36f5SAxe Yang if (host->eint_irq > 0) { 2674*527f36f5SAxe Yang host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); 2675*527f36f5SAxe Yang if (IS_ERR(host->pins_eint)) { 2676*527f36f5SAxe Yang dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); 2677*527f36f5SAxe Yang host->pins_eint = NULL; 2678*527f36f5SAxe Yang } else { 2679*527f36f5SAxe Yang device_init_wakeup(&pdev->dev, true); 2680*527f36f5SAxe Yang } 2681*527f36f5SAxe Yang } 2682*527f36f5SAxe Yang } 2683*527f36f5SAxe Yang 26841ede5cb8Syong mao msdc_of_property_parse(pdev, host); 26856397b7f5SChaotian Jing 268620848903SChaotian Jing host->dev = &pdev->dev; 2687909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 268820848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 268920848903SChaotian Jing /* Set host parameters to mmc */ 269020848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2691762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 269240ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2693762d491aSChaotian Jing else 2694762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 269520848903SChaotian Jing 2696d087bde5SNeilBrown if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2697d087bde5SNeilBrown !mmc_can_gpio_cd(mmc) && 2698d087bde5SNeilBrown host->dev_comp->use_internal_cd) { 2699d087bde5SNeilBrown /* 2700d087bde5SNeilBrown * Is removable but no GPIO declared, so 2701d087bde5SNeilBrown * use internal functionality. 2702d087bde5SNeilBrown */ 2703d087bde5SNeilBrown host->internal_cd = true; 2704d087bde5SNeilBrown } 2705d087bde5SNeilBrown 27065215b2e9Sjjian zhou if (mmc->caps & MMC_CAP_SDIO_IRQ) 27075215b2e9Sjjian zhou mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 27085215b2e9Sjjian zhou 27091be64c79SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 271088bd652bSChun-Hung Wu if (host->cqhci) 271188bd652bSChun-Hung Wu mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 271220848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 271320848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 27146ef042bdSChaotian Jing if (host->dev_comp->support_64g) 27156ef042bdSChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 27166ef042bdSChaotian Jing else 271720848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 271820848903SChaotian Jing mmc->max_blk_size = 2048; 271920848903SChaotian Jing mmc->max_req_size = 512 * 1024; 272020848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 27212a9bde19SChaotian Jing if (host->dev_comp->support_64g) 27222a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 27232a9bde19SChaotian Jing else 272420848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 272520848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 272620848903SChaotian Jing 2727e8a1ff65SWenbin Mei host->timeout_clks = 3 * 1048576; 2728e8a1ff65SWenbin Mei host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2729e8a1ff65SWenbin Mei 2 * sizeof(struct mt_gpdma_desc), 2730e8a1ff65SWenbin Mei &host->dma.gpd_addr, GFP_KERNEL); 2731e8a1ff65SWenbin Mei host->dma.bd = dma_alloc_coherent(&pdev->dev, 2732e8a1ff65SWenbin Mei MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2733e8a1ff65SWenbin Mei &host->dma.bd_addr, GFP_KERNEL); 2734e8a1ff65SWenbin Mei if (!host->dma.gpd || !host->dma.bd) { 2735e8a1ff65SWenbin Mei ret = -ENOMEM; 2736e8a1ff65SWenbin Mei goto release_mem; 2737e8a1ff65SWenbin Mei } 2738e8a1ff65SWenbin Mei msdc_init_gpd_bd(host, &host->dma); 2739e8a1ff65SWenbin Mei INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2740e8a1ff65SWenbin Mei spin_lock_init(&host->lock); 2741e8a1ff65SWenbin Mei 2742e8a1ff65SWenbin Mei platform_set_drvdata(pdev, mmc); 2743ffaea6ebSAngeloGioacchino Del Regno ret = msdc_ungate_clock(host); 2744ffaea6ebSAngeloGioacchino Del Regno if (ret) { 2745ffaea6ebSAngeloGioacchino Del Regno dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2746ffaea6ebSAngeloGioacchino Del Regno goto release_mem; 2747ffaea6ebSAngeloGioacchino Del Regno } 2748e8a1ff65SWenbin Mei msdc_init_hw(host); 2749e8a1ff65SWenbin Mei 275088bd652bSChun-Hung Wu if (mmc->caps2 & MMC_CAP2_CQE) { 27510caf60c4SAmey Narkhede host->cq_host = devm_kzalloc(mmc->parent, 275288bd652bSChun-Hung Wu sizeof(*host->cq_host), 275388bd652bSChun-Hung Wu GFP_KERNEL); 275488bd652bSChun-Hung Wu if (!host->cq_host) { 275588bd652bSChun-Hung Wu ret = -ENOMEM; 275688bd652bSChun-Hung Wu goto host_free; 275788bd652bSChun-Hung Wu } 275888bd652bSChun-Hung Wu host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 275988bd652bSChun-Hung Wu host->cq_host->mmio = host->base + 0x800; 276088bd652bSChun-Hung Wu host->cq_host->ops = &msdc_cmdq_ops; 276188bd652bSChun-Hung Wu ret = cqhci_init(host->cq_host, mmc, true); 276288bd652bSChun-Hung Wu if (ret) 276388bd652bSChun-Hung Wu goto host_free; 276488bd652bSChun-Hung Wu mmc->max_segs = 128; 276588bd652bSChun-Hung Wu /* cqhci 16bit length */ 276688bd652bSChun-Hung Wu /* 0 size, means 65536 so we don't have to -1 here */ 276788bd652bSChun-Hung Wu mmc->max_seg_size = 64 * 1024; 276888bd652bSChun-Hung Wu } 276988bd652bSChun-Hung Wu 277020848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 277142edb0d5SNeilBrown IRQF_TRIGGER_NONE, pdev->name, host); 277220848903SChaotian Jing if (ret) 277320848903SChaotian Jing goto release; 277420848903SChaotian Jing 27754b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 27764b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 27774b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 27784b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 277920848903SChaotian Jing ret = mmc_add_host(mmc); 27804b8a43e9SChaotian Jing 278120848903SChaotian Jing if (ret) 27824b8a43e9SChaotian Jing goto end; 278320848903SChaotian Jing 278420848903SChaotian Jing return 0; 27854b8a43e9SChaotian Jing end: 27864b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 278720848903SChaotian Jing release: 278820848903SChaotian Jing platform_set_drvdata(pdev, NULL); 278920848903SChaotian Jing msdc_deinit_hw(host); 279020848903SChaotian Jing msdc_gate_clock(host); 279120848903SChaotian Jing release_mem: 279220848903SChaotian Jing if (host->dma.gpd) 279320848903SChaotian Jing dma_free_coherent(&pdev->dev, 279462b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 279520848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 279620848903SChaotian Jing if (host->dma.bd) 279720848903SChaotian Jing dma_free_coherent(&pdev->dev, 279820848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 279920848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 280020848903SChaotian Jing host_free: 280120848903SChaotian Jing mmc_free_host(mmc); 280220848903SChaotian Jing 280320848903SChaotian Jing return ret; 280420848903SChaotian Jing } 280520848903SChaotian Jing 280620848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 280720848903SChaotian Jing { 280820848903SChaotian Jing struct mmc_host *mmc; 280920848903SChaotian Jing struct msdc_host *host; 281020848903SChaotian Jing 281120848903SChaotian Jing mmc = platform_get_drvdata(pdev); 281220848903SChaotian Jing host = mmc_priv(mmc); 281320848903SChaotian Jing 28144b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 28154b8a43e9SChaotian Jing 281620848903SChaotian Jing platform_set_drvdata(pdev, NULL); 28170caf60c4SAmey Narkhede mmc_remove_host(mmc); 281820848903SChaotian Jing msdc_deinit_hw(host); 281920848903SChaotian Jing msdc_gate_clock(host); 282020848903SChaotian Jing 28214b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 28224b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 282320848903SChaotian Jing dma_free_coherent(&pdev->dev, 282416f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 282520848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 282620848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 282720848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 282820848903SChaotian Jing 28290caf60c4SAmey Narkhede mmc_free_host(mmc); 283020848903SChaotian Jing 283120848903SChaotian Jing return 0; 283220848903SChaotian Jing } 283320848903SChaotian Jing 28344b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 28354b8a43e9SChaotian Jing { 283639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 283739add252SChaotian Jing 28384b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 28394b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 28404b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 28414b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 28424b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 28432fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 28446397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 28451ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 28466397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2847c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2848d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2849a2e6d1f6SChaotian Jing if (host->top_base) { 2850a2e6d1f6SChaotian Jing host->save_para.emmc_top_control = 2851a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 2852a2e6d1f6SChaotian Jing host->save_para.emmc_top_cmd = 2853a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 2854a2e6d1f6SChaotian Jing host->save_para.emmc50_pad_ds_tune = 2855a2e6d1f6SChaotian Jing readl(host->top_base + EMMC50_PAD_DS_TUNE); 2856a2e6d1f6SChaotian Jing } else { 2857a2e6d1f6SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 2858a2e6d1f6SChaotian Jing } 28594b8a43e9SChaotian Jing } 28604b8a43e9SChaotian Jing 28614b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 28624b8a43e9SChaotian Jing { 28630caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 286439add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 286539add252SChaotian Jing 28664b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 28674b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 28684b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 28694b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 28704b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 28712fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 28726397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 28731ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 28746397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2875c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2876d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2877a2e6d1f6SChaotian Jing if (host->top_base) { 2878a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_control, 2879a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 2880a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_cmd, 2881a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 2882a2e6d1f6SChaotian Jing writel(host->save_para.emmc50_pad_ds_tune, 2883a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2884a2e6d1f6SChaotian Jing } else { 2885a2e6d1f6SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 2886a2e6d1f6SChaotian Jing } 28871c81d69dSUlf Hansson 28880caf60c4SAmey Narkhede if (sdio_irq_claimed(mmc)) 28891c81d69dSUlf Hansson __msdc_enable_sdio_irq(host, 1); 28904b8a43e9SChaotian Jing } 28914b8a43e9SChaotian Jing 2892c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_suspend(struct device *dev) 28934b8a43e9SChaotian Jing { 28944b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 28954b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 28964b8a43e9SChaotian Jing 28974b8a43e9SChaotian Jing msdc_save_reg(host); 2898*527f36f5SAxe Yang 2899*527f36f5SAxe Yang if (sdio_irq_claimed(mmc)) { 2900*527f36f5SAxe Yang if (host->pins_eint) { 2901*527f36f5SAxe Yang disable_irq(host->irq); 2902*527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_eint); 2903*527f36f5SAxe Yang } 2904*527f36f5SAxe Yang 2905*527f36f5SAxe Yang __msdc_enable_sdio_irq(host, 0); 2906*527f36f5SAxe Yang } 29074b8a43e9SChaotian Jing msdc_gate_clock(host); 29084b8a43e9SChaotian Jing return 0; 29094b8a43e9SChaotian Jing } 29104b8a43e9SChaotian Jing 2911c0d638a0SArnd Bergmann static int __maybe_unused msdc_runtime_resume(struct device *dev) 29124b8a43e9SChaotian Jing { 29134b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 29144b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2915ffaea6ebSAngeloGioacchino Del Regno int ret; 29164b8a43e9SChaotian Jing 2917ffaea6ebSAngeloGioacchino Del Regno ret = msdc_ungate_clock(host); 2918ffaea6ebSAngeloGioacchino Del Regno if (ret) 2919ffaea6ebSAngeloGioacchino Del Regno return ret; 2920ffaea6ebSAngeloGioacchino Del Regno 29214b8a43e9SChaotian Jing msdc_restore_reg(host); 2922*527f36f5SAxe Yang 2923*527f36f5SAxe Yang if (sdio_irq_claimed(mmc) && host->pins_eint) { 2924*527f36f5SAxe Yang pinctrl_select_state(host->pinctrl, host->pins_uhs); 2925*527f36f5SAxe Yang enable_irq(host->irq); 2926*527f36f5SAxe Yang } 29274b8a43e9SChaotian Jing return 0; 29284b8a43e9SChaotian Jing } 2929c0a2074aSWenbin Mei 2930c0d638a0SArnd Bergmann static int __maybe_unused msdc_suspend(struct device *dev) 2931c0a2074aSWenbin Mei { 2932c0a2074aSWenbin Mei struct mmc_host *mmc = dev_get_drvdata(dev); 2933*527f36f5SAxe Yang struct msdc_host *host = mmc_priv(mmc); 2934c0a2074aSWenbin Mei int ret; 2935c0a2074aSWenbin Mei 2936c0a2074aSWenbin Mei if (mmc->caps2 & MMC_CAP2_CQE) { 2937c0a2074aSWenbin Mei ret = cqhci_suspend(mmc); 2938c0a2074aSWenbin Mei if (ret) 2939c0a2074aSWenbin Mei return ret; 2940c0a2074aSWenbin Mei } 2941c0a2074aSWenbin Mei 2942*527f36f5SAxe Yang /* 2943*527f36f5SAxe Yang * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will 2944*527f36f5SAxe Yang * not be marked as 1, pm_runtime_force_resume() will go out directly. 2945*527f36f5SAxe Yang */ 2946*527f36f5SAxe Yang if (sdio_irq_claimed(mmc) && host->pins_eint) 2947*527f36f5SAxe Yang pm_runtime_get_noresume(dev); 2948*527f36f5SAxe Yang 2949c0a2074aSWenbin Mei return pm_runtime_force_suspend(dev); 2950c0a2074aSWenbin Mei } 2951c0a2074aSWenbin Mei 2952c0d638a0SArnd Bergmann static int __maybe_unused msdc_resume(struct device *dev) 2953c0a2074aSWenbin Mei { 2954*527f36f5SAxe Yang struct mmc_host *mmc = dev_get_drvdata(dev); 2955*527f36f5SAxe Yang struct msdc_host *host = mmc_priv(mmc); 2956*527f36f5SAxe Yang 2957*527f36f5SAxe Yang if (sdio_irq_claimed(mmc) && host->pins_eint) 2958*527f36f5SAxe Yang pm_runtime_put_noidle(dev); 2959*527f36f5SAxe Yang 2960c0a2074aSWenbin Mei return pm_runtime_force_resume(dev); 2961c0a2074aSWenbin Mei } 29624b8a43e9SChaotian Jing 29634b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 2964c0a2074aSWenbin Mei SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 29654b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 29664b8a43e9SChaotian Jing }; 29674b8a43e9SChaotian Jing 296820848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 296920848903SChaotian Jing .probe = msdc_drv_probe, 297020848903SChaotian Jing .remove = msdc_drv_remove, 297120848903SChaotian Jing .driver = { 297220848903SChaotian Jing .name = "mtk-msdc", 297321b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 297420848903SChaotian Jing .of_match_table = msdc_of_ids, 29754b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 297620848903SChaotian Jing }, 297720848903SChaotian Jing }; 297820848903SChaotian Jing 297920848903SChaotian Jing module_platform_driver(mt_msdc_driver); 298020848903SChaotian Jing MODULE_LICENSE("GPL v2"); 298120848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2982