11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 220848903SChaotian Jing /* 320848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 420848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 520848903SChaotian Jing */ 620848903SChaotian Jing 720848903SChaotian Jing #include <linux/module.h> 820848903SChaotian Jing #include <linux/clk.h> 920848903SChaotian Jing #include <linux/delay.h> 1020848903SChaotian Jing #include <linux/dma-mapping.h> 1120848903SChaotian Jing #include <linux/ioport.h> 1220848903SChaotian Jing #include <linux/irq.h> 1320848903SChaotian Jing #include <linux/of_address.h> 14909b3456SRyder Lee #include <linux/of_device.h> 1520848903SChaotian Jing #include <linux/of_irq.h> 1620848903SChaotian Jing #include <linux/of_gpio.h> 1720848903SChaotian Jing #include <linux/pinctrl/consumer.h> 1820848903SChaotian Jing #include <linux/platform_device.h> 194b8a43e9SChaotian Jing #include <linux/pm.h> 204b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2120848903SChaotian Jing #include <linux/regulator/consumer.h> 226397b7f5SChaotian Jing #include <linux/slab.h> 2320848903SChaotian Jing #include <linux/spinlock.h> 24b8789ec4SUlf Hansson #include <linux/interrupt.h> 25855d388dSWenbin Mei #include <linux/reset.h> 2620848903SChaotian Jing 2720848903SChaotian Jing #include <linux/mmc/card.h> 2820848903SChaotian Jing #include <linux/mmc/core.h> 2920848903SChaotian Jing #include <linux/mmc/host.h> 3020848903SChaotian Jing #include <linux/mmc/mmc.h> 3120848903SChaotian Jing #include <linux/mmc/sd.h> 3220848903SChaotian Jing #include <linux/mmc/sdio.h> 338d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 3420848903SChaotian Jing 3588bd652bSChun-Hung Wu #include "cqhci.h" 3688bd652bSChun-Hung Wu 3720848903SChaotian Jing #define MAX_BD_NUM 1024 38f5eccd94SWenbin Mei #define MSDC_NR_CLOCKS 3 3920848903SChaotian Jing 4020848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4120848903SChaotian Jing /* Common Definition */ 4220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4320848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4420848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4520848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4620848903SChaotian Jing 4720848903SChaotian Jing #define MSDC_BURST_64B 0x6 4820848903SChaotian Jing 4920848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5020848903SChaotian Jing /* Register Offset */ 5120848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5220848903SChaotian Jing #define MSDC_CFG 0x0 5320848903SChaotian Jing #define MSDC_IOCON 0x04 5420848903SChaotian Jing #define MSDC_PS 0x08 5520848903SChaotian Jing #define MSDC_INT 0x0c 5620848903SChaotian Jing #define MSDC_INTEN 0x10 5720848903SChaotian Jing #define MSDC_FIFOCS 0x14 5820848903SChaotian Jing #define SDC_CFG 0x30 5920848903SChaotian Jing #define SDC_CMD 0x34 6020848903SChaotian Jing #define SDC_ARG 0x38 6120848903SChaotian Jing #define SDC_STS 0x3c 6220848903SChaotian Jing #define SDC_RESP0 0x40 6320848903SChaotian Jing #define SDC_RESP1 0x44 6420848903SChaotian Jing #define SDC_RESP2 0x48 6520848903SChaotian Jing #define SDC_RESP3 0x4c 6620848903SChaotian Jing #define SDC_BLK_NUM 0x50 67d9dcbfc8SChaotian Jing #define SDC_ADV_CFG0 0x64 68c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 6920848903SChaotian Jing #define SDC_ACMD_RESP 0x80 702a9bde19SChaotian Jing #define DMA_SA_H4BIT 0x8c 7120848903SChaotian Jing #define MSDC_DMA_SA 0x90 7220848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7320848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7420848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7520848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 762fea5819SChaotian Jing #define MSDC_PATCH_BIT2 0xb8 7720848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 7839add252SChaotian Jing #define MSDC_PAD_TUNE0 0xf0 796397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 801ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 81*13b4e1e9SWenbin Mei #define EMMC51_CFG0 0x204 826397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 83*13b4e1e9SWenbin Mei #define EMMC50_CFG1 0x20c 84c8609b22SChaotian Jing #define EMMC50_CFG3 0x220 85d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG 0x228 86*13b4e1e9SWenbin Mei #define CQHCI_SETTING 0x7fc 8720848903SChaotian Jing 8820848903SChaotian Jing /*--------------------------------------------------------------------------*/ 89a2e6d1f6SChaotian Jing /* Top Pad Register Offset */ 90a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 91a2e6d1f6SChaotian Jing #define EMMC_TOP_CONTROL 0x00 92a2e6d1f6SChaotian Jing #define EMMC_TOP_CMD 0x04 93a2e6d1f6SChaotian Jing #define EMMC50_PAD_DS_TUNE 0x0c 94a2e6d1f6SChaotian Jing 95a2e6d1f6SChaotian Jing /*--------------------------------------------------------------------------*/ 9620848903SChaotian Jing /* Register Mask */ 9720848903SChaotian Jing /*--------------------------------------------------------------------------*/ 9820848903SChaotian Jing 9920848903SChaotian Jing /* MSDC_CFG mask */ 10020848903SChaotian Jing #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 10120848903SChaotian Jing #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 10220848903SChaotian Jing #define MSDC_CFG_RST (0x1 << 2) /* RW */ 10320848903SChaotian Jing #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 10420848903SChaotian Jing #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 10520848903SChaotian Jing #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 10620848903SChaotian Jing #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 10720848903SChaotian Jing #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 10820848903SChaotian Jing #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 10920848903SChaotian Jing #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 1106397b7f5SChaotian Jing #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 111762d491aSChaotian Jing #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 112762d491aSChaotian Jing #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 113762d491aSChaotian Jing #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 11420848903SChaotian Jing 11520848903SChaotian Jing /* MSDC_IOCON mask */ 11620848903SChaotian Jing #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 11720848903SChaotian Jing #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 11820848903SChaotian Jing #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 11920848903SChaotian Jing #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 12020848903SChaotian Jing #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 12120848903SChaotian Jing #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 12220848903SChaotian Jing #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 12320848903SChaotian Jing #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 12420848903SChaotian Jing #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 12520848903SChaotian Jing #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 12620848903SChaotian Jing #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 12720848903SChaotian Jing #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 12820848903SChaotian Jing #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 12920848903SChaotian Jing #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 13020848903SChaotian Jing #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 13120848903SChaotian Jing #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 13220848903SChaotian Jing 13320848903SChaotian Jing /* MSDC_PS mask */ 13420848903SChaotian Jing #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 13520848903SChaotian Jing #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 13620848903SChaotian Jing #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 13720848903SChaotian Jing #define MSDC_PS_DAT (0xff << 16) /* R */ 1389e2582e5Syong mao #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 13920848903SChaotian Jing #define MSDC_PS_CMD (0x1 << 24) /* R */ 14020848903SChaotian Jing #define MSDC_PS_WP (0x1 << 31) /* R */ 14120848903SChaotian Jing 14220848903SChaotian Jing /* MSDC_INT mask */ 14320848903SChaotian Jing #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 14420848903SChaotian Jing #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 14520848903SChaotian Jing #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 14620848903SChaotian Jing #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 14720848903SChaotian Jing #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 14820848903SChaotian Jing #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 14920848903SChaotian Jing #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 15020848903SChaotian Jing #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 15120848903SChaotian Jing #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 15220848903SChaotian Jing #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 15320848903SChaotian Jing #define MSDC_INT_CSTA (0x1 << 11) /* R */ 15420848903SChaotian Jing #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 15520848903SChaotian Jing #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 15620848903SChaotian Jing #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 15720848903SChaotian Jing #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 15820848903SChaotian Jing #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 15920848903SChaotian Jing #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 16020848903SChaotian Jing #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 16120848903SChaotian Jing #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 16288bd652bSChun-Hung Wu #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 16320848903SChaotian Jing 16420848903SChaotian Jing /* MSDC_INTEN mask */ 16520848903SChaotian Jing #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 16620848903SChaotian Jing #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 16720848903SChaotian Jing #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 16820848903SChaotian Jing #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 16920848903SChaotian Jing #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 17020848903SChaotian Jing #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 17120848903SChaotian Jing #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 17220848903SChaotian Jing #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 17320848903SChaotian Jing #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 17420848903SChaotian Jing #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 17520848903SChaotian Jing #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 17620848903SChaotian Jing #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 17720848903SChaotian Jing #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 17820848903SChaotian Jing #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 17920848903SChaotian Jing #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 18020848903SChaotian Jing #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 18120848903SChaotian Jing #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 18220848903SChaotian Jing #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 18320848903SChaotian Jing #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 18420848903SChaotian Jing 18520848903SChaotian Jing /* MSDC_FIFOCS mask */ 18620848903SChaotian Jing #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 18720848903SChaotian Jing #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 18820848903SChaotian Jing #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 18920848903SChaotian Jing 19020848903SChaotian Jing /* SDC_CFG mask */ 19120848903SChaotian Jing #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 19220848903SChaotian Jing #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 19388bd652bSChun-Hung Wu #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 19420848903SChaotian Jing #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 19520848903SChaotian Jing #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 19620848903SChaotian Jing #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 19720848903SChaotian Jing #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 19820848903SChaotian Jing #define SDC_CFG_DTOC (0xff << 24) /* RW */ 19920848903SChaotian Jing 20020848903SChaotian Jing /* SDC_STS mask */ 20120848903SChaotian Jing #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 20220848903SChaotian Jing #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 20320848903SChaotian Jing #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 20420848903SChaotian Jing 20526c71a13Syong mao #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 206d9dcbfc8SChaotian Jing /* SDC_ADV_CFG0 mask */ 207d9dcbfc8SChaotian Jing #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 208d9dcbfc8SChaotian Jing 2092a9bde19SChaotian Jing /* DMA_SA_H4BIT mask */ 2102a9bde19SChaotian Jing #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 2112a9bde19SChaotian Jing 21220848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 21320848903SChaotian Jing #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 21420848903SChaotian Jing #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 21520848903SChaotian Jing #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 21620848903SChaotian Jing #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 21720848903SChaotian Jing #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 21820848903SChaotian Jing #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 21920848903SChaotian Jing 22020848903SChaotian Jing /* MSDC_DMA_CFG mask */ 22120848903SChaotian Jing #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 22220848903SChaotian Jing #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 22320848903SChaotian Jing #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 22420848903SChaotian Jing #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 22520848903SChaotian Jing #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 22620848903SChaotian Jing 22720848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 22820848903SChaotian Jing #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 22920848903SChaotian Jing #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 23020848903SChaotian Jing #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 23120848903SChaotian Jing #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 23220848903SChaotian Jing #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 23320848903SChaotian Jing #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 23420848903SChaotian Jing #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 23520848903SChaotian Jing #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 23620848903SChaotian Jing #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 23720848903SChaotian Jing #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 23820848903SChaotian Jing #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 23920848903SChaotian Jing #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 24020848903SChaotian Jing 2418f34e5bdSChaotian Jing #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 24288bd652bSChun-Hung Wu #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 243d9dcbfc8SChaotian Jing #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 244d9dcbfc8SChaotian Jing 2452fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 2462fea5819SChaotian Jing #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 2472a9bde19SChaotian Jing #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 2482fea5819SChaotian Jing #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 2492fea5819SChaotian Jing #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 2502fea5819SChaotian Jing #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 2512fea5819SChaotian Jing 2521ede5cb8Syong mao #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 2536397b7f5SChaotian Jing #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 2546397b7f5SChaotian Jing #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 2551ede5cb8Syong mao #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 2561ede5cb8Syong mao #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 2572fea5819SChaotian Jing #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 2582fea5819SChaotian Jing #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 2592fea5819SChaotian Jing #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 2606397b7f5SChaotian Jing 2616397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 2626397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 2636397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 2646397b7f5SChaotian Jing 2651ede5cb8Syong mao #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 2661ede5cb8Syong mao 267*13b4e1e9SWenbin Mei /* EMMC51_CFG0 mask */ 268*13b4e1e9SWenbin Mei #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */ 269*13b4e1e9SWenbin Mei 2706397b7f5SChaotian Jing #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 2716397b7f5SChaotian Jing #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 2726397b7f5SChaotian Jing #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 273*13b4e1e9SWenbin Mei #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */ 274*13b4e1e9SWenbin Mei 275*13b4e1e9SWenbin Mei /* EMMC50_CFG1 mask */ 276*13b4e1e9SWenbin Mei #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */ 2776397b7f5SChaotian Jing 278c8609b22SChaotian Jing #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 279c8609b22SChaotian Jing 280d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 281d9dcbfc8SChaotian Jing #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 282d9dcbfc8SChaotian Jing 283*13b4e1e9SWenbin Mei /* CQHCI_SETTING */ 284*13b4e1e9SWenbin Mei #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */ 285*13b4e1e9SWenbin Mei #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */ 286*13b4e1e9SWenbin Mei 287a2e6d1f6SChaotian Jing /* EMMC_TOP_CONTROL mask */ 288a2e6d1f6SChaotian Jing #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 289a2e6d1f6SChaotian Jing #define DELAY_EN (0x1 << 1) /* RW */ 290a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 291a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 292a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 293a2e6d1f6SChaotian Jing #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 294a2e6d1f6SChaotian Jing #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 295a2e6d1f6SChaotian Jing #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 296a2e6d1f6SChaotian Jing 297a2e6d1f6SChaotian Jing /* EMMC_TOP_CMD mask */ 298a2e6d1f6SChaotian Jing #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 299a2e6d1f6SChaotian Jing #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 300a2e6d1f6SChaotian Jing #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 301a2e6d1f6SChaotian Jing #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 302a2e6d1f6SChaotian Jing #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 303a2e6d1f6SChaotian Jing 30420848903SChaotian Jing #define REQ_CMD_EIO (0x1 << 0) 30520848903SChaotian Jing #define REQ_CMD_TMO (0x1 << 1) 30620848903SChaotian Jing #define REQ_DAT_ERR (0x1 << 2) 30720848903SChaotian Jing #define REQ_STOP_EIO (0x1 << 3) 30820848903SChaotian Jing #define REQ_STOP_TMO (0x1 << 4) 30920848903SChaotian Jing #define REQ_CMD_BUSY (0x1 << 5) 31020848903SChaotian Jing 31120848903SChaotian Jing #define MSDC_PREPARE_FLAG (0x1 << 0) 31220848903SChaotian Jing #define MSDC_ASYNC_FLAG (0x1 << 1) 31320848903SChaotian Jing #define MSDC_MMAP_FLAG (0x1 << 2) 31420848903SChaotian Jing 3154b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 31620848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 31720848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 31820848903SChaotian Jing 319d087bde5SNeilBrown #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 320d087bde5SNeilBrown 3216397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 32220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 32320848903SChaotian Jing /* Descriptor Structure */ 32420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 32520848903SChaotian Jing struct mt_gpdma_desc { 32620848903SChaotian Jing u32 gpd_info; 32720848903SChaotian Jing #define GPDMA_DESC_HWO (0x1 << 0) 32820848903SChaotian Jing #define GPDMA_DESC_BDP (0x1 << 1) 32920848903SChaotian Jing #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 33020848903SChaotian Jing #define GPDMA_DESC_INT (0x1 << 16) 3312a9bde19SChaotian Jing #define GPDMA_DESC_NEXT_H4 (0xf << 24) 3322a9bde19SChaotian Jing #define GPDMA_DESC_PTR_H4 (0xf << 28) 33320848903SChaotian Jing u32 next; 33420848903SChaotian Jing u32 ptr; 33520848903SChaotian Jing u32 gpd_data_len; 33620848903SChaotian Jing #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 33720848903SChaotian Jing #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 33820848903SChaotian Jing u32 arg; 33920848903SChaotian Jing u32 blknum; 34020848903SChaotian Jing u32 cmd; 34120848903SChaotian Jing }; 34220848903SChaotian Jing 34320848903SChaotian Jing struct mt_bdma_desc { 34420848903SChaotian Jing u32 bd_info; 34520848903SChaotian Jing #define BDMA_DESC_EOL (0x1 << 0) 34620848903SChaotian Jing #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 34720848903SChaotian Jing #define BDMA_DESC_BLKPAD (0x1 << 17) 34820848903SChaotian Jing #define BDMA_DESC_DWPAD (0x1 << 18) 3492a9bde19SChaotian Jing #define BDMA_DESC_NEXT_H4 (0xf << 24) 3502a9bde19SChaotian Jing #define BDMA_DESC_PTR_H4 (0xf << 28) 35120848903SChaotian Jing u32 next; 35220848903SChaotian Jing u32 ptr; 35320848903SChaotian Jing u32 bd_data_len; 35420848903SChaotian Jing #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 3556ef042bdSChaotian Jing #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 35620848903SChaotian Jing }; 35720848903SChaotian Jing 35820848903SChaotian Jing struct msdc_dma { 35920848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 36020848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 36120848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 36220848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 36320848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 36420848903SChaotian Jing }; 36520848903SChaotian Jing 3664b8a43e9SChaotian Jing struct msdc_save_para { 3674b8a43e9SChaotian Jing u32 msdc_cfg; 3684b8a43e9SChaotian Jing u32 iocon; 3694b8a43e9SChaotian Jing u32 sdc_cfg; 3704b8a43e9SChaotian Jing u32 pad_tune; 3714b8a43e9SChaotian Jing u32 patch_bit0; 3724b8a43e9SChaotian Jing u32 patch_bit1; 3732fea5819SChaotian Jing u32 patch_bit2; 3746397b7f5SChaotian Jing u32 pad_ds_tune; 3751ede5cb8Syong mao u32 pad_cmd_tune; 3766397b7f5SChaotian Jing u32 emmc50_cfg0; 377c8609b22SChaotian Jing u32 emmc50_cfg3; 378d9dcbfc8SChaotian Jing u32 sdc_fifo_cfg; 379a2e6d1f6SChaotian Jing u32 emmc_top_control; 380a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 381a2e6d1f6SChaotian Jing u32 emmc50_pad_ds_tune; 3826397b7f5SChaotian Jing }; 3836397b7f5SChaotian Jing 384762d491aSChaotian Jing struct mtk_mmc_compatible { 385762d491aSChaotian Jing u8 clk_div_bits; 3869e2582e5Syong mao bool recheck_sdio_irq; 3877f3d5852SChaotian Jing bool hs400_tune; /* only used for MT8173 */ 38839add252SChaotian Jing u32 pad_tune_reg; 3892fea5819SChaotian Jing bool async_fifo; 3902fea5819SChaotian Jing bool data_tune; 391acde28c4SChaotian Jing bool busy_check; 392d9dcbfc8SChaotian Jing bool stop_clk_fix; 393d9dcbfc8SChaotian Jing bool enhance_rx; 3942a9bde19SChaotian Jing bool support_64g; 395d087bde5SNeilBrown bool use_internal_cd; 396762d491aSChaotian Jing }; 397762d491aSChaotian Jing 39886beac37SChaotian Jing struct msdc_tune_para { 39986beac37SChaotian Jing u32 iocon; 40086beac37SChaotian Jing u32 pad_tune; 4011ede5cb8Syong mao u32 pad_cmd_tune; 402a2e6d1f6SChaotian Jing u32 emmc_top_control; 403a2e6d1f6SChaotian Jing u32 emmc_top_cmd; 40486beac37SChaotian Jing }; 40586beac37SChaotian Jing 4066397b7f5SChaotian Jing struct msdc_delay_phase { 4076397b7f5SChaotian Jing u8 maxlen; 4086397b7f5SChaotian Jing u8 start; 4096397b7f5SChaotian Jing u8 final_phase; 4104b8a43e9SChaotian Jing }; 4114b8a43e9SChaotian Jing 41220848903SChaotian Jing struct msdc_host { 41320848903SChaotian Jing struct device *dev; 414762d491aSChaotian Jing const struct mtk_mmc_compatible *dev_comp; 41520848903SChaotian Jing int cmd_rsp; 41620848903SChaotian Jing 41720848903SChaotian Jing spinlock_t lock; 41820848903SChaotian Jing struct mmc_request *mrq; 41920848903SChaotian Jing struct mmc_command *cmd; 42020848903SChaotian Jing struct mmc_data *data; 42120848903SChaotian Jing int error; 42220848903SChaotian Jing 42320848903SChaotian Jing void __iomem *base; /* host base address */ 424a2e6d1f6SChaotian Jing void __iomem *top_base; /* host top register base address */ 42520848903SChaotian Jing 42620848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 42720848903SChaotian Jing u64 dma_mask; 42820848903SChaotian Jing 42920848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 43020848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 43120848903SChaotian Jing 43220848903SChaotian Jing struct pinctrl *pinctrl; 43320848903SChaotian Jing struct pinctrl_state *pins_default; 43420848903SChaotian Jing struct pinctrl_state *pins_uhs; 43520848903SChaotian Jing struct delayed_work req_timeout; 43620848903SChaotian Jing int irq; /* host interrupt */ 437855d388dSWenbin Mei struct reset_control *reset; 43820848903SChaotian Jing 43920848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 44020848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 441258bac4aSChaotian Jing struct clk *bus_clk; /* bus clock which used to access register */ 4423c1a8844SChaotian Jing struct clk *src_clk_cg; /* msdc source clock control gate */ 443f5eccd94SWenbin Mei struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 444f5eccd94SWenbin Mei struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 44520848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 44620848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 4476e622947SChaotian Jing unsigned char timing; 44820848903SChaotian Jing bool vqmmc_enabled; 449d17bb71cSChaotian Jing u32 latch_ck; 4506397b7f5SChaotian Jing u32 hs400_ds_delay; 4511ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 4521ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 4531ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 4541ede5cb8Syong mao /* cmd response sample selection for HS400 */ 4555462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 456d087bde5SNeilBrown bool internal_cd; /* Use internal card-detect logic */ 45788bd652bSChun-Hung Wu bool cqhci; /* support eMMC hw cmdq */ 4584b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 45986beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 46086beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 46188bd652bSChun-Hung Wu struct cqhci_host *cq_host; 46220848903SChaotian Jing }; 46320848903SChaotian Jing 464762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8135_compat = { 465762d491aSChaotian Jing .clk_div_bits = 8, 4669e2582e5Syong mao .recheck_sdio_irq = false, 4677f3d5852SChaotian Jing .hs400_tune = false, 46839add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4692fea5819SChaotian Jing .async_fifo = false, 4702fea5819SChaotian Jing .data_tune = false, 471acde28c4SChaotian Jing .busy_check = false, 472d9dcbfc8SChaotian Jing .stop_clk_fix = false, 473d9dcbfc8SChaotian Jing .enhance_rx = false, 4742a9bde19SChaotian Jing .support_64g = false, 475762d491aSChaotian Jing }; 476762d491aSChaotian Jing 477762d491aSChaotian Jing static const struct mtk_mmc_compatible mt8173_compat = { 478762d491aSChaotian Jing .clk_div_bits = 8, 4799e2582e5Syong mao .recheck_sdio_irq = true, 4807f3d5852SChaotian Jing .hs400_tune = true, 48139add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE, 4822fea5819SChaotian Jing .async_fifo = false, 4832fea5819SChaotian Jing .data_tune = false, 484acde28c4SChaotian Jing .busy_check = false, 485d9dcbfc8SChaotian Jing .stop_clk_fix = false, 486d9dcbfc8SChaotian Jing .enhance_rx = false, 4872a9bde19SChaotian Jing .support_64g = false, 488762d491aSChaotian Jing }; 489762d491aSChaotian Jing 490a2e6d1f6SChaotian Jing static const struct mtk_mmc_compatible mt8183_compat = { 491a2e6d1f6SChaotian Jing .clk_div_bits = 12, 4929e2582e5Syong mao .recheck_sdio_irq = false, 493a2e6d1f6SChaotian Jing .hs400_tune = false, 494a2e6d1f6SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 495a2e6d1f6SChaotian Jing .async_fifo = true, 496a2e6d1f6SChaotian Jing .data_tune = true, 497a2e6d1f6SChaotian Jing .busy_check = true, 498a2e6d1f6SChaotian Jing .stop_clk_fix = true, 499a2e6d1f6SChaotian Jing .enhance_rx = true, 500a2e6d1f6SChaotian Jing .support_64g = true, 501a2e6d1f6SChaotian Jing }; 502a2e6d1f6SChaotian Jing 503762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2701_compat = { 504762d491aSChaotian Jing .clk_div_bits = 12, 5059e2582e5Syong mao .recheck_sdio_irq = false, 5067f3d5852SChaotian Jing .hs400_tune = false, 50739add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5082fea5819SChaotian Jing .async_fifo = true, 5092fea5819SChaotian Jing .data_tune = true, 510acde28c4SChaotian Jing .busy_check = false, 511d9dcbfc8SChaotian Jing .stop_clk_fix = false, 512d9dcbfc8SChaotian Jing .enhance_rx = false, 5132a9bde19SChaotian Jing .support_64g = false, 514762d491aSChaotian Jing }; 515762d491aSChaotian Jing 516762d491aSChaotian Jing static const struct mtk_mmc_compatible mt2712_compat = { 517762d491aSChaotian Jing .clk_div_bits = 12, 5189e2582e5Syong mao .recheck_sdio_irq = false, 5197f3d5852SChaotian Jing .hs400_tune = false, 52039add252SChaotian Jing .pad_tune_reg = MSDC_PAD_TUNE0, 5212fea5819SChaotian Jing .async_fifo = true, 5222fea5819SChaotian Jing .data_tune = true, 523acde28c4SChaotian Jing .busy_check = true, 524d9dcbfc8SChaotian Jing .stop_clk_fix = true, 525d9dcbfc8SChaotian Jing .enhance_rx = true, 5262a9bde19SChaotian Jing .support_64g = true, 527762d491aSChaotian Jing }; 528762d491aSChaotian Jing 529966580adSSean Wang static const struct mtk_mmc_compatible mt7622_compat = { 530966580adSSean Wang .clk_div_bits = 12, 5319e2582e5Syong mao .recheck_sdio_irq = false, 532966580adSSean Wang .hs400_tune = false, 533966580adSSean Wang .pad_tune_reg = MSDC_PAD_TUNE0, 534966580adSSean Wang .async_fifo = true, 535966580adSSean Wang .data_tune = true, 536966580adSSean Wang .busy_check = true, 537966580adSSean Wang .stop_clk_fix = true, 538966580adSSean Wang .enhance_rx = true, 5392a9bde19SChaotian Jing .support_64g = false, 540966580adSSean Wang }; 541966580adSSean Wang 54289822b73SFabien Parent static const struct mtk_mmc_compatible mt8516_compat = { 54389822b73SFabien Parent .clk_div_bits = 12, 5449e2582e5Syong mao .recheck_sdio_irq = false, 54589822b73SFabien Parent .hs400_tune = false, 54689822b73SFabien Parent .pad_tune_reg = MSDC_PAD_TUNE0, 54789822b73SFabien Parent .async_fifo = true, 54889822b73SFabien Parent .data_tune = true, 54989822b73SFabien Parent .busy_check = true, 55089822b73SFabien Parent .stop_clk_fix = true, 55189822b73SFabien Parent }; 55289822b73SFabien Parent 553afb7c791SNeilBrown static const struct mtk_mmc_compatible mt7620_compat = { 554afb7c791SNeilBrown .clk_div_bits = 8, 5559e2582e5Syong mao .recheck_sdio_irq = false, 556afb7c791SNeilBrown .hs400_tune = false, 557afb7c791SNeilBrown .pad_tune_reg = MSDC_PAD_TUNE, 558afb7c791SNeilBrown .async_fifo = false, 559afb7c791SNeilBrown .data_tune = false, 560afb7c791SNeilBrown .busy_check = false, 561afb7c791SNeilBrown .stop_clk_fix = false, 562afb7c791SNeilBrown .enhance_rx = false, 563d087bde5SNeilBrown .use_internal_cd = true, 564afb7c791SNeilBrown }; 565afb7c791SNeilBrown 5667d176b0eSChun-Hung Wu static const struct mtk_mmc_compatible mt6779_compat = { 5677d176b0eSChun-Hung Wu .clk_div_bits = 12, 5687d176b0eSChun-Hung Wu .hs400_tune = false, 5697d176b0eSChun-Hung Wu .pad_tune_reg = MSDC_PAD_TUNE0, 5707d176b0eSChun-Hung Wu .async_fifo = true, 5717d176b0eSChun-Hung Wu .data_tune = true, 5727d176b0eSChun-Hung Wu .busy_check = true, 5737d176b0eSChun-Hung Wu .stop_clk_fix = true, 5747d176b0eSChun-Hung Wu .enhance_rx = true, 5757d176b0eSChun-Hung Wu .support_64g = true, 5767d176b0eSChun-Hung Wu }; 5777d176b0eSChun-Hung Wu 578762d491aSChaotian Jing static const struct of_device_id msdc_of_ids[] = { 579762d491aSChaotian Jing { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 580762d491aSChaotian Jing { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 581a2e6d1f6SChaotian Jing { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 582762d491aSChaotian Jing { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 583762d491aSChaotian Jing { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 584966580adSSean Wang { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 58589822b73SFabien Parent { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 586afb7c791SNeilBrown { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 5877d176b0eSChun-Hung Wu { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 588762d491aSChaotian Jing {} 589762d491aSChaotian Jing }; 590762d491aSChaotian Jing MODULE_DEVICE_TABLE(of, msdc_of_ids); 591762d491aSChaotian Jing 59220848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 59320848903SChaotian Jing { 59420848903SChaotian Jing u32 val = readl(reg); 59520848903SChaotian Jing 59620848903SChaotian Jing val |= bs; 59720848903SChaotian Jing writel(val, reg); 59820848903SChaotian Jing } 59920848903SChaotian Jing 60020848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 60120848903SChaotian Jing { 60220848903SChaotian Jing u32 val = readl(reg); 60320848903SChaotian Jing 60420848903SChaotian Jing val &= ~bs; 60520848903SChaotian Jing writel(val, reg); 60620848903SChaotian Jing } 60720848903SChaotian Jing 60820848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 60920848903SChaotian Jing { 61020848903SChaotian Jing unsigned int tv = readl(reg); 61120848903SChaotian Jing 61220848903SChaotian Jing tv &= ~field; 61320848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 61420848903SChaotian Jing writel(tv, reg); 61520848903SChaotian Jing } 61620848903SChaotian Jing 61720848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 61820848903SChaotian Jing { 61920848903SChaotian Jing unsigned int tv = readl(reg); 62020848903SChaotian Jing 62120848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 62220848903SChaotian Jing } 62320848903SChaotian Jing 62420848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 62520848903SChaotian Jing { 62620848903SChaotian Jing u32 val; 62720848903SChaotian Jing 62820848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 62920848903SChaotian Jing while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 63020848903SChaotian Jing cpu_relax(); 63120848903SChaotian Jing 63220848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 63320848903SChaotian Jing while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 63420848903SChaotian Jing cpu_relax(); 63520848903SChaotian Jing 63620848903SChaotian Jing val = readl(host->base + MSDC_INT); 63720848903SChaotian Jing writel(val, host->base + MSDC_INT); 63820848903SChaotian Jing } 63920848903SChaotian Jing 64020848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 64120848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 6429e2582e5Syong mao static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 64320848903SChaotian Jing 644726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 645726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 646726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 647726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 64820848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 64920848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 65020848903SChaotian Jing 65120848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 65220848903SChaotian Jing { 65320848903SChaotian Jing u32 i, sum = 0; 65420848903SChaotian Jing 65520848903SChaotian Jing for (i = 0; i < len; i++) 65620848903SChaotian Jing sum += buf[i]; 65720848903SChaotian Jing return 0xff - (u8) sum; 65820848903SChaotian Jing } 65920848903SChaotian Jing 66020848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 66120848903SChaotian Jing struct mmc_data *data) 66220848903SChaotian Jing { 66320848903SChaotian Jing unsigned int j, dma_len; 66420848903SChaotian Jing dma_addr_t dma_address; 66520848903SChaotian Jing u32 dma_ctrl; 66620848903SChaotian Jing struct scatterlist *sg; 66720848903SChaotian Jing struct mt_gpdma_desc *gpd; 66820848903SChaotian Jing struct mt_bdma_desc *bd; 66920848903SChaotian Jing 67020848903SChaotian Jing sg = data->sg; 67120848903SChaotian Jing 67220848903SChaotian Jing gpd = dma->gpd; 67320848903SChaotian Jing bd = dma->bd; 67420848903SChaotian Jing 67520848903SChaotian Jing /* modify gpd */ 67620848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 67720848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 67820848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 67920848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 68020848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 68120848903SChaotian Jing 68220848903SChaotian Jing /* modify bd */ 68320848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 68420848903SChaotian Jing dma_address = sg_dma_address(sg); 68520848903SChaotian Jing dma_len = sg_dma_len(sg); 68620848903SChaotian Jing 68720848903SChaotian Jing /* init bd */ 68820848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 68920848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 6902a9bde19SChaotian Jing bd[j].ptr = lower_32_bits(dma_address); 6912a9bde19SChaotian Jing if (host->dev_comp->support_64g) { 6922a9bde19SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 6932a9bde19SChaotian Jing bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 6942a9bde19SChaotian Jing << 28; 6952a9bde19SChaotian Jing } 6966ef042bdSChaotian Jing 6976ef042bdSChaotian Jing if (host->dev_comp->support_64g) { 6986ef042bdSChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 6996ef042bdSChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 7006ef042bdSChaotian Jing } else { 70120848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 70220848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 7036ef042bdSChaotian Jing } 70420848903SChaotian Jing 70520848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 70620848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 70720848903SChaotian Jing else 70820848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 70920848903SChaotian Jing 71020848903SChaotian Jing /* checksume need to clear first */ 71120848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 71220848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 71320848903SChaotian Jing } 71420848903SChaotian Jing 71520848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 71620848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 71720848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 71820848903SChaotian Jing dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 71920848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 7202a9bde19SChaotian Jing if (host->dev_comp->support_64g) 7212a9bde19SChaotian Jing sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 7222a9bde19SChaotian Jing upper_32_bits(dma->gpd_addr) & 0xf); 7232a9bde19SChaotian Jing writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 72420848903SChaotian Jing } 72520848903SChaotian Jing 72620848903SChaotian Jing static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 72720848903SChaotian Jing { 72820848903SChaotian Jing struct mmc_data *data = mrq->data; 72920848903SChaotian Jing 73020848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 73120848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 73220848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 733feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 73420848903SChaotian Jing } 73520848903SChaotian Jing } 73620848903SChaotian Jing 73720848903SChaotian Jing static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 73820848903SChaotian Jing { 73920848903SChaotian Jing struct mmc_data *data = mrq->data; 74020848903SChaotian Jing 74120848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 74220848903SChaotian Jing return; 74320848903SChaotian Jing 74420848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 74520848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 746feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 74720848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 74820848903SChaotian Jing } 74920848903SChaotian Jing } 75020848903SChaotian Jing 751557011b6SChun-Hung Wu static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 75220848903SChaotian Jing { 7530caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 754557011b6SChun-Hung Wu u64 timeout, clk_ns; 75520848903SChaotian Jing u32 mode = 0; 75620848903SChaotian Jing 7570caf60c4SAmey Narkhede if (mmc->actual_clock == 0) { 75820848903SChaotian Jing timeout = 0; 75920848903SChaotian Jing } else { 760557011b6SChun-Hung Wu clk_ns = 1000000000ULL; 7610caf60c4SAmey Narkhede do_div(clk_ns, mmc->actual_clock); 762557011b6SChun-Hung Wu timeout = ns + clk_ns - 1; 763557011b6SChun-Hung Wu do_div(timeout, clk_ns); 764557011b6SChun-Hung Wu timeout += clks; 76520848903SChaotian Jing /* in 1048576 sclk cycle unit */ 766557011b6SChun-Hung Wu timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 767762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 768762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 769762d491aSChaotian Jing MSDC_CFG_CKMOD, &mode); 770762d491aSChaotian Jing else 771762d491aSChaotian Jing sdr_get_field(host->base + MSDC_CFG, 772762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA, &mode); 77320848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 77420848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 77520848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 77620848903SChaotian Jing } 777557011b6SChun-Hung Wu return timeout; 778557011b6SChun-Hung Wu } 779557011b6SChun-Hung Wu 780557011b6SChun-Hung Wu /* clock control primitives */ 781557011b6SChun-Hung Wu static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 782557011b6SChun-Hung Wu { 783557011b6SChun-Hung Wu u64 timeout; 784557011b6SChun-Hung Wu 785557011b6SChun-Hung Wu host->timeout_ns = ns; 786557011b6SChun-Hung Wu host->timeout_clks = clks; 787557011b6SChun-Hung Wu 788557011b6SChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 789557011b6SChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 790557011b6SChun-Hung Wu (u32)(timeout > 255 ? 255 : timeout)); 79120848903SChaotian Jing } 79220848903SChaotian Jing 79388bd652bSChun-Hung Wu static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 79488bd652bSChun-Hung Wu { 79588bd652bSChun-Hung Wu u64 timeout; 79688bd652bSChun-Hung Wu 79788bd652bSChun-Hung Wu timeout = msdc_timeout_cal(host, ns, clks); 79888bd652bSChun-Hung Wu sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 79988bd652bSChun-Hung Wu (u32)(timeout > 8191 ? 8191 : timeout)); 80088bd652bSChun-Hung Wu } 80188bd652bSChun-Hung Wu 80220848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 80320848903SChaotian Jing { 804f5eccd94SWenbin Mei clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 8053c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 80620848903SChaotian Jing clk_disable_unprepare(host->src_clk); 807258bac4aSChaotian Jing clk_disable_unprepare(host->bus_clk); 80820848903SChaotian Jing clk_disable_unprepare(host->h_clk); 80920848903SChaotian Jing } 81020848903SChaotian Jing 81120848903SChaotian Jing static void msdc_ungate_clock(struct msdc_host *host) 81220848903SChaotian Jing { 813f5eccd94SWenbin Mei int ret; 814f5eccd94SWenbin Mei 81520848903SChaotian Jing clk_prepare_enable(host->h_clk); 816258bac4aSChaotian Jing clk_prepare_enable(host->bus_clk); 81720848903SChaotian Jing clk_prepare_enable(host->src_clk); 8183c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 819f5eccd94SWenbin Mei ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 820f5eccd94SWenbin Mei if (ret) { 821f5eccd94SWenbin Mei dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 822f5eccd94SWenbin Mei return; 823f5eccd94SWenbin Mei } 824f5eccd94SWenbin Mei 82520848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 82620848903SChaotian Jing cpu_relax(); 82720848903SChaotian Jing } 82820848903SChaotian Jing 8296e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 83020848903SChaotian Jing { 8310caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 83220848903SChaotian Jing u32 mode; 83320848903SChaotian Jing u32 flags; 83420848903SChaotian Jing u32 div; 83520848903SChaotian Jing u32 sclk; 83639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 83720848903SChaotian Jing 83820848903SChaotian Jing if (!hz) { 83920848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 84020848903SChaotian Jing host->mclk = 0; 8410caf60c4SAmey Narkhede mmc->actual_clock = 0; 84220848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 84320848903SChaotian Jing return; 84420848903SChaotian Jing } 84520848903SChaotian Jing 84620848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 84720848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 848762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8496397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 850762d491aSChaotian Jing else 851762d491aSChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, 852762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8536e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 8546397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 8556397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 8566397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 8576397b7f5SChaotian Jing mode = 0x3; 8586397b7f5SChaotian Jing else 85920848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 8606397b7f5SChaotian Jing 86120848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 86220848903SChaotian Jing div = 0; /* mean div = 1/4 */ 86320848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 86420848903SChaotian Jing } else { 86520848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 86620848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 86720848903SChaotian Jing div = (div >> 1); 86820848903SChaotian Jing } 8696397b7f5SChaotian Jing 8706397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 8716397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 872762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 8736397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 8746397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 875762d491aSChaotian Jing else 876762d491aSChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 877762d491aSChaotian Jing MSDC_CFG_HS400_CK_MODE_EXTRA); 8786397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 8796397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 8806397b7f5SChaotian Jing } 88120848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 88220848903SChaotian Jing mode = 0x1; /* no divisor */ 88320848903SChaotian Jing div = 0; 88420848903SChaotian Jing sclk = host->src_clk_freq; 88520848903SChaotian Jing } else { 88620848903SChaotian Jing mode = 0x0; /* use divisor */ 88720848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 88820848903SChaotian Jing div = 0; /* mean div = 1/2 */ 88920848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 89020848903SChaotian Jing } else { 89120848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 89220848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 89320848903SChaotian Jing } 89420848903SChaotian Jing } 8953c1a8844SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 8963c1a8844SChaotian Jing /* 8973c1a8844SChaotian Jing * As src_clk/HCLK use the same bit to gate/ungate, 8983c1a8844SChaotian Jing * So if want to only gate src_clk, need gate its parent(mux). 8993c1a8844SChaotian Jing */ 9003c1a8844SChaotian Jing if (host->src_clk_cg) 9013c1a8844SChaotian Jing clk_disable_unprepare(host->src_clk_cg); 9023c1a8844SChaotian Jing else 9033c1a8844SChaotian Jing clk_disable_unprepare(clk_get_parent(host->src_clk)); 904762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 905762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 906762d491aSChaotian Jing MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 90740ceda09Syong mao (mode << 8) | div); 908762d491aSChaotian Jing else 909762d491aSChaotian Jing sdr_set_field(host->base + MSDC_CFG, 910762d491aSChaotian Jing MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 911762d491aSChaotian Jing (mode << 12) | div); 9123c1a8844SChaotian Jing if (host->src_clk_cg) 9133c1a8844SChaotian Jing clk_prepare_enable(host->src_clk_cg); 9143c1a8844SChaotian Jing else 9153c1a8844SChaotian Jing clk_prepare_enable(clk_get_parent(host->src_clk)); 916762d491aSChaotian Jing 91720848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 91820848903SChaotian Jing cpu_relax(); 9193c1a8844SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 9200caf60c4SAmey Narkhede mmc->actual_clock = sclk; 92120848903SChaotian Jing host->mclk = hz; 9226e622947SChaotian Jing host->timing = timing; 92320848903SChaotian Jing /* need because clk changed. */ 92420848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 92520848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 92620848903SChaotian Jing 92786beac37SChaotian Jing /* 92886beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 92986beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 93086beac37SChaotian Jing */ 9310caf60c4SAmey Narkhede if (mmc->actual_clock <= 52000000) { 93286beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 933a2e6d1f6SChaotian Jing if (host->top_base) { 934a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_control, 935a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 936a2e6d1f6SChaotian Jing writel(host->def_tune_para.emmc_top_cmd, 937a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 938a2e6d1f6SChaotian Jing } else { 939a2e6d1f6SChaotian Jing writel(host->def_tune_para.pad_tune, 940a2e6d1f6SChaotian Jing host->base + tune_reg); 941a2e6d1f6SChaotian Jing } 94286beac37SChaotian Jing } else { 94386beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 9441ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 9451ede5cb8Syong mao host->base + PAD_CMD_TUNE); 946a2e6d1f6SChaotian Jing if (host->top_base) { 947a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_control, 948a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 949a2e6d1f6SChaotian Jing writel(host->saved_tune_para.emmc_top_cmd, 950a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 951a2e6d1f6SChaotian Jing } else { 952a2e6d1f6SChaotian Jing writel(host->saved_tune_para.pad_tune, 953a2e6d1f6SChaotian Jing host->base + tune_reg); 954a2e6d1f6SChaotian Jing } 95586beac37SChaotian Jing } 95686beac37SChaotian Jing 9577f3d5852SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 9587f3d5852SChaotian Jing host->dev_comp->hs400_tune) 9593751e008SChaotian Jing sdr_set_field(host->base + tune_reg, 9601ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 9611ede5cb8Syong mao host->hs400_cmd_int_delay); 9620caf60c4SAmey Narkhede dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 96356f6cbbeSChaotian Jing timing); 96420848903SChaotian Jing } 96520848903SChaotian Jing 96620848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 96720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 96820848903SChaotian Jing { 96920848903SChaotian Jing u32 resp; 97020848903SChaotian Jing 97120848903SChaotian Jing switch (mmc_resp_type(cmd)) { 97220848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 97320848903SChaotian Jing case MMC_RSP_R1: 97420848903SChaotian Jing resp = 0x1; 97520848903SChaotian Jing break; 97620848903SChaotian Jing case MMC_RSP_R1B: 97720848903SChaotian Jing resp = 0x7; 97820848903SChaotian Jing break; 97920848903SChaotian Jing case MMC_RSP_R2: 98020848903SChaotian Jing resp = 0x2; 98120848903SChaotian Jing break; 98220848903SChaotian Jing case MMC_RSP_R3: 98320848903SChaotian Jing resp = 0x3; 98420848903SChaotian Jing break; 98520848903SChaotian Jing case MMC_RSP_NONE: 98620848903SChaotian Jing default: 98720848903SChaotian Jing resp = 0x0; 98820848903SChaotian Jing break; 98920848903SChaotian Jing } 99020848903SChaotian Jing 99120848903SChaotian Jing return resp; 99220848903SChaotian Jing } 99320848903SChaotian Jing 99420848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 99520848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 99620848903SChaotian Jing { 9970caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 99820848903SChaotian Jing /* rawcmd : 99920848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 100020848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 100120848903SChaotian Jing */ 100220848903SChaotian Jing u32 opcode = cmd->opcode; 100320848903SChaotian Jing u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 100420848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 100520848903SChaotian Jing 100620848903SChaotian Jing host->cmd_rsp = resp; 100720848903SChaotian Jing 100820848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 100920848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 101020848903SChaotian Jing rawcmd |= (0x1 << 14); 101120848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 101220848903SChaotian Jing rawcmd |= (0x1 << 30); 101320848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 101420848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 101520848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 101620848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 101720848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 101820848903SChaotian Jing rawcmd |= (0x1 << 11); 101920848903SChaotian Jing 102020848903SChaotian Jing if (cmd->data) { 102120848903SChaotian Jing struct mmc_data *data = cmd->data; 102220848903SChaotian Jing 102320848903SChaotian Jing if (mmc_op_multi(opcode)) { 10240caf60c4SAmey Narkhede if (mmc_card_mmc(mmc->card) && mrq->sbc && 102520848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 102620848903SChaotian Jing rawcmd |= 0x2 << 28; /* AutoCMD23 */ 102720848903SChaotian Jing } 102820848903SChaotian Jing 102920848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 103020848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 103120848903SChaotian Jing rawcmd |= (0x1 << 13); 103220848903SChaotian Jing if (data->blocks > 1) 103320848903SChaotian Jing rawcmd |= (0x2 << 11); 103420848903SChaotian Jing else 103520848903SChaotian Jing rawcmd |= (0x1 << 11); 103620848903SChaotian Jing /* Always use dma mode */ 103720848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 103820848903SChaotian Jing 103920848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 104020848903SChaotian Jing host->timeout_clks != data->timeout_clks) 104120848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 104220848903SChaotian Jing data->timeout_clks); 104320848903SChaotian Jing 104420848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 104520848903SChaotian Jing } 104620848903SChaotian Jing return rawcmd; 104720848903SChaotian Jing } 104820848903SChaotian Jing 104920848903SChaotian Jing static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 105020848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 105120848903SChaotian Jing { 105220848903SChaotian Jing bool read; 105320848903SChaotian Jing 105420848903SChaotian Jing WARN_ON(host->data); 105520848903SChaotian Jing host->data = data; 105620848903SChaotian Jing read = data->flags & MMC_DATA_READ; 105720848903SChaotian Jing 105820848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 105920848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 106020848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 106120848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 106220848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 106320848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 106420848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 106520848903SChaotian Jing } 106620848903SChaotian Jing 106720848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 106820848903SChaotian Jing struct mmc_command *cmd) 106920848903SChaotian Jing { 107020848903SChaotian Jing u32 *rsp = cmd->resp; 107120848903SChaotian Jing 107220848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 107320848903SChaotian Jing 107420848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 107520848903SChaotian Jing cmd->error = 0; 107620848903SChaotian Jing } else { 107720848903SChaotian Jing msdc_reset_hw(host); 107820848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 107920848903SChaotian Jing cmd->error = -EILSEQ; 108020848903SChaotian Jing host->error |= REQ_STOP_EIO; 108120848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 108220848903SChaotian Jing cmd->error = -ETIMEDOUT; 108320848903SChaotian Jing host->error |= REQ_STOP_TMO; 108420848903SChaotian Jing } 108520848903SChaotian Jing dev_err(host->dev, 108620848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 108720848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 108820848903SChaotian Jing } 108920848903SChaotian Jing return cmd->error; 109020848903SChaotian Jing } 109120848903SChaotian Jing 10926ec5a7b7SLee Jones /* 10939e2582e5Syong mao * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 10949e2582e5Syong mao * 10959e2582e5Syong mao * Host controller may lost interrupt in some special case. 10969e2582e5Syong mao * Add SDIO irq recheck mechanism to make sure all interrupts 10979e2582e5Syong mao * can be processed immediately 10989e2582e5Syong mao */ 10999e2582e5Syong mao static void msdc_recheck_sdio_irq(struct msdc_host *host) 11009e2582e5Syong mao { 11010caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 11029e2582e5Syong mao u32 reg_int, reg_inten, reg_ps; 11039e2582e5Syong mao 11040caf60c4SAmey Narkhede if (mmc->caps & MMC_CAP_SDIO_IRQ) { 11059e2582e5Syong mao reg_inten = readl(host->base + MSDC_INTEN); 11069e2582e5Syong mao if (reg_inten & MSDC_INTEN_SDIOIRQ) { 11079e2582e5Syong mao reg_int = readl(host->base + MSDC_INT); 11089e2582e5Syong mao reg_ps = readl(host->base + MSDC_PS); 11099e2582e5Syong mao if (!(reg_int & MSDC_INT_SDIOIRQ || 11109e2582e5Syong mao reg_ps & MSDC_PS_DATA1)) { 11119e2582e5Syong mao __msdc_enable_sdio_irq(host, 0); 11120caf60c4SAmey Narkhede sdio_signal_irq(mmc); 11139e2582e5Syong mao } 11149e2582e5Syong mao } 11159e2582e5Syong mao } 11169e2582e5Syong mao } 11179e2582e5Syong mao 111820848903SChaotian Jing static void msdc_track_cmd_data(struct msdc_host *host, 111920848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 112020848903SChaotian Jing { 112120848903SChaotian Jing if (host->error) 112220848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 112320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 112420848903SChaotian Jing } 112520848903SChaotian Jing 112620848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 112720848903SChaotian Jing { 112820848903SChaotian Jing unsigned long flags; 112920848903SChaotian Jing bool ret; 113020848903SChaotian Jing 113120848903SChaotian Jing ret = cancel_delayed_work(&host->req_timeout); 113220848903SChaotian Jing if (!ret) { 113320848903SChaotian Jing /* delay work already running */ 113420848903SChaotian Jing return; 113520848903SChaotian Jing } 113620848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 113720848903SChaotian Jing host->mrq = NULL; 113820848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 113920848903SChaotian Jing 114020848903SChaotian Jing msdc_track_cmd_data(host, mrq->cmd, mrq->data); 114120848903SChaotian Jing if (mrq->data) 114220848903SChaotian Jing msdc_unprepare_data(host, mrq); 114320314ce3Sjjian zhou if (host->error) 114420314ce3Sjjian zhou msdc_reset_hw(host); 11450caf60c4SAmey Narkhede mmc_request_done(mmc_from_priv(host), mrq); 11469e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 11479e2582e5Syong mao msdc_recheck_sdio_irq(host); 114820848903SChaotian Jing } 114920848903SChaotian Jing 115020848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 115120848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 115220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 115320848903SChaotian Jing { 115420848903SChaotian Jing bool done = false; 115520848903SChaotian Jing bool sbc_error; 115620848903SChaotian Jing unsigned long flags; 115720848903SChaotian Jing u32 *rsp = cmd->resp; 115820848903SChaotian Jing 115920848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 116020848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 116120848903SChaotian Jing | MSDC_INT_ACMDTMO))) 116220848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 116320848903SChaotian Jing 116420848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 116520848903SChaotian Jing 116620848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 116720848903SChaotian Jing | MSDC_INT_RSPCRCERR 116820848903SChaotian Jing | MSDC_INT_CMDTMO))) 116920848903SChaotian Jing return done; 117020848903SChaotian Jing 117120848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 117220848903SChaotian Jing done = !host->cmd; 117320848903SChaotian Jing host->cmd = NULL; 117420848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 117520848903SChaotian Jing 117620848903SChaotian Jing if (done) 117720848903SChaotian Jing return true; 117820848903SChaotian Jing 1179726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 118020848903SChaotian Jing 118120848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 118220848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 118320848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 118420848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 118520848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 118620848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 118720848903SChaotian Jing } else { 118820848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 118920848903SChaotian Jing } 119020848903SChaotian Jing } 119120848903SChaotian Jing 119220848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1193da6e0f70SChaotian Jing if (events & MSDC_INT_CMDTMO || 1194da6e0f70SChaotian Jing (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1195da6e0f70SChaotian Jing cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1196ddc71387SChaotian Jing /* 1197ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 1198da6e0f70SChaotian Jing * may have alreay come when cmd19/cmd21 gets response 1199da6e0f70SChaotian Jing * CRC error. 1200ddc71387SChaotian Jing */ 120120848903SChaotian Jing msdc_reset_hw(host); 120220848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 120320848903SChaotian Jing cmd->error = -EILSEQ; 120420848903SChaotian Jing host->error |= REQ_CMD_EIO; 120520848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 120620848903SChaotian Jing cmd->error = -ETIMEDOUT; 120720848903SChaotian Jing host->error |= REQ_CMD_TMO; 120820848903SChaotian Jing } 120920848903SChaotian Jing } 121020848903SChaotian Jing if (cmd->error) 121120848903SChaotian Jing dev_dbg(host->dev, 121220848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 121320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 121420848903SChaotian Jing cmd->error); 121520848903SChaotian Jing 121620848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 121720848903SChaotian Jing return true; 121820848903SChaotian Jing } 121920848903SChaotian Jing 122020848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 122120848903SChaotian Jing * is correct before issue a request. but host design do below 122220848903SChaotian Jing * checks recommended. 122320848903SChaotian Jing */ 122420848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 122520848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 122620848903SChaotian Jing { 122720848903SChaotian Jing /* The max busy time we can endure is 20ms */ 122820848903SChaotian Jing unsigned long tmo = jiffies + msecs_to_jiffies(20); 122920848903SChaotian Jing 123020848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 123120848903SChaotian Jing time_before(jiffies, tmo)) 123220848903SChaotian Jing cpu_relax(); 123320848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 123420848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 123520848903SChaotian Jing host->error |= REQ_CMD_BUSY; 123620848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 123720848903SChaotian Jing return false; 123820848903SChaotian Jing } 123920848903SChaotian Jing 124020848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 124120848903SChaotian Jing tmo = jiffies + msecs_to_jiffies(20); 124220848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 124320848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 124420848903SChaotian Jing time_before(jiffies, tmo)) 124520848903SChaotian Jing cpu_relax(); 124620848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 124720848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 124820848903SChaotian Jing host->error |= REQ_CMD_BUSY; 124920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 125020848903SChaotian Jing return false; 125120848903SChaotian Jing } 125220848903SChaotian Jing } 125320848903SChaotian Jing return true; 125420848903SChaotian Jing } 125520848903SChaotian Jing 125620848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 125720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 125820848903SChaotian Jing { 125920848903SChaotian Jing u32 rawcmd; 12605215b2e9Sjjian zhou unsigned long flags; 126120848903SChaotian Jing 126220848903SChaotian Jing WARN_ON(host->cmd); 126320848903SChaotian Jing host->cmd = cmd; 126420848903SChaotian Jing 1265f38a9774SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 126620848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 126720848903SChaotian Jing return; 126820848903SChaotian Jing 126920848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 127020848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 127120848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 127220848903SChaotian Jing msdc_reset_hw(host); 127320848903SChaotian Jing } 127420848903SChaotian Jing 127520848903SChaotian Jing cmd->error = 0; 127620848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 127720848903SChaotian Jing 12785215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 1279726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 12805215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 12815215b2e9Sjjian zhou 128220848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 128320848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 128420848903SChaotian Jing } 128520848903SChaotian Jing 128620848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 128720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 128820848903SChaotian Jing { 1289ddc71387SChaotian Jing if ((cmd->error && 1290ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 1291ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1292ddc71387SChaotian Jing cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1293ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 129420848903SChaotian Jing msdc_request_done(host, mrq); 129520848903SChaotian Jing else if (cmd == mrq->sbc) 129620848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 129720848903SChaotian Jing else if (!cmd->data) 129820848903SChaotian Jing msdc_request_done(host, mrq); 129920848903SChaotian Jing else 130020848903SChaotian Jing msdc_start_data(host, mrq, cmd, cmd->data); 130120848903SChaotian Jing } 130220848903SChaotian Jing 130320848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 130420848903SChaotian Jing { 130520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 130620848903SChaotian Jing 130720848903SChaotian Jing host->error = 0; 130820848903SChaotian Jing WARN_ON(host->mrq); 130920848903SChaotian Jing host->mrq = mrq; 131020848903SChaotian Jing 131120848903SChaotian Jing if (mrq->data) 131220848903SChaotian Jing msdc_prepare_data(host, mrq); 131320848903SChaotian Jing 131420848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 131520848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 131620848903SChaotian Jing * use HW option, otherwise use SW option 131720848903SChaotian Jing */ 131820848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 131920848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 132020848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 132120848903SChaotian Jing else 132220848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 132320848903SChaotian Jing } 132420848903SChaotian Jing 1325d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 132620848903SChaotian Jing { 132720848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 132820848903SChaotian Jing struct mmc_data *data = mrq->data; 132920848903SChaotian Jing 133020848903SChaotian Jing if (!data) 133120848903SChaotian Jing return; 133220848903SChaotian Jing 133320848903SChaotian Jing msdc_prepare_data(host, mrq); 133420848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 133520848903SChaotian Jing } 133620848903SChaotian Jing 133720848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 133820848903SChaotian Jing int err) 133920848903SChaotian Jing { 134020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 134120848903SChaotian Jing struct mmc_data *data; 134220848903SChaotian Jing 134320848903SChaotian Jing data = mrq->data; 134420848903SChaotian Jing if (!data) 134520848903SChaotian Jing return; 134620848903SChaotian Jing if (data->host_cookie) { 134720848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 134820848903SChaotian Jing msdc_unprepare_data(host, mrq); 134920848903SChaotian Jing } 135020848903SChaotian Jing } 135120848903SChaotian Jing 135220848903SChaotian Jing static void msdc_data_xfer_next(struct msdc_host *host, 135320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 135420848903SChaotian Jing { 135520848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 13566397b7f5SChaotian Jing !mrq->sbc) 135720848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 135820848903SChaotian Jing else 135920848903SChaotian Jing msdc_request_done(host, mrq); 136020848903SChaotian Jing } 136120848903SChaotian Jing 136220848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 136320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 136420848903SChaotian Jing { 136520848903SChaotian Jing struct mmc_command *stop = data->stop; 136620848903SChaotian Jing unsigned long flags; 136720848903SChaotian Jing bool done; 136820848903SChaotian Jing unsigned int check_data = events & 136920848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 137020848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 137120848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 137220848903SChaotian Jing 137320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 137420848903SChaotian Jing done = !host->data; 137520848903SChaotian Jing if (check_data) 137620848903SChaotian Jing host->data = NULL; 137720848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 137820848903SChaotian Jing 137920848903SChaotian Jing if (done) 138020848903SChaotian Jing return true; 138120848903SChaotian Jing 138220848903SChaotian Jing if (check_data || (stop && stop->error)) { 138320848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 138420848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 138520848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 138620848903SChaotian Jing 1); 138720848903SChaotian Jing while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 138820848903SChaotian Jing cpu_relax(); 138920848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 139020848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 139120848903SChaotian Jing 139220848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 139320848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 139420848903SChaotian Jing } else { 13952066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 139620848903SChaotian Jing msdc_reset_hw(host); 139720848903SChaotian Jing host->error |= REQ_DAT_ERR; 139820848903SChaotian Jing data->bytes_xfered = 0; 139920848903SChaotian Jing 140020848903SChaotian Jing if (events & MSDC_INT_DATTMO) 140120848903SChaotian Jing data->error = -ETIMEDOUT; 14026397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 14036397b7f5SChaotian Jing data->error = -EILSEQ; 140420848903SChaotian Jing 14052066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 140620848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 14072066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 140820848903SChaotian Jing (int)data->error, data->bytes_xfered); 140920848903SChaotian Jing } 141020848903SChaotian Jing 141120848903SChaotian Jing msdc_data_xfer_next(host, mrq, data); 141220848903SChaotian Jing done = true; 141320848903SChaotian Jing } 141420848903SChaotian Jing return done; 141520848903SChaotian Jing } 141620848903SChaotian Jing 141720848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 141820848903SChaotian Jing { 141920848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 142020848903SChaotian Jing 142120848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 142220848903SChaotian Jing 142320848903SChaotian Jing switch (width) { 142420848903SChaotian Jing default: 142520848903SChaotian Jing case MMC_BUS_WIDTH_1: 142620848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 142720848903SChaotian Jing break; 142820848903SChaotian Jing case MMC_BUS_WIDTH_4: 142920848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 143020848903SChaotian Jing break; 143120848903SChaotian Jing case MMC_BUS_WIDTH_8: 143220848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 143320848903SChaotian Jing break; 143420848903SChaotian Jing } 143520848903SChaotian Jing 143620848903SChaotian Jing writel(val, host->base + SDC_CFG); 143720848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 143820848903SChaotian Jing } 143920848903SChaotian Jing 144020848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 144120848903SChaotian Jing { 144220848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14439cbe0fc8SMarek Vasut int ret; 144420848903SChaotian Jing 144520848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1446fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1447fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 144820848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 144920848903SChaotian Jing return -EINVAL; 145020848903SChaotian Jing } 145120848903SChaotian Jing 1452fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 14539cbe0fc8SMarek Vasut if (ret < 0) { 1454fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1455fac49ce5SNicolas Boichat ret, ios->signal_voltage); 14569cbe0fc8SMarek Vasut return ret; 14579cbe0fc8SMarek Vasut } 14589cbe0fc8SMarek Vasut 145920848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 146020848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 146120848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 146220848903SChaotian Jing else 146320848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 146420848903SChaotian Jing } 14659cbe0fc8SMarek Vasut return 0; 146620848903SChaotian Jing } 146720848903SChaotian Jing 146820848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 146920848903SChaotian Jing { 147020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 147120848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 147220848903SChaotian Jing 14733bc702edSyong mao /* only check if data0 is low */ 14743bc702edSyong mao return !(status & BIT(16)); 147520848903SChaotian Jing } 147620848903SChaotian Jing 147720848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 147820848903SChaotian Jing { 147920848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 148020848903SChaotian Jing req_timeout.work); 148120848903SChaotian Jing 148220848903SChaotian Jing /* simulate HW timeout status */ 148320848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 148420848903SChaotian Jing if (host->mrq) { 148520848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 148620848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 148720848903SChaotian Jing if (host->cmd) { 148820848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 148920848903SChaotian Jing __func__, host->cmd->opcode); 149020848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 149120848903SChaotian Jing host->cmd); 149220848903SChaotian Jing } else if (host->data) { 149320848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 149420848903SChaotian Jing __func__, host->mrq->cmd->opcode, 149520848903SChaotian Jing host->data->blocks); 149620848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 149720848903SChaotian Jing host->data); 149820848903SChaotian Jing } 149920848903SChaotian Jing } 150020848903SChaotian Jing } 150120848903SChaotian Jing 15028a5df8acSjjian zhou static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 15038a5df8acSjjian zhou { 15048a5df8acSjjian zhou if (enb) { 15058a5df8acSjjian zhou sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15068a5df8acSjjian zhou sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15079e2582e5Syong mao if (host->dev_comp->recheck_sdio_irq) 15089e2582e5Syong mao msdc_recheck_sdio_irq(host); 15098a5df8acSjjian zhou } else { 15108a5df8acSjjian zhou sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 15118a5df8acSjjian zhou sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 15128a5df8acSjjian zhou } 15138a5df8acSjjian zhou } 15148a5df8acSjjian zhou 15158a5df8acSjjian zhou static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 15165215b2e9Sjjian zhou { 15175215b2e9Sjjian zhou unsigned long flags; 15185215b2e9Sjjian zhou struct msdc_host *host = mmc_priv(mmc); 15195215b2e9Sjjian zhou 15205215b2e9Sjjian zhou spin_lock_irqsave(&host->lock, flags); 15218a5df8acSjjian zhou __msdc_enable_sdio_irq(host, enb); 15225215b2e9Sjjian zhou spin_unlock_irqrestore(&host->lock, flags); 15235215b2e9Sjjian zhou 15245215b2e9Sjjian zhou if (enb) 15255215b2e9Sjjian zhou pm_runtime_get_noresume(host->dev); 15265215b2e9Sjjian zhou else 15275215b2e9Sjjian zhou pm_runtime_put_noidle(host->dev); 15285215b2e9Sjjian zhou } 15295215b2e9Sjjian zhou 153088bd652bSChun-Hung Wu static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 153188bd652bSChun-Hung Wu { 15320caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 153388bd652bSChun-Hung Wu int cmd_err = 0, dat_err = 0; 153488bd652bSChun-Hung Wu 153588bd652bSChun-Hung Wu if (intsts & MSDC_INT_RSPCRCERR) { 153688bd652bSChun-Hung Wu cmd_err = -EILSEQ; 153788bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD CRC ERR", __func__); 153888bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_CMDTMO) { 153988bd652bSChun-Hung Wu cmd_err = -ETIMEDOUT; 154088bd652bSChun-Hung Wu dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 154188bd652bSChun-Hung Wu } 154288bd652bSChun-Hung Wu 154388bd652bSChun-Hung Wu if (intsts & MSDC_INT_DATCRCERR) { 154488bd652bSChun-Hung Wu dat_err = -EILSEQ; 154588bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA CRC ERR", __func__); 154688bd652bSChun-Hung Wu } else if (intsts & MSDC_INT_DATTMO) { 154788bd652bSChun-Hung Wu dat_err = -ETIMEDOUT; 154888bd652bSChun-Hung Wu dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 154988bd652bSChun-Hung Wu } 155088bd652bSChun-Hung Wu 155188bd652bSChun-Hung Wu if (cmd_err || dat_err) { 155288bd652bSChun-Hung Wu dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 155388bd652bSChun-Hung Wu cmd_err, dat_err, intsts); 155488bd652bSChun-Hung Wu } 155588bd652bSChun-Hung Wu 15560caf60c4SAmey Narkhede return cqhci_irq(mmc, 0, cmd_err, dat_err); 155788bd652bSChun-Hung Wu } 155888bd652bSChun-Hung Wu 155920848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 156020848903SChaotian Jing { 156120848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 15620caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 156320848903SChaotian Jing 156420848903SChaotian Jing while (true) { 156520848903SChaotian Jing struct mmc_request *mrq; 156620848903SChaotian Jing struct mmc_command *cmd; 156720848903SChaotian Jing struct mmc_data *data; 156820848903SChaotian Jing u32 events, event_mask; 156920848903SChaotian Jing 15709baf7c5eSTian Tao spin_lock(&host->lock); 157120848903SChaotian Jing events = readl(host->base + MSDC_INT); 157220848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 15738a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 15748a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 0); 157520848903SChaotian Jing /* clear interrupts */ 157620848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 157720848903SChaotian Jing 157820848903SChaotian Jing mrq = host->mrq; 157920848903SChaotian Jing cmd = host->cmd; 158020848903SChaotian Jing data = host->data; 15819baf7c5eSTian Tao spin_unlock(&host->lock); 158220848903SChaotian Jing 15838a5df8acSjjian zhou if ((events & event_mask) & MSDC_INT_SDIOIRQ) 15840caf60c4SAmey Narkhede sdio_signal_irq(mmc); 15855215b2e9Sjjian zhou 1586d087bde5SNeilBrown if ((events & event_mask) & MSDC_INT_CDSC) { 1587d087bde5SNeilBrown if (host->internal_cd) 15880caf60c4SAmey Narkhede mmc_detect_change(mmc, msecs_to_jiffies(20)); 1589d087bde5SNeilBrown events &= ~MSDC_INT_CDSC; 1590d087bde5SNeilBrown } 1591d087bde5SNeilBrown 15925215b2e9Sjjian zhou if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 159320848903SChaotian Jing break; 159420848903SChaotian Jing 15950caf60c4SAmey Narkhede if ((mmc->caps2 & MMC_CAP2_CQE) && 159688bd652bSChun-Hung Wu (events & MSDC_INT_CMDQ)) { 159788bd652bSChun-Hung Wu msdc_cmdq_irq(host, events); 159888bd652bSChun-Hung Wu /* clear interrupts */ 159988bd652bSChun-Hung Wu writel(events, host->base + MSDC_INT); 160088bd652bSChun-Hung Wu return IRQ_HANDLED; 160188bd652bSChun-Hung Wu } 160288bd652bSChun-Hung Wu 160320848903SChaotian Jing if (!mrq) { 160420848903SChaotian Jing dev_err(host->dev, 160520848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 160620848903SChaotian Jing __func__, events, event_mask); 160720848903SChaotian Jing WARN_ON(1); 160820848903SChaotian Jing break; 160920848903SChaotian Jing } 161020848903SChaotian Jing 161120848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 161220848903SChaotian Jing 161320848903SChaotian Jing if (cmd) 161420848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 161520848903SChaotian Jing else if (data) 161620848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 161720848903SChaotian Jing } 161820848903SChaotian Jing 161920848903SChaotian Jing return IRQ_HANDLED; 162020848903SChaotian Jing } 162120848903SChaotian Jing 162220848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 162320848903SChaotian Jing { 162420848903SChaotian Jing u32 val; 162539add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 162620848903SChaotian Jing 1627855d388dSWenbin Mei if (host->reset) { 1628855d388dSWenbin Mei reset_control_assert(host->reset); 1629855d388dSWenbin Mei usleep_range(10, 50); 1630855d388dSWenbin Mei reset_control_deassert(host->reset); 1631855d388dSWenbin Mei } 1632855d388dSWenbin Mei 163320848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 163420848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 163520848903SChaotian Jing 163620848903SChaotian Jing /* Reset */ 163720848903SChaotian Jing msdc_reset_hw(host); 163820848903SChaotian Jing 163920848903SChaotian Jing /* Disable and clear all interrupts */ 164020848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 164120848903SChaotian Jing val = readl(host->base + MSDC_INT); 164220848903SChaotian Jing writel(val, host->base + MSDC_INT); 164320848903SChaotian Jing 1644d087bde5SNeilBrown /* Configure card detection */ 1645d087bde5SNeilBrown if (host->internal_cd) { 1646d087bde5SNeilBrown sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1647d087bde5SNeilBrown DEFAULT_DEBOUNCE); 1648d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1649d087bde5SNeilBrown sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1650d087bde5SNeilBrown sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1651d087bde5SNeilBrown } else { 1652d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1653d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1654d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1655d087bde5SNeilBrown } 1656d087bde5SNeilBrown 1657a2e6d1f6SChaotian Jing if (host->top_base) { 1658a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CONTROL); 1659a2e6d1f6SChaotian Jing writel(0, host->top_base + EMMC_TOP_CMD); 1660a2e6d1f6SChaotian Jing } else { 166139add252SChaotian Jing writel(0, host->base + tune_reg); 1662a2e6d1f6SChaotian Jing } 166320848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 16646397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 16656397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 166620848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 16672fea5819SChaotian Jing writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 16686397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1669d9dcbfc8SChaotian Jing 1670d9dcbfc8SChaotian Jing if (host->dev_comp->stop_clk_fix) { 1671d9dcbfc8SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, 1672d9dcbfc8SChaotian Jing MSDC_PATCH_BIT1_STOP_DLY, 3); 1673d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1674d9dcbfc8SChaotian Jing SDC_FIFO_CFG_WRVALIDSEL); 1675d9dcbfc8SChaotian Jing sdr_clr_bits(host->base + SDC_FIFO_CFG, 1676d9dcbfc8SChaotian Jing SDC_FIFO_CFG_RDVALIDSEL); 1677d9dcbfc8SChaotian Jing } 1678d9dcbfc8SChaotian Jing 1679acde28c4SChaotian Jing if (host->dev_comp->busy_check) 1680acde28c4SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1681d9dcbfc8SChaotian Jing 16822fea5819SChaotian Jing if (host->dev_comp->async_fifo) { 16832fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16842fea5819SChaotian Jing MSDC_PB2_RESPWAIT, 3); 1685d9dcbfc8SChaotian Jing if (host->dev_comp->enhance_rx) { 1686a2e6d1f6SChaotian Jing if (host->top_base) 1687a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1688a2e6d1f6SChaotian Jing SDC_RX_ENH_EN); 1689a2e6d1f6SChaotian Jing else 1690d9dcbfc8SChaotian Jing sdr_set_bits(host->base + SDC_ADV_CFG0, 1691d9dcbfc8SChaotian Jing SDC_RX_ENHANCE_EN); 1692d9dcbfc8SChaotian Jing } else { 16932fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16942fea5819SChaotian Jing MSDC_PB2_RESPSTSENSEL, 2); 16952fea5819SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT2, 16962fea5819SChaotian Jing MSDC_PB2_CRCSTSENSEL, 2); 1697d9dcbfc8SChaotian Jing } 16982fea5819SChaotian Jing /* use async fifo, then no need tune internal delay */ 16992fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 17002fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGRESP); 17012fea5819SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17022fea5819SChaotian Jing MSDC_PATCH_BIT2_CFGCRCSTS); 17032fea5819SChaotian Jing } 17042fea5819SChaotian Jing 17052a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17062a9bde19SChaotian Jing sdr_set_bits(host->base + MSDC_PATCH_BIT2, 17072a9bde19SChaotian Jing MSDC_PB2_SUPPORT_64G); 17082fea5819SChaotian Jing if (host->dev_comp->data_tune) { 1709a2e6d1f6SChaotian Jing if (host->top_base) { 1710a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1711a2e6d1f6SChaotian Jing PAD_DAT_RD_RXDLY_SEL); 1712a2e6d1f6SChaotian Jing sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1713a2e6d1f6SChaotian Jing DATA_K_VALUE_SEL); 1714a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1715a2e6d1f6SChaotian Jing PAD_CMD_RD_RXDLY_SEL); 1716a2e6d1f6SChaotian Jing } else { 17172fea5819SChaotian Jing sdr_set_bits(host->base + tune_reg, 1718a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RD_SEL | 1719a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_CMD_SEL); 1720a2e6d1f6SChaotian Jing } 17212fea5819SChaotian Jing } else { 17222fea5819SChaotian Jing /* choose clock tune */ 1723a2e6d1f6SChaotian Jing if (host->top_base) 1724a2e6d1f6SChaotian Jing sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1725a2e6d1f6SChaotian Jing PAD_RXDLY_SEL); 1726a2e6d1f6SChaotian Jing else 1727a2e6d1f6SChaotian Jing sdr_set_bits(host->base + tune_reg, 1728a2e6d1f6SChaotian Jing MSDC_PAD_TUNE_RXDLYSEL); 17292fea5819SChaotian Jing } 17306397b7f5SChaotian Jing 173120848903SChaotian Jing /* Configure to enable SDIO mode. 173220848903SChaotian Jing * it's must otherwise sdio cmd5 failed 173320848903SChaotian Jing */ 173420848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 173520848903SChaotian Jing 17365215b2e9Sjjian zhou /* Config SDIO device detect interrupt function */ 173720848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 173826c71a13Syong mao sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 173920848903SChaotian Jing 174020848903SChaotian Jing /* Configure to default data timeout */ 174120848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 174220848903SChaotian Jing 174386beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 17442fea5819SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1745a2e6d1f6SChaotian Jing if (host->top_base) { 1746a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_control = 1747a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1748a2e6d1f6SChaotian Jing host->def_tune_para.emmc_top_cmd = 1749a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1750a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = 1751a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 1752a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = 1753a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 1754a2e6d1f6SChaotian Jing } else { 1755a2e6d1f6SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + tune_reg); 17562fea5819SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1757a2e6d1f6SChaotian Jing } 175820848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 175920848903SChaotian Jing } 176020848903SChaotian Jing 176120848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 176220848903SChaotian Jing { 176320848903SChaotian Jing u32 val; 1764d087bde5SNeilBrown 1765d087bde5SNeilBrown if (host->internal_cd) { 1766d087bde5SNeilBrown /* Disabled card-detect */ 1767d087bde5SNeilBrown sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1768d087bde5SNeilBrown sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1769d087bde5SNeilBrown } 1770d087bde5SNeilBrown 177120848903SChaotian Jing /* Disable and clear all interrupts */ 177220848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 177320848903SChaotian Jing 177420848903SChaotian Jing val = readl(host->base + MSDC_INT); 177520848903SChaotian Jing writel(val, host->base + MSDC_INT); 177620848903SChaotian Jing } 177720848903SChaotian Jing 177820848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 177920848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 178020848903SChaotian Jing { 178120848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 178220848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 17832a9bde19SChaotian Jing dma_addr_t dma_addr; 178420848903SChaotian Jing int i; 178520848903SChaotian Jing 178662b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 178720848903SChaotian Jing 17882a9bde19SChaotian Jing dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 178920848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 179062b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 179162b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 179262b0d27aSChaotian Jing */ 17932a9bde19SChaotian Jing gpd->next = lower_32_bits(dma_addr); 17942a9bde19SChaotian Jing if (host->dev_comp->support_64g) 17952a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 17962a9bde19SChaotian Jing 17972a9bde19SChaotian Jing dma_addr = dma->bd_addr; 17982a9bde19SChaotian Jing gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 17992a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18002a9bde19SChaotian Jing gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 18012a9bde19SChaotian Jing 180220848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 18032a9bde19SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) { 18042a9bde19SChaotian Jing dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 18052a9bde19SChaotian Jing bd[i].next = lower_32_bits(dma_addr); 18062a9bde19SChaotian Jing if (host->dev_comp->support_64g) 18072a9bde19SChaotian Jing bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 18082a9bde19SChaotian Jing } 180920848903SChaotian Jing } 181020848903SChaotian Jing 181120848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 181220848903SChaotian Jing { 181320848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 181420848903SChaotian Jing int ret; 181520848903SChaotian Jing 181620848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 181720848903SChaotian Jing 181820848903SChaotian Jing /* Suspend/Resume will do power off/on */ 181920848903SChaotian Jing switch (ios->power_mode) { 182020848903SChaotian Jing case MMC_POWER_UP: 182120848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 18226397b7f5SChaotian Jing msdc_init_hw(host); 182320848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 182420848903SChaotian Jing ios->vdd); 182520848903SChaotian Jing if (ret) { 182620848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1827567979fbSUlf Hansson return; 182820848903SChaotian Jing } 182920848903SChaotian Jing } 183020848903SChaotian Jing break; 183120848903SChaotian Jing case MMC_POWER_ON: 183220848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 183320848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 183420848903SChaotian Jing if (ret) 183520848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 183620848903SChaotian Jing else 183720848903SChaotian Jing host->vqmmc_enabled = true; 183820848903SChaotian Jing } 183920848903SChaotian Jing break; 184020848903SChaotian Jing case MMC_POWER_OFF: 184120848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 184220848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 184320848903SChaotian Jing 184420848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 184520848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 184620848903SChaotian Jing host->vqmmc_enabled = false; 184720848903SChaotian Jing } 184820848903SChaotian Jing break; 184920848903SChaotian Jing default: 185020848903SChaotian Jing break; 185120848903SChaotian Jing } 185220848903SChaotian Jing 18536e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 18546e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 185520848903SChaotian Jing } 185620848903SChaotian Jing 18576397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 18586397b7f5SChaotian Jing { 18596397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 18606397b7f5SChaotian Jing return delay & (1 << bit); 18616397b7f5SChaotian Jing } 18626397b7f5SChaotian Jing 18636397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 18646397b7f5SChaotian Jing { 18656397b7f5SChaotian Jing int i; 18666397b7f5SChaotian Jing 18676397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 18686397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 18696397b7f5SChaotian Jing return i; 18706397b7f5SChaotian Jing } 18716397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 18726397b7f5SChaotian Jing } 18736397b7f5SChaotian Jing 18746397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 18756397b7f5SChaotian Jing { 18766397b7f5SChaotian Jing int start = 0, len = 0; 18776397b7f5SChaotian Jing int start_final = 0, len_final = 0; 18786397b7f5SChaotian Jing u8 final_phase = 0xff; 187962d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 18806397b7f5SChaotian Jing 18816397b7f5SChaotian Jing if (delay == 0) { 18826397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 18836397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 18846397b7f5SChaotian Jing return delay_phase; 18856397b7f5SChaotian Jing } 18866397b7f5SChaotian Jing 18876397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 18886397b7f5SChaotian Jing len = get_delay_len(delay, start); 18896397b7f5SChaotian Jing if (len_final < len) { 18906397b7f5SChaotian Jing start_final = start; 18916397b7f5SChaotian Jing len_final = len; 18926397b7f5SChaotian Jing } 18936397b7f5SChaotian Jing start += len ? len : 1; 18941ede5cb8Syong mao if (len >= 12 && start_final < 4) 18956397b7f5SChaotian Jing break; 18966397b7f5SChaotian Jing } 18976397b7f5SChaotian Jing 18986397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 18996397b7f5SChaotian Jing if (start_final == 0) 19006397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 19016397b7f5SChaotian Jing else 19026397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 19036397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 19046397b7f5SChaotian Jing delay, len_final, final_phase); 19056397b7f5SChaotian Jing 19066397b7f5SChaotian Jing delay_phase.maxlen = len_final; 19076397b7f5SChaotian Jing delay_phase.start = start_final; 19086397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 19096397b7f5SChaotian Jing return delay_phase; 19106397b7f5SChaotian Jing } 19116397b7f5SChaotian Jing 1912fd82cc30SChaotian Jing static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1913fd82cc30SChaotian Jing { 1914fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1915fd82cc30SChaotian Jing 1916fd82cc30SChaotian Jing if (host->top_base) 1917fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1918fd82cc30SChaotian Jing value); 1919fd82cc30SChaotian Jing else 1920fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1921fd82cc30SChaotian Jing value); 1922fd82cc30SChaotian Jing } 1923fd82cc30SChaotian Jing 1924fd82cc30SChaotian Jing static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1925fd82cc30SChaotian Jing { 1926fd82cc30SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 1927fd82cc30SChaotian Jing 1928fd82cc30SChaotian Jing if (host->top_base) 1929fd82cc30SChaotian Jing sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1930fd82cc30SChaotian Jing PAD_DAT_RD_RXDLY, value); 1931fd82cc30SChaotian Jing else 1932fd82cc30SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1933fd82cc30SChaotian Jing value); 1934fd82cc30SChaotian Jing } 1935fd82cc30SChaotian Jing 19366397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 19376397b7f5SChaotian Jing { 19386397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 19396397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1940ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 19411ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 19426397b7f5SChaotian Jing u8 final_delay, final_maxlen; 19431ede5cb8Syong mao u32 internal_delay = 0; 194439add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 19456397b7f5SChaotian Jing int cmd_err; 19461ede5cb8Syong mao int i, j; 19471ede5cb8Syong mao 19481ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 19491ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 195039add252SChaotian Jing sdr_set_field(host->base + tune_reg, 19511ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 19521ede5cb8Syong mao host->hs200_cmd_int_delay); 19536397b7f5SChaotian Jing 19546397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19556397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1956fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 19571ede5cb8Syong mao /* 19581ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19591ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19601ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19611ede5cb8Syong mao */ 19621ede5cb8Syong mao for (j = 0; j < 3; j++) { 19636397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 19641ede5cb8Syong mao if (!cmd_err) { 19656397b7f5SChaotian Jing rise_delay |= (1 << i); 19661ede5cb8Syong mao } else { 19671ede5cb8Syong mao rise_delay &= ~(1 << i); 19681ede5cb8Syong mao break; 19691ede5cb8Syong mao } 19701ede5cb8Syong mao } 19716397b7f5SChaotian Jing } 1972ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1973ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 19746b10c9abSChaotian Jing if (final_rise_delay.maxlen >= 12 || 19756b10c9abSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1976ae9c657eSChaotian Jing goto skip_fall; 19776397b7f5SChaotian Jing 19786397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 19796397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 1980fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 19811ede5cb8Syong mao /* 19821ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 19831ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 19841ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 19851ede5cb8Syong mao */ 19861ede5cb8Syong mao for (j = 0; j < 3; j++) { 19876397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 19881ede5cb8Syong mao if (!cmd_err) { 19896397b7f5SChaotian Jing fall_delay |= (1 << i); 19901ede5cb8Syong mao } else { 19911ede5cb8Syong mao fall_delay &= ~(1 << i); 19921ede5cb8Syong mao break; 19931ede5cb8Syong mao } 19941ede5cb8Syong mao } 19956397b7f5SChaotian Jing } 19966397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 19976397b7f5SChaotian Jing 1998ae9c657eSChaotian Jing skip_fall: 19996397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 20001ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 20011ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 20026397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 20036397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20046397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 20056397b7f5SChaotian Jing } else { 20066397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20076397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 20086397b7f5SChaotian Jing } 2009fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2010fd82cc30SChaotian Jing 20112fea5819SChaotian Jing if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 20121ede5cb8Syong mao goto skip_internal; 20136397b7f5SChaotian Jing 20141ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 201539add252SChaotian Jing sdr_set_field(host->base + tune_reg, 20161ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 20171ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20181ede5cb8Syong mao if (!cmd_err) 20191ede5cb8Syong mao internal_delay |= (1 << i); 20201ede5cb8Syong mao } 20211ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 20221ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 202339add252SChaotian Jing sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 20241ede5cb8Syong mao internal_delay_phase.final_phase); 20251ede5cb8Syong mao skip_internal: 20261ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20271ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 20281ede5cb8Syong mao } 20291ede5cb8Syong mao 20301ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 20311ede5cb8Syong mao { 20321ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 20331ede5cb8Syong mao u32 cmd_delay = 0; 20341ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 20351ede5cb8Syong mao u8 final_delay; 20361ede5cb8Syong mao int cmd_err; 20371ede5cb8Syong mao int i, j; 20381ede5cb8Syong mao 20391ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 20401ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 20418f34e5bdSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 20421ede5cb8Syong mao 20431ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 20441ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 20451ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 20461ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 20471ede5cb8Syong mao host->hs200_cmd_int_delay); 20481ede5cb8Syong mao 20491ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 20501ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20511ede5cb8Syong mao else 20521ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 20531ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 20541ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 20551ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 20561ede5cb8Syong mao /* 20571ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 20581ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 20591ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 20601ede5cb8Syong mao */ 20611ede5cb8Syong mao for (j = 0; j < 3; j++) { 20621ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 20631ede5cb8Syong mao if (!cmd_err) { 20641ede5cb8Syong mao cmd_delay |= (1 << i); 20651ede5cb8Syong mao } else { 20661ede5cb8Syong mao cmd_delay &= ~(1 << i); 20671ede5cb8Syong mao break; 20681ede5cb8Syong mao } 20691ede5cb8Syong mao } 20701ede5cb8Syong mao } 20711ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 20721ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 20731ede5cb8Syong mao final_cmd_delay.final_phase); 20741ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 20751ede5cb8Syong mao 20761ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 20776397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 20786397b7f5SChaotian Jing } 20796397b7f5SChaotian Jing 20806397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 20816397b7f5SChaotian Jing { 20826397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 20836397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 2084ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 20856397b7f5SChaotian Jing u8 final_delay, final_maxlen; 20866397b7f5SChaotian Jing int i, ret; 20876397b7f5SChaotian Jing 2088d17bb71cSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2089d17bb71cSChaotian Jing host->latch_ck); 20906397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 20916397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 20926397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2093fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 20946397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 20956397b7f5SChaotian Jing if (!ret) 20966397b7f5SChaotian Jing rise_delay |= (1 << i); 20976397b7f5SChaotian Jing } 2098ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 2099ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 21001ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 2101ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2102ae9c657eSChaotian Jing goto skip_fall; 21036397b7f5SChaotian Jing 21046397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21056397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21066397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2107fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 21086397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 21096397b7f5SChaotian Jing if (!ret) 21106397b7f5SChaotian Jing fall_delay |= (1 << i); 21116397b7f5SChaotian Jing } 21126397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 21136397b7f5SChaotian Jing 2114ae9c657eSChaotian Jing skip_fall: 21156397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 21166397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 21176397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21186397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21196397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 21206397b7f5SChaotian Jing } else { 21216397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 21226397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 21236397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 21246397b7f5SChaotian Jing } 2125fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 21266397b7f5SChaotian Jing 21271ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 21286397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 21296397b7f5SChaotian Jing } 21306397b7f5SChaotian Jing 213186601d0eSChaotian Jing /* 213286601d0eSChaotian Jing * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 213386601d0eSChaotian Jing * together, which can save the tuning time. 213486601d0eSChaotian Jing */ 213586601d0eSChaotian Jing static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 213686601d0eSChaotian Jing { 213786601d0eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 213886601d0eSChaotian Jing u32 rise_delay = 0, fall_delay = 0; 213986601d0eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 214086601d0eSChaotian Jing u8 final_delay, final_maxlen; 214186601d0eSChaotian Jing int i, ret; 214286601d0eSChaotian Jing 214386601d0eSChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 214486601d0eSChaotian Jing host->latch_ck); 214586601d0eSChaotian Jing 214686601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 214786601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 214886601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 214986601d0eSChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2150fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2151fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 215286601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 215386601d0eSChaotian Jing if (!ret) 215486601d0eSChaotian Jing rise_delay |= (1 << i); 215586601d0eSChaotian Jing } 215686601d0eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 215786601d0eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 215886601d0eSChaotian Jing if (final_rise_delay.maxlen >= 12 || 215986601d0eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 216086601d0eSChaotian Jing goto skip_fall; 216186601d0eSChaotian Jing 216286601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 216386601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 216486601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 216586601d0eSChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 2166fd82cc30SChaotian Jing msdc_set_cmd_delay(host, i); 2167fd82cc30SChaotian Jing msdc_set_data_delay(host, i); 216886601d0eSChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 216986601d0eSChaotian Jing if (!ret) 217086601d0eSChaotian Jing fall_delay |= (1 << i); 217186601d0eSChaotian Jing } 217286601d0eSChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 217386601d0eSChaotian Jing 217486601d0eSChaotian Jing skip_fall: 217586601d0eSChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 217686601d0eSChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 217786601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 217886601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 217986601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 218086601d0eSChaotian Jing final_delay = final_rise_delay.final_phase; 218186601d0eSChaotian Jing } else { 218286601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 218386601d0eSChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, 218486601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 218586601d0eSChaotian Jing final_delay = final_fall_delay.final_phase; 218686601d0eSChaotian Jing } 218786601d0eSChaotian Jing 2188fd82cc30SChaotian Jing msdc_set_cmd_delay(host, final_delay); 2189fd82cc30SChaotian Jing msdc_set_data_delay(host, final_delay); 2190a2e6d1f6SChaotian Jing 219186601d0eSChaotian Jing dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 219286601d0eSChaotian Jing return final_delay == 0xff ? -EIO : 0; 219386601d0eSChaotian Jing } 219486601d0eSChaotian Jing 21956397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 21966397b7f5SChaotian Jing { 21976397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 21986397b7f5SChaotian Jing int ret; 219939add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 22006397b7f5SChaotian Jing 220186601d0eSChaotian Jing if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 220286601d0eSChaotian Jing ret = msdc_tune_together(mmc, opcode); 220386601d0eSChaotian Jing if (host->hs400_mode) { 220486601d0eSChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, 220586601d0eSChaotian Jing MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2206fd82cc30SChaotian Jing msdc_set_data_delay(host, 0); 220786601d0eSChaotian Jing } 220886601d0eSChaotian Jing goto tune_done; 220986601d0eSChaotian Jing } 22107f3d5852SChaotian Jing if (host->hs400_mode && 22117f3d5852SChaotian Jing host->dev_comp->hs400_tune) 22121ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 22131ede5cb8Syong mao else 22146397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 22156397b7f5SChaotian Jing if (ret == -EIO) { 22166397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 2217567979fbSUlf Hansson return ret; 22186397b7f5SChaotian Jing } 22195462ff39SChaotian Jing if (host->hs400_mode == false) { 22206397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 22216397b7f5SChaotian Jing if (ret == -EIO) 22226397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 22235462ff39SChaotian Jing } 22246397b7f5SChaotian Jing 222586601d0eSChaotian Jing tune_done: 222686beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 222739add252SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 22281ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2229a2e6d1f6SChaotian Jing if (host->top_base) { 2230a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_control = readl(host->top_base + 2231a2e6d1f6SChaotian Jing EMMC_TOP_CONTROL); 2232a2e6d1f6SChaotian Jing host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2233a2e6d1f6SChaotian Jing EMMC_TOP_CMD); 2234a2e6d1f6SChaotian Jing } 22356397b7f5SChaotian Jing return ret; 22366397b7f5SChaotian Jing } 22376397b7f5SChaotian Jing 22386397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 22396397b7f5SChaotian Jing { 22406397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 22415462ff39SChaotian Jing host->hs400_mode = true; 22426397b7f5SChaotian Jing 2243a2e6d1f6SChaotian Jing if (host->top_base) 2244a2e6d1f6SChaotian Jing writel(host->hs400_ds_delay, 2245a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2246a2e6d1f6SChaotian Jing else 22476397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 22482fea5819SChaotian Jing /* hs400 mode must set it to 0 */ 22492fea5819SChaotian Jing sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2250c8609b22SChaotian Jing /* to improve read performance, set outstanding to 2 */ 2251c8609b22SChaotian Jing sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2252c8609b22SChaotian Jing 22536397b7f5SChaotian Jing return 0; 22546397b7f5SChaotian Jing } 22556397b7f5SChaotian Jing 2256c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 2257c9b5061eSChaotian Jing { 2258c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 2259c9b5061eSChaotian Jing 2260c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 2261c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 2262c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 2263c9b5061eSChaotian Jing } 2264c9b5061eSChaotian Jing 22655215b2e9Sjjian zhou static void msdc_ack_sdio_irq(struct mmc_host *mmc) 22665215b2e9Sjjian zhou { 22678a5df8acSjjian zhou unsigned long flags; 22688a5df8acSjjian zhou struct msdc_host *host = mmc_priv(mmc); 22698a5df8acSjjian zhou 22708a5df8acSjjian zhou spin_lock_irqsave(&host->lock, flags); 22718a5df8acSjjian zhou __msdc_enable_sdio_irq(host, 1); 22728a5df8acSjjian zhou spin_unlock_irqrestore(&host->lock, flags); 22735215b2e9Sjjian zhou } 22745215b2e9Sjjian zhou 2275d087bde5SNeilBrown static int msdc_get_cd(struct mmc_host *mmc) 2276d087bde5SNeilBrown { 2277d087bde5SNeilBrown struct msdc_host *host = mmc_priv(mmc); 2278d087bde5SNeilBrown int val; 2279d087bde5SNeilBrown 2280d087bde5SNeilBrown if (mmc->caps & MMC_CAP_NONREMOVABLE) 2281d087bde5SNeilBrown return 1; 2282d087bde5SNeilBrown 2283d087bde5SNeilBrown if (!host->internal_cd) 2284d087bde5SNeilBrown return mmc_gpio_get_cd(mmc); 2285d087bde5SNeilBrown 2286d087bde5SNeilBrown val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2287d087bde5SNeilBrown if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2288d087bde5SNeilBrown return !!val; 2289d087bde5SNeilBrown else 2290d087bde5SNeilBrown return !val; 2291d087bde5SNeilBrown } 2292d087bde5SNeilBrown 2293*13b4e1e9SWenbin Mei static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2294*13b4e1e9SWenbin Mei struct mmc_ios *ios) 2295*13b4e1e9SWenbin Mei { 2296*13b4e1e9SWenbin Mei struct msdc_host *host = mmc_priv(mmc); 2297*13b4e1e9SWenbin Mei 2298*13b4e1e9SWenbin Mei if (ios->enhanced_strobe) { 2299*13b4e1e9SWenbin Mei msdc_prepare_hs400_tuning(mmc, ios); 2300*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2301*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2302*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2303*13b4e1e9SWenbin Mei 2304*13b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2305*13b4e1e9SWenbin Mei sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2306*13b4e1e9SWenbin Mei sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2307*13b4e1e9SWenbin Mei } else { 2308*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2309*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2310*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2311*13b4e1e9SWenbin Mei 2312*13b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2313*13b4e1e9SWenbin Mei sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2314*13b4e1e9SWenbin Mei sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2315*13b4e1e9SWenbin Mei } 2316*13b4e1e9SWenbin Mei } 2317*13b4e1e9SWenbin Mei 231888bd652bSChun-Hung Wu static void msdc_cqe_enable(struct mmc_host *mmc) 231988bd652bSChun-Hung Wu { 232088bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 232188bd652bSChun-Hung Wu 232288bd652bSChun-Hung Wu /* enable cmdq irq */ 232388bd652bSChun-Hung Wu writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 232488bd652bSChun-Hung Wu /* enable busy check */ 232588bd652bSChun-Hung Wu sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 232688bd652bSChun-Hung Wu /* default write data / busy timeout 20s */ 232788bd652bSChun-Hung Wu msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 232888bd652bSChun-Hung Wu /* default read data timeout 1s */ 232988bd652bSChun-Hung Wu msdc_set_timeout(host, 1000000000ULL, 0); 233088bd652bSChun-Hung Wu } 233188bd652bSChun-Hung Wu 23327f4bc2e8SWei Yongjun static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 233388bd652bSChun-Hung Wu { 233488bd652bSChun-Hung Wu struct msdc_host *host = mmc_priv(mmc); 233588bd652bSChun-Hung Wu 233688bd652bSChun-Hung Wu /* disable cmdq irq */ 233788bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 233888bd652bSChun-Hung Wu /* disable busy check */ 233988bd652bSChun-Hung Wu sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 234088bd652bSChun-Hung Wu 234188bd652bSChun-Hung Wu if (recovery) { 234288bd652bSChun-Hung Wu sdr_set_field(host->base + MSDC_DMA_CTRL, 234388bd652bSChun-Hung Wu MSDC_DMA_CTRL_STOP, 1); 234488bd652bSChun-Hung Wu msdc_reset_hw(host); 234588bd652bSChun-Hung Wu } 234688bd652bSChun-Hung Wu } 234788bd652bSChun-Hung Wu 2348e282f204SChun-Hung Wu static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2349e282f204SChun-Hung Wu { 2350e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2351e282f204SChun-Hung Wu u32 reg; 2352e282f204SChun-Hung Wu 2353e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2354e282f204SChun-Hung Wu reg |= CQHCI_ENABLE; 2355e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2356e282f204SChun-Hung Wu } 2357e282f204SChun-Hung Wu 2358e282f204SChun-Hung Wu static void msdc_cqe_post_disable(struct mmc_host *mmc) 2359e282f204SChun-Hung Wu { 2360e282f204SChun-Hung Wu struct cqhci_host *cq_host = mmc->cqe_private; 2361e282f204SChun-Hung Wu u32 reg; 2362e282f204SChun-Hung Wu 2363e282f204SChun-Hung Wu reg = cqhci_readl(cq_host, CQHCI_CFG); 2364e282f204SChun-Hung Wu reg &= ~CQHCI_ENABLE; 2365e282f204SChun-Hung Wu cqhci_writel(cq_host, reg, CQHCI_CFG); 2366e282f204SChun-Hung Wu } 2367e282f204SChun-Hung Wu 2368be7815d6SJulia Lawall static const struct mmc_host_ops mt_msdc_ops = { 236920848903SChaotian Jing .post_req = msdc_post_req, 237020848903SChaotian Jing .pre_req = msdc_pre_req, 237120848903SChaotian Jing .request = msdc_ops_request, 237220848903SChaotian Jing .set_ios = msdc_ops_set_ios, 23738d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 2374d087bde5SNeilBrown .get_cd = msdc_get_cd, 2375*13b4e1e9SWenbin Mei .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 23765215b2e9Sjjian zhou .enable_sdio_irq = msdc_enable_sdio_irq, 23775215b2e9Sjjian zhou .ack_sdio_irq = msdc_ack_sdio_irq, 237820848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 237920848903SChaotian Jing .card_busy = msdc_card_busy, 23806397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 23816397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2382c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 238320848903SChaotian Jing }; 238420848903SChaotian Jing 238588bd652bSChun-Hung Wu static const struct cqhci_host_ops msdc_cmdq_ops = { 238688bd652bSChun-Hung Wu .enable = msdc_cqe_enable, 238788bd652bSChun-Hung Wu .disable = msdc_cqe_disable, 2388e282f204SChun-Hung Wu .pre_enable = msdc_cqe_pre_enable, 2389e282f204SChun-Hung Wu .post_disable = msdc_cqe_post_disable, 239088bd652bSChun-Hung Wu }; 239188bd652bSChun-Hung Wu 23921ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 23931ede5cb8Syong mao struct msdc_host *host) 23941ede5cb8Syong mao { 2395d17bb71cSChaotian Jing of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2396d17bb71cSChaotian Jing &host->latch_ck); 2397d17bb71cSChaotian Jing 23981ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 23991ede5cb8Syong mao &host->hs400_ds_delay); 24001ede5cb8Syong mao 24011ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 24021ede5cb8Syong mao &host->hs200_cmd_int_delay); 24031ede5cb8Syong mao 24041ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 24051ede5cb8Syong mao &host->hs400_cmd_int_delay); 24061ede5cb8Syong mao 24071ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 24081ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 24091ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 24101ede5cb8Syong mao else 24111ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 241288bd652bSChun-Hung Wu 241388bd652bSChun-Hung Wu if (of_property_read_bool(pdev->dev.of_node, 241488bd652bSChun-Hung Wu "supports-cqe")) 241588bd652bSChun-Hung Wu host->cqhci = true; 241688bd652bSChun-Hung Wu else 241788bd652bSChun-Hung Wu host->cqhci = false; 24181ede5cb8Syong mao } 24191ede5cb8Syong mao 2420f5eccd94SWenbin Mei static int msdc_of_clock_parse(struct platform_device *pdev, 2421f5eccd94SWenbin Mei struct msdc_host *host) 2422f5eccd94SWenbin Mei { 2423f5eccd94SWenbin Mei int ret; 2424f5eccd94SWenbin Mei 2425f5eccd94SWenbin Mei host->src_clk = devm_clk_get(&pdev->dev, "source"); 2426f5eccd94SWenbin Mei if (IS_ERR(host->src_clk)) 2427f5eccd94SWenbin Mei return PTR_ERR(host->src_clk); 2428f5eccd94SWenbin Mei 2429f5eccd94SWenbin Mei host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2430f5eccd94SWenbin Mei if (IS_ERR(host->h_clk)) 2431f5eccd94SWenbin Mei return PTR_ERR(host->h_clk); 2432f5eccd94SWenbin Mei 2433f5eccd94SWenbin Mei host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2434f5eccd94SWenbin Mei if (IS_ERR(host->bus_clk)) 2435f5eccd94SWenbin Mei host->bus_clk = NULL; 2436f5eccd94SWenbin Mei 2437f5eccd94SWenbin Mei /*source clock control gate is optional clock*/ 2438f5eccd94SWenbin Mei host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2439f5eccd94SWenbin Mei if (IS_ERR(host->src_clk_cg)) 2440f5eccd94SWenbin Mei host->src_clk_cg = NULL; 2441f5eccd94SWenbin Mei 2442f5eccd94SWenbin Mei host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2443f5eccd94SWenbin Mei if (IS_ERR(host->sys_clk_cg)) 2444f5eccd94SWenbin Mei host->sys_clk_cg = NULL; 2445f5eccd94SWenbin Mei 2446f5eccd94SWenbin Mei /* If present, always enable for this clock gate */ 2447f5eccd94SWenbin Mei clk_prepare_enable(host->sys_clk_cg); 2448f5eccd94SWenbin Mei 2449f5eccd94SWenbin Mei host->bulk_clks[0].id = "pclk_cg"; 2450f5eccd94SWenbin Mei host->bulk_clks[1].id = "axi_cg"; 2451f5eccd94SWenbin Mei host->bulk_clks[2].id = "ahb_cg"; 2452f5eccd94SWenbin Mei ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2453f5eccd94SWenbin Mei host->bulk_clks); 2454f5eccd94SWenbin Mei if (ret) { 2455f5eccd94SWenbin Mei dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2456f5eccd94SWenbin Mei return ret; 2457f5eccd94SWenbin Mei } 2458f5eccd94SWenbin Mei 2459f5eccd94SWenbin Mei return 0; 2460f5eccd94SWenbin Mei } 2461f5eccd94SWenbin Mei 246220848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 246320848903SChaotian Jing { 246420848903SChaotian Jing struct mmc_host *mmc; 246520848903SChaotian Jing struct msdc_host *host; 246620848903SChaotian Jing struct resource *res; 246720848903SChaotian Jing int ret; 246820848903SChaotian Jing 246920848903SChaotian Jing if (!pdev->dev.of_node) { 247020848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 247120848903SChaotian Jing return -EINVAL; 247220848903SChaotian Jing } 2473762d491aSChaotian Jing 247420848903SChaotian Jing /* Allocate MMC host for this device */ 247520848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 247620848903SChaotian Jing if (!mmc) 247720848903SChaotian Jing return -ENOMEM; 247820848903SChaotian Jing 247920848903SChaotian Jing host = mmc_priv(mmc); 248020848903SChaotian Jing ret = mmc_of_parse(mmc); 248120848903SChaotian Jing if (ret) 248220848903SChaotian Jing goto host_free; 248320848903SChaotian Jing 2484bc068d38SYangtao Li host->base = devm_platform_ioremap_resource(pdev, 0); 248520848903SChaotian Jing if (IS_ERR(host->base)) { 248620848903SChaotian Jing ret = PTR_ERR(host->base); 248720848903SChaotian Jing goto host_free; 248820848903SChaotian Jing } 248920848903SChaotian Jing 2490a2e6d1f6SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2491b65be635SFabien Parent if (res) { 2492a2e6d1f6SChaotian Jing host->top_base = devm_ioremap_resource(&pdev->dev, res); 2493a2e6d1f6SChaotian Jing if (IS_ERR(host->top_base)) 2494a2e6d1f6SChaotian Jing host->top_base = NULL; 2495b65be635SFabien Parent } 2496a2e6d1f6SChaotian Jing 249720848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 24982f98ef63SWolfram Sang if (ret) 249920848903SChaotian Jing goto host_free; 250020848903SChaotian Jing 2501f5eccd94SWenbin Mei ret = msdc_of_clock_parse(pdev, host); 2502f5eccd94SWenbin Mei if (ret) 250320848903SChaotian Jing goto host_free; 25043c1a8844SChaotian Jing 2505855d388dSWenbin Mei host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2506855d388dSWenbin Mei "hrst"); 2507855d388dSWenbin Mei if (IS_ERR(host->reset)) 2508855d388dSWenbin Mei return PTR_ERR(host->reset); 2509855d388dSWenbin Mei 251020848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 251120848903SChaotian Jing if (host->irq < 0) { 251220848903SChaotian Jing ret = -EINVAL; 251320848903SChaotian Jing goto host_free; 251420848903SChaotian Jing } 251520848903SChaotian Jing 251620848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 251720848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 251820848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 251920848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 252020848903SChaotian Jing goto host_free; 252120848903SChaotian Jing } 252220848903SChaotian Jing 252320848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 252420848903SChaotian Jing if (IS_ERR(host->pins_default)) { 252520848903SChaotian Jing ret = PTR_ERR(host->pins_default); 252620848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 252720848903SChaotian Jing goto host_free; 252820848903SChaotian Jing } 252920848903SChaotian Jing 253020848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 253120848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 253220848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 253320848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 253420848903SChaotian Jing goto host_free; 253520848903SChaotian Jing } 253620848903SChaotian Jing 25371ede5cb8Syong mao msdc_of_property_parse(pdev, host); 25386397b7f5SChaotian Jing 253920848903SChaotian Jing host->dev = &pdev->dev; 2540909b3456SRyder Lee host->dev_comp = of_device_get_match_data(&pdev->dev); 254120848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 254220848903SChaotian Jing /* Set host parameters to mmc */ 254320848903SChaotian Jing mmc->ops = &mt_msdc_ops; 2544762d491aSChaotian Jing if (host->dev_comp->clk_div_bits == 8) 254540ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2546762d491aSChaotian Jing else 2547762d491aSChaotian Jing mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 254820848903SChaotian Jing 2549d087bde5SNeilBrown if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2550d087bde5SNeilBrown !mmc_can_gpio_cd(mmc) && 2551d087bde5SNeilBrown host->dev_comp->use_internal_cd) { 2552d087bde5SNeilBrown /* 2553d087bde5SNeilBrown * Is removable but no GPIO declared, so 2554d087bde5SNeilBrown * use internal functionality. 2555d087bde5SNeilBrown */ 2556d087bde5SNeilBrown host->internal_cd = true; 2557d087bde5SNeilBrown } 2558d087bde5SNeilBrown 25595215b2e9Sjjian zhou if (mmc->caps & MMC_CAP_SDIO_IRQ) 25605215b2e9Sjjian zhou mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 25615215b2e9Sjjian zhou 25621be64c79SUlf Hansson mmc->caps |= MMC_CAP_CMD23; 256388bd652bSChun-Hung Wu if (host->cqhci) 256488bd652bSChun-Hung Wu mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 256520848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 256620848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 25676ef042bdSChaotian Jing if (host->dev_comp->support_64g) 25686ef042bdSChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 25696ef042bdSChaotian Jing else 257020848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 257120848903SChaotian Jing mmc->max_blk_size = 2048; 257220848903SChaotian Jing mmc->max_req_size = 512 * 1024; 257320848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 25742a9bde19SChaotian Jing if (host->dev_comp->support_64g) 25752a9bde19SChaotian Jing host->dma_mask = DMA_BIT_MASK(36); 25762a9bde19SChaotian Jing else 257720848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 257820848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 257920848903SChaotian Jing 258088bd652bSChun-Hung Wu if (mmc->caps2 & MMC_CAP2_CQE) { 25810caf60c4SAmey Narkhede host->cq_host = devm_kzalloc(mmc->parent, 258288bd652bSChun-Hung Wu sizeof(*host->cq_host), 258388bd652bSChun-Hung Wu GFP_KERNEL); 258488bd652bSChun-Hung Wu if (!host->cq_host) { 258588bd652bSChun-Hung Wu ret = -ENOMEM; 258688bd652bSChun-Hung Wu goto host_free; 258788bd652bSChun-Hung Wu } 258888bd652bSChun-Hung Wu host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 258988bd652bSChun-Hung Wu host->cq_host->mmio = host->base + 0x800; 259088bd652bSChun-Hung Wu host->cq_host->ops = &msdc_cmdq_ops; 259188bd652bSChun-Hung Wu ret = cqhci_init(host->cq_host, mmc, true); 259288bd652bSChun-Hung Wu if (ret) 259388bd652bSChun-Hung Wu goto host_free; 259488bd652bSChun-Hung Wu mmc->max_segs = 128; 259588bd652bSChun-Hung Wu /* cqhci 16bit length */ 259688bd652bSChun-Hung Wu /* 0 size, means 65536 so we don't have to -1 here */ 259788bd652bSChun-Hung Wu mmc->max_seg_size = 64 * 1024; 259888bd652bSChun-Hung Wu } 259988bd652bSChun-Hung Wu 260020848903SChaotian Jing host->timeout_clks = 3 * 1048576; 260120848903SChaotian Jing host->dma.gpd = dma_alloc_coherent(&pdev->dev, 260262b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 260320848903SChaotian Jing &host->dma.gpd_addr, GFP_KERNEL); 260420848903SChaotian Jing host->dma.bd = dma_alloc_coherent(&pdev->dev, 260520848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 260620848903SChaotian Jing &host->dma.bd_addr, GFP_KERNEL); 260720848903SChaotian Jing if (!host->dma.gpd || !host->dma.bd) { 260820848903SChaotian Jing ret = -ENOMEM; 260920848903SChaotian Jing goto release_mem; 261020848903SChaotian Jing } 261120848903SChaotian Jing msdc_init_gpd_bd(host, &host->dma); 261220848903SChaotian Jing INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 261320848903SChaotian Jing spin_lock_init(&host->lock); 261420848903SChaotian Jing 261520848903SChaotian Jing platform_set_drvdata(pdev, mmc); 261620848903SChaotian Jing msdc_ungate_clock(host); 261720848903SChaotian Jing msdc_init_hw(host); 261820848903SChaotian Jing 261920848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 262042edb0d5SNeilBrown IRQF_TRIGGER_NONE, pdev->name, host); 262120848903SChaotian Jing if (ret) 262220848903SChaotian Jing goto release; 262320848903SChaotian Jing 26244b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 26254b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 26264b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 26274b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 262820848903SChaotian Jing ret = mmc_add_host(mmc); 26294b8a43e9SChaotian Jing 263020848903SChaotian Jing if (ret) 26314b8a43e9SChaotian Jing goto end; 263220848903SChaotian Jing 263320848903SChaotian Jing return 0; 26344b8a43e9SChaotian Jing end: 26354b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 263620848903SChaotian Jing release: 263720848903SChaotian Jing platform_set_drvdata(pdev, NULL); 263820848903SChaotian Jing msdc_deinit_hw(host); 263920848903SChaotian Jing msdc_gate_clock(host); 264020848903SChaotian Jing release_mem: 264120848903SChaotian Jing if (host->dma.gpd) 264220848903SChaotian Jing dma_free_coherent(&pdev->dev, 264362b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 264420848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 264520848903SChaotian Jing if (host->dma.bd) 264620848903SChaotian Jing dma_free_coherent(&pdev->dev, 264720848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 264820848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 264920848903SChaotian Jing host_free: 265020848903SChaotian Jing mmc_free_host(mmc); 265120848903SChaotian Jing 265220848903SChaotian Jing return ret; 265320848903SChaotian Jing } 265420848903SChaotian Jing 265520848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 265620848903SChaotian Jing { 265720848903SChaotian Jing struct mmc_host *mmc; 265820848903SChaotian Jing struct msdc_host *host; 265920848903SChaotian Jing 266020848903SChaotian Jing mmc = platform_get_drvdata(pdev); 266120848903SChaotian Jing host = mmc_priv(mmc); 266220848903SChaotian Jing 26634b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 26644b8a43e9SChaotian Jing 266520848903SChaotian Jing platform_set_drvdata(pdev, NULL); 26660caf60c4SAmey Narkhede mmc_remove_host(mmc); 266720848903SChaotian Jing msdc_deinit_hw(host); 266820848903SChaotian Jing msdc_gate_clock(host); 266920848903SChaotian Jing 26704b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 26714b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 267220848903SChaotian Jing dma_free_coherent(&pdev->dev, 267316f2e0c6SPhong LE 2 * sizeof(struct mt_gpdma_desc), 267420848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 267520848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 267620848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 267720848903SChaotian Jing 26780caf60c4SAmey Narkhede mmc_free_host(mmc); 267920848903SChaotian Jing 268020848903SChaotian Jing return 0; 268120848903SChaotian Jing } 268220848903SChaotian Jing 26834b8a43e9SChaotian Jing #ifdef CONFIG_PM 26844b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 26854b8a43e9SChaotian Jing { 268639add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 268739add252SChaotian Jing 26884b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 26894b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 26904b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 26914b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 26924b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 26932fea5819SChaotian Jing host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 26946397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 26951ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 26966397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2697c8609b22SChaotian Jing host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2698d9dcbfc8SChaotian Jing host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2699a2e6d1f6SChaotian Jing if (host->top_base) { 2700a2e6d1f6SChaotian Jing host->save_para.emmc_top_control = 2701a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CONTROL); 2702a2e6d1f6SChaotian Jing host->save_para.emmc_top_cmd = 2703a2e6d1f6SChaotian Jing readl(host->top_base + EMMC_TOP_CMD); 2704a2e6d1f6SChaotian Jing host->save_para.emmc50_pad_ds_tune = 2705a2e6d1f6SChaotian Jing readl(host->top_base + EMMC50_PAD_DS_TUNE); 2706a2e6d1f6SChaotian Jing } else { 2707a2e6d1f6SChaotian Jing host->save_para.pad_tune = readl(host->base + tune_reg); 2708a2e6d1f6SChaotian Jing } 27094b8a43e9SChaotian Jing } 27104b8a43e9SChaotian Jing 27114b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 27124b8a43e9SChaotian Jing { 27130caf60c4SAmey Narkhede struct mmc_host *mmc = mmc_from_priv(host); 271439add252SChaotian Jing u32 tune_reg = host->dev_comp->pad_tune_reg; 271539add252SChaotian Jing 27164b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 27174b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 27184b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 27194b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 27204b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 27212fea5819SChaotian Jing writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 27226397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 27231ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 27246397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2725c8609b22SChaotian Jing writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2726d9dcbfc8SChaotian Jing writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2727a2e6d1f6SChaotian Jing if (host->top_base) { 2728a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_control, 2729a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CONTROL); 2730a2e6d1f6SChaotian Jing writel(host->save_para.emmc_top_cmd, 2731a2e6d1f6SChaotian Jing host->top_base + EMMC_TOP_CMD); 2732a2e6d1f6SChaotian Jing writel(host->save_para.emmc50_pad_ds_tune, 2733a2e6d1f6SChaotian Jing host->top_base + EMMC50_PAD_DS_TUNE); 2734a2e6d1f6SChaotian Jing } else { 2735a2e6d1f6SChaotian Jing writel(host->save_para.pad_tune, host->base + tune_reg); 2736a2e6d1f6SChaotian Jing } 27371c81d69dSUlf Hansson 27380caf60c4SAmey Narkhede if (sdio_irq_claimed(mmc)) 27391c81d69dSUlf Hansson __msdc_enable_sdio_irq(host, 1); 27404b8a43e9SChaotian Jing } 27414b8a43e9SChaotian Jing 27424b8a43e9SChaotian Jing static int msdc_runtime_suspend(struct device *dev) 27434b8a43e9SChaotian Jing { 27444b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 27454b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 27464b8a43e9SChaotian Jing 27474b8a43e9SChaotian Jing msdc_save_reg(host); 27484b8a43e9SChaotian Jing msdc_gate_clock(host); 27494b8a43e9SChaotian Jing return 0; 27504b8a43e9SChaotian Jing } 27514b8a43e9SChaotian Jing 27524b8a43e9SChaotian Jing static int msdc_runtime_resume(struct device *dev) 27534b8a43e9SChaotian Jing { 27544b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 27554b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 27564b8a43e9SChaotian Jing 27574b8a43e9SChaotian Jing msdc_ungate_clock(host); 27584b8a43e9SChaotian Jing msdc_restore_reg(host); 27594b8a43e9SChaotian Jing return 0; 27604b8a43e9SChaotian Jing } 27614b8a43e9SChaotian Jing #endif 27624b8a43e9SChaotian Jing 27634b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 27644b8a43e9SChaotian Jing SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 27654b8a43e9SChaotian Jing pm_runtime_force_resume) 27664b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 27674b8a43e9SChaotian Jing }; 27684b8a43e9SChaotian Jing 276920848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 277020848903SChaotian Jing .probe = msdc_drv_probe, 277120848903SChaotian Jing .remove = msdc_drv_remove, 277220848903SChaotian Jing .driver = { 277320848903SChaotian Jing .name = "mtk-msdc", 277421b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 277520848903SChaotian Jing .of_match_table = msdc_of_ids, 27764b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 277720848903SChaotian Jing }, 277820848903SChaotian Jing }; 277920848903SChaotian Jing 278020848903SChaotian Jing module_platform_driver(mt_msdc_driver); 278120848903SChaotian Jing MODULE_LICENSE("GPL v2"); 278220848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2783