1 /* 2 * MOXA ART MMC host driver. 3 * 4 * Copyright (C) 2014 Jonas Jensen 5 * 6 * Jonas Jensen <jonas.jensen@gmail.com> 7 * 8 * Based on code from 9 * Moxa Technologies Co., Ltd. <www.moxa.com> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/version.h> 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/blkdev.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/dmaengine.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/sd.h> 27 #include <linux/sched.h> 28 #include <linux/io.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/clk.h> 32 #include <linux/bitops.h> 33 #include <linux/of_dma.h> 34 #include <linux/spinlock.h> 35 36 #define REG_COMMAND 0 37 #define REG_ARGUMENT 4 38 #define REG_RESPONSE0 8 39 #define REG_RESPONSE1 12 40 #define REG_RESPONSE2 16 41 #define REG_RESPONSE3 20 42 #define REG_RESPONSE_COMMAND 24 43 #define REG_DATA_CONTROL 28 44 #define REG_DATA_TIMER 32 45 #define REG_DATA_LENGTH 36 46 #define REG_STATUS 40 47 #define REG_CLEAR 44 48 #define REG_INTERRUPT_MASK 48 49 #define REG_POWER_CONTROL 52 50 #define REG_CLOCK_CONTROL 56 51 #define REG_BUS_WIDTH 60 52 #define REG_DATA_WINDOW 64 53 #define REG_FEATURE 68 54 #define REG_REVISION 72 55 56 /* REG_COMMAND */ 57 #define CMD_SDC_RESET BIT(10) 58 #define CMD_EN BIT(9) 59 #define CMD_APP_CMD BIT(8) 60 #define CMD_LONG_RSP BIT(7) 61 #define CMD_NEED_RSP BIT(6) 62 #define CMD_IDX_MASK 0x3f 63 64 /* REG_RESPONSE_COMMAND */ 65 #define RSP_CMD_APP BIT(6) 66 #define RSP_CMD_IDX_MASK 0x3f 67 68 /* REG_DATA_CONTROL */ 69 #define DCR_DATA_FIFO_RESET BIT(8) 70 #define DCR_DATA_THRES BIT(7) 71 #define DCR_DATA_EN BIT(6) 72 #define DCR_DMA_EN BIT(5) 73 #define DCR_DATA_WRITE BIT(4) 74 #define DCR_BLK_SIZE 0x0f 75 76 /* REG_DATA_LENGTH */ 77 #define DATA_LEN_MASK 0xffffff 78 79 /* REG_STATUS */ 80 #define WRITE_PROT BIT(12) 81 #define CARD_DETECT BIT(11) 82 /* 1-10 below can be sent to either registers, interrupt or clear. */ 83 #define CARD_CHANGE BIT(10) 84 #define FIFO_ORUN BIT(9) 85 #define FIFO_URUN BIT(8) 86 #define DATA_END BIT(7) 87 #define CMD_SENT BIT(6) 88 #define DATA_CRC_OK BIT(5) 89 #define RSP_CRC_OK BIT(4) 90 #define DATA_TIMEOUT BIT(3) 91 #define RSP_TIMEOUT BIT(2) 92 #define DATA_CRC_FAIL BIT(1) 93 #define RSP_CRC_FAIL BIT(0) 94 95 #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \ 96 RSP_CRC_OK | CARD_DETECT | CMD_SENT) 97 98 #define MASK_DATA (DATA_CRC_OK | DATA_END | \ 99 DATA_CRC_FAIL | DATA_TIMEOUT) 100 101 #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE) 102 103 /* REG_POWER_CONTROL */ 104 #define SD_POWER_ON BIT(4) 105 #define SD_POWER_MASK 0x0f 106 107 /* REG_CLOCK_CONTROL */ 108 #define CLK_HISPD BIT(9) 109 #define CLK_OFF BIT(8) 110 #define CLK_SD BIT(7) 111 #define CLK_DIV_MASK 0x7f 112 113 /* REG_BUS_WIDTH */ 114 #define BUS_WIDTH_8 BIT(2) 115 #define BUS_WIDTH_4 BIT(1) 116 #define BUS_WIDTH_1 BIT(0) 117 118 #define MMC_VDD_360 23 119 #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK) 120 #define MAX_RETRIES 500000 121 122 struct moxart_host { 123 spinlock_t lock; 124 125 void __iomem *base; 126 127 phys_addr_t reg_phys; 128 129 struct dma_chan *dma_chan_tx; 130 struct dma_chan *dma_chan_rx; 131 struct dma_async_tx_descriptor *tx_desc; 132 struct mmc_host *mmc; 133 struct mmc_request *mrq; 134 struct scatterlist *cur_sg; 135 struct completion dma_complete; 136 struct completion pio_complete; 137 138 u32 num_sg; 139 u32 data_remain; 140 u32 data_len; 141 u32 fifo_width; 142 u32 timeout; 143 u32 rate; 144 145 long sysclk; 146 147 bool have_dma; 148 bool is_removed; 149 }; 150 151 static inline void moxart_init_sg(struct moxart_host *host, 152 struct mmc_data *data) 153 { 154 host->cur_sg = data->sg; 155 host->num_sg = data->sg_len; 156 host->data_remain = host->cur_sg->length; 157 158 if (host->data_remain > host->data_len) 159 host->data_remain = host->data_len; 160 } 161 162 static inline int moxart_next_sg(struct moxart_host *host) 163 { 164 int remain; 165 struct mmc_data *data = host->mrq->cmd->data; 166 167 host->cur_sg++; 168 host->num_sg--; 169 170 if (host->num_sg > 0) { 171 host->data_remain = host->cur_sg->length; 172 remain = host->data_len - data->bytes_xfered; 173 if (remain > 0 && remain < host->data_remain) 174 host->data_remain = remain; 175 } 176 177 return host->num_sg; 178 } 179 180 static int moxart_wait_for_status(struct moxart_host *host, 181 u32 mask, u32 *status) 182 { 183 int ret = -ETIMEDOUT; 184 u32 i; 185 186 for (i = 0; i < MAX_RETRIES; i++) { 187 *status = readl(host->base + REG_STATUS); 188 if (!(*status & mask)) { 189 udelay(5); 190 continue; 191 } 192 writel(*status & mask, host->base + REG_CLEAR); 193 ret = 0; 194 break; 195 } 196 197 if (ret) 198 dev_err(mmc_dev(host->mmc), "timed out waiting for status\n"); 199 200 return ret; 201 } 202 203 204 static void moxart_send_command(struct moxart_host *host, 205 struct mmc_command *cmd) 206 { 207 u32 status, cmdctrl; 208 209 writel(RSP_TIMEOUT | RSP_CRC_OK | 210 RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR); 211 writel(cmd->arg, host->base + REG_ARGUMENT); 212 213 cmdctrl = cmd->opcode & CMD_IDX_MASK; 214 if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND || 215 cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS || 216 cmdctrl == SD_APP_SEND_NUM_WR_BLKS) 217 cmdctrl |= CMD_APP_CMD; 218 219 if (cmd->flags & MMC_RSP_PRESENT) 220 cmdctrl |= CMD_NEED_RSP; 221 222 if (cmd->flags & MMC_RSP_136) 223 cmdctrl |= CMD_LONG_RSP; 224 225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); 226 227 if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT) 228 cmd->error = -ETIMEDOUT; 229 230 if (status & RSP_TIMEOUT) { 231 cmd->error = -ETIMEDOUT; 232 return; 233 } 234 if (status & RSP_CRC_FAIL) { 235 cmd->error = -EIO; 236 return; 237 } 238 if (status & RSP_CRC_OK) { 239 if (cmd->flags & MMC_RSP_136) { 240 cmd->resp[3] = readl(host->base + REG_RESPONSE0); 241 cmd->resp[2] = readl(host->base + REG_RESPONSE1); 242 cmd->resp[1] = readl(host->base + REG_RESPONSE2); 243 cmd->resp[0] = readl(host->base + REG_RESPONSE3); 244 } else { 245 cmd->resp[0] = readl(host->base + REG_RESPONSE0); 246 } 247 } 248 } 249 250 static void moxart_dma_complete(void *param) 251 { 252 struct moxart_host *host = param; 253 254 complete(&host->dma_complete); 255 } 256 257 static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host) 258 { 259 u32 len, dir_data, dir_slave; 260 unsigned long dma_time; 261 struct dma_async_tx_descriptor *desc = NULL; 262 struct dma_chan *dma_chan; 263 264 if (host->data_len == data->bytes_xfered) 265 return; 266 267 if (data->flags & MMC_DATA_WRITE) { 268 dma_chan = host->dma_chan_tx; 269 dir_data = DMA_TO_DEVICE; 270 dir_slave = DMA_MEM_TO_DEV; 271 } else { 272 dma_chan = host->dma_chan_rx; 273 dir_data = DMA_FROM_DEVICE; 274 dir_slave = DMA_DEV_TO_MEM; 275 } 276 277 len = dma_map_sg(dma_chan->device->dev, data->sg, 278 data->sg_len, dir_data); 279 280 if (len > 0) { 281 desc = dmaengine_prep_slave_sg(dma_chan, data->sg, 282 len, dir_slave, 283 DMA_PREP_INTERRUPT | 284 DMA_CTRL_ACK); 285 } else { 286 dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); 287 } 288 289 if (desc) { 290 host->tx_desc = desc; 291 desc->callback = moxart_dma_complete; 292 desc->callback_param = host; 293 dmaengine_submit(desc); 294 dma_async_issue_pending(dma_chan); 295 } 296 297 data->bytes_xfered += host->data_remain; 298 299 dma_time = wait_for_completion_interruptible_timeout( 300 &host->dma_complete, host->timeout); 301 302 dma_unmap_sg(dma_chan->device->dev, 303 data->sg, data->sg_len, 304 dir_data); 305 } 306 307 308 static void moxart_transfer_pio(struct moxart_host *host) 309 { 310 struct mmc_data *data = host->mrq->cmd->data; 311 u32 *sgp, len = 0, remain, status; 312 313 if (host->data_len == data->bytes_xfered) 314 return; 315 316 sgp = sg_virt(host->cur_sg); 317 remain = host->data_remain; 318 319 if (data->flags & MMC_DATA_WRITE) { 320 while (remain > 0) { 321 if (moxart_wait_for_status(host, FIFO_URUN, &status) 322 == -ETIMEDOUT) { 323 data->error = -ETIMEDOUT; 324 complete(&host->pio_complete); 325 return; 326 } 327 for (len = 0; len < remain && len < host->fifo_width;) { 328 iowrite32(*sgp, host->base + REG_DATA_WINDOW); 329 sgp++; 330 len += 4; 331 } 332 remain -= len; 333 } 334 335 } else { 336 while (remain > 0) { 337 if (moxart_wait_for_status(host, FIFO_ORUN, &status) 338 == -ETIMEDOUT) { 339 data->error = -ETIMEDOUT; 340 complete(&host->pio_complete); 341 return; 342 } 343 for (len = 0; len < remain && len < host->fifo_width;) { 344 /* SCR data must be read in big endian. */ 345 if (data->mrq->cmd->opcode == SD_APP_SEND_SCR) 346 *sgp = ioread32be(host->base + 347 REG_DATA_WINDOW); 348 else 349 *sgp = ioread32(host->base + 350 REG_DATA_WINDOW); 351 sgp++; 352 len += 4; 353 } 354 remain -= len; 355 } 356 } 357 358 data->bytes_xfered += host->data_remain - remain; 359 host->data_remain = remain; 360 361 if (host->data_len != data->bytes_xfered) 362 moxart_next_sg(host); 363 else 364 complete(&host->pio_complete); 365 } 366 367 static void moxart_prepare_data(struct moxart_host *host) 368 { 369 struct mmc_data *data = host->mrq->cmd->data; 370 u32 datactrl; 371 int blksz_bits; 372 373 if (!data) 374 return; 375 376 host->data_len = data->blocks * data->blksz; 377 blksz_bits = ffs(data->blksz) - 1; 378 BUG_ON(1 << blksz_bits != data->blksz); 379 380 moxart_init_sg(host, data); 381 382 datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE); 383 384 if (data->flags & MMC_DATA_WRITE) 385 datactrl |= DCR_DATA_WRITE; 386 387 if ((host->data_len > host->fifo_width) && host->have_dma) 388 datactrl |= DCR_DMA_EN; 389 390 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); 391 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); 392 writel(host->rate, host->base + REG_DATA_TIMER); 393 writel(host->data_len, host->base + REG_DATA_LENGTH); 394 writel(datactrl, host->base + REG_DATA_CONTROL); 395 } 396 397 static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq) 398 { 399 struct moxart_host *host = mmc_priv(mmc); 400 unsigned long pio_time, flags; 401 u32 status; 402 403 spin_lock_irqsave(&host->lock, flags); 404 405 init_completion(&host->dma_complete); 406 init_completion(&host->pio_complete); 407 408 host->mrq = mrq; 409 410 if (readl(host->base + REG_STATUS) & CARD_DETECT) { 411 mrq->cmd->error = -ETIMEDOUT; 412 goto request_done; 413 } 414 415 moxart_prepare_data(host); 416 moxart_send_command(host, host->mrq->cmd); 417 418 if (mrq->cmd->data) { 419 if ((host->data_len > host->fifo_width) && host->have_dma) { 420 421 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); 422 423 spin_unlock_irqrestore(&host->lock, flags); 424 425 moxart_transfer_dma(mrq->cmd->data, host); 426 427 spin_lock_irqsave(&host->lock, flags); 428 } else { 429 430 writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK); 431 432 spin_unlock_irqrestore(&host->lock, flags); 433 434 /* PIO transfers start from interrupt. */ 435 pio_time = wait_for_completion_interruptible_timeout( 436 &host->pio_complete, host->timeout); 437 438 spin_lock_irqsave(&host->lock, flags); 439 } 440 441 if (host->is_removed) { 442 dev_err(mmc_dev(host->mmc), "card removed\n"); 443 mrq->cmd->error = -ETIMEDOUT; 444 goto request_done; 445 } 446 447 if (moxart_wait_for_status(host, MASK_DATA, &status) 448 == -ETIMEDOUT) { 449 mrq->cmd->data->error = -ETIMEDOUT; 450 goto request_done; 451 } 452 453 if (status & DATA_CRC_FAIL) 454 mrq->cmd->data->error = -ETIMEDOUT; 455 456 if (mrq->cmd->data->stop) 457 moxart_send_command(host, mrq->cmd->data->stop); 458 } 459 460 request_done: 461 spin_unlock_irqrestore(&host->lock, flags); 462 mmc_request_done(host->mmc, mrq); 463 } 464 465 static irqreturn_t moxart_irq(int irq, void *devid) 466 { 467 struct moxart_host *host = (struct moxart_host *)devid; 468 u32 status; 469 unsigned long flags; 470 471 spin_lock_irqsave(&host->lock, flags); 472 473 status = readl(host->base + REG_STATUS); 474 if (status & CARD_CHANGE) { 475 host->is_removed = status & CARD_DETECT; 476 if (host->is_removed && host->have_dma) { 477 dmaengine_terminate_all(host->dma_chan_tx); 478 dmaengine_terminate_all(host->dma_chan_rx); 479 } 480 host->mrq = NULL; 481 writel(MASK_INTR_PIO, host->base + REG_CLEAR); 482 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); 483 mmc_detect_change(host->mmc, 0); 484 } 485 if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq) 486 moxart_transfer_pio(host); 487 488 spin_unlock_irqrestore(&host->lock, flags); 489 490 return IRQ_HANDLED; 491 } 492 493 static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 494 { 495 struct moxart_host *host = mmc_priv(mmc); 496 unsigned long flags; 497 u8 power, div; 498 u32 ctrl; 499 500 spin_lock_irqsave(&host->lock, flags); 501 502 if (ios->clock) { 503 for (div = 0; div < CLK_DIV_MASK; ++div) { 504 if (ios->clock >= host->sysclk / (2 * (div + 1))) 505 break; 506 } 507 ctrl = CLK_SD | div; 508 host->rate = host->sysclk / (2 * (div + 1)); 509 if (host->rate > host->sysclk) 510 ctrl |= CLK_HISPD; 511 writel(ctrl, host->base + REG_CLOCK_CONTROL); 512 } 513 514 if (ios->power_mode == MMC_POWER_OFF) { 515 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, 516 host->base + REG_POWER_CONTROL); 517 } else { 518 if (ios->vdd < MIN_POWER) 519 power = 0; 520 else 521 power = ios->vdd - MIN_POWER; 522 523 writel(SD_POWER_ON | (u32) power, 524 host->base + REG_POWER_CONTROL); 525 } 526 527 switch (ios->bus_width) { 528 case MMC_BUS_WIDTH_4: 529 writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH); 530 break; 531 case MMC_BUS_WIDTH_8: 532 writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH); 533 break; 534 default: 535 writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH); 536 break; 537 } 538 539 spin_unlock_irqrestore(&host->lock, flags); 540 } 541 542 543 static int moxart_get_ro(struct mmc_host *mmc) 544 { 545 struct moxart_host *host = mmc_priv(mmc); 546 547 return !!(readl(host->base + REG_STATUS) & WRITE_PROT); 548 } 549 550 static struct mmc_host_ops moxart_ops = { 551 .request = moxart_request, 552 .set_ios = moxart_set_ios, 553 .get_ro = moxart_get_ro, 554 }; 555 556 static int moxart_probe(struct platform_device *pdev) 557 { 558 struct device *dev = &pdev->dev; 559 struct device_node *node = dev->of_node; 560 struct resource res_mmc; 561 struct mmc_host *mmc; 562 struct moxart_host *host = NULL; 563 struct dma_slave_config cfg; 564 struct clk *clk; 565 void __iomem *reg_mmc; 566 dma_cap_mask_t mask; 567 int irq, ret; 568 u32 i; 569 570 mmc = mmc_alloc_host(sizeof(struct moxart_host), dev); 571 if (!mmc) { 572 dev_err(dev, "mmc_alloc_host failed\n"); 573 ret = -ENOMEM; 574 goto out; 575 } 576 577 ret = of_address_to_resource(node, 0, &res_mmc); 578 if (ret) { 579 dev_err(dev, "of_address_to_resource failed\n"); 580 goto out; 581 } 582 583 irq = irq_of_parse_and_map(node, 0); 584 if (irq <= 0) { 585 dev_err(dev, "irq_of_parse_and_map failed\n"); 586 ret = -EINVAL; 587 goto out; 588 } 589 590 clk = of_clk_get(node, 0); 591 if (IS_ERR(clk)) { 592 dev_err(dev, "of_clk_get failed\n"); 593 ret = PTR_ERR(clk); 594 goto out; 595 } 596 597 reg_mmc = devm_ioremap_resource(dev, &res_mmc); 598 if (IS_ERR(reg_mmc)) { 599 ret = PTR_ERR(reg_mmc); 600 goto out; 601 } 602 603 mmc_of_parse(mmc); 604 605 dma_cap_zero(mask); 606 dma_cap_set(DMA_SLAVE, mask); 607 608 host = mmc_priv(mmc); 609 host->mmc = mmc; 610 host->base = reg_mmc; 611 host->reg_phys = res_mmc.start; 612 host->timeout = msecs_to_jiffies(1000); 613 host->sysclk = clk_get_rate(clk); 614 host->fifo_width = readl(host->base + REG_FEATURE) << 2; 615 host->dma_chan_tx = of_dma_request_slave_channel(node, "tx"); 616 host->dma_chan_rx = of_dma_request_slave_channel(node, "rx"); 617 618 spin_lock_init(&host->lock); 619 620 mmc->ops = &moxart_ops; 621 mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2); 622 mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2); 623 mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */ 624 625 if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) { 626 dev_dbg(dev, "PIO mode transfer enabled\n"); 627 host->have_dma = false; 628 } else { 629 dev_dbg(dev, "DMA channels found (%p,%p)\n", 630 host->dma_chan_tx, host->dma_chan_rx); 631 host->have_dma = true; 632 633 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 634 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 635 636 cfg.direction = DMA_MEM_TO_DEV; 637 cfg.src_addr = 0; 638 cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW; 639 dmaengine_slave_config(host->dma_chan_tx, &cfg); 640 641 cfg.direction = DMA_DEV_TO_MEM; 642 cfg.src_addr = host->reg_phys + REG_DATA_WINDOW; 643 cfg.dst_addr = 0; 644 dmaengine_slave_config(host->dma_chan_rx, &cfg); 645 } 646 647 switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) { 648 case 1: 649 mmc->caps |= MMC_CAP_4_BIT_DATA; 650 break; 651 case 2: 652 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 653 break; 654 default: 655 break; 656 } 657 658 writel(0, host->base + REG_INTERRUPT_MASK); 659 660 writel(CMD_SDC_RESET, host->base + REG_COMMAND); 661 for (i = 0; i < MAX_RETRIES; i++) { 662 if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET)) 663 break; 664 udelay(5); 665 } 666 667 ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host); 668 if (ret) 669 goto out; 670 671 dev_set_drvdata(dev, mmc); 672 mmc_add_host(mmc); 673 674 dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width); 675 676 return 0; 677 678 out: 679 if (mmc) 680 mmc_free_host(mmc); 681 return ret; 682 } 683 684 static int moxart_remove(struct platform_device *pdev) 685 { 686 struct mmc_host *mmc = dev_get_drvdata(&pdev->dev); 687 struct moxart_host *host = mmc_priv(mmc); 688 689 dev_set_drvdata(&pdev->dev, NULL); 690 691 if (mmc) { 692 if (!IS_ERR(host->dma_chan_tx)) 693 dma_release_channel(host->dma_chan_tx); 694 if (!IS_ERR(host->dma_chan_rx)) 695 dma_release_channel(host->dma_chan_rx); 696 mmc_remove_host(mmc); 697 mmc_free_host(mmc); 698 699 writel(0, host->base + REG_INTERRUPT_MASK); 700 writel(0, host->base + REG_POWER_CONTROL); 701 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, 702 host->base + REG_CLOCK_CONTROL); 703 } 704 705 kfree(host); 706 707 return 0; 708 } 709 710 static const struct of_device_id moxart_mmc_match[] = { 711 { .compatible = "moxa,moxart-mmc" }, 712 { .compatible = "faraday,ftsdc010" }, 713 { } 714 }; 715 716 static struct platform_driver moxart_mmc_driver = { 717 .probe = moxart_probe, 718 .remove = moxart_remove, 719 .driver = { 720 .name = "mmc-moxart", 721 .owner = THIS_MODULE, 722 .of_match_table = moxart_mmc_match, 723 }, 724 }; 725 module_platform_driver(moxart_mmc_driver); 726 727 MODULE_ALIAS("platform:mmc-moxart"); 728 MODULE_DESCRIPTION("MOXA ART MMC driver"); 729 MODULE_LICENSE("GPL v2"); 730 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); 731