xref: /openbmc/linux/drivers/mmc/host/moxart-mmc.c (revision 82003e04)
1 /*
2  * MOXA ART MMC host driver.
3  *
4  * Copyright (C) 2014 Jonas Jensen
5  *
6  * Jonas Jensen <jonas.jensen@gmail.com>
7  *
8  * Based on code from
9  * Moxa Technologies Co., Ltd. <www.moxa.com>
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2.  This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/blkdev.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/sd.h>
27 #include <linux/sched.h>
28 #include <linux/io.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/clk.h>
32 #include <linux/bitops.h>
33 #include <linux/of_dma.h>
34 #include <linux/spinlock.h>
35 
36 #define REG_COMMAND		0
37 #define REG_ARGUMENT		4
38 #define REG_RESPONSE0		8
39 #define REG_RESPONSE1		12
40 #define REG_RESPONSE2		16
41 #define REG_RESPONSE3		20
42 #define REG_RESPONSE_COMMAND	24
43 #define REG_DATA_CONTROL	28
44 #define REG_DATA_TIMER		32
45 #define REG_DATA_LENGTH		36
46 #define REG_STATUS		40
47 #define REG_CLEAR		44
48 #define REG_INTERRUPT_MASK	48
49 #define REG_POWER_CONTROL	52
50 #define REG_CLOCK_CONTROL	56
51 #define REG_BUS_WIDTH		60
52 #define REG_DATA_WINDOW		64
53 #define REG_FEATURE		68
54 #define REG_REVISION		72
55 
56 /* REG_COMMAND */
57 #define CMD_SDC_RESET		BIT(10)
58 #define CMD_EN			BIT(9)
59 #define CMD_APP_CMD		BIT(8)
60 #define CMD_LONG_RSP		BIT(7)
61 #define CMD_NEED_RSP		BIT(6)
62 #define CMD_IDX_MASK		0x3f
63 
64 /* REG_RESPONSE_COMMAND */
65 #define RSP_CMD_APP		BIT(6)
66 #define RSP_CMD_IDX_MASK	0x3f
67 
68 /* REG_DATA_CONTROL */
69 #define DCR_DATA_FIFO_RESET     BIT(8)
70 #define DCR_DATA_THRES          BIT(7)
71 #define DCR_DATA_EN		BIT(6)
72 #define DCR_DMA_EN		BIT(5)
73 #define DCR_DATA_WRITE		BIT(4)
74 #define DCR_BLK_SIZE		0x0f
75 
76 /* REG_DATA_LENGTH */
77 #define DATA_LEN_MASK		0xffffff
78 
79 /* REG_STATUS */
80 #define WRITE_PROT		BIT(12)
81 #define CARD_DETECT		BIT(11)
82 /* 1-10 below can be sent to either registers, interrupt or clear. */
83 #define CARD_CHANGE		BIT(10)
84 #define FIFO_ORUN		BIT(9)
85 #define FIFO_URUN		BIT(8)
86 #define DATA_END		BIT(7)
87 #define CMD_SENT		BIT(6)
88 #define DATA_CRC_OK		BIT(5)
89 #define RSP_CRC_OK		BIT(4)
90 #define DATA_TIMEOUT		BIT(3)
91 #define RSP_TIMEOUT		BIT(2)
92 #define DATA_CRC_FAIL		BIT(1)
93 #define RSP_CRC_FAIL		BIT(0)
94 
95 #define MASK_RSP		(RSP_TIMEOUT | RSP_CRC_FAIL | \
96 				 RSP_CRC_OK  | CARD_DETECT  | CMD_SENT)
97 
98 #define MASK_DATA		(DATA_CRC_OK   | DATA_END | \
99 				 DATA_CRC_FAIL | DATA_TIMEOUT)
100 
101 #define MASK_INTR_PIO		(FIFO_URUN | FIFO_ORUN | CARD_CHANGE)
102 
103 /* REG_POWER_CONTROL */
104 #define SD_POWER_ON		BIT(4)
105 #define SD_POWER_MASK		0x0f
106 
107 /* REG_CLOCK_CONTROL */
108 #define CLK_HISPD		BIT(9)
109 #define CLK_OFF			BIT(8)
110 #define CLK_SD			BIT(7)
111 #define CLK_DIV_MASK		0x7f
112 
113 /* REG_BUS_WIDTH */
114 #define BUS_WIDTH_8		BIT(2)
115 #define BUS_WIDTH_4		BIT(1)
116 #define BUS_WIDTH_1		BIT(0)
117 
118 #define MMC_VDD_360		23
119 #define MIN_POWER		(MMC_VDD_360 - SD_POWER_MASK)
120 #define MAX_RETRIES		500000
121 
122 struct moxart_host {
123 	spinlock_t			lock;
124 
125 	void __iomem			*base;
126 
127 	phys_addr_t			reg_phys;
128 
129 	struct dma_chan			*dma_chan_tx;
130 	struct dma_chan                 *dma_chan_rx;
131 	struct dma_async_tx_descriptor	*tx_desc;
132 	struct mmc_host			*mmc;
133 	struct mmc_request		*mrq;
134 	struct scatterlist		*cur_sg;
135 	struct completion		dma_complete;
136 	struct completion		pio_complete;
137 
138 	u32				num_sg;
139 	u32				data_remain;
140 	u32				data_len;
141 	u32				fifo_width;
142 	u32				timeout;
143 	u32				rate;
144 
145 	long				sysclk;
146 
147 	bool				have_dma;
148 	bool				is_removed;
149 };
150 
151 static inline void moxart_init_sg(struct moxart_host *host,
152 				  struct mmc_data *data)
153 {
154 	host->cur_sg = data->sg;
155 	host->num_sg = data->sg_len;
156 	host->data_remain = host->cur_sg->length;
157 
158 	if (host->data_remain > host->data_len)
159 		host->data_remain = host->data_len;
160 }
161 
162 static inline int moxart_next_sg(struct moxart_host *host)
163 {
164 	int remain;
165 	struct mmc_data *data = host->mrq->cmd->data;
166 
167 	host->cur_sg++;
168 	host->num_sg--;
169 
170 	if (host->num_sg > 0) {
171 		host->data_remain = host->cur_sg->length;
172 		remain = host->data_len - data->bytes_xfered;
173 		if (remain > 0 && remain < host->data_remain)
174 			host->data_remain = remain;
175 	}
176 
177 	return host->num_sg;
178 }
179 
180 static int moxart_wait_for_status(struct moxart_host *host,
181 				  u32 mask, u32 *status)
182 {
183 	int ret = -ETIMEDOUT;
184 	u32 i;
185 
186 	for (i = 0; i < MAX_RETRIES; i++) {
187 		*status = readl(host->base + REG_STATUS);
188 		if (!(*status & mask)) {
189 			udelay(5);
190 			continue;
191 		}
192 		writel(*status & mask, host->base + REG_CLEAR);
193 		ret = 0;
194 		break;
195 	}
196 
197 	if (ret)
198 		dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");
199 
200 	return ret;
201 }
202 
203 
204 static void moxart_send_command(struct moxart_host *host,
205 	struct mmc_command *cmd)
206 {
207 	u32 status, cmdctrl;
208 
209 	writel(RSP_TIMEOUT  | RSP_CRC_OK |
210 	       RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);
211 	writel(cmd->arg, host->base + REG_ARGUMENT);
212 
213 	cmdctrl = cmd->opcode & CMD_IDX_MASK;
214 	if (cmdctrl == SD_APP_SET_BUS_WIDTH    || cmdctrl == SD_APP_OP_COND   ||
215 	    cmdctrl == SD_APP_SEND_SCR         || cmdctrl == SD_APP_SD_STATUS ||
216 	    cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
217 		cmdctrl |= CMD_APP_CMD;
218 
219 	if (cmd->flags & MMC_RSP_PRESENT)
220 		cmdctrl |= CMD_NEED_RSP;
221 
222 	if (cmd->flags & MMC_RSP_136)
223 		cmdctrl |= CMD_LONG_RSP;
224 
225 	writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
226 
227 	if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)
228 		cmd->error = -ETIMEDOUT;
229 
230 	if (status & RSP_TIMEOUT) {
231 		cmd->error = -ETIMEDOUT;
232 		return;
233 	}
234 	if (status & RSP_CRC_FAIL) {
235 		cmd->error = -EIO;
236 		return;
237 	}
238 	if (status & RSP_CRC_OK) {
239 		if (cmd->flags & MMC_RSP_136) {
240 			cmd->resp[3] = readl(host->base + REG_RESPONSE0);
241 			cmd->resp[2] = readl(host->base + REG_RESPONSE1);
242 			cmd->resp[1] = readl(host->base + REG_RESPONSE2);
243 			cmd->resp[0] = readl(host->base + REG_RESPONSE3);
244 		} else {
245 			cmd->resp[0] = readl(host->base + REG_RESPONSE0);
246 		}
247 	}
248 }
249 
250 static void moxart_dma_complete(void *param)
251 {
252 	struct moxart_host *host = param;
253 
254 	complete(&host->dma_complete);
255 }
256 
257 static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)
258 {
259 	u32 len, dir_data, dir_slave;
260 	long dma_time;
261 	struct dma_async_tx_descriptor *desc = NULL;
262 	struct dma_chan *dma_chan;
263 
264 	if (host->data_len == data->bytes_xfered)
265 		return;
266 
267 	if (data->flags & MMC_DATA_WRITE) {
268 		dma_chan = host->dma_chan_tx;
269 		dir_data = DMA_TO_DEVICE;
270 		dir_slave = DMA_MEM_TO_DEV;
271 	} else {
272 		dma_chan = host->dma_chan_rx;
273 		dir_data = DMA_FROM_DEVICE;
274 		dir_slave = DMA_DEV_TO_MEM;
275 	}
276 
277 	len = dma_map_sg(dma_chan->device->dev, data->sg,
278 			 data->sg_len, dir_data);
279 
280 	if (len > 0) {
281 		desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
282 					       len, dir_slave,
283 					       DMA_PREP_INTERRUPT |
284 					       DMA_CTRL_ACK);
285 	} else {
286 		dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
287 	}
288 
289 	if (desc) {
290 		host->tx_desc = desc;
291 		desc->callback = moxart_dma_complete;
292 		desc->callback_param = host;
293 		dmaengine_submit(desc);
294 		dma_async_issue_pending(dma_chan);
295 	}
296 
297 	data->bytes_xfered += host->data_remain;
298 
299 	dma_time = wait_for_completion_interruptible_timeout(
300 		   &host->dma_complete, host->timeout);
301 
302 	dma_unmap_sg(dma_chan->device->dev,
303 		     data->sg, data->sg_len,
304 		     dir_data);
305 }
306 
307 
308 static void moxart_transfer_pio(struct moxart_host *host)
309 {
310 	struct mmc_data *data = host->mrq->cmd->data;
311 	u32 *sgp, len = 0, remain, status;
312 
313 	if (host->data_len == data->bytes_xfered)
314 		return;
315 
316 	sgp = sg_virt(host->cur_sg);
317 	remain = host->data_remain;
318 
319 	if (data->flags & MMC_DATA_WRITE) {
320 		while (remain > 0) {
321 			if (moxart_wait_for_status(host, FIFO_URUN, &status)
322 			     == -ETIMEDOUT) {
323 				data->error = -ETIMEDOUT;
324 				complete(&host->pio_complete);
325 				return;
326 			}
327 			for (len = 0; len < remain && len < host->fifo_width;) {
328 				iowrite32(*sgp, host->base + REG_DATA_WINDOW);
329 				sgp++;
330 				len += 4;
331 			}
332 			remain -= len;
333 		}
334 
335 	} else {
336 		while (remain > 0) {
337 			if (moxart_wait_for_status(host, FIFO_ORUN, &status)
338 			    == -ETIMEDOUT) {
339 				data->error = -ETIMEDOUT;
340 				complete(&host->pio_complete);
341 				return;
342 			}
343 			for (len = 0; len < remain && len < host->fifo_width;) {
344 				/* SCR data must be read in big endian. */
345 				if (data->mrq->cmd->opcode == SD_APP_SEND_SCR)
346 					*sgp = ioread32be(host->base +
347 							  REG_DATA_WINDOW);
348 				else
349 					*sgp = ioread32(host->base +
350 							REG_DATA_WINDOW);
351 				sgp++;
352 				len += 4;
353 			}
354 			remain -= len;
355 		}
356 	}
357 
358 	data->bytes_xfered += host->data_remain - remain;
359 	host->data_remain = remain;
360 
361 	if (host->data_len != data->bytes_xfered)
362 		moxart_next_sg(host);
363 	else
364 		complete(&host->pio_complete);
365 }
366 
367 static void moxart_prepare_data(struct moxart_host *host)
368 {
369 	struct mmc_data *data = host->mrq->cmd->data;
370 	u32 datactrl;
371 	int blksz_bits;
372 
373 	if (!data)
374 		return;
375 
376 	host->data_len = data->blocks * data->blksz;
377 	blksz_bits = ffs(data->blksz) - 1;
378 	BUG_ON(1 << blksz_bits != data->blksz);
379 
380 	moxart_init_sg(host, data);
381 
382 	datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);
383 
384 	if (data->flags & MMC_DATA_WRITE)
385 		datactrl |= DCR_DATA_WRITE;
386 
387 	if ((host->data_len > host->fifo_width) && host->have_dma)
388 		datactrl |= DCR_DMA_EN;
389 
390 	writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
391 	writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
392 	writel(host->rate, host->base + REG_DATA_TIMER);
393 	writel(host->data_len, host->base + REG_DATA_LENGTH);
394 	writel(datactrl, host->base + REG_DATA_CONTROL);
395 }
396 
397 static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)
398 {
399 	struct moxart_host *host = mmc_priv(mmc);
400 	long pio_time;
401 	unsigned long flags;
402 	u32 status;
403 
404 	spin_lock_irqsave(&host->lock, flags);
405 
406 	init_completion(&host->dma_complete);
407 	init_completion(&host->pio_complete);
408 
409 	host->mrq = mrq;
410 
411 	if (readl(host->base + REG_STATUS) & CARD_DETECT) {
412 		mrq->cmd->error = -ETIMEDOUT;
413 		goto request_done;
414 	}
415 
416 	moxart_prepare_data(host);
417 	moxart_send_command(host, host->mrq->cmd);
418 
419 	if (mrq->cmd->data) {
420 		if ((host->data_len > host->fifo_width) && host->have_dma) {
421 
422 			writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
423 
424 			spin_unlock_irqrestore(&host->lock, flags);
425 
426 			moxart_transfer_dma(mrq->cmd->data, host);
427 
428 			spin_lock_irqsave(&host->lock, flags);
429 		} else {
430 
431 			writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
432 
433 			spin_unlock_irqrestore(&host->lock, flags);
434 
435 			/* PIO transfers start from interrupt. */
436 			pio_time = wait_for_completion_interruptible_timeout(
437 				   &host->pio_complete, host->timeout);
438 
439 			spin_lock_irqsave(&host->lock, flags);
440 		}
441 
442 		if (host->is_removed) {
443 			dev_err(mmc_dev(host->mmc), "card removed\n");
444 			mrq->cmd->error = -ETIMEDOUT;
445 			goto request_done;
446 		}
447 
448 		if (moxart_wait_for_status(host, MASK_DATA, &status)
449 		    == -ETIMEDOUT) {
450 			mrq->cmd->data->error = -ETIMEDOUT;
451 			goto request_done;
452 		}
453 
454 		if (status & DATA_CRC_FAIL)
455 			mrq->cmd->data->error = -ETIMEDOUT;
456 
457 		if (mrq->cmd->data->stop)
458 			moxart_send_command(host, mrq->cmd->data->stop);
459 	}
460 
461 request_done:
462 	spin_unlock_irqrestore(&host->lock, flags);
463 	mmc_request_done(host->mmc, mrq);
464 }
465 
466 static irqreturn_t moxart_irq(int irq, void *devid)
467 {
468 	struct moxart_host *host = (struct moxart_host *)devid;
469 	u32 status;
470 	unsigned long flags;
471 
472 	spin_lock_irqsave(&host->lock, flags);
473 
474 	status = readl(host->base + REG_STATUS);
475 	if (status & CARD_CHANGE) {
476 		host->is_removed = status & CARD_DETECT;
477 		if (host->is_removed && host->have_dma) {
478 			dmaengine_terminate_all(host->dma_chan_tx);
479 			dmaengine_terminate_all(host->dma_chan_rx);
480 		}
481 		host->mrq = NULL;
482 		writel(MASK_INTR_PIO, host->base + REG_CLEAR);
483 		writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
484 		mmc_detect_change(host->mmc, 0);
485 	}
486 	if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)
487 		moxart_transfer_pio(host);
488 
489 	spin_unlock_irqrestore(&host->lock, flags);
490 
491 	return IRQ_HANDLED;
492 }
493 
494 static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
495 {
496 	struct moxart_host *host = mmc_priv(mmc);
497 	unsigned long flags;
498 	u8 power, div;
499 	u32 ctrl;
500 
501 	spin_lock_irqsave(&host->lock, flags);
502 
503 	if (ios->clock) {
504 		for (div = 0; div < CLK_DIV_MASK; ++div) {
505 			if (ios->clock >= host->sysclk / (2 * (div + 1)))
506 				break;
507 		}
508 		ctrl = CLK_SD | div;
509 		host->rate = host->sysclk / (2 * (div + 1));
510 		if (host->rate > host->sysclk)
511 			ctrl |= CLK_HISPD;
512 		writel(ctrl, host->base + REG_CLOCK_CONTROL);
513 	}
514 
515 	if (ios->power_mode == MMC_POWER_OFF) {
516 		writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
517 		       host->base + REG_POWER_CONTROL);
518 	} else {
519 		if (ios->vdd < MIN_POWER)
520 			power = 0;
521 		else
522 			power = ios->vdd - MIN_POWER;
523 
524 		writel(SD_POWER_ON | (u32) power,
525 		       host->base + REG_POWER_CONTROL);
526 	}
527 
528 	switch (ios->bus_width) {
529 	case MMC_BUS_WIDTH_4:
530 		writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
531 		break;
532 	case MMC_BUS_WIDTH_8:
533 		writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);
534 		break;
535 	default:
536 		writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
537 		break;
538 	}
539 
540 	spin_unlock_irqrestore(&host->lock, flags);
541 }
542 
543 
544 static int moxart_get_ro(struct mmc_host *mmc)
545 {
546 	struct moxart_host *host = mmc_priv(mmc);
547 
548 	return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
549 }
550 
551 static struct mmc_host_ops moxart_ops = {
552 	.request = moxart_request,
553 	.set_ios = moxart_set_ios,
554 	.get_ro = moxart_get_ro,
555 };
556 
557 static int moxart_probe(struct platform_device *pdev)
558 {
559 	struct device *dev = &pdev->dev;
560 	struct device_node *node = dev->of_node;
561 	struct resource res_mmc;
562 	struct mmc_host *mmc;
563 	struct moxart_host *host = NULL;
564 	struct dma_slave_config cfg;
565 	struct clk *clk;
566 	void __iomem *reg_mmc;
567 	int irq, ret;
568 	u32 i;
569 
570 	mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);
571 	if (!mmc) {
572 		dev_err(dev, "mmc_alloc_host failed\n");
573 		ret = -ENOMEM;
574 		goto out;
575 	}
576 
577 	ret = of_address_to_resource(node, 0, &res_mmc);
578 	if (ret) {
579 		dev_err(dev, "of_address_to_resource failed\n");
580 		goto out;
581 	}
582 
583 	irq = irq_of_parse_and_map(node, 0);
584 	if (irq <= 0) {
585 		dev_err(dev, "irq_of_parse_and_map failed\n");
586 		ret = -EINVAL;
587 		goto out;
588 	}
589 
590 	clk = devm_clk_get(dev, NULL);
591 	if (IS_ERR(clk)) {
592 		ret = PTR_ERR(clk);
593 		goto out;
594 	}
595 
596 	reg_mmc = devm_ioremap_resource(dev, &res_mmc);
597 	if (IS_ERR(reg_mmc)) {
598 		ret = PTR_ERR(reg_mmc);
599 		goto out;
600 	}
601 
602 	ret = mmc_of_parse(mmc);
603 	if (ret)
604 		goto out;
605 
606 	host = mmc_priv(mmc);
607 	host->mmc = mmc;
608 	host->base = reg_mmc;
609 	host->reg_phys = res_mmc.start;
610 	host->timeout = msecs_to_jiffies(1000);
611 	host->sysclk = clk_get_rate(clk);
612 	host->fifo_width = readl(host->base + REG_FEATURE) << 2;
613 	host->dma_chan_tx = dma_request_slave_channel_reason(dev, "tx");
614 	host->dma_chan_rx = dma_request_slave_channel_reason(dev, "rx");
615 
616 	spin_lock_init(&host->lock);
617 
618 	mmc->ops = &moxart_ops;
619 	mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);
620 	mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
621 	mmc->ocr_avail = 0xffff00;	/* Support 2.0v - 3.6v power. */
622 
623 	if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
624 		if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||
625 		    PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {
626 			ret = -EPROBE_DEFER;
627 			goto out;
628 		}
629 		dev_dbg(dev, "PIO mode transfer enabled\n");
630 		host->have_dma = false;
631 	} else {
632 		dev_dbg(dev, "DMA channels found (%p,%p)\n",
633 			 host->dma_chan_tx, host->dma_chan_rx);
634 		host->have_dma = true;
635 
636 		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
637 		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
638 
639 		cfg.direction = DMA_MEM_TO_DEV;
640 		cfg.src_addr = 0;
641 		cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;
642 		dmaengine_slave_config(host->dma_chan_tx, &cfg);
643 
644 		cfg.direction = DMA_DEV_TO_MEM;
645 		cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;
646 		cfg.dst_addr = 0;
647 		dmaengine_slave_config(host->dma_chan_rx, &cfg);
648 	}
649 
650 	switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) {
651 	case 1:
652 		mmc->caps |= MMC_CAP_4_BIT_DATA;
653 		break;
654 	case 2:
655 		mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
656 		break;
657 	default:
658 		break;
659 	}
660 
661 	writel(0, host->base + REG_INTERRUPT_MASK);
662 
663 	writel(CMD_SDC_RESET, host->base + REG_COMMAND);
664 	for (i = 0; i < MAX_RETRIES; i++) {
665 		if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))
666 			break;
667 		udelay(5);
668 	}
669 
670 	ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);
671 	if (ret)
672 		goto out;
673 
674 	dev_set_drvdata(dev, mmc);
675 	mmc_add_host(mmc);
676 
677 	dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);
678 
679 	return 0;
680 
681 out:
682 	if (mmc)
683 		mmc_free_host(mmc);
684 	return ret;
685 }
686 
687 static int moxart_remove(struct platform_device *pdev)
688 {
689 	struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);
690 	struct moxart_host *host = mmc_priv(mmc);
691 
692 	dev_set_drvdata(&pdev->dev, NULL);
693 
694 	if (mmc) {
695 		if (!IS_ERR(host->dma_chan_tx))
696 			dma_release_channel(host->dma_chan_tx);
697 		if (!IS_ERR(host->dma_chan_rx))
698 			dma_release_channel(host->dma_chan_rx);
699 		mmc_remove_host(mmc);
700 		mmc_free_host(mmc);
701 
702 		writel(0, host->base + REG_INTERRUPT_MASK);
703 		writel(0, host->base + REG_POWER_CONTROL);
704 		writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
705 		       host->base + REG_CLOCK_CONTROL);
706 	}
707 	return 0;
708 }
709 
710 static const struct of_device_id moxart_mmc_match[] = {
711 	{ .compatible = "moxa,moxart-mmc" },
712 	{ .compatible = "faraday,ftsdc010" },
713 	{ }
714 };
715 MODULE_DEVICE_TABLE(of, moxart_mmc_match);
716 
717 static struct platform_driver moxart_mmc_driver = {
718 	.probe      = moxart_probe,
719 	.remove     = moxart_remove,
720 	.driver     = {
721 		.name		= "mmc-moxart",
722 		.of_match_table	= moxart_mmc_match,
723 	},
724 };
725 module_platform_driver(moxart_mmc_driver);
726 
727 MODULE_ALIAS("platform:mmc-moxart");
728 MODULE_DESCRIPTION("MOXA ART MMC driver");
729 MODULE_LICENSE("GPL v2");
730 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
731