1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4  * Author: Ludovic.barre@st.com for STMicroelectronics.
5  */
6 #include <linux/bitfield.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/iopoll.h>
10 #include <linux/mmc/host.h>
11 #include <linux/mmc/card.h>
12 #include <linux/of_address.h>
13 #include <linux/reset.h>
14 #include <linux/scatterlist.h>
15 #include "mmci.h"
16 
17 #define SDMMC_LLI_BUF_LEN	PAGE_SIZE
18 #define SDMMC_IDMA_BURST	BIT(MMCI_STM32_IDMABNDT_SHIFT)
19 
20 #define DLYB_CR			0x0
21 #define DLYB_CR_DEN		BIT(0)
22 #define DLYB_CR_SEN		BIT(1)
23 
24 #define DLYB_CFGR		0x4
25 #define DLYB_CFGR_SEL_MASK	GENMASK(3, 0)
26 #define DLYB_CFGR_UNIT_MASK	GENMASK(14, 8)
27 #define DLYB_CFGR_LNG_MASK	GENMASK(27, 16)
28 #define DLYB_CFGR_LNGF		BIT(31)
29 
30 #define DLYB_NB_DELAY		11
31 #define DLYB_CFGR_SEL_MAX	(DLYB_NB_DELAY + 1)
32 #define DLYB_CFGR_UNIT_MAX	127
33 
34 #define DLYB_LNG_TIMEOUT_US	1000
35 #define SDMMC_VSWEND_TIMEOUT_US 10000
36 
37 struct sdmmc_lli_desc {
38 	u32 idmalar;
39 	u32 idmabase;
40 	u32 idmasize;
41 };
42 
43 struct sdmmc_idma {
44 	dma_addr_t sg_dma;
45 	void *sg_cpu;
46 };
47 
48 struct sdmmc_dlyb {
49 	void __iomem *base;
50 	u32 unit;
51 	u32 max;
52 };
53 
54 static int sdmmc_idma_validate_data(struct mmci_host *host,
55 				    struct mmc_data *data)
56 {
57 	struct scatterlist *sg;
58 	int i;
59 
60 	/*
61 	 * idma has constraints on idmabase & idmasize for each element
62 	 * excepted the last element which has no constraint on idmasize
63 	 */
64 	for_each_sg(data->sg, sg, data->sg_len - 1, i) {
65 		if (!IS_ALIGNED(data->sg->offset, sizeof(u32)) ||
66 		    !IS_ALIGNED(data->sg->length, SDMMC_IDMA_BURST)) {
67 			dev_err(mmc_dev(host->mmc),
68 				"unaligned scatterlist: ofst:%x length:%d\n",
69 				data->sg->offset, data->sg->length);
70 			return -EINVAL;
71 		}
72 	}
73 
74 	if (!IS_ALIGNED(data->sg->offset, sizeof(u32))) {
75 		dev_err(mmc_dev(host->mmc),
76 			"unaligned last scatterlist: ofst:%x length:%d\n",
77 			data->sg->offset, data->sg->length);
78 		return -EINVAL;
79 	}
80 
81 	return 0;
82 }
83 
84 static int _sdmmc_idma_prep_data(struct mmci_host *host,
85 				 struct mmc_data *data)
86 {
87 	int n_elem;
88 
89 	n_elem = dma_map_sg(mmc_dev(host->mmc),
90 			    data->sg,
91 			    data->sg_len,
92 			    mmc_get_dma_dir(data));
93 
94 	if (!n_elem) {
95 		dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
96 		return -EINVAL;
97 	}
98 
99 	return 0;
100 }
101 
102 static int sdmmc_idma_prep_data(struct mmci_host *host,
103 				struct mmc_data *data, bool next)
104 {
105 	/* Check if job is already prepared. */
106 	if (!next && data->host_cookie == host->next_cookie)
107 		return 0;
108 
109 	return _sdmmc_idma_prep_data(host, data);
110 }
111 
112 static void sdmmc_idma_unprep_data(struct mmci_host *host,
113 				   struct mmc_data *data, int err)
114 {
115 	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
116 		     mmc_get_dma_dir(data));
117 }
118 
119 static int sdmmc_idma_setup(struct mmci_host *host)
120 {
121 	struct sdmmc_idma *idma;
122 	struct device *dev = mmc_dev(host->mmc);
123 
124 	idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
125 	if (!idma)
126 		return -ENOMEM;
127 
128 	host->dma_priv = idma;
129 
130 	if (host->variant->dma_lli) {
131 		idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
132 						   &idma->sg_dma, GFP_KERNEL);
133 		if (!idma->sg_cpu) {
134 			dev_err(dev, "Failed to alloc IDMA descriptor\n");
135 			return -ENOMEM;
136 		}
137 		host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
138 			sizeof(struct sdmmc_lli_desc);
139 		host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
140 	} else {
141 		host->mmc->max_segs = 1;
142 		host->mmc->max_seg_size = host->mmc->max_req_size;
143 	}
144 
145 	return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
146 }
147 
148 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
149 
150 {
151 	struct sdmmc_idma *idma = host->dma_priv;
152 	struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
153 	struct mmc_data *data = host->data;
154 	struct scatterlist *sg;
155 	int i;
156 
157 	if (!host->variant->dma_lli || data->sg_len == 1) {
158 		writel_relaxed(sg_dma_address(data->sg),
159 			       host->base + MMCI_STM32_IDMABASE0R);
160 		writel_relaxed(MMCI_STM32_IDMAEN,
161 			       host->base + MMCI_STM32_IDMACTRLR);
162 		return 0;
163 	}
164 
165 	for_each_sg(data->sg, sg, data->sg_len, i) {
166 		desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
167 		desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
168 			| MMCI_STM32_ABR;
169 		desc[i].idmabase = sg_dma_address(sg);
170 		desc[i].idmasize = sg_dma_len(sg);
171 	}
172 
173 	/* notice the end of link list */
174 	desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
175 
176 	dma_wmb();
177 	writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
178 	writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
179 	writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
180 	writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
181 	writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
182 		       host->base + MMCI_STM32_IDMACTRLR);
183 
184 	return 0;
185 }
186 
187 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
188 {
189 	writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
190 
191 	if (!data->host_cookie)
192 		sdmmc_idma_unprep_data(host, data, 0);
193 }
194 
195 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
196 {
197 	unsigned int clk = 0, ddr = 0;
198 
199 	if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
200 	    host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
201 		ddr = MCI_STM32_CLK_DDR;
202 
203 	/*
204 	 * cclk = mclk / (2 * clkdiv)
205 	 * clkdiv 0 => bypass
206 	 * in ddr mode bypass is not possible
207 	 */
208 	if (desired) {
209 		if (desired >= host->mclk && !ddr) {
210 			host->cclk = host->mclk;
211 		} else {
212 			clk = DIV_ROUND_UP(host->mclk, 2 * desired);
213 			if (clk > MCI_STM32_CLK_CLKDIV_MSK)
214 				clk = MCI_STM32_CLK_CLKDIV_MSK;
215 			host->cclk = host->mclk / (2 * clk);
216 		}
217 	} else {
218 		/*
219 		 * while power-on phase the clock can't be define to 0,
220 		 * Only power-off and power-cyc deactivate the clock.
221 		 * if desired clock is 0, set max divider
222 		 */
223 		clk = MCI_STM32_CLK_CLKDIV_MSK;
224 		host->cclk = host->mclk / (2 * clk);
225 	}
226 
227 	/* Set actual clock for debug */
228 	if (host->mmc->ios.power_mode == MMC_POWER_ON)
229 		host->mmc->actual_clock = host->cclk;
230 	else
231 		host->mmc->actual_clock = 0;
232 
233 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
234 		clk |= MCI_STM32_CLK_WIDEBUS_4;
235 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
236 		clk |= MCI_STM32_CLK_WIDEBUS_8;
237 
238 	clk |= MCI_STM32_CLK_HWFCEN;
239 	clk |= host->clk_reg_add;
240 	clk |= ddr;
241 
242 	/*
243 	 * SDMMC_FBCK is selected when an external Delay Block is needed
244 	 * with SDR104 or HS200.
245 	 */
246 	if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
247 		clk |= MCI_STM32_CLK_BUSSPEED;
248 		if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
249 		    host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
250 			clk &= ~MCI_STM32_CLK_SEL_MSK;
251 			clk |= MCI_STM32_CLK_SELFBCK;
252 		}
253 	}
254 
255 	mmci_write_clkreg(host, clk);
256 }
257 
258 static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb)
259 {
260 	if (!dlyb || !dlyb->base)
261 		return;
262 
263 	/* Output clock = Input clock */
264 	writel_relaxed(0, dlyb->base + DLYB_CR);
265 }
266 
267 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
268 {
269 	struct mmc_ios ios = host->mmc->ios;
270 	struct sdmmc_dlyb *dlyb = host->variant_priv;
271 
272 	/* adds OF options */
273 	pwr = host->pwr_reg_add;
274 
275 	sdmmc_dlyb_input_ck(dlyb);
276 
277 	if (ios.power_mode == MMC_POWER_OFF) {
278 		/* Only a reset could power-off sdmmc */
279 		reset_control_assert(host->rst);
280 		udelay(2);
281 		reset_control_deassert(host->rst);
282 
283 		/*
284 		 * Set the SDMMC in Power-cycle state.
285 		 * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
286 		 * are driven low, to prevent the Card from being supplied
287 		 * through the signal lines.
288 		 */
289 		mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
290 	} else if (ios.power_mode == MMC_POWER_ON) {
291 		/*
292 		 * After power-off (reset): the irq mask defined in probe
293 		 * functionis lost
294 		 * ault irq mask (probe) must be activated
295 		 */
296 		writel(MCI_IRQENABLE | host->variant->start_err,
297 		       host->base + MMCIMASK0);
298 
299 		/* preserves voltage switch bits */
300 		pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
301 					MCI_STM32_VSWITCH);
302 
303 		/*
304 		 * After a power-cycle state, we must set the SDMMC in
305 		 * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
306 		 * driven high. Then we can set the SDMMC to Power-on state
307 		 */
308 		mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
309 		mdelay(1);
310 		mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
311 	}
312 }
313 
314 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
315 {
316 	u32 datactrl;
317 
318 	datactrl = mmci_dctrl_blksz(host);
319 
320 	if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
321 	    host->data->blocks == 1)
322 		datactrl |= MCI_DPSM_STM32_MODE_SDIO;
323 	else if (host->data->stop && !host->mrq->sbc)
324 		datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
325 	else
326 		datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
327 
328 	return datactrl;
329 }
330 
331 static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
332 {
333 	void __iomem *base = host->base;
334 	u32 busy_d0, busy_d0end, mask, sdmmc_status;
335 
336 	mask = readl_relaxed(base + MMCIMASK0);
337 	sdmmc_status = readl_relaxed(base + MMCISTATUS);
338 	busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
339 	busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
340 
341 	/* complete if there is an error or busy_d0end */
342 	if ((status & err_msk) || busy_d0end)
343 		goto complete;
344 
345 	/*
346 	 * On response the busy signaling is reflected in the BUSYD0 flag.
347 	 * if busy_d0 is in-progress we must activate busyd0end interrupt
348 	 * to wait this completion. Else this request has no busy step.
349 	 */
350 	if (busy_d0) {
351 		if (!host->busy_status) {
352 			writel_relaxed(mask | host->variant->busy_detect_mask,
353 				       base + MMCIMASK0);
354 			host->busy_status = status &
355 				(MCI_CMDSENT | MCI_CMDRESPEND);
356 		}
357 		return false;
358 	}
359 
360 complete:
361 	if (host->busy_status) {
362 		writel_relaxed(mask & ~host->variant->busy_detect_mask,
363 			       base + MMCIMASK0);
364 		host->busy_status = 0;
365 	}
366 
367 	writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
368 
369 	return true;
370 }
371 
372 static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb,
373 				int unit, int phase, bool sampler)
374 {
375 	u32 cfgr;
376 
377 	writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
378 
379 	cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
380 	       FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
381 	writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
382 
383 	if (!sampler)
384 		writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
385 }
386 
387 static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
388 {
389 	struct sdmmc_dlyb *dlyb = host->variant_priv;
390 	u32 cfgr;
391 	int i, lng, ret;
392 
393 	for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
394 		sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true);
395 
396 		ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
397 						 (cfgr & DLYB_CFGR_LNGF),
398 						 1, DLYB_LNG_TIMEOUT_US);
399 		if (ret) {
400 			dev_warn(mmc_dev(host->mmc),
401 				 "delay line cfg timeout unit:%d cfgr:%d\n",
402 				 i, cfgr);
403 			continue;
404 		}
405 
406 		lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
407 		if (lng < BIT(DLYB_NB_DELAY) && lng > 0)
408 			break;
409 	}
410 
411 	if (i > DLYB_CFGR_UNIT_MAX)
412 		return -EINVAL;
413 
414 	dlyb->unit = i;
415 	dlyb->max = __fls(lng);
416 
417 	return 0;
418 }
419 
420 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
421 {
422 	struct sdmmc_dlyb *dlyb = host->variant_priv;
423 	int cur_len = 0, max_len = 0, end_of_len = 0;
424 	int phase;
425 
426 	for (phase = 0; phase <= dlyb->max; phase++) {
427 		sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
428 
429 		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
430 			cur_len = 0;
431 		} else {
432 			cur_len++;
433 			if (cur_len > max_len) {
434 				max_len = cur_len;
435 				end_of_len = phase;
436 			}
437 		}
438 	}
439 
440 	if (!max_len) {
441 		dev_err(mmc_dev(host->mmc), "no tuning point found\n");
442 		return -EINVAL;
443 	}
444 
445 	writel_relaxed(0, dlyb->base + DLYB_CR);
446 
447 	phase = end_of_len - max_len / 2;
448 	sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
449 
450 	dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
451 		dlyb->unit, dlyb->max, phase);
452 
453 	return 0;
454 }
455 
456 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
457 {
458 	struct mmci_host *host = mmc_priv(mmc);
459 	struct sdmmc_dlyb *dlyb = host->variant_priv;
460 
461 	if (!dlyb || !dlyb->base)
462 		return -EINVAL;
463 
464 	if (sdmmc_dlyb_lng_tuning(host))
465 		return -EINVAL;
466 
467 	return sdmmc_dlyb_phase_tuning(host, opcode);
468 }
469 
470 static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
471 {
472 	/* clear the voltage switch completion flag */
473 	writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
474 	/* enable Voltage switch procedure */
475 	mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
476 }
477 
478 static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
479 				      struct mmc_ios *ios)
480 {
481 	unsigned long flags;
482 	u32 status;
483 	int ret = 0;
484 
485 	spin_lock_irqsave(&host->lock, flags);
486 	if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 &&
487 	    host->pwr_reg & MCI_STM32_VSWITCHEN) {
488 		mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
489 		spin_unlock_irqrestore(&host->lock, flags);
490 
491 		/* wait voltage switch completion while 10ms */
492 		ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
493 						 status,
494 						 (status & MCI_STM32_VSWEND),
495 						 10, SDMMC_VSWEND_TIMEOUT_US);
496 
497 		writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
498 			       host->base + MMCICLEAR);
499 		spin_lock_irqsave(&host->lock, flags);
500 		mmci_write_pwrreg(host, host->pwr_reg &
501 				  ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
502 	}
503 	spin_unlock_irqrestore(&host->lock, flags);
504 
505 	return ret;
506 }
507 
508 static struct mmci_host_ops sdmmc_variant_ops = {
509 	.validate_data = sdmmc_idma_validate_data,
510 	.prep_data = sdmmc_idma_prep_data,
511 	.unprep_data = sdmmc_idma_unprep_data,
512 	.get_datactrl_cfg = sdmmc_get_dctrl_cfg,
513 	.dma_setup = sdmmc_idma_setup,
514 	.dma_start = sdmmc_idma_start,
515 	.dma_finalize = sdmmc_idma_finalize,
516 	.set_clkreg = mmci_sdmmc_set_clkreg,
517 	.set_pwrreg = mmci_sdmmc_set_pwrreg,
518 	.busy_complete = sdmmc_busy_complete,
519 	.pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch,
520 	.post_sig_volt_switch = sdmmc_post_sig_volt_switch,
521 };
522 
523 void sdmmc_variant_init(struct mmci_host *host)
524 {
525 	struct device_node *np = host->mmc->parent->of_node;
526 	void __iomem *base_dlyb;
527 	struct sdmmc_dlyb *dlyb;
528 
529 	host->ops = &sdmmc_variant_ops;
530 	host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
531 
532 	base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
533 	if (IS_ERR(base_dlyb))
534 		return;
535 
536 	dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
537 	if (!dlyb)
538 		return;
539 
540 	dlyb->base = base_dlyb;
541 	host->variant_priv = dlyb;
542 	host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
543 }
544