1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4  * Author: Ludovic.barre@st.com for STMicroelectronics.
5  */
6 #include <linux/bitfield.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/iopoll.h>
10 #include <linux/mmc/host.h>
11 #include <linux/mmc/card.h>
12 #include <linux/of_address.h>
13 #include <linux/reset.h>
14 #include <linux/scatterlist.h>
15 #include "mmci.h"
16 
17 #define SDMMC_LLI_BUF_LEN	PAGE_SIZE
18 #define SDMMC_IDMA_BURST	BIT(MMCI_STM32_IDMABNDT_SHIFT)
19 
20 #define DLYB_CR			0x0
21 #define DLYB_CR_DEN		BIT(0)
22 #define DLYB_CR_SEN		BIT(1)
23 
24 #define DLYB_CFGR		0x4
25 #define DLYB_CFGR_SEL_MASK	GENMASK(3, 0)
26 #define DLYB_CFGR_UNIT_MASK	GENMASK(14, 8)
27 #define DLYB_CFGR_LNG_MASK	GENMASK(27, 16)
28 #define DLYB_CFGR_LNGF		BIT(31)
29 
30 #define DLYB_NB_DELAY		11
31 #define DLYB_CFGR_SEL_MAX	(DLYB_NB_DELAY + 1)
32 #define DLYB_CFGR_UNIT_MAX	127
33 
34 #define DLYB_LNG_TIMEOUT_US	1000
35 
36 struct sdmmc_lli_desc {
37 	u32 idmalar;
38 	u32 idmabase;
39 	u32 idmasize;
40 };
41 
42 struct sdmmc_idma {
43 	dma_addr_t sg_dma;
44 	void *sg_cpu;
45 };
46 
47 struct sdmmc_dlyb {
48 	void __iomem *base;
49 	u32 unit;
50 	u32 max;
51 };
52 
53 static int sdmmc_idma_validate_data(struct mmci_host *host,
54 				    struct mmc_data *data)
55 {
56 	struct scatterlist *sg;
57 	int i;
58 
59 	/*
60 	 * idma has constraints on idmabase & idmasize for each element
61 	 * excepted the last element which has no constraint on idmasize
62 	 */
63 	for_each_sg(data->sg, sg, data->sg_len - 1, i) {
64 		if (!IS_ALIGNED(data->sg->offset, sizeof(u32)) ||
65 		    !IS_ALIGNED(data->sg->length, SDMMC_IDMA_BURST)) {
66 			dev_err(mmc_dev(host->mmc),
67 				"unaligned scatterlist: ofst:%x length:%d\n",
68 				data->sg->offset, data->sg->length);
69 			return -EINVAL;
70 		}
71 	}
72 
73 	if (!IS_ALIGNED(data->sg->offset, sizeof(u32))) {
74 		dev_err(mmc_dev(host->mmc),
75 			"unaligned last scatterlist: ofst:%x length:%d\n",
76 			data->sg->offset, data->sg->length);
77 		return -EINVAL;
78 	}
79 
80 	return 0;
81 }
82 
83 static int _sdmmc_idma_prep_data(struct mmci_host *host,
84 				 struct mmc_data *data)
85 {
86 	int n_elem;
87 
88 	n_elem = dma_map_sg(mmc_dev(host->mmc),
89 			    data->sg,
90 			    data->sg_len,
91 			    mmc_get_dma_dir(data));
92 
93 	if (!n_elem) {
94 		dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
95 		return -EINVAL;
96 	}
97 
98 	return 0;
99 }
100 
101 static int sdmmc_idma_prep_data(struct mmci_host *host,
102 				struct mmc_data *data, bool next)
103 {
104 	/* Check if job is already prepared. */
105 	if (!next && data->host_cookie == host->next_cookie)
106 		return 0;
107 
108 	return _sdmmc_idma_prep_data(host, data);
109 }
110 
111 static void sdmmc_idma_unprep_data(struct mmci_host *host,
112 				   struct mmc_data *data, int err)
113 {
114 	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
115 		     mmc_get_dma_dir(data));
116 }
117 
118 static int sdmmc_idma_setup(struct mmci_host *host)
119 {
120 	struct sdmmc_idma *idma;
121 
122 	idma = devm_kzalloc(mmc_dev(host->mmc), sizeof(*idma), GFP_KERNEL);
123 	if (!idma)
124 		return -ENOMEM;
125 
126 	host->dma_priv = idma;
127 
128 	if (host->variant->dma_lli) {
129 		idma->sg_cpu = dmam_alloc_coherent(mmc_dev(host->mmc),
130 						   SDMMC_LLI_BUF_LEN,
131 						   &idma->sg_dma, GFP_KERNEL);
132 		if (!idma->sg_cpu) {
133 			dev_err(mmc_dev(host->mmc),
134 				"Failed to alloc IDMA descriptor\n");
135 			return -ENOMEM;
136 		}
137 		host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
138 			sizeof(struct sdmmc_lli_desc);
139 		host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
140 	} else {
141 		host->mmc->max_segs = 1;
142 		host->mmc->max_seg_size = host->mmc->max_req_size;
143 	}
144 
145 	return 0;
146 }
147 
148 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
149 
150 {
151 	struct sdmmc_idma *idma = host->dma_priv;
152 	struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
153 	struct mmc_data *data = host->data;
154 	struct scatterlist *sg;
155 	int i;
156 
157 	if (!host->variant->dma_lli || data->sg_len == 1) {
158 		writel_relaxed(sg_dma_address(data->sg),
159 			       host->base + MMCI_STM32_IDMABASE0R);
160 		writel_relaxed(MMCI_STM32_IDMAEN,
161 			       host->base + MMCI_STM32_IDMACTRLR);
162 		return 0;
163 	}
164 
165 	for_each_sg(data->sg, sg, data->sg_len, i) {
166 		desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
167 		desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
168 			| MMCI_STM32_ABR;
169 		desc[i].idmabase = sg_dma_address(sg);
170 		desc[i].idmasize = sg_dma_len(sg);
171 	}
172 
173 	/* notice the end of link list */
174 	desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
175 
176 	dma_wmb();
177 	writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
178 	writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
179 	writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
180 	writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
181 	writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
182 		       host->base + MMCI_STM32_IDMACTRLR);
183 
184 	return 0;
185 }
186 
187 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
188 {
189 	writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
190 }
191 
192 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
193 {
194 	unsigned int clk = 0, ddr = 0;
195 
196 	if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
197 	    host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
198 		ddr = MCI_STM32_CLK_DDR;
199 
200 	/*
201 	 * cclk = mclk / (2 * clkdiv)
202 	 * clkdiv 0 => bypass
203 	 * in ddr mode bypass is not possible
204 	 */
205 	if (desired) {
206 		if (desired >= host->mclk && !ddr) {
207 			host->cclk = host->mclk;
208 		} else {
209 			clk = DIV_ROUND_UP(host->mclk, 2 * desired);
210 			if (clk > MCI_STM32_CLK_CLKDIV_MSK)
211 				clk = MCI_STM32_CLK_CLKDIV_MSK;
212 			host->cclk = host->mclk / (2 * clk);
213 		}
214 	} else {
215 		/*
216 		 * while power-on phase the clock can't be define to 0,
217 		 * Only power-off and power-cyc deactivate the clock.
218 		 * if desired clock is 0, set max divider
219 		 */
220 		clk = MCI_STM32_CLK_CLKDIV_MSK;
221 		host->cclk = host->mclk / (2 * clk);
222 	}
223 
224 	/* Set actual clock for debug */
225 	if (host->mmc->ios.power_mode == MMC_POWER_ON)
226 		host->mmc->actual_clock = host->cclk;
227 	else
228 		host->mmc->actual_clock = 0;
229 
230 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
231 		clk |= MCI_STM32_CLK_WIDEBUS_4;
232 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
233 		clk |= MCI_STM32_CLK_WIDEBUS_8;
234 
235 	clk |= MCI_STM32_CLK_HWFCEN;
236 	clk |= host->clk_reg_add;
237 	clk |= ddr;
238 
239 	/*
240 	 * SDMMC_FBCK is selected when an external Delay Block is needed
241 	 * with SDR104.
242 	 */
243 	if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
244 		clk |= MCI_STM32_CLK_BUSSPEED;
245 		if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
246 			clk &= ~MCI_STM32_CLK_SEL_MSK;
247 			clk |= MCI_STM32_CLK_SELFBCK;
248 		}
249 	}
250 
251 	mmci_write_clkreg(host, clk);
252 }
253 
254 static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb)
255 {
256 	if (!dlyb || !dlyb->base)
257 		return;
258 
259 	/* Output clock = Input clock */
260 	writel_relaxed(0, dlyb->base + DLYB_CR);
261 }
262 
263 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
264 {
265 	struct mmc_ios ios = host->mmc->ios;
266 	struct sdmmc_dlyb *dlyb = host->variant_priv;
267 
268 	pwr = host->pwr_reg_add;
269 
270 	sdmmc_dlyb_input_ck(dlyb);
271 
272 	if (ios.power_mode == MMC_POWER_OFF) {
273 		/* Only a reset could power-off sdmmc */
274 		reset_control_assert(host->rst);
275 		udelay(2);
276 		reset_control_deassert(host->rst);
277 
278 		/*
279 		 * Set the SDMMC in Power-cycle state.
280 		 * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
281 		 * are driven low, to prevent the Card from being supplied
282 		 * through the signal lines.
283 		 */
284 		mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
285 	} else if (ios.power_mode == MMC_POWER_ON) {
286 		/*
287 		 * After power-off (reset): the irq mask defined in probe
288 		 * functionis lost
289 		 * ault irq mask (probe) must be activated
290 		 */
291 		writel(MCI_IRQENABLE | host->variant->start_err,
292 		       host->base + MMCIMASK0);
293 
294 		/*
295 		 * After a power-cycle state, we must set the SDMMC in
296 		 * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
297 		 * driven high. Then we can set the SDMMC to Power-on state
298 		 */
299 		mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
300 		mdelay(1);
301 		mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
302 	}
303 }
304 
305 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
306 {
307 	u32 datactrl;
308 
309 	datactrl = mmci_dctrl_blksz(host);
310 
311 	if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
312 	    host->data->blocks == 1)
313 		datactrl |= MCI_DPSM_STM32_MODE_SDIO;
314 	else if (host->data->stop && !host->mrq->sbc)
315 		datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
316 	else
317 		datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
318 
319 	return datactrl;
320 }
321 
322 static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
323 {
324 	void __iomem *base = host->base;
325 	u32 busy_d0, busy_d0end, mask, sdmmc_status;
326 
327 	mask = readl_relaxed(base + MMCIMASK0);
328 	sdmmc_status = readl_relaxed(base + MMCISTATUS);
329 	busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
330 	busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
331 
332 	/* complete if there is an error or busy_d0end */
333 	if ((status & err_msk) || busy_d0end)
334 		goto complete;
335 
336 	/*
337 	 * On response the busy signaling is reflected in the BUSYD0 flag.
338 	 * if busy_d0 is in-progress we must activate busyd0end interrupt
339 	 * to wait this completion. Else this request has no busy step.
340 	 */
341 	if (busy_d0) {
342 		if (!host->busy_status) {
343 			writel_relaxed(mask | host->variant->busy_detect_mask,
344 				       base + MMCIMASK0);
345 			host->busy_status = status &
346 				(MCI_CMDSENT | MCI_CMDRESPEND);
347 		}
348 		return false;
349 	}
350 
351 complete:
352 	if (host->busy_status) {
353 		writel_relaxed(mask & ~host->variant->busy_detect_mask,
354 			       base + MMCIMASK0);
355 		writel_relaxed(host->variant->busy_detect_mask,
356 			       base + MMCICLEAR);
357 		host->busy_status = 0;
358 	}
359 
360 	return true;
361 }
362 
363 static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb,
364 				int unit, int phase, bool sampler)
365 {
366 	u32 cfgr;
367 
368 	writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
369 
370 	cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
371 	       FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
372 	writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
373 
374 	if (!sampler)
375 		writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
376 }
377 
378 static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
379 {
380 	struct sdmmc_dlyb *dlyb = host->variant_priv;
381 	u32 cfgr;
382 	int i, lng, ret;
383 
384 	for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
385 		sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true);
386 
387 		ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
388 						 (cfgr & DLYB_CFGR_LNGF),
389 						 1, DLYB_LNG_TIMEOUT_US);
390 		if (ret) {
391 			dev_warn(mmc_dev(host->mmc),
392 				 "delay line cfg timeout unit:%d cfgr:%d\n",
393 				 i, cfgr);
394 			continue;
395 		}
396 
397 		lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
398 		if (lng < BIT(DLYB_NB_DELAY) && lng > 0)
399 			break;
400 	}
401 
402 	if (i > DLYB_CFGR_UNIT_MAX)
403 		return -EINVAL;
404 
405 	dlyb->unit = i;
406 	dlyb->max = __fls(lng);
407 
408 	return 0;
409 }
410 
411 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
412 {
413 	struct sdmmc_dlyb *dlyb = host->variant_priv;
414 	int cur_len = 0, max_len = 0, end_of_len = 0;
415 	int phase;
416 
417 	for (phase = 0; phase <= dlyb->max; phase++) {
418 		sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
419 
420 		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
421 			cur_len = 0;
422 		} else {
423 			cur_len++;
424 			if (cur_len > max_len) {
425 				max_len = cur_len;
426 				end_of_len = phase;
427 			}
428 		}
429 	}
430 
431 	if (!max_len) {
432 		dev_err(mmc_dev(host->mmc), "no tuning point found\n");
433 		return -EINVAL;
434 	}
435 
436 	phase = end_of_len - max_len / 2;
437 	sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
438 
439 	dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
440 		dlyb->unit, dlyb->max, phase);
441 
442 	return 0;
443 }
444 
445 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
446 {
447 	struct mmci_host *host = mmc_priv(mmc);
448 	struct sdmmc_dlyb *dlyb = host->variant_priv;
449 
450 	if (!dlyb || !dlyb->base)
451 		return -EINVAL;
452 
453 	if (sdmmc_dlyb_lng_tuning(host))
454 		return -EINVAL;
455 
456 	return sdmmc_dlyb_phase_tuning(host, opcode);
457 }
458 
459 static struct mmci_host_ops sdmmc_variant_ops = {
460 	.validate_data = sdmmc_idma_validate_data,
461 	.prep_data = sdmmc_idma_prep_data,
462 	.unprep_data = sdmmc_idma_unprep_data,
463 	.get_datactrl_cfg = sdmmc_get_dctrl_cfg,
464 	.dma_setup = sdmmc_idma_setup,
465 	.dma_start = sdmmc_idma_start,
466 	.dma_finalize = sdmmc_idma_finalize,
467 	.set_clkreg = mmci_sdmmc_set_clkreg,
468 	.set_pwrreg = mmci_sdmmc_set_pwrreg,
469 	.busy_complete = sdmmc_busy_complete,
470 };
471 
472 void sdmmc_variant_init(struct mmci_host *host)
473 {
474 	struct device_node *np = host->mmc->parent->of_node;
475 	void __iomem *base_dlyb;
476 	struct sdmmc_dlyb *dlyb;
477 
478 	host->ops = &sdmmc_variant_ops;
479 
480 	base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
481 	if (IS_ERR(base_dlyb))
482 		return;
483 
484 	dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
485 	if (!dlyb)
486 		return;
487 
488 	dlyb->base = base_dlyb;
489 	host->variant_priv = dlyb;
490 	host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
491 }
492