146b723ddSLudovic Barre // SPDX-License-Identifier: GPL-2.0 246b723ddSLudovic Barre /* 346b723ddSLudovic Barre * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 446b723ddSLudovic Barre * Author: Ludovic.barre@st.com for STMicroelectronics. 546b723ddSLudovic Barre */ 61103f807SLudovic Barre #include <linux/bitfield.h> 746b723ddSLudovic Barre #include <linux/delay.h> 846b723ddSLudovic Barre #include <linux/dma-mapping.h> 91103f807SLudovic Barre #include <linux/iopoll.h> 1046b723ddSLudovic Barre #include <linux/mmc/host.h> 1146b723ddSLudovic Barre #include <linux/mmc/card.h> 121103f807SLudovic Barre #include <linux/of_address.h> 1346b723ddSLudovic Barre #include <linux/reset.h> 1446b723ddSLudovic Barre #include <linux/scatterlist.h> 1546b723ddSLudovic Barre #include "mmci.h" 1646b723ddSLudovic Barre 1746b723ddSLudovic Barre #define SDMMC_LLI_BUF_LEN PAGE_SIZE 1846b723ddSLudovic Barre 191103f807SLudovic Barre #define DLYB_CR 0x0 201103f807SLudovic Barre #define DLYB_CR_DEN BIT(0) 211103f807SLudovic Barre #define DLYB_CR_SEN BIT(1) 221103f807SLudovic Barre 231103f807SLudovic Barre #define DLYB_CFGR 0x4 241103f807SLudovic Barre #define DLYB_CFGR_SEL_MASK GENMASK(3, 0) 251103f807SLudovic Barre #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8) 261103f807SLudovic Barre #define DLYB_CFGR_LNG_MASK GENMASK(27, 16) 271103f807SLudovic Barre #define DLYB_CFGR_LNGF BIT(31) 281103f807SLudovic Barre 291103f807SLudovic Barre #define DLYB_NB_DELAY 11 301103f807SLudovic Barre #define DLYB_CFGR_SEL_MAX (DLYB_NB_DELAY + 1) 311103f807SLudovic Barre #define DLYB_CFGR_UNIT_MAX 127 321103f807SLudovic Barre 331103f807SLudovic Barre #define DLYB_LNG_TIMEOUT_US 1000 3494b94a93SLudovic Barre #define SDMMC_VSWEND_TIMEOUT_US 10000 351103f807SLudovic Barre 36*b5c3eb38SYann Gautier #define SYSCFG_DLYBSD_CR 0x0 37*b5c3eb38SYann Gautier #define DLYBSD_CR_EN BIT(0) 38*b5c3eb38SYann Gautier #define DLYBSD_CR_RXTAPSEL_MASK GENMASK(6, 1) 39*b5c3eb38SYann Gautier #define DLYBSD_TAPSEL_NB 32 40*b5c3eb38SYann Gautier #define DLYBSD_BYP_EN BIT(16) 41*b5c3eb38SYann Gautier #define DLYBSD_BYP_CMD GENMASK(21, 17) 42*b5c3eb38SYann Gautier #define DLYBSD_ANTIGLITCH_EN BIT(22) 43*b5c3eb38SYann Gautier 44*b5c3eb38SYann Gautier #define SYSCFG_DLYBSD_SR 0x4 45*b5c3eb38SYann Gautier #define DLYBSD_SR_LOCK BIT(0) 46*b5c3eb38SYann Gautier #define DLYBSD_SR_RXTAPSEL_ACK BIT(1) 47*b5c3eb38SYann Gautier 48*b5c3eb38SYann Gautier #define DLYBSD_TIMEOUT_1S_IN_US 1000000 49*b5c3eb38SYann Gautier 5046b723ddSLudovic Barre struct sdmmc_lli_desc { 5146b723ddSLudovic Barre u32 idmalar; 5246b723ddSLudovic Barre u32 idmabase; 5346b723ddSLudovic Barre u32 idmasize; 5446b723ddSLudovic Barre }; 5546b723ddSLudovic Barre 56bdbf9fafSLudovic Barre struct sdmmc_idma { 5746b723ddSLudovic Barre dma_addr_t sg_dma; 5846b723ddSLudovic Barre void *sg_cpu; 59970dc9c1SYann Gautier dma_addr_t bounce_dma_addr; 60970dc9c1SYann Gautier void *bounce_buf; 61970dc9c1SYann Gautier bool use_bounce_buffer; 6246b723ddSLudovic Barre }; 6346b723ddSLudovic Barre 6483efc782SYann Gautier struct sdmmc_dlyb; 6583efc782SYann Gautier 6683efc782SYann Gautier struct sdmmc_tuning_ops { 6783efc782SYann Gautier int (*dlyb_enable)(struct sdmmc_dlyb *dlyb); 6883efc782SYann Gautier void (*set_input_ck)(struct sdmmc_dlyb *dlyb); 6983efc782SYann Gautier int (*tuning_prepare)(struct mmci_host *host); 7083efc782SYann Gautier int (*set_cfg)(struct sdmmc_dlyb *dlyb, int unit __maybe_unused, 7183efc782SYann Gautier int phase, bool sampler __maybe_unused); 7283efc782SYann Gautier }; 7383efc782SYann Gautier 741103f807SLudovic Barre struct sdmmc_dlyb { 751103f807SLudovic Barre void __iomem *base; 761103f807SLudovic Barre u32 unit; 771103f807SLudovic Barre u32 max; 7883efc782SYann Gautier struct sdmmc_tuning_ops *ops; 791103f807SLudovic Barre }; 801103f807SLudovic Barre 8161a14e52SBen Dooks static int sdmmc_idma_validate_data(struct mmci_host *host, 8246b723ddSLudovic Barre struct mmc_data *data) 8346b723ddSLudovic Barre { 84970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 85970dc9c1SYann Gautier struct device *dev = mmc_dev(host->mmc); 8646b723ddSLudovic Barre struct scatterlist *sg; 8746b723ddSLudovic Barre int i; 8846b723ddSLudovic Barre 8946b723ddSLudovic Barre /* 9046b723ddSLudovic Barre * idma has constraints on idmabase & idmasize for each element 9146b723ddSLudovic Barre * excepted the last element which has no constraint on idmasize 9246b723ddSLudovic Barre */ 93970dc9c1SYann Gautier idma->use_bounce_buffer = false; 9446b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len - 1, i) { 950d319dd5SYann Gautier if (!IS_ALIGNED(sg->offset, sizeof(u32)) || 9688167e6cSYann Gautier !IS_ALIGNED(sg->length, 9788167e6cSYann Gautier host->variant->stm32_idmabsize_align)) { 98970dc9c1SYann Gautier dev_dbg(mmc_dev(host->mmc), 9946b723ddSLudovic Barre "unaligned scatterlist: ofst:%x length:%d\n", 10046b723ddSLudovic Barre data->sg->offset, data->sg->length); 101970dc9c1SYann Gautier goto use_bounce_buffer; 10246b723ddSLudovic Barre } 10346b723ddSLudovic Barre } 10446b723ddSLudovic Barre 1050d319dd5SYann Gautier if (!IS_ALIGNED(sg->offset, sizeof(u32))) { 106970dc9c1SYann Gautier dev_dbg(mmc_dev(host->mmc), 10746b723ddSLudovic Barre "unaligned last scatterlist: ofst:%x length:%d\n", 10846b723ddSLudovic Barre data->sg->offset, data->sg->length); 109970dc9c1SYann Gautier goto use_bounce_buffer; 11046b723ddSLudovic Barre } 11146b723ddSLudovic Barre 11246b723ddSLudovic Barre return 0; 113970dc9c1SYann Gautier 114970dc9c1SYann Gautier use_bounce_buffer: 115970dc9c1SYann Gautier if (!idma->bounce_buf) { 116970dc9c1SYann Gautier idma->bounce_buf = dmam_alloc_coherent(dev, 117970dc9c1SYann Gautier host->mmc->max_req_size, 118970dc9c1SYann Gautier &idma->bounce_dma_addr, 119970dc9c1SYann Gautier GFP_KERNEL); 120970dc9c1SYann Gautier if (!idma->bounce_buf) { 121970dc9c1SYann Gautier dev_err(dev, "Unable to map allocate DMA bounce buffer.\n"); 122970dc9c1SYann Gautier return -ENOMEM; 123970dc9c1SYann Gautier } 124970dc9c1SYann Gautier } 125970dc9c1SYann Gautier 126970dc9c1SYann Gautier idma->use_bounce_buffer = true; 127970dc9c1SYann Gautier 128970dc9c1SYann Gautier return 0; 12946b723ddSLudovic Barre } 13046b723ddSLudovic Barre 13146b723ddSLudovic Barre static int _sdmmc_idma_prep_data(struct mmci_host *host, 13246b723ddSLudovic Barre struct mmc_data *data) 13346b723ddSLudovic Barre { 134970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 135970dc9c1SYann Gautier 136970dc9c1SYann Gautier if (idma->use_bounce_buffer) { 137970dc9c1SYann Gautier if (data->flags & MMC_DATA_WRITE) { 138970dc9c1SYann Gautier unsigned int xfer_bytes = data->blksz * data->blocks; 139970dc9c1SYann Gautier 140970dc9c1SYann Gautier sg_copy_to_buffer(data->sg, data->sg_len, 141970dc9c1SYann Gautier idma->bounce_buf, xfer_bytes); 142970dc9c1SYann Gautier dma_wmb(); 143970dc9c1SYann Gautier } 144970dc9c1SYann Gautier } else { 14546b723ddSLudovic Barre int n_elem; 14646b723ddSLudovic Barre 14746b723ddSLudovic Barre n_elem = dma_map_sg(mmc_dev(host->mmc), 14846b723ddSLudovic Barre data->sg, 14946b723ddSLudovic Barre data->sg_len, 15046b723ddSLudovic Barre mmc_get_dma_dir(data)); 15146b723ddSLudovic Barre 15246b723ddSLudovic Barre if (!n_elem) { 15346b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 15446b723ddSLudovic Barre return -EINVAL; 15546b723ddSLudovic Barre } 156970dc9c1SYann Gautier } 15746b723ddSLudovic Barre return 0; 15846b723ddSLudovic Barre } 15946b723ddSLudovic Barre 16046b723ddSLudovic Barre static int sdmmc_idma_prep_data(struct mmci_host *host, 16146b723ddSLudovic Barre struct mmc_data *data, bool next) 16246b723ddSLudovic Barre { 16346b723ddSLudovic Barre /* Check if job is already prepared. */ 16446b723ddSLudovic Barre if (!next && data->host_cookie == host->next_cookie) 16546b723ddSLudovic Barre return 0; 16646b723ddSLudovic Barre 16746b723ddSLudovic Barre return _sdmmc_idma_prep_data(host, data); 16846b723ddSLudovic Barre } 16946b723ddSLudovic Barre 17046b723ddSLudovic Barre static void sdmmc_idma_unprep_data(struct mmci_host *host, 17146b723ddSLudovic Barre struct mmc_data *data, int err) 17246b723ddSLudovic Barre { 173970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 174970dc9c1SYann Gautier 175970dc9c1SYann Gautier if (idma->use_bounce_buffer) { 176970dc9c1SYann Gautier if (data->flags & MMC_DATA_READ) { 177970dc9c1SYann Gautier unsigned int xfer_bytes = data->blksz * data->blocks; 178970dc9c1SYann Gautier 179970dc9c1SYann Gautier sg_copy_from_buffer(data->sg, data->sg_len, 180970dc9c1SYann Gautier idma->bounce_buf, xfer_bytes); 181970dc9c1SYann Gautier } 182970dc9c1SYann Gautier } else { 18346b723ddSLudovic Barre dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 18446b723ddSLudovic Barre mmc_get_dma_dir(data)); 18546b723ddSLudovic Barre } 186970dc9c1SYann Gautier } 18746b723ddSLudovic Barre 18846b723ddSLudovic Barre static int sdmmc_idma_setup(struct mmci_host *host) 18946b723ddSLudovic Barre { 190bdbf9fafSLudovic Barre struct sdmmc_idma *idma; 191942d5e7bSLudovic Barre struct device *dev = mmc_dev(host->mmc); 19246b723ddSLudovic Barre 193942d5e7bSLudovic Barre idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL); 19446b723ddSLudovic Barre if (!idma) 19546b723ddSLudovic Barre return -ENOMEM; 19646b723ddSLudovic Barre 19746b723ddSLudovic Barre host->dma_priv = idma; 19846b723ddSLudovic Barre 19946b723ddSLudovic Barre if (host->variant->dma_lli) { 200942d5e7bSLudovic Barre idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN, 20146b723ddSLudovic Barre &idma->sg_dma, GFP_KERNEL); 20246b723ddSLudovic Barre if (!idma->sg_cpu) { 203942d5e7bSLudovic Barre dev_err(dev, "Failed to alloc IDMA descriptor\n"); 20446b723ddSLudovic Barre return -ENOMEM; 20546b723ddSLudovic Barre } 20646b723ddSLudovic Barre host->mmc->max_segs = SDMMC_LLI_BUF_LEN / 20746b723ddSLudovic Barre sizeof(struct sdmmc_lli_desc); 20846b723ddSLudovic Barre host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask; 209970dc9c1SYann Gautier 210970dc9c1SYann Gautier host->mmc->max_req_size = SZ_1M; 21146b723ddSLudovic Barre } else { 21246b723ddSLudovic Barre host->mmc->max_segs = 1; 21346b723ddSLudovic Barre host->mmc->max_seg_size = host->mmc->max_req_size; 21446b723ddSLudovic Barre } 21546b723ddSLudovic Barre 216942d5e7bSLudovic Barre return dma_set_max_seg_size(dev, host->mmc->max_seg_size); 21746b723ddSLudovic Barre } 21846b723ddSLudovic Barre 21946b723ddSLudovic Barre static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) 22046b723ddSLudovic Barre 22146b723ddSLudovic Barre { 222bdbf9fafSLudovic Barre struct sdmmc_idma *idma = host->dma_priv; 22346b723ddSLudovic Barre struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu; 22446b723ddSLudovic Barre struct mmc_data *data = host->data; 22546b723ddSLudovic Barre struct scatterlist *sg; 22646b723ddSLudovic Barre int i; 22746b723ddSLudovic Barre 228970dc9c1SYann Gautier if (!host->variant->dma_lli || data->sg_len == 1 || 229970dc9c1SYann Gautier idma->use_bounce_buffer) { 230970dc9c1SYann Gautier u32 dma_addr; 231970dc9c1SYann Gautier 232970dc9c1SYann Gautier if (idma->use_bounce_buffer) 233970dc9c1SYann Gautier dma_addr = idma->bounce_dma_addr; 234970dc9c1SYann Gautier else 235970dc9c1SYann Gautier dma_addr = sg_dma_address(data->sg); 236970dc9c1SYann Gautier 237970dc9c1SYann Gautier writel_relaxed(dma_addr, 23846b723ddSLudovic Barre host->base + MMCI_STM32_IDMABASE0R); 23946b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN, 24046b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 24146b723ddSLudovic Barre return 0; 24246b723ddSLudovic Barre } 24346b723ddSLudovic Barre 24446b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len, i) { 24546b723ddSLudovic Barre desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc); 24646b723ddSLudovic Barre desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS 24746b723ddSLudovic Barre | MMCI_STM32_ABR; 24846b723ddSLudovic Barre desc[i].idmabase = sg_dma_address(sg); 24946b723ddSLudovic Barre desc[i].idmasize = sg_dma_len(sg); 25046b723ddSLudovic Barre } 25146b723ddSLudovic Barre 25246b723ddSLudovic Barre /* notice the end of link list */ 25346b723ddSLudovic Barre desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA; 25446b723ddSLudovic Barre 25546b723ddSLudovic Barre dma_wmb(); 25646b723ddSLudovic Barre writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR); 25746b723ddSLudovic Barre writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR); 25846b723ddSLudovic Barre writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R); 25946b723ddSLudovic Barre writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER); 26046b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN, 26146b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 26246b723ddSLudovic Barre 26346b723ddSLudovic Barre return 0; 26446b723ddSLudovic Barre } 26546b723ddSLudovic Barre 26646b723ddSLudovic Barre static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data) 26746b723ddSLudovic Barre { 26846b723ddSLudovic Barre writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); 269fe8d33bdSLudovic Barre 270fe8d33bdSLudovic Barre if (!data->host_cookie) 271fe8d33bdSLudovic Barre sdmmc_idma_unprep_data(host, data, 0); 27246b723ddSLudovic Barre } 27346b723ddSLudovic Barre 27446b723ddSLudovic Barre static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired) 27546b723ddSLudovic Barre { 27646b723ddSLudovic Barre unsigned int clk = 0, ddr = 0; 27746b723ddSLudovic Barre 27846b723ddSLudovic Barre if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || 27946b723ddSLudovic Barre host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 28046b723ddSLudovic Barre ddr = MCI_STM32_CLK_DDR; 28146b723ddSLudovic Barre 28246b723ddSLudovic Barre /* 28346b723ddSLudovic Barre * cclk = mclk / (2 * clkdiv) 28446b723ddSLudovic Barre * clkdiv 0 => bypass 28546b723ddSLudovic Barre * in ddr mode bypass is not possible 28646b723ddSLudovic Barre */ 28746b723ddSLudovic Barre if (desired) { 28846b723ddSLudovic Barre if (desired >= host->mclk && !ddr) { 28946b723ddSLudovic Barre host->cclk = host->mclk; 29046b723ddSLudovic Barre } else { 29146b723ddSLudovic Barre clk = DIV_ROUND_UP(host->mclk, 2 * desired); 29246b723ddSLudovic Barre if (clk > MCI_STM32_CLK_CLKDIV_MSK) 29346b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 29446b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 29546b723ddSLudovic Barre } 29646b723ddSLudovic Barre } else { 29746b723ddSLudovic Barre /* 29846b723ddSLudovic Barre * while power-on phase the clock can't be define to 0, 29946b723ddSLudovic Barre * Only power-off and power-cyc deactivate the clock. 30046b723ddSLudovic Barre * if desired clock is 0, set max divider 30146b723ddSLudovic Barre */ 30246b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 30346b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 30446b723ddSLudovic Barre } 30546b723ddSLudovic Barre 30646b723ddSLudovic Barre /* Set actual clock for debug */ 30746b723ddSLudovic Barre if (host->mmc->ios.power_mode == MMC_POWER_ON) 30846b723ddSLudovic Barre host->mmc->actual_clock = host->cclk; 30946b723ddSLudovic Barre else 31046b723ddSLudovic Barre host->mmc->actual_clock = 0; 31146b723ddSLudovic Barre 31246b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 31346b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_4; 31446b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 31546b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_8; 31646b723ddSLudovic Barre 31746b723ddSLudovic Barre clk |= MCI_STM32_CLK_HWFCEN; 31846b723ddSLudovic Barre clk |= host->clk_reg_add; 31946b723ddSLudovic Barre clk |= ddr; 32046b723ddSLudovic Barre 32116f2e6c0SYann Gautier if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) 32246b723ddSLudovic Barre clk |= MCI_STM32_CLK_BUSSPEED; 32346b723ddSLudovic Barre 32446b723ddSLudovic Barre mmci_write_clkreg(host, clk); 32546b723ddSLudovic Barre } 32646b723ddSLudovic Barre 32783efc782SYann Gautier static void sdmmc_dlyb_mp15_input_ck(struct sdmmc_dlyb *dlyb) 3281103f807SLudovic Barre { 3291103f807SLudovic Barre if (!dlyb || !dlyb->base) 3301103f807SLudovic Barre return; 3311103f807SLudovic Barre 3321103f807SLudovic Barre /* Output clock = Input clock */ 3331103f807SLudovic Barre writel_relaxed(0, dlyb->base + DLYB_CR); 3341103f807SLudovic Barre } 3351103f807SLudovic Barre 33646b723ddSLudovic Barre static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr) 33746b723ddSLudovic Barre { 33846b723ddSLudovic Barre struct mmc_ios ios = host->mmc->ios; 3391103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 34046b723ddSLudovic Barre 34194b94a93SLudovic Barre /* adds OF options */ 34246b723ddSLudovic Barre pwr = host->pwr_reg_add; 34346b723ddSLudovic Barre 34483efc782SYann Gautier if (dlyb && dlyb->ops->set_input_ck) 34583efc782SYann Gautier dlyb->ops->set_input_ck(dlyb); 3461103f807SLudovic Barre 34746b723ddSLudovic Barre if (ios.power_mode == MMC_POWER_OFF) { 34846b723ddSLudovic Barre /* Only a reset could power-off sdmmc */ 34946b723ddSLudovic Barre reset_control_assert(host->rst); 35046b723ddSLudovic Barre udelay(2); 35146b723ddSLudovic Barre reset_control_deassert(host->rst); 35246b723ddSLudovic Barre 35346b723ddSLudovic Barre /* 35446b723ddSLudovic Barre * Set the SDMMC in Power-cycle state. 35546b723ddSLudovic Barre * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK 35646b723ddSLudovic Barre * are driven low, to prevent the Card from being supplied 35746b723ddSLudovic Barre * through the signal lines. 35846b723ddSLudovic Barre */ 35946b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr); 36046b723ddSLudovic Barre } else if (ios.power_mode == MMC_POWER_ON) { 36146b723ddSLudovic Barre /* 36246b723ddSLudovic Barre * After power-off (reset): the irq mask defined in probe 36346b723ddSLudovic Barre * functionis lost 36446b723ddSLudovic Barre * ault irq mask (probe) must be activated 36546b723ddSLudovic Barre */ 36646b723ddSLudovic Barre writel(MCI_IRQENABLE | host->variant->start_err, 36746b723ddSLudovic Barre host->base + MMCIMASK0); 36846b723ddSLudovic Barre 36994b94a93SLudovic Barre /* preserves voltage switch bits */ 37094b94a93SLudovic Barre pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | 37194b94a93SLudovic Barre MCI_STM32_VSWITCH); 37294b94a93SLudovic Barre 37346b723ddSLudovic Barre /* 37446b723ddSLudovic Barre * After a power-cycle state, we must set the SDMMC in 37546b723ddSLudovic Barre * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are 37646b723ddSLudovic Barre * driven high. Then we can set the SDMMC to Power-on state 37746b723ddSLudovic Barre */ 37846b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_OFF | pwr); 37946b723ddSLudovic Barre mdelay(1); 38046b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_ON | pwr); 38146b723ddSLudovic Barre } 38246b723ddSLudovic Barre } 38346b723ddSLudovic Barre 3848372f9d0SLudovic Barre static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) 3858372f9d0SLudovic Barre { 3868372f9d0SLudovic Barre u32 datactrl; 3878372f9d0SLudovic Barre 3888372f9d0SLudovic Barre datactrl = mmci_dctrl_blksz(host); 3898372f9d0SLudovic Barre 39027bdc37cSYann Gautier if (host->hw_revision >= 3) { 39127bdc37cSYann Gautier u32 thr = 0; 39227bdc37cSYann Gautier 39327bdc37cSYann Gautier if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 || 39427bdc37cSYann Gautier host->mmc->ios.timing == MMC_TIMING_MMC_HS200) { 39527bdc37cSYann Gautier thr = ffs(min_t(unsigned int, host->data->blksz, 39627bdc37cSYann Gautier host->variant->fifosize)); 39727bdc37cSYann Gautier thr = min_t(u32, thr, MMCI_STM32_THR_MASK); 39827bdc37cSYann Gautier } 39927bdc37cSYann Gautier 40027bdc37cSYann Gautier writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR); 40127bdc37cSYann Gautier } 40227bdc37cSYann Gautier 4038372f9d0SLudovic Barre if (host->mmc->card && mmc_card_sdio(host->mmc->card) && 4048372f9d0SLudovic Barre host->data->blocks == 1) 4058372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_SDIO; 4068372f9d0SLudovic Barre else if (host->data->stop && !host->mrq->sbc) 4078372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; 4088372f9d0SLudovic Barre else 4098372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK; 4108372f9d0SLudovic Barre 4118372f9d0SLudovic Barre return datactrl; 4128372f9d0SLudovic Barre } 4138372f9d0SLudovic Barre 4140e68de6aSLudovic Barre static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 4150e68de6aSLudovic Barre { 4160e68de6aSLudovic Barre void __iomem *base = host->base; 4170e68de6aSLudovic Barre u32 busy_d0, busy_d0end, mask, sdmmc_status; 4180e68de6aSLudovic Barre 4190e68de6aSLudovic Barre mask = readl_relaxed(base + MMCIMASK0); 4200e68de6aSLudovic Barre sdmmc_status = readl_relaxed(base + MMCISTATUS); 4210e68de6aSLudovic Barre busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END; 4220e68de6aSLudovic Barre busy_d0 = sdmmc_status & MCI_STM32_BUSYD0; 4230e68de6aSLudovic Barre 4240e68de6aSLudovic Barre /* complete if there is an error or busy_d0end */ 4250e68de6aSLudovic Barre if ((status & err_msk) || busy_d0end) 4260e68de6aSLudovic Barre goto complete; 4270e68de6aSLudovic Barre 4280e68de6aSLudovic Barre /* 4290e68de6aSLudovic Barre * On response the busy signaling is reflected in the BUSYD0 flag. 4300e68de6aSLudovic Barre * if busy_d0 is in-progress we must activate busyd0end interrupt 4310e68de6aSLudovic Barre * to wait this completion. Else this request has no busy step. 4320e68de6aSLudovic Barre */ 4330e68de6aSLudovic Barre if (busy_d0) { 4340e68de6aSLudovic Barre if (!host->busy_status) { 4350e68de6aSLudovic Barre writel_relaxed(mask | host->variant->busy_detect_mask, 4360e68de6aSLudovic Barre base + MMCIMASK0); 4370e68de6aSLudovic Barre host->busy_status = status & 4380e68de6aSLudovic Barre (MCI_CMDSENT | MCI_CMDRESPEND); 4390e68de6aSLudovic Barre } 4400e68de6aSLudovic Barre return false; 4410e68de6aSLudovic Barre } 4420e68de6aSLudovic Barre 4430e68de6aSLudovic Barre complete: 4440e68de6aSLudovic Barre if (host->busy_status) { 4450e68de6aSLudovic Barre writel_relaxed(mask & ~host->variant->busy_detect_mask, 4460e68de6aSLudovic Barre base + MMCIMASK0); 4470e68de6aSLudovic Barre host->busy_status = 0; 4480e68de6aSLudovic Barre } 4490e68de6aSLudovic Barre 450d4a384cbSLudovic Barre writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR); 451d4a384cbSLudovic Barre 4520e68de6aSLudovic Barre return true; 4530e68de6aSLudovic Barre } 4540e68de6aSLudovic Barre 45583efc782SYann Gautier static int sdmmc_dlyb_mp15_enable(struct sdmmc_dlyb *dlyb) 45683efc782SYann Gautier { 45783efc782SYann Gautier writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 45883efc782SYann Gautier 45983efc782SYann Gautier return 0; 46083efc782SYann Gautier } 46183efc782SYann Gautier 46283efc782SYann Gautier static int sdmmc_dlyb_mp15_set_cfg(struct sdmmc_dlyb *dlyb, 4631103f807SLudovic Barre int unit, int phase, bool sampler) 4641103f807SLudovic Barre { 4651103f807SLudovic Barre u32 cfgr; 4661103f807SLudovic Barre 4671103f807SLudovic Barre writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR); 4681103f807SLudovic Barre 4691103f807SLudovic Barre cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | 4701103f807SLudovic Barre FIELD_PREP(DLYB_CFGR_SEL_MASK, phase); 4711103f807SLudovic Barre writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); 4721103f807SLudovic Barre 4731103f807SLudovic Barre if (!sampler) 4741103f807SLudovic Barre writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 47583efc782SYann Gautier 47683efc782SYann Gautier return 0; 4771103f807SLudovic Barre } 4781103f807SLudovic Barre 47983efc782SYann Gautier static int sdmmc_dlyb_mp15_prepare(struct mmci_host *host) 4801103f807SLudovic Barre { 4811103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 4821103f807SLudovic Barre u32 cfgr; 4831103f807SLudovic Barre int i, lng, ret; 4841103f807SLudovic Barre 4851103f807SLudovic Barre for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) { 48683efc782SYann Gautier dlyb->ops->set_cfg(dlyb, i, DLYB_CFGR_SEL_MAX, true); 4871103f807SLudovic Barre 4881103f807SLudovic Barre ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, 4891103f807SLudovic Barre (cfgr & DLYB_CFGR_LNGF), 4901103f807SLudovic Barre 1, DLYB_LNG_TIMEOUT_US); 4911103f807SLudovic Barre if (ret) { 4921103f807SLudovic Barre dev_warn(mmc_dev(host->mmc), 4931103f807SLudovic Barre "delay line cfg timeout unit:%d cfgr:%d\n", 4941103f807SLudovic Barre i, cfgr); 4951103f807SLudovic Barre continue; 4961103f807SLudovic Barre } 4971103f807SLudovic Barre 4981103f807SLudovic Barre lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); 4991103f807SLudovic Barre if (lng < BIT(DLYB_NB_DELAY) && lng > 0) 5001103f807SLudovic Barre break; 5011103f807SLudovic Barre } 5021103f807SLudovic Barre 5031103f807SLudovic Barre if (i > DLYB_CFGR_UNIT_MAX) 5041103f807SLudovic Barre return -EINVAL; 5051103f807SLudovic Barre 5061103f807SLudovic Barre dlyb->unit = i; 5071103f807SLudovic Barre dlyb->max = __fls(lng); 5081103f807SLudovic Barre 5091103f807SLudovic Barre return 0; 5101103f807SLudovic Barre } 5111103f807SLudovic Barre 512*b5c3eb38SYann Gautier static int sdmmc_dlyb_mp25_enable(struct sdmmc_dlyb *dlyb) 513*b5c3eb38SYann Gautier { 514*b5c3eb38SYann Gautier u32 cr, sr; 515*b5c3eb38SYann Gautier 516*b5c3eb38SYann Gautier cr = readl_relaxed(dlyb->base + SYSCFG_DLYBSD_CR); 517*b5c3eb38SYann Gautier cr |= DLYBSD_CR_EN; 518*b5c3eb38SYann Gautier 519*b5c3eb38SYann Gautier writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR); 520*b5c3eb38SYann Gautier 521*b5c3eb38SYann Gautier return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR, 522*b5c3eb38SYann Gautier sr, sr & DLYBSD_SR_LOCK, 1, 523*b5c3eb38SYann Gautier DLYBSD_TIMEOUT_1S_IN_US); 524*b5c3eb38SYann Gautier } 525*b5c3eb38SYann Gautier 526*b5c3eb38SYann Gautier static int sdmmc_dlyb_mp25_set_cfg(struct sdmmc_dlyb *dlyb, 527*b5c3eb38SYann Gautier int unit __maybe_unused, int phase, 528*b5c3eb38SYann Gautier bool sampler __maybe_unused) 529*b5c3eb38SYann Gautier { 530*b5c3eb38SYann Gautier u32 cr, sr; 531*b5c3eb38SYann Gautier 532*b5c3eb38SYann Gautier cr = readl_relaxed(dlyb->base + SYSCFG_DLYBSD_CR); 533*b5c3eb38SYann Gautier cr &= ~DLYBSD_CR_RXTAPSEL_MASK; 534*b5c3eb38SYann Gautier cr |= FIELD_PREP(DLYBSD_CR_RXTAPSEL_MASK, phase); 535*b5c3eb38SYann Gautier 536*b5c3eb38SYann Gautier writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR); 537*b5c3eb38SYann Gautier 538*b5c3eb38SYann Gautier return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR, 539*b5c3eb38SYann Gautier sr, sr & DLYBSD_SR_RXTAPSEL_ACK, 1, 540*b5c3eb38SYann Gautier DLYBSD_TIMEOUT_1S_IN_US); 541*b5c3eb38SYann Gautier } 542*b5c3eb38SYann Gautier 543*b5c3eb38SYann Gautier static int sdmmc_dlyb_mp25_prepare(struct mmci_host *host) 544*b5c3eb38SYann Gautier { 545*b5c3eb38SYann Gautier struct sdmmc_dlyb *dlyb = host->variant_priv; 546*b5c3eb38SYann Gautier 547*b5c3eb38SYann Gautier dlyb->max = DLYBSD_TAPSEL_NB; 548*b5c3eb38SYann Gautier 549*b5c3eb38SYann Gautier return 0; 550*b5c3eb38SYann Gautier } 551*b5c3eb38SYann Gautier 5521103f807SLudovic Barre static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode) 5531103f807SLudovic Barre { 5541103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 5551103f807SLudovic Barre int cur_len = 0, max_len = 0, end_of_len = 0; 55683efc782SYann Gautier int phase, ret; 5571103f807SLudovic Barre 5581103f807SLudovic Barre for (phase = 0; phase <= dlyb->max; phase++) { 55983efc782SYann Gautier ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false); 56083efc782SYann Gautier if (ret) { 56183efc782SYann Gautier dev_err(mmc_dev(host->mmc), "tuning config failed\n"); 56283efc782SYann Gautier return ret; 56383efc782SYann Gautier } 5641103f807SLudovic Barre 5651103f807SLudovic Barre if (mmc_send_tuning(host->mmc, opcode, NULL)) { 5661103f807SLudovic Barre cur_len = 0; 5671103f807SLudovic Barre } else { 5681103f807SLudovic Barre cur_len++; 5691103f807SLudovic Barre if (cur_len > max_len) { 5701103f807SLudovic Barre max_len = cur_len; 5711103f807SLudovic Barre end_of_len = phase; 5721103f807SLudovic Barre } 5731103f807SLudovic Barre } 5741103f807SLudovic Barre } 5751103f807SLudovic Barre 5761103f807SLudovic Barre if (!max_len) { 5771103f807SLudovic Barre dev_err(mmc_dev(host->mmc), "no tuning point found\n"); 5781103f807SLudovic Barre return -EINVAL; 5791103f807SLudovic Barre } 5801103f807SLudovic Barre 58183efc782SYann Gautier if (dlyb->ops->set_input_ck) 58283efc782SYann Gautier dlyb->ops->set_input_ck(dlyb); 583ff31ee0aSYann Gautier 5841103f807SLudovic Barre phase = end_of_len - max_len / 2; 58583efc782SYann Gautier ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false); 58683efc782SYann Gautier if (ret) { 58783efc782SYann Gautier dev_err(mmc_dev(host->mmc), "tuning reconfig failed\n"); 58883efc782SYann Gautier return ret; 58983efc782SYann Gautier } 5901103f807SLudovic Barre 5911103f807SLudovic Barre dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n", 5921103f807SLudovic Barre dlyb->unit, dlyb->max, phase); 5931103f807SLudovic Barre 5941103f807SLudovic Barre return 0; 5951103f807SLudovic Barre } 5961103f807SLudovic Barre 5971103f807SLudovic Barre static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 5981103f807SLudovic Barre { 5991103f807SLudovic Barre struct mmci_host *host = mmc_priv(mmc); 6001103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 60116f2e6c0SYann Gautier u32 clk; 60283efc782SYann Gautier int ret; 60316f2e6c0SYann Gautier 60416f2e6c0SYann Gautier if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 && 60516f2e6c0SYann Gautier host->mmc->ios.timing != MMC_TIMING_MMC_HS200) || 60616f2e6c0SYann Gautier host->mmc->actual_clock <= 50000000) 60716f2e6c0SYann Gautier return 0; 6081103f807SLudovic Barre 6091103f807SLudovic Barre if (!dlyb || !dlyb->base) 6101103f807SLudovic Barre return -EINVAL; 6111103f807SLudovic Barre 61283efc782SYann Gautier ret = dlyb->ops->dlyb_enable(dlyb); 61383efc782SYann Gautier if (ret) 61483efc782SYann Gautier return ret; 61516f2e6c0SYann Gautier 61616f2e6c0SYann Gautier /* 61716f2e6c0SYann Gautier * SDMMC_FBCK is selected when an external Delay Block is needed 61816f2e6c0SYann Gautier * with SDR104 or HS200. 61916f2e6c0SYann Gautier */ 62016f2e6c0SYann Gautier clk = host->clk_reg; 62116f2e6c0SYann Gautier clk &= ~MCI_STM32_CLK_SEL_MSK; 62216f2e6c0SYann Gautier clk |= MCI_STM32_CLK_SELFBCK; 62316f2e6c0SYann Gautier mmci_write_clkreg(host, clk); 62416f2e6c0SYann Gautier 62583efc782SYann Gautier ret = dlyb->ops->tuning_prepare(host); 62683efc782SYann Gautier if (ret) 62783efc782SYann Gautier return ret; 6281103f807SLudovic Barre 6291103f807SLudovic Barre return sdmmc_dlyb_phase_tuning(host, opcode); 6301103f807SLudovic Barre } 6311103f807SLudovic Barre 63294b94a93SLudovic Barre static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host) 63394b94a93SLudovic Barre { 63494b94a93SLudovic Barre /* clear the voltage switch completion flag */ 63594b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR); 63694b94a93SLudovic Barre /* enable Voltage switch procedure */ 63794b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); 63894b94a93SLudovic Barre } 63994b94a93SLudovic Barre 64094b94a93SLudovic Barre static int sdmmc_post_sig_volt_switch(struct mmci_host *host, 64194b94a93SLudovic Barre struct mmc_ios *ios) 64294b94a93SLudovic Barre { 64394b94a93SLudovic Barre unsigned long flags; 64494b94a93SLudovic Barre u32 status; 64594b94a93SLudovic Barre int ret = 0; 64694b94a93SLudovic Barre 64794b94a93SLudovic Barre spin_lock_irqsave(&host->lock, flags); 648d8e193f1SChristophe Kerello if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 && 649d8e193f1SChristophe Kerello host->pwr_reg & MCI_STM32_VSWITCHEN) { 65094b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); 65194b94a93SLudovic Barre spin_unlock_irqrestore(&host->lock, flags); 65294b94a93SLudovic Barre 65394b94a93SLudovic Barre /* wait voltage switch completion while 10ms */ 65494b94a93SLudovic Barre ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS, 65594b94a93SLudovic Barre status, 65694b94a93SLudovic Barre (status & MCI_STM32_VSWEND), 65794b94a93SLudovic Barre 10, SDMMC_VSWEND_TIMEOUT_US); 65894b94a93SLudovic Barre 65994b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC, 66094b94a93SLudovic Barre host->base + MMCICLEAR); 661d8e193f1SChristophe Kerello spin_lock_irqsave(&host->lock, flags); 66294b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg & 66394b94a93SLudovic Barre ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH)); 66494b94a93SLudovic Barre } 665d8e193f1SChristophe Kerello spin_unlock_irqrestore(&host->lock, flags); 66694b94a93SLudovic Barre 66794b94a93SLudovic Barre return ret; 66894b94a93SLudovic Barre } 66994b94a93SLudovic Barre 67046b723ddSLudovic Barre static struct mmci_host_ops sdmmc_variant_ops = { 67146b723ddSLudovic Barre .validate_data = sdmmc_idma_validate_data, 67246b723ddSLudovic Barre .prep_data = sdmmc_idma_prep_data, 67346b723ddSLudovic Barre .unprep_data = sdmmc_idma_unprep_data, 6748372f9d0SLudovic Barre .get_datactrl_cfg = sdmmc_get_dctrl_cfg, 67546b723ddSLudovic Barre .dma_setup = sdmmc_idma_setup, 67646b723ddSLudovic Barre .dma_start = sdmmc_idma_start, 67746b723ddSLudovic Barre .dma_finalize = sdmmc_idma_finalize, 67846b723ddSLudovic Barre .set_clkreg = mmci_sdmmc_set_clkreg, 67946b723ddSLudovic Barre .set_pwrreg = mmci_sdmmc_set_pwrreg, 6800e68de6aSLudovic Barre .busy_complete = sdmmc_busy_complete, 68194b94a93SLudovic Barre .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch, 68294b94a93SLudovic Barre .post_sig_volt_switch = sdmmc_post_sig_volt_switch, 68346b723ddSLudovic Barre }; 68446b723ddSLudovic Barre 68583efc782SYann Gautier static struct sdmmc_tuning_ops dlyb_tuning_mp15_ops = { 68683efc782SYann Gautier .dlyb_enable = sdmmc_dlyb_mp15_enable, 68783efc782SYann Gautier .set_input_ck = sdmmc_dlyb_mp15_input_ck, 68883efc782SYann Gautier .tuning_prepare = sdmmc_dlyb_mp15_prepare, 68983efc782SYann Gautier .set_cfg = sdmmc_dlyb_mp15_set_cfg, 69083efc782SYann Gautier }; 69183efc782SYann Gautier 692*b5c3eb38SYann Gautier static struct sdmmc_tuning_ops dlyb_tuning_mp25_ops = { 693*b5c3eb38SYann Gautier .dlyb_enable = sdmmc_dlyb_mp25_enable, 694*b5c3eb38SYann Gautier .tuning_prepare = sdmmc_dlyb_mp25_prepare, 695*b5c3eb38SYann Gautier .set_cfg = sdmmc_dlyb_mp25_set_cfg, 696*b5c3eb38SYann Gautier }; 697*b5c3eb38SYann Gautier 69846b723ddSLudovic Barre void sdmmc_variant_init(struct mmci_host *host) 69946b723ddSLudovic Barre { 7001103f807SLudovic Barre struct device_node *np = host->mmc->parent->of_node; 7011103f807SLudovic Barre void __iomem *base_dlyb; 7021103f807SLudovic Barre struct sdmmc_dlyb *dlyb; 7031103f807SLudovic Barre 70446b723ddSLudovic Barre host->ops = &sdmmc_variant_ops; 70533ba6fecSLudovic Barre host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); 7061103f807SLudovic Barre 7071103f807SLudovic Barre base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL); 7081103f807SLudovic Barre if (IS_ERR(base_dlyb)) 7091103f807SLudovic Barre return; 7101103f807SLudovic Barre 7111103f807SLudovic Barre dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL); 7121103f807SLudovic Barre if (!dlyb) 7131103f807SLudovic Barre return; 7141103f807SLudovic Barre 7151103f807SLudovic Barre dlyb->base = base_dlyb; 716*b5c3eb38SYann Gautier if (of_device_is_compatible(np, "st,stm32mp25-sdmmc2")) 717*b5c3eb38SYann Gautier dlyb->ops = &dlyb_tuning_mp25_ops; 718*b5c3eb38SYann Gautier else 71983efc782SYann Gautier dlyb->ops = &dlyb_tuning_mp15_ops; 720*b5c3eb38SYann Gautier 7211103f807SLudovic Barre host->variant_priv = dlyb; 7221103f807SLudovic Barre host->mmc_ops->execute_tuning = sdmmc_execute_tuning; 72346b723ddSLudovic Barre } 724