146b723ddSLudovic Barre // SPDX-License-Identifier: GPL-2.0 246b723ddSLudovic Barre /* 346b723ddSLudovic Barre * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 446b723ddSLudovic Barre * Author: Ludovic.barre@st.com for STMicroelectronics. 546b723ddSLudovic Barre */ 61103f807SLudovic Barre #include <linux/bitfield.h> 746b723ddSLudovic Barre #include <linux/delay.h> 846b723ddSLudovic Barre #include <linux/dma-mapping.h> 91103f807SLudovic Barre #include <linux/iopoll.h> 1046b723ddSLudovic Barre #include <linux/mmc/host.h> 1146b723ddSLudovic Barre #include <linux/mmc/card.h> 121103f807SLudovic Barre #include <linux/of_address.h> 1346b723ddSLudovic Barre #include <linux/reset.h> 1446b723ddSLudovic Barre #include <linux/scatterlist.h> 1546b723ddSLudovic Barre #include "mmci.h" 1646b723ddSLudovic Barre 1746b723ddSLudovic Barre #define SDMMC_LLI_BUF_LEN PAGE_SIZE 1846b723ddSLudovic Barre #define SDMMC_IDMA_BURST BIT(MMCI_STM32_IDMABNDT_SHIFT) 1946b723ddSLudovic Barre 201103f807SLudovic Barre #define DLYB_CR 0x0 211103f807SLudovic Barre #define DLYB_CR_DEN BIT(0) 221103f807SLudovic Barre #define DLYB_CR_SEN BIT(1) 231103f807SLudovic Barre 241103f807SLudovic Barre #define DLYB_CFGR 0x4 251103f807SLudovic Barre #define DLYB_CFGR_SEL_MASK GENMASK(3, 0) 261103f807SLudovic Barre #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8) 271103f807SLudovic Barre #define DLYB_CFGR_LNG_MASK GENMASK(27, 16) 281103f807SLudovic Barre #define DLYB_CFGR_LNGF BIT(31) 291103f807SLudovic Barre 301103f807SLudovic Barre #define DLYB_NB_DELAY 11 311103f807SLudovic Barre #define DLYB_CFGR_SEL_MAX (DLYB_NB_DELAY + 1) 321103f807SLudovic Barre #define DLYB_CFGR_UNIT_MAX 127 331103f807SLudovic Barre 341103f807SLudovic Barre #define DLYB_LNG_TIMEOUT_US 1000 3594b94a93SLudovic Barre #define SDMMC_VSWEND_TIMEOUT_US 10000 361103f807SLudovic Barre 3746b723ddSLudovic Barre struct sdmmc_lli_desc { 3846b723ddSLudovic Barre u32 idmalar; 3946b723ddSLudovic Barre u32 idmabase; 4046b723ddSLudovic Barre u32 idmasize; 4146b723ddSLudovic Barre }; 4246b723ddSLudovic Barre 43bdbf9fafSLudovic Barre struct sdmmc_idma { 4446b723ddSLudovic Barre dma_addr_t sg_dma; 4546b723ddSLudovic Barre void *sg_cpu; 4646b723ddSLudovic Barre }; 4746b723ddSLudovic Barre 481103f807SLudovic Barre struct sdmmc_dlyb { 491103f807SLudovic Barre void __iomem *base; 501103f807SLudovic Barre u32 unit; 511103f807SLudovic Barre u32 max; 521103f807SLudovic Barre }; 531103f807SLudovic Barre 5461a14e52SBen Dooks static int sdmmc_idma_validate_data(struct mmci_host *host, 5546b723ddSLudovic Barre struct mmc_data *data) 5646b723ddSLudovic Barre { 5746b723ddSLudovic Barre struct scatterlist *sg; 5846b723ddSLudovic Barre int i; 5946b723ddSLudovic Barre 6046b723ddSLudovic Barre /* 6146b723ddSLudovic Barre * idma has constraints on idmabase & idmasize for each element 6246b723ddSLudovic Barre * excepted the last element which has no constraint on idmasize 6346b723ddSLudovic Barre */ 6446b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len - 1, i) { 65127e6e98SLudovic Barre if (!IS_ALIGNED(data->sg->offset, sizeof(u32)) || 66127e6e98SLudovic Barre !IS_ALIGNED(data->sg->length, SDMMC_IDMA_BURST)) { 6746b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), 6846b723ddSLudovic Barre "unaligned scatterlist: ofst:%x length:%d\n", 6946b723ddSLudovic Barre data->sg->offset, data->sg->length); 7046b723ddSLudovic Barre return -EINVAL; 7146b723ddSLudovic Barre } 7246b723ddSLudovic Barre } 7346b723ddSLudovic Barre 74127e6e98SLudovic Barre if (!IS_ALIGNED(data->sg->offset, sizeof(u32))) { 7546b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), 7646b723ddSLudovic Barre "unaligned last scatterlist: ofst:%x length:%d\n", 7746b723ddSLudovic Barre data->sg->offset, data->sg->length); 7846b723ddSLudovic Barre return -EINVAL; 7946b723ddSLudovic Barre } 8046b723ddSLudovic Barre 8146b723ddSLudovic Barre return 0; 8246b723ddSLudovic Barre } 8346b723ddSLudovic Barre 8446b723ddSLudovic Barre static int _sdmmc_idma_prep_data(struct mmci_host *host, 8546b723ddSLudovic Barre struct mmc_data *data) 8646b723ddSLudovic Barre { 8746b723ddSLudovic Barre int n_elem; 8846b723ddSLudovic Barre 8946b723ddSLudovic Barre n_elem = dma_map_sg(mmc_dev(host->mmc), 9046b723ddSLudovic Barre data->sg, 9146b723ddSLudovic Barre data->sg_len, 9246b723ddSLudovic Barre mmc_get_dma_dir(data)); 9346b723ddSLudovic Barre 9446b723ddSLudovic Barre if (!n_elem) { 9546b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 9646b723ddSLudovic Barre return -EINVAL; 9746b723ddSLudovic Barre } 9846b723ddSLudovic Barre 9946b723ddSLudovic Barre return 0; 10046b723ddSLudovic Barre } 10146b723ddSLudovic Barre 10246b723ddSLudovic Barre static int sdmmc_idma_prep_data(struct mmci_host *host, 10346b723ddSLudovic Barre struct mmc_data *data, bool next) 10446b723ddSLudovic Barre { 10546b723ddSLudovic Barre /* Check if job is already prepared. */ 10646b723ddSLudovic Barre if (!next && data->host_cookie == host->next_cookie) 10746b723ddSLudovic Barre return 0; 10846b723ddSLudovic Barre 10946b723ddSLudovic Barre return _sdmmc_idma_prep_data(host, data); 11046b723ddSLudovic Barre } 11146b723ddSLudovic Barre 11246b723ddSLudovic Barre static void sdmmc_idma_unprep_data(struct mmci_host *host, 11346b723ddSLudovic Barre struct mmc_data *data, int err) 11446b723ddSLudovic Barre { 11546b723ddSLudovic Barre dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 11646b723ddSLudovic Barre mmc_get_dma_dir(data)); 11746b723ddSLudovic Barre } 11846b723ddSLudovic Barre 11946b723ddSLudovic Barre static int sdmmc_idma_setup(struct mmci_host *host) 12046b723ddSLudovic Barre { 121bdbf9fafSLudovic Barre struct sdmmc_idma *idma; 12246b723ddSLudovic Barre 12346b723ddSLudovic Barre idma = devm_kzalloc(mmc_dev(host->mmc), sizeof(*idma), GFP_KERNEL); 12446b723ddSLudovic Barre if (!idma) 12546b723ddSLudovic Barre return -ENOMEM; 12646b723ddSLudovic Barre 12746b723ddSLudovic Barre host->dma_priv = idma; 12846b723ddSLudovic Barre 12946b723ddSLudovic Barre if (host->variant->dma_lli) { 13046b723ddSLudovic Barre idma->sg_cpu = dmam_alloc_coherent(mmc_dev(host->mmc), 13146b723ddSLudovic Barre SDMMC_LLI_BUF_LEN, 13246b723ddSLudovic Barre &idma->sg_dma, GFP_KERNEL); 13346b723ddSLudovic Barre if (!idma->sg_cpu) { 13446b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), 13546b723ddSLudovic Barre "Failed to alloc IDMA descriptor\n"); 13646b723ddSLudovic Barre return -ENOMEM; 13746b723ddSLudovic Barre } 13846b723ddSLudovic Barre host->mmc->max_segs = SDMMC_LLI_BUF_LEN / 13946b723ddSLudovic Barre sizeof(struct sdmmc_lli_desc); 14046b723ddSLudovic Barre host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask; 14146b723ddSLudovic Barre } else { 14246b723ddSLudovic Barre host->mmc->max_segs = 1; 14346b723ddSLudovic Barre host->mmc->max_seg_size = host->mmc->max_req_size; 14446b723ddSLudovic Barre } 14546b723ddSLudovic Barre 14646b723ddSLudovic Barre return 0; 14746b723ddSLudovic Barre } 14846b723ddSLudovic Barre 14946b723ddSLudovic Barre static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) 15046b723ddSLudovic Barre 15146b723ddSLudovic Barre { 152bdbf9fafSLudovic Barre struct sdmmc_idma *idma = host->dma_priv; 15346b723ddSLudovic Barre struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu; 15446b723ddSLudovic Barre struct mmc_data *data = host->data; 15546b723ddSLudovic Barre struct scatterlist *sg; 15646b723ddSLudovic Barre int i; 15746b723ddSLudovic Barre 15846b723ddSLudovic Barre if (!host->variant->dma_lli || data->sg_len == 1) { 15946b723ddSLudovic Barre writel_relaxed(sg_dma_address(data->sg), 16046b723ddSLudovic Barre host->base + MMCI_STM32_IDMABASE0R); 16146b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN, 16246b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 16346b723ddSLudovic Barre return 0; 16446b723ddSLudovic Barre } 16546b723ddSLudovic Barre 16646b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len, i) { 16746b723ddSLudovic Barre desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc); 16846b723ddSLudovic Barre desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS 16946b723ddSLudovic Barre | MMCI_STM32_ABR; 17046b723ddSLudovic Barre desc[i].idmabase = sg_dma_address(sg); 17146b723ddSLudovic Barre desc[i].idmasize = sg_dma_len(sg); 17246b723ddSLudovic Barre } 17346b723ddSLudovic Barre 17446b723ddSLudovic Barre /* notice the end of link list */ 17546b723ddSLudovic Barre desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA; 17646b723ddSLudovic Barre 17746b723ddSLudovic Barre dma_wmb(); 17846b723ddSLudovic Barre writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR); 17946b723ddSLudovic Barre writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR); 18046b723ddSLudovic Barre writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R); 18146b723ddSLudovic Barre writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER); 18246b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN, 18346b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 18446b723ddSLudovic Barre 18546b723ddSLudovic Barre return 0; 18646b723ddSLudovic Barre } 18746b723ddSLudovic Barre 18846b723ddSLudovic Barre static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data) 18946b723ddSLudovic Barre { 19046b723ddSLudovic Barre writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); 19146b723ddSLudovic Barre } 19246b723ddSLudovic Barre 19346b723ddSLudovic Barre static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired) 19446b723ddSLudovic Barre { 19546b723ddSLudovic Barre unsigned int clk = 0, ddr = 0; 19646b723ddSLudovic Barre 19746b723ddSLudovic Barre if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || 19846b723ddSLudovic Barre host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 19946b723ddSLudovic Barre ddr = MCI_STM32_CLK_DDR; 20046b723ddSLudovic Barre 20146b723ddSLudovic Barre /* 20246b723ddSLudovic Barre * cclk = mclk / (2 * clkdiv) 20346b723ddSLudovic Barre * clkdiv 0 => bypass 20446b723ddSLudovic Barre * in ddr mode bypass is not possible 20546b723ddSLudovic Barre */ 20646b723ddSLudovic Barre if (desired) { 20746b723ddSLudovic Barre if (desired >= host->mclk && !ddr) { 20846b723ddSLudovic Barre host->cclk = host->mclk; 20946b723ddSLudovic Barre } else { 21046b723ddSLudovic Barre clk = DIV_ROUND_UP(host->mclk, 2 * desired); 21146b723ddSLudovic Barre if (clk > MCI_STM32_CLK_CLKDIV_MSK) 21246b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 21346b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 21446b723ddSLudovic Barre } 21546b723ddSLudovic Barre } else { 21646b723ddSLudovic Barre /* 21746b723ddSLudovic Barre * while power-on phase the clock can't be define to 0, 21846b723ddSLudovic Barre * Only power-off and power-cyc deactivate the clock. 21946b723ddSLudovic Barre * if desired clock is 0, set max divider 22046b723ddSLudovic Barre */ 22146b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 22246b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 22346b723ddSLudovic Barre } 22446b723ddSLudovic Barre 22546b723ddSLudovic Barre /* Set actual clock for debug */ 22646b723ddSLudovic Barre if (host->mmc->ios.power_mode == MMC_POWER_ON) 22746b723ddSLudovic Barre host->mmc->actual_clock = host->cclk; 22846b723ddSLudovic Barre else 22946b723ddSLudovic Barre host->mmc->actual_clock = 0; 23046b723ddSLudovic Barre 23146b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 23246b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_4; 23346b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 23446b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_8; 23546b723ddSLudovic Barre 23646b723ddSLudovic Barre clk |= MCI_STM32_CLK_HWFCEN; 23746b723ddSLudovic Barre clk |= host->clk_reg_add; 23846b723ddSLudovic Barre clk |= ddr; 23946b723ddSLudovic Barre 24046b723ddSLudovic Barre /* 24146b723ddSLudovic Barre * SDMMC_FBCK is selected when an external Delay Block is needed 24246b723ddSLudovic Barre * with SDR104. 24346b723ddSLudovic Barre */ 24446b723ddSLudovic Barre if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) { 24546b723ddSLudovic Barre clk |= MCI_STM32_CLK_BUSSPEED; 24646b723ddSLudovic Barre if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) { 24746b723ddSLudovic Barre clk &= ~MCI_STM32_CLK_SEL_MSK; 24846b723ddSLudovic Barre clk |= MCI_STM32_CLK_SELFBCK; 24946b723ddSLudovic Barre } 25046b723ddSLudovic Barre } 25146b723ddSLudovic Barre 25246b723ddSLudovic Barre mmci_write_clkreg(host, clk); 25346b723ddSLudovic Barre } 25446b723ddSLudovic Barre 2551103f807SLudovic Barre static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb) 2561103f807SLudovic Barre { 2571103f807SLudovic Barre if (!dlyb || !dlyb->base) 2581103f807SLudovic Barre return; 2591103f807SLudovic Barre 2601103f807SLudovic Barre /* Output clock = Input clock */ 2611103f807SLudovic Barre writel_relaxed(0, dlyb->base + DLYB_CR); 2621103f807SLudovic Barre } 2631103f807SLudovic Barre 26446b723ddSLudovic Barre static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr) 26546b723ddSLudovic Barre { 26646b723ddSLudovic Barre struct mmc_ios ios = host->mmc->ios; 2671103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 26846b723ddSLudovic Barre 26994b94a93SLudovic Barre /* adds OF options */ 27046b723ddSLudovic Barre pwr = host->pwr_reg_add; 27146b723ddSLudovic Barre 2721103f807SLudovic Barre sdmmc_dlyb_input_ck(dlyb); 2731103f807SLudovic Barre 27446b723ddSLudovic Barre if (ios.power_mode == MMC_POWER_OFF) { 27546b723ddSLudovic Barre /* Only a reset could power-off sdmmc */ 27646b723ddSLudovic Barre reset_control_assert(host->rst); 27746b723ddSLudovic Barre udelay(2); 27846b723ddSLudovic Barre reset_control_deassert(host->rst); 27946b723ddSLudovic Barre 28046b723ddSLudovic Barre /* 28146b723ddSLudovic Barre * Set the SDMMC in Power-cycle state. 28246b723ddSLudovic Barre * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK 28346b723ddSLudovic Barre * are driven low, to prevent the Card from being supplied 28446b723ddSLudovic Barre * through the signal lines. 28546b723ddSLudovic Barre */ 28646b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr); 28746b723ddSLudovic Barre } else if (ios.power_mode == MMC_POWER_ON) { 28846b723ddSLudovic Barre /* 28946b723ddSLudovic Barre * After power-off (reset): the irq mask defined in probe 29046b723ddSLudovic Barre * functionis lost 29146b723ddSLudovic Barre * ault irq mask (probe) must be activated 29246b723ddSLudovic Barre */ 29346b723ddSLudovic Barre writel(MCI_IRQENABLE | host->variant->start_err, 29446b723ddSLudovic Barre host->base + MMCIMASK0); 29546b723ddSLudovic Barre 29694b94a93SLudovic Barre /* preserves voltage switch bits */ 29794b94a93SLudovic Barre pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | 29894b94a93SLudovic Barre MCI_STM32_VSWITCH); 29994b94a93SLudovic Barre 30046b723ddSLudovic Barre /* 30146b723ddSLudovic Barre * After a power-cycle state, we must set the SDMMC in 30246b723ddSLudovic Barre * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are 30346b723ddSLudovic Barre * driven high. Then we can set the SDMMC to Power-on state 30446b723ddSLudovic Barre */ 30546b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_OFF | pwr); 30646b723ddSLudovic Barre mdelay(1); 30746b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_ON | pwr); 30846b723ddSLudovic Barre } 30946b723ddSLudovic Barre } 31046b723ddSLudovic Barre 3118372f9d0SLudovic Barre static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) 3128372f9d0SLudovic Barre { 3138372f9d0SLudovic Barre u32 datactrl; 3148372f9d0SLudovic Barre 3158372f9d0SLudovic Barre datactrl = mmci_dctrl_blksz(host); 3168372f9d0SLudovic Barre 3178372f9d0SLudovic Barre if (host->mmc->card && mmc_card_sdio(host->mmc->card) && 3188372f9d0SLudovic Barre host->data->blocks == 1) 3198372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_SDIO; 3208372f9d0SLudovic Barre else if (host->data->stop && !host->mrq->sbc) 3218372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; 3228372f9d0SLudovic Barre else 3238372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK; 3248372f9d0SLudovic Barre 3258372f9d0SLudovic Barre return datactrl; 3268372f9d0SLudovic Barre } 3278372f9d0SLudovic Barre 3280e68de6aSLudovic Barre static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 3290e68de6aSLudovic Barre { 3300e68de6aSLudovic Barre void __iomem *base = host->base; 3310e68de6aSLudovic Barre u32 busy_d0, busy_d0end, mask, sdmmc_status; 3320e68de6aSLudovic Barre 3330e68de6aSLudovic Barre mask = readl_relaxed(base + MMCIMASK0); 3340e68de6aSLudovic Barre sdmmc_status = readl_relaxed(base + MMCISTATUS); 3350e68de6aSLudovic Barre busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END; 3360e68de6aSLudovic Barre busy_d0 = sdmmc_status & MCI_STM32_BUSYD0; 3370e68de6aSLudovic Barre 3380e68de6aSLudovic Barre /* complete if there is an error or busy_d0end */ 3390e68de6aSLudovic Barre if ((status & err_msk) || busy_d0end) 3400e68de6aSLudovic Barre goto complete; 3410e68de6aSLudovic Barre 3420e68de6aSLudovic Barre /* 3430e68de6aSLudovic Barre * On response the busy signaling is reflected in the BUSYD0 flag. 3440e68de6aSLudovic Barre * if busy_d0 is in-progress we must activate busyd0end interrupt 3450e68de6aSLudovic Barre * to wait this completion. Else this request has no busy step. 3460e68de6aSLudovic Barre */ 3470e68de6aSLudovic Barre if (busy_d0) { 3480e68de6aSLudovic Barre if (!host->busy_status) { 3490e68de6aSLudovic Barre writel_relaxed(mask | host->variant->busy_detect_mask, 3500e68de6aSLudovic Barre base + MMCIMASK0); 3510e68de6aSLudovic Barre host->busy_status = status & 3520e68de6aSLudovic Barre (MCI_CMDSENT | MCI_CMDRESPEND); 3530e68de6aSLudovic Barre } 3540e68de6aSLudovic Barre return false; 3550e68de6aSLudovic Barre } 3560e68de6aSLudovic Barre 3570e68de6aSLudovic Barre complete: 3580e68de6aSLudovic Barre if (host->busy_status) { 3590e68de6aSLudovic Barre writel_relaxed(mask & ~host->variant->busy_detect_mask, 3600e68de6aSLudovic Barre base + MMCIMASK0); 3610e68de6aSLudovic Barre writel_relaxed(host->variant->busy_detect_mask, 3620e68de6aSLudovic Barre base + MMCICLEAR); 3630e68de6aSLudovic Barre host->busy_status = 0; 3640e68de6aSLudovic Barre } 3650e68de6aSLudovic Barre 3660e68de6aSLudovic Barre return true; 3670e68de6aSLudovic Barre } 3680e68de6aSLudovic Barre 3691103f807SLudovic Barre static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb, 3701103f807SLudovic Barre int unit, int phase, bool sampler) 3711103f807SLudovic Barre { 3721103f807SLudovic Barre u32 cfgr; 3731103f807SLudovic Barre 3741103f807SLudovic Barre writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR); 3751103f807SLudovic Barre 3761103f807SLudovic Barre cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | 3771103f807SLudovic Barre FIELD_PREP(DLYB_CFGR_SEL_MASK, phase); 3781103f807SLudovic Barre writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); 3791103f807SLudovic Barre 3801103f807SLudovic Barre if (!sampler) 3811103f807SLudovic Barre writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 3821103f807SLudovic Barre } 3831103f807SLudovic Barre 3841103f807SLudovic Barre static int sdmmc_dlyb_lng_tuning(struct mmci_host *host) 3851103f807SLudovic Barre { 3861103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 3871103f807SLudovic Barre u32 cfgr; 3881103f807SLudovic Barre int i, lng, ret; 3891103f807SLudovic Barre 3901103f807SLudovic Barre for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) { 3911103f807SLudovic Barre sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true); 3921103f807SLudovic Barre 3931103f807SLudovic Barre ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, 3941103f807SLudovic Barre (cfgr & DLYB_CFGR_LNGF), 3951103f807SLudovic Barre 1, DLYB_LNG_TIMEOUT_US); 3961103f807SLudovic Barre if (ret) { 3971103f807SLudovic Barre dev_warn(mmc_dev(host->mmc), 3981103f807SLudovic Barre "delay line cfg timeout unit:%d cfgr:%d\n", 3991103f807SLudovic Barre i, cfgr); 4001103f807SLudovic Barre continue; 4011103f807SLudovic Barre } 4021103f807SLudovic Barre 4031103f807SLudovic Barre lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); 4041103f807SLudovic Barre if (lng < BIT(DLYB_NB_DELAY) && lng > 0) 4051103f807SLudovic Barre break; 4061103f807SLudovic Barre } 4071103f807SLudovic Barre 4081103f807SLudovic Barre if (i > DLYB_CFGR_UNIT_MAX) 4091103f807SLudovic Barre return -EINVAL; 4101103f807SLudovic Barre 4111103f807SLudovic Barre dlyb->unit = i; 4121103f807SLudovic Barre dlyb->max = __fls(lng); 4131103f807SLudovic Barre 4141103f807SLudovic Barre return 0; 4151103f807SLudovic Barre } 4161103f807SLudovic Barre 4171103f807SLudovic Barre static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode) 4181103f807SLudovic Barre { 4191103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 4201103f807SLudovic Barre int cur_len = 0, max_len = 0, end_of_len = 0; 4211103f807SLudovic Barre int phase; 4221103f807SLudovic Barre 4231103f807SLudovic Barre for (phase = 0; phase <= dlyb->max; phase++) { 4241103f807SLudovic Barre sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false); 4251103f807SLudovic Barre 4261103f807SLudovic Barre if (mmc_send_tuning(host->mmc, opcode, NULL)) { 4271103f807SLudovic Barre cur_len = 0; 4281103f807SLudovic Barre } else { 4291103f807SLudovic Barre cur_len++; 4301103f807SLudovic Barre if (cur_len > max_len) { 4311103f807SLudovic Barre max_len = cur_len; 4321103f807SLudovic Barre end_of_len = phase; 4331103f807SLudovic Barre } 4341103f807SLudovic Barre } 4351103f807SLudovic Barre } 4361103f807SLudovic Barre 4371103f807SLudovic Barre if (!max_len) { 4381103f807SLudovic Barre dev_err(mmc_dev(host->mmc), "no tuning point found\n"); 4391103f807SLudovic Barre return -EINVAL; 4401103f807SLudovic Barre } 4411103f807SLudovic Barre 4421103f807SLudovic Barre phase = end_of_len - max_len / 2; 4431103f807SLudovic Barre sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false); 4441103f807SLudovic Barre 4451103f807SLudovic Barre dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n", 4461103f807SLudovic Barre dlyb->unit, dlyb->max, phase); 4471103f807SLudovic Barre 4481103f807SLudovic Barre return 0; 4491103f807SLudovic Barre } 4501103f807SLudovic Barre 4511103f807SLudovic Barre static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 4521103f807SLudovic Barre { 4531103f807SLudovic Barre struct mmci_host *host = mmc_priv(mmc); 4541103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 4551103f807SLudovic Barre 4561103f807SLudovic Barre if (!dlyb || !dlyb->base) 4571103f807SLudovic Barre return -EINVAL; 4581103f807SLudovic Barre 4591103f807SLudovic Barre if (sdmmc_dlyb_lng_tuning(host)) 4601103f807SLudovic Barre return -EINVAL; 4611103f807SLudovic Barre 4621103f807SLudovic Barre return sdmmc_dlyb_phase_tuning(host, opcode); 4631103f807SLudovic Barre } 4641103f807SLudovic Barre 46594b94a93SLudovic Barre static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host) 46694b94a93SLudovic Barre { 46794b94a93SLudovic Barre /* clear the voltage switch completion flag */ 46894b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR); 46994b94a93SLudovic Barre /* enable Voltage switch procedure */ 47094b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); 47194b94a93SLudovic Barre } 47294b94a93SLudovic Barre 47394b94a93SLudovic Barre static int sdmmc_post_sig_volt_switch(struct mmci_host *host, 47494b94a93SLudovic Barre struct mmc_ios *ios) 47594b94a93SLudovic Barre { 47694b94a93SLudovic Barre unsigned long flags; 47794b94a93SLudovic Barre u32 status; 47894b94a93SLudovic Barre int ret = 0; 47994b94a93SLudovic Barre 48094b94a93SLudovic Barre if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 48194b94a93SLudovic Barre spin_lock_irqsave(&host->lock, flags); 48294b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); 48394b94a93SLudovic Barre spin_unlock_irqrestore(&host->lock, flags); 48494b94a93SLudovic Barre 48594b94a93SLudovic Barre /* wait voltage switch completion while 10ms */ 48694b94a93SLudovic Barre ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS, 48794b94a93SLudovic Barre status, 48894b94a93SLudovic Barre (status & MCI_STM32_VSWEND), 48994b94a93SLudovic Barre 10, SDMMC_VSWEND_TIMEOUT_US); 49094b94a93SLudovic Barre 49194b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC, 49294b94a93SLudovic Barre host->base + MMCICLEAR); 49394b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg & 49494b94a93SLudovic Barre ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH)); 49594b94a93SLudovic Barre } 49694b94a93SLudovic Barre 49794b94a93SLudovic Barre return ret; 49894b94a93SLudovic Barre } 49994b94a93SLudovic Barre 50046b723ddSLudovic Barre static struct mmci_host_ops sdmmc_variant_ops = { 50146b723ddSLudovic Barre .validate_data = sdmmc_idma_validate_data, 50246b723ddSLudovic Barre .prep_data = sdmmc_idma_prep_data, 50346b723ddSLudovic Barre .unprep_data = sdmmc_idma_unprep_data, 5048372f9d0SLudovic Barre .get_datactrl_cfg = sdmmc_get_dctrl_cfg, 50546b723ddSLudovic Barre .dma_setup = sdmmc_idma_setup, 50646b723ddSLudovic Barre .dma_start = sdmmc_idma_start, 50746b723ddSLudovic Barre .dma_finalize = sdmmc_idma_finalize, 50846b723ddSLudovic Barre .set_clkreg = mmci_sdmmc_set_clkreg, 50946b723ddSLudovic Barre .set_pwrreg = mmci_sdmmc_set_pwrreg, 5100e68de6aSLudovic Barre .busy_complete = sdmmc_busy_complete, 51194b94a93SLudovic Barre .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch, 51294b94a93SLudovic Barre .post_sig_volt_switch = sdmmc_post_sig_volt_switch, 51346b723ddSLudovic Barre }; 51446b723ddSLudovic Barre 51546b723ddSLudovic Barre void sdmmc_variant_init(struct mmci_host *host) 51646b723ddSLudovic Barre { 5171103f807SLudovic Barre struct device_node *np = host->mmc->parent->of_node; 5181103f807SLudovic Barre void __iomem *base_dlyb; 5191103f807SLudovic Barre struct sdmmc_dlyb *dlyb; 5201103f807SLudovic Barre 52146b723ddSLudovic Barre host->ops = &sdmmc_variant_ops; 5221103f807SLudovic Barre 5231103f807SLudovic Barre base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL); 5241103f807SLudovic Barre if (IS_ERR(base_dlyb)) 5251103f807SLudovic Barre return; 5261103f807SLudovic Barre 5271103f807SLudovic Barre dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL); 5281103f807SLudovic Barre if (!dlyb) 5291103f807SLudovic Barre return; 5301103f807SLudovic Barre 5311103f807SLudovic Barre dlyb->base = base_dlyb; 5321103f807SLudovic Barre host->variant_priv = dlyb; 5331103f807SLudovic Barre host->mmc_ops->execute_tuning = sdmmc_execute_tuning; 53446b723ddSLudovic Barre } 535