146b723ddSLudovic Barre // SPDX-License-Identifier: GPL-2.0 246b723ddSLudovic Barre /* 346b723ddSLudovic Barre * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 446b723ddSLudovic Barre * Author: Ludovic.barre@st.com for STMicroelectronics. 546b723ddSLudovic Barre */ 61103f807SLudovic Barre #include <linux/bitfield.h> 746b723ddSLudovic Barre #include <linux/delay.h> 846b723ddSLudovic Barre #include <linux/dma-mapping.h> 91103f807SLudovic Barre #include <linux/iopoll.h> 1046b723ddSLudovic Barre #include <linux/mmc/host.h> 1146b723ddSLudovic Barre #include <linux/mmc/card.h> 121103f807SLudovic Barre #include <linux/of_address.h> 1346b723ddSLudovic Barre #include <linux/reset.h> 1446b723ddSLudovic Barre #include <linux/scatterlist.h> 1546b723ddSLudovic Barre #include "mmci.h" 1646b723ddSLudovic Barre 1746b723ddSLudovic Barre #define SDMMC_LLI_BUF_LEN PAGE_SIZE 1846b723ddSLudovic Barre 191103f807SLudovic Barre #define DLYB_CR 0x0 201103f807SLudovic Barre #define DLYB_CR_DEN BIT(0) 211103f807SLudovic Barre #define DLYB_CR_SEN BIT(1) 221103f807SLudovic Barre 231103f807SLudovic Barre #define DLYB_CFGR 0x4 241103f807SLudovic Barre #define DLYB_CFGR_SEL_MASK GENMASK(3, 0) 251103f807SLudovic Barre #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8) 261103f807SLudovic Barre #define DLYB_CFGR_LNG_MASK GENMASK(27, 16) 271103f807SLudovic Barre #define DLYB_CFGR_LNGF BIT(31) 281103f807SLudovic Barre 291103f807SLudovic Barre #define DLYB_NB_DELAY 11 301103f807SLudovic Barre #define DLYB_CFGR_SEL_MAX (DLYB_NB_DELAY + 1) 311103f807SLudovic Barre #define DLYB_CFGR_UNIT_MAX 127 321103f807SLudovic Barre 331103f807SLudovic Barre #define DLYB_LNG_TIMEOUT_US 1000 3494b94a93SLudovic Barre #define SDMMC_VSWEND_TIMEOUT_US 10000 351103f807SLudovic Barre 3646b723ddSLudovic Barre struct sdmmc_lli_desc { 3746b723ddSLudovic Barre u32 idmalar; 3846b723ddSLudovic Barre u32 idmabase; 3946b723ddSLudovic Barre u32 idmasize; 4046b723ddSLudovic Barre }; 4146b723ddSLudovic Barre 42bdbf9fafSLudovic Barre struct sdmmc_idma { 4346b723ddSLudovic Barre dma_addr_t sg_dma; 4446b723ddSLudovic Barre void *sg_cpu; 45970dc9c1SYann Gautier dma_addr_t bounce_dma_addr; 46970dc9c1SYann Gautier void *bounce_buf; 47970dc9c1SYann Gautier bool use_bounce_buffer; 4846b723ddSLudovic Barre }; 4946b723ddSLudovic Barre 50*83efc782SYann Gautier struct sdmmc_dlyb; 51*83efc782SYann Gautier 52*83efc782SYann Gautier struct sdmmc_tuning_ops { 53*83efc782SYann Gautier int (*dlyb_enable)(struct sdmmc_dlyb *dlyb); 54*83efc782SYann Gautier void (*set_input_ck)(struct sdmmc_dlyb *dlyb); 55*83efc782SYann Gautier int (*tuning_prepare)(struct mmci_host *host); 56*83efc782SYann Gautier int (*set_cfg)(struct sdmmc_dlyb *dlyb, int unit __maybe_unused, 57*83efc782SYann Gautier int phase, bool sampler __maybe_unused); 58*83efc782SYann Gautier }; 59*83efc782SYann Gautier 601103f807SLudovic Barre struct sdmmc_dlyb { 611103f807SLudovic Barre void __iomem *base; 621103f807SLudovic Barre u32 unit; 631103f807SLudovic Barre u32 max; 64*83efc782SYann Gautier struct sdmmc_tuning_ops *ops; 651103f807SLudovic Barre }; 661103f807SLudovic Barre 6761a14e52SBen Dooks static int sdmmc_idma_validate_data(struct mmci_host *host, 6846b723ddSLudovic Barre struct mmc_data *data) 6946b723ddSLudovic Barre { 70970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 71970dc9c1SYann Gautier struct device *dev = mmc_dev(host->mmc); 7246b723ddSLudovic Barre struct scatterlist *sg; 7346b723ddSLudovic Barre int i; 7446b723ddSLudovic Barre 7546b723ddSLudovic Barre /* 7646b723ddSLudovic Barre * idma has constraints on idmabase & idmasize for each element 7746b723ddSLudovic Barre * excepted the last element which has no constraint on idmasize 7846b723ddSLudovic Barre */ 79970dc9c1SYann Gautier idma->use_bounce_buffer = false; 8046b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len - 1, i) { 810d319dd5SYann Gautier if (!IS_ALIGNED(sg->offset, sizeof(u32)) || 8288167e6cSYann Gautier !IS_ALIGNED(sg->length, 8388167e6cSYann Gautier host->variant->stm32_idmabsize_align)) { 84970dc9c1SYann Gautier dev_dbg(mmc_dev(host->mmc), 8546b723ddSLudovic Barre "unaligned scatterlist: ofst:%x length:%d\n", 8646b723ddSLudovic Barre data->sg->offset, data->sg->length); 87970dc9c1SYann Gautier goto use_bounce_buffer; 8846b723ddSLudovic Barre } 8946b723ddSLudovic Barre } 9046b723ddSLudovic Barre 910d319dd5SYann Gautier if (!IS_ALIGNED(sg->offset, sizeof(u32))) { 92970dc9c1SYann Gautier dev_dbg(mmc_dev(host->mmc), 9346b723ddSLudovic Barre "unaligned last scatterlist: ofst:%x length:%d\n", 9446b723ddSLudovic Barre data->sg->offset, data->sg->length); 95970dc9c1SYann Gautier goto use_bounce_buffer; 9646b723ddSLudovic Barre } 9746b723ddSLudovic Barre 9846b723ddSLudovic Barre return 0; 99970dc9c1SYann Gautier 100970dc9c1SYann Gautier use_bounce_buffer: 101970dc9c1SYann Gautier if (!idma->bounce_buf) { 102970dc9c1SYann Gautier idma->bounce_buf = dmam_alloc_coherent(dev, 103970dc9c1SYann Gautier host->mmc->max_req_size, 104970dc9c1SYann Gautier &idma->bounce_dma_addr, 105970dc9c1SYann Gautier GFP_KERNEL); 106970dc9c1SYann Gautier if (!idma->bounce_buf) { 107970dc9c1SYann Gautier dev_err(dev, "Unable to map allocate DMA bounce buffer.\n"); 108970dc9c1SYann Gautier return -ENOMEM; 109970dc9c1SYann Gautier } 110970dc9c1SYann Gautier } 111970dc9c1SYann Gautier 112970dc9c1SYann Gautier idma->use_bounce_buffer = true; 113970dc9c1SYann Gautier 114970dc9c1SYann Gautier return 0; 11546b723ddSLudovic Barre } 11646b723ddSLudovic Barre 11746b723ddSLudovic Barre static int _sdmmc_idma_prep_data(struct mmci_host *host, 11846b723ddSLudovic Barre struct mmc_data *data) 11946b723ddSLudovic Barre { 120970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 121970dc9c1SYann Gautier 122970dc9c1SYann Gautier if (idma->use_bounce_buffer) { 123970dc9c1SYann Gautier if (data->flags & MMC_DATA_WRITE) { 124970dc9c1SYann Gautier unsigned int xfer_bytes = data->blksz * data->blocks; 125970dc9c1SYann Gautier 126970dc9c1SYann Gautier sg_copy_to_buffer(data->sg, data->sg_len, 127970dc9c1SYann Gautier idma->bounce_buf, xfer_bytes); 128970dc9c1SYann Gautier dma_wmb(); 129970dc9c1SYann Gautier } 130970dc9c1SYann Gautier } else { 13146b723ddSLudovic Barre int n_elem; 13246b723ddSLudovic Barre 13346b723ddSLudovic Barre n_elem = dma_map_sg(mmc_dev(host->mmc), 13446b723ddSLudovic Barre data->sg, 13546b723ddSLudovic Barre data->sg_len, 13646b723ddSLudovic Barre mmc_get_dma_dir(data)); 13746b723ddSLudovic Barre 13846b723ddSLudovic Barre if (!n_elem) { 13946b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 14046b723ddSLudovic Barre return -EINVAL; 14146b723ddSLudovic Barre } 142970dc9c1SYann Gautier } 14346b723ddSLudovic Barre return 0; 14446b723ddSLudovic Barre } 14546b723ddSLudovic Barre 14646b723ddSLudovic Barre static int sdmmc_idma_prep_data(struct mmci_host *host, 14746b723ddSLudovic Barre struct mmc_data *data, bool next) 14846b723ddSLudovic Barre { 14946b723ddSLudovic Barre /* Check if job is already prepared. */ 15046b723ddSLudovic Barre if (!next && data->host_cookie == host->next_cookie) 15146b723ddSLudovic Barre return 0; 15246b723ddSLudovic Barre 15346b723ddSLudovic Barre return _sdmmc_idma_prep_data(host, data); 15446b723ddSLudovic Barre } 15546b723ddSLudovic Barre 15646b723ddSLudovic Barre static void sdmmc_idma_unprep_data(struct mmci_host *host, 15746b723ddSLudovic Barre struct mmc_data *data, int err) 15846b723ddSLudovic Barre { 159970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 160970dc9c1SYann Gautier 161970dc9c1SYann Gautier if (idma->use_bounce_buffer) { 162970dc9c1SYann Gautier if (data->flags & MMC_DATA_READ) { 163970dc9c1SYann Gautier unsigned int xfer_bytes = data->blksz * data->blocks; 164970dc9c1SYann Gautier 165970dc9c1SYann Gautier sg_copy_from_buffer(data->sg, data->sg_len, 166970dc9c1SYann Gautier idma->bounce_buf, xfer_bytes); 167970dc9c1SYann Gautier } 168970dc9c1SYann Gautier } else { 16946b723ddSLudovic Barre dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 17046b723ddSLudovic Barre mmc_get_dma_dir(data)); 17146b723ddSLudovic Barre } 172970dc9c1SYann Gautier } 17346b723ddSLudovic Barre 17446b723ddSLudovic Barre static int sdmmc_idma_setup(struct mmci_host *host) 17546b723ddSLudovic Barre { 176bdbf9fafSLudovic Barre struct sdmmc_idma *idma; 177942d5e7bSLudovic Barre struct device *dev = mmc_dev(host->mmc); 17846b723ddSLudovic Barre 179942d5e7bSLudovic Barre idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL); 18046b723ddSLudovic Barre if (!idma) 18146b723ddSLudovic Barre return -ENOMEM; 18246b723ddSLudovic Barre 18346b723ddSLudovic Barre host->dma_priv = idma; 18446b723ddSLudovic Barre 18546b723ddSLudovic Barre if (host->variant->dma_lli) { 186942d5e7bSLudovic Barre idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN, 18746b723ddSLudovic Barre &idma->sg_dma, GFP_KERNEL); 18846b723ddSLudovic Barre if (!idma->sg_cpu) { 189942d5e7bSLudovic Barre dev_err(dev, "Failed to alloc IDMA descriptor\n"); 19046b723ddSLudovic Barre return -ENOMEM; 19146b723ddSLudovic Barre } 19246b723ddSLudovic Barre host->mmc->max_segs = SDMMC_LLI_BUF_LEN / 19346b723ddSLudovic Barre sizeof(struct sdmmc_lli_desc); 19446b723ddSLudovic Barre host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask; 195970dc9c1SYann Gautier 196970dc9c1SYann Gautier host->mmc->max_req_size = SZ_1M; 19746b723ddSLudovic Barre } else { 19846b723ddSLudovic Barre host->mmc->max_segs = 1; 19946b723ddSLudovic Barre host->mmc->max_seg_size = host->mmc->max_req_size; 20046b723ddSLudovic Barre } 20146b723ddSLudovic Barre 202942d5e7bSLudovic Barre return dma_set_max_seg_size(dev, host->mmc->max_seg_size); 20346b723ddSLudovic Barre } 20446b723ddSLudovic Barre 20546b723ddSLudovic Barre static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) 20646b723ddSLudovic Barre 20746b723ddSLudovic Barre { 208bdbf9fafSLudovic Barre struct sdmmc_idma *idma = host->dma_priv; 20946b723ddSLudovic Barre struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu; 21046b723ddSLudovic Barre struct mmc_data *data = host->data; 21146b723ddSLudovic Barre struct scatterlist *sg; 21246b723ddSLudovic Barre int i; 21346b723ddSLudovic Barre 214970dc9c1SYann Gautier if (!host->variant->dma_lli || data->sg_len == 1 || 215970dc9c1SYann Gautier idma->use_bounce_buffer) { 216970dc9c1SYann Gautier u32 dma_addr; 217970dc9c1SYann Gautier 218970dc9c1SYann Gautier if (idma->use_bounce_buffer) 219970dc9c1SYann Gautier dma_addr = idma->bounce_dma_addr; 220970dc9c1SYann Gautier else 221970dc9c1SYann Gautier dma_addr = sg_dma_address(data->sg); 222970dc9c1SYann Gautier 223970dc9c1SYann Gautier writel_relaxed(dma_addr, 22446b723ddSLudovic Barre host->base + MMCI_STM32_IDMABASE0R); 22546b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN, 22646b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 22746b723ddSLudovic Barre return 0; 22846b723ddSLudovic Barre } 22946b723ddSLudovic Barre 23046b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len, i) { 23146b723ddSLudovic Barre desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc); 23246b723ddSLudovic Barre desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS 23346b723ddSLudovic Barre | MMCI_STM32_ABR; 23446b723ddSLudovic Barre desc[i].idmabase = sg_dma_address(sg); 23546b723ddSLudovic Barre desc[i].idmasize = sg_dma_len(sg); 23646b723ddSLudovic Barre } 23746b723ddSLudovic Barre 23846b723ddSLudovic Barre /* notice the end of link list */ 23946b723ddSLudovic Barre desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA; 24046b723ddSLudovic Barre 24146b723ddSLudovic Barre dma_wmb(); 24246b723ddSLudovic Barre writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR); 24346b723ddSLudovic Barre writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR); 24446b723ddSLudovic Barre writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R); 24546b723ddSLudovic Barre writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER); 24646b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN, 24746b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 24846b723ddSLudovic Barre 24946b723ddSLudovic Barre return 0; 25046b723ddSLudovic Barre } 25146b723ddSLudovic Barre 25246b723ddSLudovic Barre static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data) 25346b723ddSLudovic Barre { 25446b723ddSLudovic Barre writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); 255fe8d33bdSLudovic Barre 256fe8d33bdSLudovic Barre if (!data->host_cookie) 257fe8d33bdSLudovic Barre sdmmc_idma_unprep_data(host, data, 0); 25846b723ddSLudovic Barre } 25946b723ddSLudovic Barre 26046b723ddSLudovic Barre static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired) 26146b723ddSLudovic Barre { 26246b723ddSLudovic Barre unsigned int clk = 0, ddr = 0; 26346b723ddSLudovic Barre 26446b723ddSLudovic Barre if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || 26546b723ddSLudovic Barre host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 26646b723ddSLudovic Barre ddr = MCI_STM32_CLK_DDR; 26746b723ddSLudovic Barre 26846b723ddSLudovic Barre /* 26946b723ddSLudovic Barre * cclk = mclk / (2 * clkdiv) 27046b723ddSLudovic Barre * clkdiv 0 => bypass 27146b723ddSLudovic Barre * in ddr mode bypass is not possible 27246b723ddSLudovic Barre */ 27346b723ddSLudovic Barre if (desired) { 27446b723ddSLudovic Barre if (desired >= host->mclk && !ddr) { 27546b723ddSLudovic Barre host->cclk = host->mclk; 27646b723ddSLudovic Barre } else { 27746b723ddSLudovic Barre clk = DIV_ROUND_UP(host->mclk, 2 * desired); 27846b723ddSLudovic Barre if (clk > MCI_STM32_CLK_CLKDIV_MSK) 27946b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 28046b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 28146b723ddSLudovic Barre } 28246b723ddSLudovic Barre } else { 28346b723ddSLudovic Barre /* 28446b723ddSLudovic Barre * while power-on phase the clock can't be define to 0, 28546b723ddSLudovic Barre * Only power-off and power-cyc deactivate the clock. 28646b723ddSLudovic Barre * if desired clock is 0, set max divider 28746b723ddSLudovic Barre */ 28846b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 28946b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 29046b723ddSLudovic Barre } 29146b723ddSLudovic Barre 29246b723ddSLudovic Barre /* Set actual clock for debug */ 29346b723ddSLudovic Barre if (host->mmc->ios.power_mode == MMC_POWER_ON) 29446b723ddSLudovic Barre host->mmc->actual_clock = host->cclk; 29546b723ddSLudovic Barre else 29646b723ddSLudovic Barre host->mmc->actual_clock = 0; 29746b723ddSLudovic Barre 29846b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 29946b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_4; 30046b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 30146b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_8; 30246b723ddSLudovic Barre 30346b723ddSLudovic Barre clk |= MCI_STM32_CLK_HWFCEN; 30446b723ddSLudovic Barre clk |= host->clk_reg_add; 30546b723ddSLudovic Barre clk |= ddr; 30646b723ddSLudovic Barre 30716f2e6c0SYann Gautier if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) 30846b723ddSLudovic Barre clk |= MCI_STM32_CLK_BUSSPEED; 30946b723ddSLudovic Barre 31046b723ddSLudovic Barre mmci_write_clkreg(host, clk); 31146b723ddSLudovic Barre } 31246b723ddSLudovic Barre 313*83efc782SYann Gautier static void sdmmc_dlyb_mp15_input_ck(struct sdmmc_dlyb *dlyb) 3141103f807SLudovic Barre { 3151103f807SLudovic Barre if (!dlyb || !dlyb->base) 3161103f807SLudovic Barre return; 3171103f807SLudovic Barre 3181103f807SLudovic Barre /* Output clock = Input clock */ 3191103f807SLudovic Barre writel_relaxed(0, dlyb->base + DLYB_CR); 3201103f807SLudovic Barre } 3211103f807SLudovic Barre 32246b723ddSLudovic Barre static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr) 32346b723ddSLudovic Barre { 32446b723ddSLudovic Barre struct mmc_ios ios = host->mmc->ios; 3251103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 32646b723ddSLudovic Barre 32794b94a93SLudovic Barre /* adds OF options */ 32846b723ddSLudovic Barre pwr = host->pwr_reg_add; 32946b723ddSLudovic Barre 330*83efc782SYann Gautier if (dlyb && dlyb->ops->set_input_ck) 331*83efc782SYann Gautier dlyb->ops->set_input_ck(dlyb); 3321103f807SLudovic Barre 33346b723ddSLudovic Barre if (ios.power_mode == MMC_POWER_OFF) { 33446b723ddSLudovic Barre /* Only a reset could power-off sdmmc */ 33546b723ddSLudovic Barre reset_control_assert(host->rst); 33646b723ddSLudovic Barre udelay(2); 33746b723ddSLudovic Barre reset_control_deassert(host->rst); 33846b723ddSLudovic Barre 33946b723ddSLudovic Barre /* 34046b723ddSLudovic Barre * Set the SDMMC in Power-cycle state. 34146b723ddSLudovic Barre * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK 34246b723ddSLudovic Barre * are driven low, to prevent the Card from being supplied 34346b723ddSLudovic Barre * through the signal lines. 34446b723ddSLudovic Barre */ 34546b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr); 34646b723ddSLudovic Barre } else if (ios.power_mode == MMC_POWER_ON) { 34746b723ddSLudovic Barre /* 34846b723ddSLudovic Barre * After power-off (reset): the irq mask defined in probe 34946b723ddSLudovic Barre * functionis lost 35046b723ddSLudovic Barre * ault irq mask (probe) must be activated 35146b723ddSLudovic Barre */ 35246b723ddSLudovic Barre writel(MCI_IRQENABLE | host->variant->start_err, 35346b723ddSLudovic Barre host->base + MMCIMASK0); 35446b723ddSLudovic Barre 35594b94a93SLudovic Barre /* preserves voltage switch bits */ 35694b94a93SLudovic Barre pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | 35794b94a93SLudovic Barre MCI_STM32_VSWITCH); 35894b94a93SLudovic Barre 35946b723ddSLudovic Barre /* 36046b723ddSLudovic Barre * After a power-cycle state, we must set the SDMMC in 36146b723ddSLudovic Barre * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are 36246b723ddSLudovic Barre * driven high. Then we can set the SDMMC to Power-on state 36346b723ddSLudovic Barre */ 36446b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_OFF | pwr); 36546b723ddSLudovic Barre mdelay(1); 36646b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_ON | pwr); 36746b723ddSLudovic Barre } 36846b723ddSLudovic Barre } 36946b723ddSLudovic Barre 3708372f9d0SLudovic Barre static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) 3718372f9d0SLudovic Barre { 3728372f9d0SLudovic Barre u32 datactrl; 3738372f9d0SLudovic Barre 3748372f9d0SLudovic Barre datactrl = mmci_dctrl_blksz(host); 3758372f9d0SLudovic Barre 37627bdc37cSYann Gautier if (host->hw_revision >= 3) { 37727bdc37cSYann Gautier u32 thr = 0; 37827bdc37cSYann Gautier 37927bdc37cSYann Gautier if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 || 38027bdc37cSYann Gautier host->mmc->ios.timing == MMC_TIMING_MMC_HS200) { 38127bdc37cSYann Gautier thr = ffs(min_t(unsigned int, host->data->blksz, 38227bdc37cSYann Gautier host->variant->fifosize)); 38327bdc37cSYann Gautier thr = min_t(u32, thr, MMCI_STM32_THR_MASK); 38427bdc37cSYann Gautier } 38527bdc37cSYann Gautier 38627bdc37cSYann Gautier writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR); 38727bdc37cSYann Gautier } 38827bdc37cSYann Gautier 3898372f9d0SLudovic Barre if (host->mmc->card && mmc_card_sdio(host->mmc->card) && 3908372f9d0SLudovic Barre host->data->blocks == 1) 3918372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_SDIO; 3928372f9d0SLudovic Barre else if (host->data->stop && !host->mrq->sbc) 3938372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; 3948372f9d0SLudovic Barre else 3958372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK; 3968372f9d0SLudovic Barre 3978372f9d0SLudovic Barre return datactrl; 3988372f9d0SLudovic Barre } 3998372f9d0SLudovic Barre 4000e68de6aSLudovic Barre static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 4010e68de6aSLudovic Barre { 4020e68de6aSLudovic Barre void __iomem *base = host->base; 4030e68de6aSLudovic Barre u32 busy_d0, busy_d0end, mask, sdmmc_status; 4040e68de6aSLudovic Barre 4050e68de6aSLudovic Barre mask = readl_relaxed(base + MMCIMASK0); 4060e68de6aSLudovic Barre sdmmc_status = readl_relaxed(base + MMCISTATUS); 4070e68de6aSLudovic Barre busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END; 4080e68de6aSLudovic Barre busy_d0 = sdmmc_status & MCI_STM32_BUSYD0; 4090e68de6aSLudovic Barre 4100e68de6aSLudovic Barre /* complete if there is an error or busy_d0end */ 4110e68de6aSLudovic Barre if ((status & err_msk) || busy_d0end) 4120e68de6aSLudovic Barre goto complete; 4130e68de6aSLudovic Barre 4140e68de6aSLudovic Barre /* 4150e68de6aSLudovic Barre * On response the busy signaling is reflected in the BUSYD0 flag. 4160e68de6aSLudovic Barre * if busy_d0 is in-progress we must activate busyd0end interrupt 4170e68de6aSLudovic Barre * to wait this completion. Else this request has no busy step. 4180e68de6aSLudovic Barre */ 4190e68de6aSLudovic Barre if (busy_d0) { 4200e68de6aSLudovic Barre if (!host->busy_status) { 4210e68de6aSLudovic Barre writel_relaxed(mask | host->variant->busy_detect_mask, 4220e68de6aSLudovic Barre base + MMCIMASK0); 4230e68de6aSLudovic Barre host->busy_status = status & 4240e68de6aSLudovic Barre (MCI_CMDSENT | MCI_CMDRESPEND); 4250e68de6aSLudovic Barre } 4260e68de6aSLudovic Barre return false; 4270e68de6aSLudovic Barre } 4280e68de6aSLudovic Barre 4290e68de6aSLudovic Barre complete: 4300e68de6aSLudovic Barre if (host->busy_status) { 4310e68de6aSLudovic Barre writel_relaxed(mask & ~host->variant->busy_detect_mask, 4320e68de6aSLudovic Barre base + MMCIMASK0); 4330e68de6aSLudovic Barre host->busy_status = 0; 4340e68de6aSLudovic Barre } 4350e68de6aSLudovic Barre 436d4a384cbSLudovic Barre writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR); 437d4a384cbSLudovic Barre 4380e68de6aSLudovic Barre return true; 4390e68de6aSLudovic Barre } 4400e68de6aSLudovic Barre 441*83efc782SYann Gautier static int sdmmc_dlyb_mp15_enable(struct sdmmc_dlyb *dlyb) 442*83efc782SYann Gautier { 443*83efc782SYann Gautier writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 444*83efc782SYann Gautier 445*83efc782SYann Gautier return 0; 446*83efc782SYann Gautier } 447*83efc782SYann Gautier 448*83efc782SYann Gautier static int sdmmc_dlyb_mp15_set_cfg(struct sdmmc_dlyb *dlyb, 4491103f807SLudovic Barre int unit, int phase, bool sampler) 4501103f807SLudovic Barre { 4511103f807SLudovic Barre u32 cfgr; 4521103f807SLudovic Barre 4531103f807SLudovic Barre writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR); 4541103f807SLudovic Barre 4551103f807SLudovic Barre cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | 4561103f807SLudovic Barre FIELD_PREP(DLYB_CFGR_SEL_MASK, phase); 4571103f807SLudovic Barre writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); 4581103f807SLudovic Barre 4591103f807SLudovic Barre if (!sampler) 4601103f807SLudovic Barre writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 461*83efc782SYann Gautier 462*83efc782SYann Gautier return 0; 4631103f807SLudovic Barre } 4641103f807SLudovic Barre 465*83efc782SYann Gautier static int sdmmc_dlyb_mp15_prepare(struct mmci_host *host) 4661103f807SLudovic Barre { 4671103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 4681103f807SLudovic Barre u32 cfgr; 4691103f807SLudovic Barre int i, lng, ret; 4701103f807SLudovic Barre 4711103f807SLudovic Barre for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) { 472*83efc782SYann Gautier dlyb->ops->set_cfg(dlyb, i, DLYB_CFGR_SEL_MAX, true); 4731103f807SLudovic Barre 4741103f807SLudovic Barre ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, 4751103f807SLudovic Barre (cfgr & DLYB_CFGR_LNGF), 4761103f807SLudovic Barre 1, DLYB_LNG_TIMEOUT_US); 4771103f807SLudovic Barre if (ret) { 4781103f807SLudovic Barre dev_warn(mmc_dev(host->mmc), 4791103f807SLudovic Barre "delay line cfg timeout unit:%d cfgr:%d\n", 4801103f807SLudovic Barre i, cfgr); 4811103f807SLudovic Barre continue; 4821103f807SLudovic Barre } 4831103f807SLudovic Barre 4841103f807SLudovic Barre lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); 4851103f807SLudovic Barre if (lng < BIT(DLYB_NB_DELAY) && lng > 0) 4861103f807SLudovic Barre break; 4871103f807SLudovic Barre } 4881103f807SLudovic Barre 4891103f807SLudovic Barre if (i > DLYB_CFGR_UNIT_MAX) 4901103f807SLudovic Barre return -EINVAL; 4911103f807SLudovic Barre 4921103f807SLudovic Barre dlyb->unit = i; 4931103f807SLudovic Barre dlyb->max = __fls(lng); 4941103f807SLudovic Barre 4951103f807SLudovic Barre return 0; 4961103f807SLudovic Barre } 4971103f807SLudovic Barre 4981103f807SLudovic Barre static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode) 4991103f807SLudovic Barre { 5001103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 5011103f807SLudovic Barre int cur_len = 0, max_len = 0, end_of_len = 0; 502*83efc782SYann Gautier int phase, ret; 5031103f807SLudovic Barre 5041103f807SLudovic Barre for (phase = 0; phase <= dlyb->max; phase++) { 505*83efc782SYann Gautier ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false); 506*83efc782SYann Gautier if (ret) { 507*83efc782SYann Gautier dev_err(mmc_dev(host->mmc), "tuning config failed\n"); 508*83efc782SYann Gautier return ret; 509*83efc782SYann Gautier } 5101103f807SLudovic Barre 5111103f807SLudovic Barre if (mmc_send_tuning(host->mmc, opcode, NULL)) { 5121103f807SLudovic Barre cur_len = 0; 5131103f807SLudovic Barre } else { 5141103f807SLudovic Barre cur_len++; 5151103f807SLudovic Barre if (cur_len > max_len) { 5161103f807SLudovic Barre max_len = cur_len; 5171103f807SLudovic Barre end_of_len = phase; 5181103f807SLudovic Barre } 5191103f807SLudovic Barre } 5201103f807SLudovic Barre } 5211103f807SLudovic Barre 5221103f807SLudovic Barre if (!max_len) { 5231103f807SLudovic Barre dev_err(mmc_dev(host->mmc), "no tuning point found\n"); 5241103f807SLudovic Barre return -EINVAL; 5251103f807SLudovic Barre } 5261103f807SLudovic Barre 527*83efc782SYann Gautier if (dlyb->ops->set_input_ck) 528*83efc782SYann Gautier dlyb->ops->set_input_ck(dlyb); 529ff31ee0aSYann Gautier 5301103f807SLudovic Barre phase = end_of_len - max_len / 2; 531*83efc782SYann Gautier ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false); 532*83efc782SYann Gautier if (ret) { 533*83efc782SYann Gautier dev_err(mmc_dev(host->mmc), "tuning reconfig failed\n"); 534*83efc782SYann Gautier return ret; 535*83efc782SYann Gautier } 5361103f807SLudovic Barre 5371103f807SLudovic Barre dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n", 5381103f807SLudovic Barre dlyb->unit, dlyb->max, phase); 5391103f807SLudovic Barre 5401103f807SLudovic Barre return 0; 5411103f807SLudovic Barre } 5421103f807SLudovic Barre 5431103f807SLudovic Barre static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 5441103f807SLudovic Barre { 5451103f807SLudovic Barre struct mmci_host *host = mmc_priv(mmc); 5461103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 54716f2e6c0SYann Gautier u32 clk; 548*83efc782SYann Gautier int ret; 54916f2e6c0SYann Gautier 55016f2e6c0SYann Gautier if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 && 55116f2e6c0SYann Gautier host->mmc->ios.timing != MMC_TIMING_MMC_HS200) || 55216f2e6c0SYann Gautier host->mmc->actual_clock <= 50000000) 55316f2e6c0SYann Gautier return 0; 5541103f807SLudovic Barre 5551103f807SLudovic Barre if (!dlyb || !dlyb->base) 5561103f807SLudovic Barre return -EINVAL; 5571103f807SLudovic Barre 558*83efc782SYann Gautier ret = dlyb->ops->dlyb_enable(dlyb); 559*83efc782SYann Gautier if (ret) 560*83efc782SYann Gautier return ret; 56116f2e6c0SYann Gautier 56216f2e6c0SYann Gautier /* 56316f2e6c0SYann Gautier * SDMMC_FBCK is selected when an external Delay Block is needed 56416f2e6c0SYann Gautier * with SDR104 or HS200. 56516f2e6c0SYann Gautier */ 56616f2e6c0SYann Gautier clk = host->clk_reg; 56716f2e6c0SYann Gautier clk &= ~MCI_STM32_CLK_SEL_MSK; 56816f2e6c0SYann Gautier clk |= MCI_STM32_CLK_SELFBCK; 56916f2e6c0SYann Gautier mmci_write_clkreg(host, clk); 57016f2e6c0SYann Gautier 571*83efc782SYann Gautier ret = dlyb->ops->tuning_prepare(host); 572*83efc782SYann Gautier if (ret) 573*83efc782SYann Gautier return ret; 5741103f807SLudovic Barre 5751103f807SLudovic Barre return sdmmc_dlyb_phase_tuning(host, opcode); 5761103f807SLudovic Barre } 5771103f807SLudovic Barre 57894b94a93SLudovic Barre static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host) 57994b94a93SLudovic Barre { 58094b94a93SLudovic Barre /* clear the voltage switch completion flag */ 58194b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR); 58294b94a93SLudovic Barre /* enable Voltage switch procedure */ 58394b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); 58494b94a93SLudovic Barre } 58594b94a93SLudovic Barre 58694b94a93SLudovic Barre static int sdmmc_post_sig_volt_switch(struct mmci_host *host, 58794b94a93SLudovic Barre struct mmc_ios *ios) 58894b94a93SLudovic Barre { 58994b94a93SLudovic Barre unsigned long flags; 59094b94a93SLudovic Barre u32 status; 59194b94a93SLudovic Barre int ret = 0; 59294b94a93SLudovic Barre 59394b94a93SLudovic Barre spin_lock_irqsave(&host->lock, flags); 594d8e193f1SChristophe Kerello if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 && 595d8e193f1SChristophe Kerello host->pwr_reg & MCI_STM32_VSWITCHEN) { 59694b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); 59794b94a93SLudovic Barre spin_unlock_irqrestore(&host->lock, flags); 59894b94a93SLudovic Barre 59994b94a93SLudovic Barre /* wait voltage switch completion while 10ms */ 60094b94a93SLudovic Barre ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS, 60194b94a93SLudovic Barre status, 60294b94a93SLudovic Barre (status & MCI_STM32_VSWEND), 60394b94a93SLudovic Barre 10, SDMMC_VSWEND_TIMEOUT_US); 60494b94a93SLudovic Barre 60594b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC, 60694b94a93SLudovic Barre host->base + MMCICLEAR); 607d8e193f1SChristophe Kerello spin_lock_irqsave(&host->lock, flags); 60894b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg & 60994b94a93SLudovic Barre ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH)); 61094b94a93SLudovic Barre } 611d8e193f1SChristophe Kerello spin_unlock_irqrestore(&host->lock, flags); 61294b94a93SLudovic Barre 61394b94a93SLudovic Barre return ret; 61494b94a93SLudovic Barre } 61594b94a93SLudovic Barre 61646b723ddSLudovic Barre static struct mmci_host_ops sdmmc_variant_ops = { 61746b723ddSLudovic Barre .validate_data = sdmmc_idma_validate_data, 61846b723ddSLudovic Barre .prep_data = sdmmc_idma_prep_data, 61946b723ddSLudovic Barre .unprep_data = sdmmc_idma_unprep_data, 6208372f9d0SLudovic Barre .get_datactrl_cfg = sdmmc_get_dctrl_cfg, 62146b723ddSLudovic Barre .dma_setup = sdmmc_idma_setup, 62246b723ddSLudovic Barre .dma_start = sdmmc_idma_start, 62346b723ddSLudovic Barre .dma_finalize = sdmmc_idma_finalize, 62446b723ddSLudovic Barre .set_clkreg = mmci_sdmmc_set_clkreg, 62546b723ddSLudovic Barre .set_pwrreg = mmci_sdmmc_set_pwrreg, 6260e68de6aSLudovic Barre .busy_complete = sdmmc_busy_complete, 62794b94a93SLudovic Barre .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch, 62894b94a93SLudovic Barre .post_sig_volt_switch = sdmmc_post_sig_volt_switch, 62946b723ddSLudovic Barre }; 63046b723ddSLudovic Barre 631*83efc782SYann Gautier static struct sdmmc_tuning_ops dlyb_tuning_mp15_ops = { 632*83efc782SYann Gautier .dlyb_enable = sdmmc_dlyb_mp15_enable, 633*83efc782SYann Gautier .set_input_ck = sdmmc_dlyb_mp15_input_ck, 634*83efc782SYann Gautier .tuning_prepare = sdmmc_dlyb_mp15_prepare, 635*83efc782SYann Gautier .set_cfg = sdmmc_dlyb_mp15_set_cfg, 636*83efc782SYann Gautier }; 637*83efc782SYann Gautier 63846b723ddSLudovic Barre void sdmmc_variant_init(struct mmci_host *host) 63946b723ddSLudovic Barre { 6401103f807SLudovic Barre struct device_node *np = host->mmc->parent->of_node; 6411103f807SLudovic Barre void __iomem *base_dlyb; 6421103f807SLudovic Barre struct sdmmc_dlyb *dlyb; 6431103f807SLudovic Barre 64446b723ddSLudovic Barre host->ops = &sdmmc_variant_ops; 64533ba6fecSLudovic Barre host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); 6461103f807SLudovic Barre 6471103f807SLudovic Barre base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL); 6481103f807SLudovic Barre if (IS_ERR(base_dlyb)) 6491103f807SLudovic Barre return; 6501103f807SLudovic Barre 6511103f807SLudovic Barre dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL); 6521103f807SLudovic Barre if (!dlyb) 6531103f807SLudovic Barre return; 6541103f807SLudovic Barre 6551103f807SLudovic Barre dlyb->base = base_dlyb; 656*83efc782SYann Gautier dlyb->ops = &dlyb_tuning_mp15_ops; 6571103f807SLudovic Barre host->variant_priv = dlyb; 6581103f807SLudovic Barre host->mmc_ops->execute_tuning = sdmmc_execute_tuning; 65946b723ddSLudovic Barre } 660