146b723ddSLudovic Barre // SPDX-License-Identifier: GPL-2.0 246b723ddSLudovic Barre /* 346b723ddSLudovic Barre * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 446b723ddSLudovic Barre * Author: Ludovic.barre@st.com for STMicroelectronics. 546b723ddSLudovic Barre */ 61103f807SLudovic Barre #include <linux/bitfield.h> 746b723ddSLudovic Barre #include <linux/delay.h> 846b723ddSLudovic Barre #include <linux/dma-mapping.h> 91103f807SLudovic Barre #include <linux/iopoll.h> 1046b723ddSLudovic Barre #include <linux/mmc/host.h> 1146b723ddSLudovic Barre #include <linux/mmc/card.h> 121103f807SLudovic Barre #include <linux/of_address.h> 1346b723ddSLudovic Barre #include <linux/reset.h> 1446b723ddSLudovic Barre #include <linux/scatterlist.h> 1546b723ddSLudovic Barre #include "mmci.h" 1646b723ddSLudovic Barre 1746b723ddSLudovic Barre #define SDMMC_LLI_BUF_LEN PAGE_SIZE 1846b723ddSLudovic Barre #define SDMMC_IDMA_BURST BIT(MMCI_STM32_IDMABNDT_SHIFT) 1946b723ddSLudovic Barre 201103f807SLudovic Barre #define DLYB_CR 0x0 211103f807SLudovic Barre #define DLYB_CR_DEN BIT(0) 221103f807SLudovic Barre #define DLYB_CR_SEN BIT(1) 231103f807SLudovic Barre 241103f807SLudovic Barre #define DLYB_CFGR 0x4 251103f807SLudovic Barre #define DLYB_CFGR_SEL_MASK GENMASK(3, 0) 261103f807SLudovic Barre #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8) 271103f807SLudovic Barre #define DLYB_CFGR_LNG_MASK GENMASK(27, 16) 281103f807SLudovic Barre #define DLYB_CFGR_LNGF BIT(31) 291103f807SLudovic Barre 301103f807SLudovic Barre #define DLYB_NB_DELAY 11 311103f807SLudovic Barre #define DLYB_CFGR_SEL_MAX (DLYB_NB_DELAY + 1) 321103f807SLudovic Barre #define DLYB_CFGR_UNIT_MAX 127 331103f807SLudovic Barre 341103f807SLudovic Barre #define DLYB_LNG_TIMEOUT_US 1000 3594b94a93SLudovic Barre #define SDMMC_VSWEND_TIMEOUT_US 10000 361103f807SLudovic Barre 3746b723ddSLudovic Barre struct sdmmc_lli_desc { 3846b723ddSLudovic Barre u32 idmalar; 3946b723ddSLudovic Barre u32 idmabase; 4046b723ddSLudovic Barre u32 idmasize; 4146b723ddSLudovic Barre }; 4246b723ddSLudovic Barre 43bdbf9fafSLudovic Barre struct sdmmc_idma { 4446b723ddSLudovic Barre dma_addr_t sg_dma; 4546b723ddSLudovic Barre void *sg_cpu; 46970dc9c1SYann Gautier dma_addr_t bounce_dma_addr; 47970dc9c1SYann Gautier void *bounce_buf; 48970dc9c1SYann Gautier bool use_bounce_buffer; 4946b723ddSLudovic Barre }; 5046b723ddSLudovic Barre 511103f807SLudovic Barre struct sdmmc_dlyb { 521103f807SLudovic Barre void __iomem *base; 531103f807SLudovic Barre u32 unit; 541103f807SLudovic Barre u32 max; 551103f807SLudovic Barre }; 561103f807SLudovic Barre 5761a14e52SBen Dooks static int sdmmc_idma_validate_data(struct mmci_host *host, 5846b723ddSLudovic Barre struct mmc_data *data) 5946b723ddSLudovic Barre { 60970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 61970dc9c1SYann Gautier struct device *dev = mmc_dev(host->mmc); 6246b723ddSLudovic Barre struct scatterlist *sg; 6346b723ddSLudovic Barre int i; 6446b723ddSLudovic Barre 6546b723ddSLudovic Barre /* 6646b723ddSLudovic Barre * idma has constraints on idmabase & idmasize for each element 6746b723ddSLudovic Barre * excepted the last element which has no constraint on idmasize 6846b723ddSLudovic Barre */ 69970dc9c1SYann Gautier idma->use_bounce_buffer = false; 7046b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len - 1, i) { 710d319dd5SYann Gautier if (!IS_ALIGNED(sg->offset, sizeof(u32)) || 720d319dd5SYann Gautier !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) { 73970dc9c1SYann Gautier dev_dbg(mmc_dev(host->mmc), 7446b723ddSLudovic Barre "unaligned scatterlist: ofst:%x length:%d\n", 7546b723ddSLudovic Barre data->sg->offset, data->sg->length); 76970dc9c1SYann Gautier goto use_bounce_buffer; 7746b723ddSLudovic Barre } 7846b723ddSLudovic Barre } 7946b723ddSLudovic Barre 800d319dd5SYann Gautier if (!IS_ALIGNED(sg->offset, sizeof(u32))) { 81970dc9c1SYann Gautier dev_dbg(mmc_dev(host->mmc), 8246b723ddSLudovic Barre "unaligned last scatterlist: ofst:%x length:%d\n", 8346b723ddSLudovic Barre data->sg->offset, data->sg->length); 84970dc9c1SYann Gautier goto use_bounce_buffer; 8546b723ddSLudovic Barre } 8646b723ddSLudovic Barre 8746b723ddSLudovic Barre return 0; 88970dc9c1SYann Gautier 89970dc9c1SYann Gautier use_bounce_buffer: 90970dc9c1SYann Gautier if (!idma->bounce_buf) { 91970dc9c1SYann Gautier idma->bounce_buf = dmam_alloc_coherent(dev, 92970dc9c1SYann Gautier host->mmc->max_req_size, 93970dc9c1SYann Gautier &idma->bounce_dma_addr, 94970dc9c1SYann Gautier GFP_KERNEL); 95970dc9c1SYann Gautier if (!idma->bounce_buf) { 96970dc9c1SYann Gautier dev_err(dev, "Unable to map allocate DMA bounce buffer.\n"); 97970dc9c1SYann Gautier return -ENOMEM; 98970dc9c1SYann Gautier } 99970dc9c1SYann Gautier } 100970dc9c1SYann Gautier 101970dc9c1SYann Gautier idma->use_bounce_buffer = true; 102970dc9c1SYann Gautier 103970dc9c1SYann Gautier return 0; 10446b723ddSLudovic Barre } 10546b723ddSLudovic Barre 10646b723ddSLudovic Barre static int _sdmmc_idma_prep_data(struct mmci_host *host, 10746b723ddSLudovic Barre struct mmc_data *data) 10846b723ddSLudovic Barre { 109970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 110970dc9c1SYann Gautier 111970dc9c1SYann Gautier if (idma->use_bounce_buffer) { 112970dc9c1SYann Gautier if (data->flags & MMC_DATA_WRITE) { 113970dc9c1SYann Gautier unsigned int xfer_bytes = data->blksz * data->blocks; 114970dc9c1SYann Gautier 115970dc9c1SYann Gautier sg_copy_to_buffer(data->sg, data->sg_len, 116970dc9c1SYann Gautier idma->bounce_buf, xfer_bytes); 117970dc9c1SYann Gautier dma_wmb(); 118970dc9c1SYann Gautier } 119970dc9c1SYann Gautier } else { 12046b723ddSLudovic Barre int n_elem; 12146b723ddSLudovic Barre 12246b723ddSLudovic Barre n_elem = dma_map_sg(mmc_dev(host->mmc), 12346b723ddSLudovic Barre data->sg, 12446b723ddSLudovic Barre data->sg_len, 12546b723ddSLudovic Barre mmc_get_dma_dir(data)); 12646b723ddSLudovic Barre 12746b723ddSLudovic Barre if (!n_elem) { 12846b723ddSLudovic Barre dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 12946b723ddSLudovic Barre return -EINVAL; 13046b723ddSLudovic Barre } 131970dc9c1SYann Gautier } 13246b723ddSLudovic Barre return 0; 13346b723ddSLudovic Barre } 13446b723ddSLudovic Barre 13546b723ddSLudovic Barre static int sdmmc_idma_prep_data(struct mmci_host *host, 13646b723ddSLudovic Barre struct mmc_data *data, bool next) 13746b723ddSLudovic Barre { 13846b723ddSLudovic Barre /* Check if job is already prepared. */ 13946b723ddSLudovic Barre if (!next && data->host_cookie == host->next_cookie) 14046b723ddSLudovic Barre return 0; 14146b723ddSLudovic Barre 14246b723ddSLudovic Barre return _sdmmc_idma_prep_data(host, data); 14346b723ddSLudovic Barre } 14446b723ddSLudovic Barre 14546b723ddSLudovic Barre static void sdmmc_idma_unprep_data(struct mmci_host *host, 14646b723ddSLudovic Barre struct mmc_data *data, int err) 14746b723ddSLudovic Barre { 148970dc9c1SYann Gautier struct sdmmc_idma *idma = host->dma_priv; 149970dc9c1SYann Gautier 150970dc9c1SYann Gautier if (idma->use_bounce_buffer) { 151970dc9c1SYann Gautier if (data->flags & MMC_DATA_READ) { 152970dc9c1SYann Gautier unsigned int xfer_bytes = data->blksz * data->blocks; 153970dc9c1SYann Gautier 154970dc9c1SYann Gautier sg_copy_from_buffer(data->sg, data->sg_len, 155970dc9c1SYann Gautier idma->bounce_buf, xfer_bytes); 156970dc9c1SYann Gautier } 157970dc9c1SYann Gautier } else { 15846b723ddSLudovic Barre dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 15946b723ddSLudovic Barre mmc_get_dma_dir(data)); 16046b723ddSLudovic Barre } 161970dc9c1SYann Gautier } 16246b723ddSLudovic Barre 16346b723ddSLudovic Barre static int sdmmc_idma_setup(struct mmci_host *host) 16446b723ddSLudovic Barre { 165bdbf9fafSLudovic Barre struct sdmmc_idma *idma; 166942d5e7bSLudovic Barre struct device *dev = mmc_dev(host->mmc); 16746b723ddSLudovic Barre 168942d5e7bSLudovic Barre idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL); 16946b723ddSLudovic Barre if (!idma) 17046b723ddSLudovic Barre return -ENOMEM; 17146b723ddSLudovic Barre 17246b723ddSLudovic Barre host->dma_priv = idma; 17346b723ddSLudovic Barre 17446b723ddSLudovic Barre if (host->variant->dma_lli) { 175942d5e7bSLudovic Barre idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN, 17646b723ddSLudovic Barre &idma->sg_dma, GFP_KERNEL); 17746b723ddSLudovic Barre if (!idma->sg_cpu) { 178942d5e7bSLudovic Barre dev_err(dev, "Failed to alloc IDMA descriptor\n"); 17946b723ddSLudovic Barre return -ENOMEM; 18046b723ddSLudovic Barre } 18146b723ddSLudovic Barre host->mmc->max_segs = SDMMC_LLI_BUF_LEN / 18246b723ddSLudovic Barre sizeof(struct sdmmc_lli_desc); 18346b723ddSLudovic Barre host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask; 184970dc9c1SYann Gautier 185970dc9c1SYann Gautier host->mmc->max_req_size = SZ_1M; 18646b723ddSLudovic Barre } else { 18746b723ddSLudovic Barre host->mmc->max_segs = 1; 18846b723ddSLudovic Barre host->mmc->max_seg_size = host->mmc->max_req_size; 18946b723ddSLudovic Barre } 19046b723ddSLudovic Barre 191942d5e7bSLudovic Barre return dma_set_max_seg_size(dev, host->mmc->max_seg_size); 19246b723ddSLudovic Barre } 19346b723ddSLudovic Barre 19446b723ddSLudovic Barre static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl) 19546b723ddSLudovic Barre 19646b723ddSLudovic Barre { 197bdbf9fafSLudovic Barre struct sdmmc_idma *idma = host->dma_priv; 19846b723ddSLudovic Barre struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu; 19946b723ddSLudovic Barre struct mmc_data *data = host->data; 20046b723ddSLudovic Barre struct scatterlist *sg; 20146b723ddSLudovic Barre int i; 20246b723ddSLudovic Barre 203970dc9c1SYann Gautier if (!host->variant->dma_lli || data->sg_len == 1 || 204970dc9c1SYann Gautier idma->use_bounce_buffer) { 205970dc9c1SYann Gautier u32 dma_addr; 206970dc9c1SYann Gautier 207970dc9c1SYann Gautier if (idma->use_bounce_buffer) 208970dc9c1SYann Gautier dma_addr = idma->bounce_dma_addr; 209970dc9c1SYann Gautier else 210970dc9c1SYann Gautier dma_addr = sg_dma_address(data->sg); 211970dc9c1SYann Gautier 212970dc9c1SYann Gautier writel_relaxed(dma_addr, 21346b723ddSLudovic Barre host->base + MMCI_STM32_IDMABASE0R); 21446b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN, 21546b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 21646b723ddSLudovic Barre return 0; 21746b723ddSLudovic Barre } 21846b723ddSLudovic Barre 21946b723ddSLudovic Barre for_each_sg(data->sg, sg, data->sg_len, i) { 22046b723ddSLudovic Barre desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc); 22146b723ddSLudovic Barre desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS 22246b723ddSLudovic Barre | MMCI_STM32_ABR; 22346b723ddSLudovic Barre desc[i].idmabase = sg_dma_address(sg); 22446b723ddSLudovic Barre desc[i].idmasize = sg_dma_len(sg); 22546b723ddSLudovic Barre } 22646b723ddSLudovic Barre 22746b723ddSLudovic Barre /* notice the end of link list */ 22846b723ddSLudovic Barre desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA; 22946b723ddSLudovic Barre 23046b723ddSLudovic Barre dma_wmb(); 23146b723ddSLudovic Barre writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR); 23246b723ddSLudovic Barre writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR); 23346b723ddSLudovic Barre writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R); 23446b723ddSLudovic Barre writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER); 23546b723ddSLudovic Barre writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN, 23646b723ddSLudovic Barre host->base + MMCI_STM32_IDMACTRLR); 23746b723ddSLudovic Barre 23846b723ddSLudovic Barre return 0; 23946b723ddSLudovic Barre } 24046b723ddSLudovic Barre 24146b723ddSLudovic Barre static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data) 24246b723ddSLudovic Barre { 24346b723ddSLudovic Barre writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR); 244fe8d33bdSLudovic Barre 245fe8d33bdSLudovic Barre if (!data->host_cookie) 246fe8d33bdSLudovic Barre sdmmc_idma_unprep_data(host, data, 0); 24746b723ddSLudovic Barre } 24846b723ddSLudovic Barre 24946b723ddSLudovic Barre static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired) 25046b723ddSLudovic Barre { 25146b723ddSLudovic Barre unsigned int clk = 0, ddr = 0; 25246b723ddSLudovic Barre 25346b723ddSLudovic Barre if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 || 25446b723ddSLudovic Barre host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 25546b723ddSLudovic Barre ddr = MCI_STM32_CLK_DDR; 25646b723ddSLudovic Barre 25746b723ddSLudovic Barre /* 25846b723ddSLudovic Barre * cclk = mclk / (2 * clkdiv) 25946b723ddSLudovic Barre * clkdiv 0 => bypass 26046b723ddSLudovic Barre * in ddr mode bypass is not possible 26146b723ddSLudovic Barre */ 26246b723ddSLudovic Barre if (desired) { 26346b723ddSLudovic Barre if (desired >= host->mclk && !ddr) { 26446b723ddSLudovic Barre host->cclk = host->mclk; 26546b723ddSLudovic Barre } else { 26646b723ddSLudovic Barre clk = DIV_ROUND_UP(host->mclk, 2 * desired); 26746b723ddSLudovic Barre if (clk > MCI_STM32_CLK_CLKDIV_MSK) 26846b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 26946b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 27046b723ddSLudovic Barre } 27146b723ddSLudovic Barre } else { 27246b723ddSLudovic Barre /* 27346b723ddSLudovic Barre * while power-on phase the clock can't be define to 0, 27446b723ddSLudovic Barre * Only power-off and power-cyc deactivate the clock. 27546b723ddSLudovic Barre * if desired clock is 0, set max divider 27646b723ddSLudovic Barre */ 27746b723ddSLudovic Barre clk = MCI_STM32_CLK_CLKDIV_MSK; 27846b723ddSLudovic Barre host->cclk = host->mclk / (2 * clk); 27946b723ddSLudovic Barre } 28046b723ddSLudovic Barre 28146b723ddSLudovic Barre /* Set actual clock for debug */ 28246b723ddSLudovic Barre if (host->mmc->ios.power_mode == MMC_POWER_ON) 28346b723ddSLudovic Barre host->mmc->actual_clock = host->cclk; 28446b723ddSLudovic Barre else 28546b723ddSLudovic Barre host->mmc->actual_clock = 0; 28646b723ddSLudovic Barre 28746b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 28846b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_4; 28946b723ddSLudovic Barre if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 29046b723ddSLudovic Barre clk |= MCI_STM32_CLK_WIDEBUS_8; 29146b723ddSLudovic Barre 29246b723ddSLudovic Barre clk |= MCI_STM32_CLK_HWFCEN; 29346b723ddSLudovic Barre clk |= host->clk_reg_add; 29446b723ddSLudovic Barre clk |= ddr; 29546b723ddSLudovic Barre 296*16f2e6c0SYann Gautier if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) 29746b723ddSLudovic Barre clk |= MCI_STM32_CLK_BUSSPEED; 29846b723ddSLudovic Barre 29946b723ddSLudovic Barre mmci_write_clkreg(host, clk); 30046b723ddSLudovic Barre } 30146b723ddSLudovic Barre 3021103f807SLudovic Barre static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb) 3031103f807SLudovic Barre { 3041103f807SLudovic Barre if (!dlyb || !dlyb->base) 3051103f807SLudovic Barre return; 3061103f807SLudovic Barre 3071103f807SLudovic Barre /* Output clock = Input clock */ 3081103f807SLudovic Barre writel_relaxed(0, dlyb->base + DLYB_CR); 3091103f807SLudovic Barre } 3101103f807SLudovic Barre 31146b723ddSLudovic Barre static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr) 31246b723ddSLudovic Barre { 31346b723ddSLudovic Barre struct mmc_ios ios = host->mmc->ios; 3141103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 31546b723ddSLudovic Barre 31694b94a93SLudovic Barre /* adds OF options */ 31746b723ddSLudovic Barre pwr = host->pwr_reg_add; 31846b723ddSLudovic Barre 3191103f807SLudovic Barre sdmmc_dlyb_input_ck(dlyb); 3201103f807SLudovic Barre 32146b723ddSLudovic Barre if (ios.power_mode == MMC_POWER_OFF) { 32246b723ddSLudovic Barre /* Only a reset could power-off sdmmc */ 32346b723ddSLudovic Barre reset_control_assert(host->rst); 32446b723ddSLudovic Barre udelay(2); 32546b723ddSLudovic Barre reset_control_deassert(host->rst); 32646b723ddSLudovic Barre 32746b723ddSLudovic Barre /* 32846b723ddSLudovic Barre * Set the SDMMC in Power-cycle state. 32946b723ddSLudovic Barre * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK 33046b723ddSLudovic Barre * are driven low, to prevent the Card from being supplied 33146b723ddSLudovic Barre * through the signal lines. 33246b723ddSLudovic Barre */ 33346b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr); 33446b723ddSLudovic Barre } else if (ios.power_mode == MMC_POWER_ON) { 33546b723ddSLudovic Barre /* 33646b723ddSLudovic Barre * After power-off (reset): the irq mask defined in probe 33746b723ddSLudovic Barre * functionis lost 33846b723ddSLudovic Barre * ault irq mask (probe) must be activated 33946b723ddSLudovic Barre */ 34046b723ddSLudovic Barre writel(MCI_IRQENABLE | host->variant->start_err, 34146b723ddSLudovic Barre host->base + MMCIMASK0); 34246b723ddSLudovic Barre 34394b94a93SLudovic Barre /* preserves voltage switch bits */ 34494b94a93SLudovic Barre pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | 34594b94a93SLudovic Barre MCI_STM32_VSWITCH); 34694b94a93SLudovic Barre 34746b723ddSLudovic Barre /* 34846b723ddSLudovic Barre * After a power-cycle state, we must set the SDMMC in 34946b723ddSLudovic Barre * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are 35046b723ddSLudovic Barre * driven high. Then we can set the SDMMC to Power-on state 35146b723ddSLudovic Barre */ 35246b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_OFF | pwr); 35346b723ddSLudovic Barre mdelay(1); 35446b723ddSLudovic Barre mmci_write_pwrreg(host, MCI_PWR_ON | pwr); 35546b723ddSLudovic Barre } 35646b723ddSLudovic Barre } 35746b723ddSLudovic Barre 3588372f9d0SLudovic Barre static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) 3598372f9d0SLudovic Barre { 3608372f9d0SLudovic Barre u32 datactrl; 3618372f9d0SLudovic Barre 3628372f9d0SLudovic Barre datactrl = mmci_dctrl_blksz(host); 3638372f9d0SLudovic Barre 3648372f9d0SLudovic Barre if (host->mmc->card && mmc_card_sdio(host->mmc->card) && 3658372f9d0SLudovic Barre host->data->blocks == 1) 3668372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_SDIO; 3678372f9d0SLudovic Barre else if (host->data->stop && !host->mrq->sbc) 3688372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; 3698372f9d0SLudovic Barre else 3708372f9d0SLudovic Barre datactrl |= MCI_DPSM_STM32_MODE_BLOCK; 3718372f9d0SLudovic Barre 3728372f9d0SLudovic Barre return datactrl; 3738372f9d0SLudovic Barre } 3748372f9d0SLudovic Barre 3750e68de6aSLudovic Barre static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 3760e68de6aSLudovic Barre { 3770e68de6aSLudovic Barre void __iomem *base = host->base; 3780e68de6aSLudovic Barre u32 busy_d0, busy_d0end, mask, sdmmc_status; 3790e68de6aSLudovic Barre 3800e68de6aSLudovic Barre mask = readl_relaxed(base + MMCIMASK0); 3810e68de6aSLudovic Barre sdmmc_status = readl_relaxed(base + MMCISTATUS); 3820e68de6aSLudovic Barre busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END; 3830e68de6aSLudovic Barre busy_d0 = sdmmc_status & MCI_STM32_BUSYD0; 3840e68de6aSLudovic Barre 3850e68de6aSLudovic Barre /* complete if there is an error or busy_d0end */ 3860e68de6aSLudovic Barre if ((status & err_msk) || busy_d0end) 3870e68de6aSLudovic Barre goto complete; 3880e68de6aSLudovic Barre 3890e68de6aSLudovic Barre /* 3900e68de6aSLudovic Barre * On response the busy signaling is reflected in the BUSYD0 flag. 3910e68de6aSLudovic Barre * if busy_d0 is in-progress we must activate busyd0end interrupt 3920e68de6aSLudovic Barre * to wait this completion. Else this request has no busy step. 3930e68de6aSLudovic Barre */ 3940e68de6aSLudovic Barre if (busy_d0) { 3950e68de6aSLudovic Barre if (!host->busy_status) { 3960e68de6aSLudovic Barre writel_relaxed(mask | host->variant->busy_detect_mask, 3970e68de6aSLudovic Barre base + MMCIMASK0); 3980e68de6aSLudovic Barre host->busy_status = status & 3990e68de6aSLudovic Barre (MCI_CMDSENT | MCI_CMDRESPEND); 4000e68de6aSLudovic Barre } 4010e68de6aSLudovic Barre return false; 4020e68de6aSLudovic Barre } 4030e68de6aSLudovic Barre 4040e68de6aSLudovic Barre complete: 4050e68de6aSLudovic Barre if (host->busy_status) { 4060e68de6aSLudovic Barre writel_relaxed(mask & ~host->variant->busy_detect_mask, 4070e68de6aSLudovic Barre base + MMCIMASK0); 4080e68de6aSLudovic Barre host->busy_status = 0; 4090e68de6aSLudovic Barre } 4100e68de6aSLudovic Barre 411d4a384cbSLudovic Barre writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR); 412d4a384cbSLudovic Barre 4130e68de6aSLudovic Barre return true; 4140e68de6aSLudovic Barre } 4150e68de6aSLudovic Barre 4161103f807SLudovic Barre static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb, 4171103f807SLudovic Barre int unit, int phase, bool sampler) 4181103f807SLudovic Barre { 4191103f807SLudovic Barre u32 cfgr; 4201103f807SLudovic Barre 4211103f807SLudovic Barre writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR); 4221103f807SLudovic Barre 4231103f807SLudovic Barre cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | 4241103f807SLudovic Barre FIELD_PREP(DLYB_CFGR_SEL_MASK, phase); 4251103f807SLudovic Barre writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); 4261103f807SLudovic Barre 4271103f807SLudovic Barre if (!sampler) 4281103f807SLudovic Barre writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 4291103f807SLudovic Barre } 4301103f807SLudovic Barre 4311103f807SLudovic Barre static int sdmmc_dlyb_lng_tuning(struct mmci_host *host) 4321103f807SLudovic Barre { 4331103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 4341103f807SLudovic Barre u32 cfgr; 4351103f807SLudovic Barre int i, lng, ret; 4361103f807SLudovic Barre 4371103f807SLudovic Barre for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) { 4381103f807SLudovic Barre sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true); 4391103f807SLudovic Barre 4401103f807SLudovic Barre ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, 4411103f807SLudovic Barre (cfgr & DLYB_CFGR_LNGF), 4421103f807SLudovic Barre 1, DLYB_LNG_TIMEOUT_US); 4431103f807SLudovic Barre if (ret) { 4441103f807SLudovic Barre dev_warn(mmc_dev(host->mmc), 4451103f807SLudovic Barre "delay line cfg timeout unit:%d cfgr:%d\n", 4461103f807SLudovic Barre i, cfgr); 4471103f807SLudovic Barre continue; 4481103f807SLudovic Barre } 4491103f807SLudovic Barre 4501103f807SLudovic Barre lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); 4511103f807SLudovic Barre if (lng < BIT(DLYB_NB_DELAY) && lng > 0) 4521103f807SLudovic Barre break; 4531103f807SLudovic Barre } 4541103f807SLudovic Barre 4551103f807SLudovic Barre if (i > DLYB_CFGR_UNIT_MAX) 4561103f807SLudovic Barre return -EINVAL; 4571103f807SLudovic Barre 4581103f807SLudovic Barre dlyb->unit = i; 4591103f807SLudovic Barre dlyb->max = __fls(lng); 4601103f807SLudovic Barre 4611103f807SLudovic Barre return 0; 4621103f807SLudovic Barre } 4631103f807SLudovic Barre 4641103f807SLudovic Barre static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode) 4651103f807SLudovic Barre { 4661103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 4671103f807SLudovic Barre int cur_len = 0, max_len = 0, end_of_len = 0; 4681103f807SLudovic Barre int phase; 4691103f807SLudovic Barre 4701103f807SLudovic Barre for (phase = 0; phase <= dlyb->max; phase++) { 4711103f807SLudovic Barre sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false); 4721103f807SLudovic Barre 4731103f807SLudovic Barre if (mmc_send_tuning(host->mmc, opcode, NULL)) { 4741103f807SLudovic Barre cur_len = 0; 4751103f807SLudovic Barre } else { 4761103f807SLudovic Barre cur_len++; 4771103f807SLudovic Barre if (cur_len > max_len) { 4781103f807SLudovic Barre max_len = cur_len; 4791103f807SLudovic Barre end_of_len = phase; 4801103f807SLudovic Barre } 4811103f807SLudovic Barre } 4821103f807SLudovic Barre } 4831103f807SLudovic Barre 4841103f807SLudovic Barre if (!max_len) { 4851103f807SLudovic Barre dev_err(mmc_dev(host->mmc), "no tuning point found\n"); 4861103f807SLudovic Barre return -EINVAL; 4871103f807SLudovic Barre } 4881103f807SLudovic Barre 489ff31ee0aSYann Gautier writel_relaxed(0, dlyb->base + DLYB_CR); 490ff31ee0aSYann Gautier 4911103f807SLudovic Barre phase = end_of_len - max_len / 2; 4921103f807SLudovic Barre sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false); 4931103f807SLudovic Barre 4941103f807SLudovic Barre dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n", 4951103f807SLudovic Barre dlyb->unit, dlyb->max, phase); 4961103f807SLudovic Barre 4971103f807SLudovic Barre return 0; 4981103f807SLudovic Barre } 4991103f807SLudovic Barre 5001103f807SLudovic Barre static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 5011103f807SLudovic Barre { 5021103f807SLudovic Barre struct mmci_host *host = mmc_priv(mmc); 5031103f807SLudovic Barre struct sdmmc_dlyb *dlyb = host->variant_priv; 504*16f2e6c0SYann Gautier u32 clk; 505*16f2e6c0SYann Gautier 506*16f2e6c0SYann Gautier if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 && 507*16f2e6c0SYann Gautier host->mmc->ios.timing != MMC_TIMING_MMC_HS200) || 508*16f2e6c0SYann Gautier host->mmc->actual_clock <= 50000000) 509*16f2e6c0SYann Gautier return 0; 5101103f807SLudovic Barre 5111103f807SLudovic Barre if (!dlyb || !dlyb->base) 5121103f807SLudovic Barre return -EINVAL; 5131103f807SLudovic Barre 514*16f2e6c0SYann Gautier writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR); 515*16f2e6c0SYann Gautier 516*16f2e6c0SYann Gautier /* 517*16f2e6c0SYann Gautier * SDMMC_FBCK is selected when an external Delay Block is needed 518*16f2e6c0SYann Gautier * with SDR104 or HS200. 519*16f2e6c0SYann Gautier */ 520*16f2e6c0SYann Gautier clk = host->clk_reg; 521*16f2e6c0SYann Gautier clk &= ~MCI_STM32_CLK_SEL_MSK; 522*16f2e6c0SYann Gautier clk |= MCI_STM32_CLK_SELFBCK; 523*16f2e6c0SYann Gautier mmci_write_clkreg(host, clk); 524*16f2e6c0SYann Gautier 5251103f807SLudovic Barre if (sdmmc_dlyb_lng_tuning(host)) 5261103f807SLudovic Barre return -EINVAL; 5271103f807SLudovic Barre 5281103f807SLudovic Barre return sdmmc_dlyb_phase_tuning(host, opcode); 5291103f807SLudovic Barre } 5301103f807SLudovic Barre 53194b94a93SLudovic Barre static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host) 53294b94a93SLudovic Barre { 53394b94a93SLudovic Barre /* clear the voltage switch completion flag */ 53494b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR); 53594b94a93SLudovic Barre /* enable Voltage switch procedure */ 53694b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); 53794b94a93SLudovic Barre } 53894b94a93SLudovic Barre 53994b94a93SLudovic Barre static int sdmmc_post_sig_volt_switch(struct mmci_host *host, 54094b94a93SLudovic Barre struct mmc_ios *ios) 54194b94a93SLudovic Barre { 54294b94a93SLudovic Barre unsigned long flags; 54394b94a93SLudovic Barre u32 status; 54494b94a93SLudovic Barre int ret = 0; 54594b94a93SLudovic Barre 54694b94a93SLudovic Barre spin_lock_irqsave(&host->lock, flags); 547d8e193f1SChristophe Kerello if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 && 548d8e193f1SChristophe Kerello host->pwr_reg & MCI_STM32_VSWITCHEN) { 54994b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); 55094b94a93SLudovic Barre spin_unlock_irqrestore(&host->lock, flags); 55194b94a93SLudovic Barre 55294b94a93SLudovic Barre /* wait voltage switch completion while 10ms */ 55394b94a93SLudovic Barre ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS, 55494b94a93SLudovic Barre status, 55594b94a93SLudovic Barre (status & MCI_STM32_VSWEND), 55694b94a93SLudovic Barre 10, SDMMC_VSWEND_TIMEOUT_US); 55794b94a93SLudovic Barre 55894b94a93SLudovic Barre writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC, 55994b94a93SLudovic Barre host->base + MMCICLEAR); 560d8e193f1SChristophe Kerello spin_lock_irqsave(&host->lock, flags); 56194b94a93SLudovic Barre mmci_write_pwrreg(host, host->pwr_reg & 56294b94a93SLudovic Barre ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH)); 56394b94a93SLudovic Barre } 564d8e193f1SChristophe Kerello spin_unlock_irqrestore(&host->lock, flags); 56594b94a93SLudovic Barre 56694b94a93SLudovic Barre return ret; 56794b94a93SLudovic Barre } 56894b94a93SLudovic Barre 56946b723ddSLudovic Barre static struct mmci_host_ops sdmmc_variant_ops = { 57046b723ddSLudovic Barre .validate_data = sdmmc_idma_validate_data, 57146b723ddSLudovic Barre .prep_data = sdmmc_idma_prep_data, 57246b723ddSLudovic Barre .unprep_data = sdmmc_idma_unprep_data, 5738372f9d0SLudovic Barre .get_datactrl_cfg = sdmmc_get_dctrl_cfg, 57446b723ddSLudovic Barre .dma_setup = sdmmc_idma_setup, 57546b723ddSLudovic Barre .dma_start = sdmmc_idma_start, 57646b723ddSLudovic Barre .dma_finalize = sdmmc_idma_finalize, 57746b723ddSLudovic Barre .set_clkreg = mmci_sdmmc_set_clkreg, 57846b723ddSLudovic Barre .set_pwrreg = mmci_sdmmc_set_pwrreg, 5790e68de6aSLudovic Barre .busy_complete = sdmmc_busy_complete, 58094b94a93SLudovic Barre .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch, 58194b94a93SLudovic Barre .post_sig_volt_switch = sdmmc_post_sig_volt_switch, 58246b723ddSLudovic Barre }; 58346b723ddSLudovic Barre 58446b723ddSLudovic Barre void sdmmc_variant_init(struct mmci_host *host) 58546b723ddSLudovic Barre { 5861103f807SLudovic Barre struct device_node *np = host->mmc->parent->of_node; 5871103f807SLudovic Barre void __iomem *base_dlyb; 5881103f807SLudovic Barre struct sdmmc_dlyb *dlyb; 5891103f807SLudovic Barre 59046b723ddSLudovic Barre host->ops = &sdmmc_variant_ops; 59133ba6fecSLudovic Barre host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); 5921103f807SLudovic Barre 5931103f807SLudovic Barre base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL); 5941103f807SLudovic Barre if (IS_ERR(base_dlyb)) 5951103f807SLudovic Barre return; 5961103f807SLudovic Barre 5971103f807SLudovic Barre dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL); 5981103f807SLudovic Barre if (!dlyb) 5991103f807SLudovic Barre return; 6001103f807SLudovic Barre 6011103f807SLudovic Barre dlyb->base = base_dlyb; 6021103f807SLudovic Barre host->variant_priv = dlyb; 6031103f807SLudovic Barre host->mmc_ops->execute_tuning = sdmmc_execute_tuning; 60446b723ddSLudovic Barre } 605