1 /* 2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #define MMCIPOWER 0x000 11 #define MCI_PWR_OFF 0x00 12 #define MCI_PWR_UP 0x02 13 #define MCI_PWR_ON 0x03 14 #define MCI_OD (1 << 6) 15 #define MCI_ROD (1 << 7) 16 /* 17 * The ST Micro version does not have ROD and reuse the voltage registers for 18 * direction settings. 19 */ 20 #define MCI_ST_DATA2DIREN (1 << 2) 21 #define MCI_ST_CMDDIREN (1 << 3) 22 #define MCI_ST_DATA0DIREN (1 << 4) 23 #define MCI_ST_DATA31DIREN (1 << 5) 24 #define MCI_ST_FBCLKEN (1 << 7) 25 #define MCI_ST_DATA74DIREN (1 << 8) 26 27 #define MMCICLOCK 0x004 28 #define MCI_CLK_ENABLE (1 << 8) 29 #define MCI_CLK_PWRSAVE (1 << 9) 30 #define MCI_CLK_BYPASS (1 << 10) 31 #define MCI_4BIT_BUS (1 << 11) 32 /* 33 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 34 * supported in ST Micro U300 and Ux500 versions 35 */ 36 #define MCI_ST_8BIT_BUS (1 << 12) 37 #define MCI_ST_U300_HWFCEN (1 << 13) 38 #define MCI_ST_UX500_NEG_EDGE (1 << 13) 39 #define MCI_ST_UX500_HWFCEN (1 << 14) 40 #define MCI_ST_UX500_CLK_INV (1 << 15) 41 /* Modified PL180 on Versatile Express platform */ 42 #define MCI_ARM_HWFCEN (1 << 12) 43 44 #define MMCIARGUMENT 0x008 45 #define MMCICOMMAND 0x00c 46 #define MCI_CPSM_RESPONSE (1 << 6) 47 #define MCI_CPSM_LONGRSP (1 << 7) 48 #define MCI_CPSM_INTERRUPT (1 << 8) 49 #define MCI_CPSM_PENDING (1 << 9) 50 #define MCI_CPSM_ENABLE (1 << 10) 51 /* Argument flag extenstions in the ST Micro versions */ 52 #define MCI_ST_SDIO_SUSP (1 << 11) 53 #define MCI_ST_ENCMD_COMPL (1 << 12) 54 #define MCI_ST_NIEN (1 << 13) 55 #define MCI_ST_CE_ATACMD (1 << 14) 56 57 #define MMCIRESPCMD 0x010 58 #define MMCIRESPONSE0 0x014 59 #define MMCIRESPONSE1 0x018 60 #define MMCIRESPONSE2 0x01c 61 #define MMCIRESPONSE3 0x020 62 #define MMCIDATATIMER 0x024 63 #define MMCIDATALENGTH 0x028 64 #define MMCIDATACTRL 0x02c 65 #define MCI_DPSM_ENABLE (1 << 0) 66 #define MCI_DPSM_DIRECTION (1 << 1) 67 #define MCI_DPSM_MODE (1 << 2) 68 #define MCI_DPSM_DMAENABLE (1 << 3) 69 #define MCI_DPSM_BLOCKSIZE (1 << 4) 70 /* Control register extensions in the ST Micro U300 and Ux500 versions */ 71 #define MCI_ST_DPSM_RWSTART (1 << 8) 72 #define MCI_ST_DPSM_RWSTOP (1 << 9) 73 #define MCI_ST_DPSM_RWMOD (1 << 10) 74 #define MCI_ST_DPSM_SDIOEN (1 << 11) 75 /* Control register extensions in the ST Micro Ux500 versions */ 76 #define MCI_ST_DPSM_DMAREQCTL (1 << 12) 77 #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) 78 #define MCI_ST_DPSM_BUSYMODE (1 << 14) 79 #define MCI_ST_DPSM_DDRMODE (1 << 15) 80 81 #define MMCIDATACNT 0x030 82 #define MMCISTATUS 0x034 83 #define MCI_CMDCRCFAIL (1 << 0) 84 #define MCI_DATACRCFAIL (1 << 1) 85 #define MCI_CMDTIMEOUT (1 << 2) 86 #define MCI_DATATIMEOUT (1 << 3) 87 #define MCI_TXUNDERRUN (1 << 4) 88 #define MCI_RXOVERRUN (1 << 5) 89 #define MCI_CMDRESPEND (1 << 6) 90 #define MCI_CMDSENT (1 << 7) 91 #define MCI_DATAEND (1 << 8) 92 #define MCI_STARTBITERR (1 << 9) 93 #define MCI_DATABLOCKEND (1 << 10) 94 #define MCI_CMDACTIVE (1 << 11) 95 #define MCI_TXACTIVE (1 << 12) 96 #define MCI_RXACTIVE (1 << 13) 97 #define MCI_TXFIFOHALFEMPTY (1 << 14) 98 #define MCI_RXFIFOHALFFULL (1 << 15) 99 #define MCI_TXFIFOFULL (1 << 16) 100 #define MCI_RXFIFOFULL (1 << 17) 101 #define MCI_TXFIFOEMPTY (1 << 18) 102 #define MCI_RXFIFOEMPTY (1 << 19) 103 #define MCI_TXDATAAVLBL (1 << 20) 104 #define MCI_RXDATAAVLBL (1 << 21) 105 /* Extended status bits for the ST Micro variants */ 106 #define MCI_ST_SDIOIT (1 << 22) 107 #define MCI_ST_CEATAEND (1 << 23) 108 #define MCI_ST_CARDBUSY (1 << 24) 109 110 #define MMCICLEAR 0x038 111 #define MCI_CMDCRCFAILCLR (1 << 0) 112 #define MCI_DATACRCFAILCLR (1 << 1) 113 #define MCI_CMDTIMEOUTCLR (1 << 2) 114 #define MCI_DATATIMEOUTCLR (1 << 3) 115 #define MCI_TXUNDERRUNCLR (1 << 4) 116 #define MCI_RXOVERRUNCLR (1 << 5) 117 #define MCI_CMDRESPENDCLR (1 << 6) 118 #define MCI_CMDSENTCLR (1 << 7) 119 #define MCI_DATAENDCLR (1 << 8) 120 #define MCI_STARTBITERRCLR (1 << 9) 121 #define MCI_DATABLOCKENDCLR (1 << 10) 122 /* Extended status bits for the ST Micro variants */ 123 #define MCI_ST_SDIOITC (1 << 22) 124 #define MCI_ST_CEATAENDC (1 << 23) 125 #define MCI_ST_BUSYENDC (1 << 24) 126 127 #define MMCIMASK0 0x03c 128 #define MCI_CMDCRCFAILMASK (1 << 0) 129 #define MCI_DATACRCFAILMASK (1 << 1) 130 #define MCI_CMDTIMEOUTMASK (1 << 2) 131 #define MCI_DATATIMEOUTMASK (1 << 3) 132 #define MCI_TXUNDERRUNMASK (1 << 4) 133 #define MCI_RXOVERRUNMASK (1 << 5) 134 #define MCI_CMDRESPENDMASK (1 << 6) 135 #define MCI_CMDSENTMASK (1 << 7) 136 #define MCI_DATAENDMASK (1 << 8) 137 #define MCI_STARTBITERRMASK (1 << 9) 138 #define MCI_DATABLOCKENDMASK (1 << 10) 139 #define MCI_CMDACTIVEMASK (1 << 11) 140 #define MCI_TXACTIVEMASK (1 << 12) 141 #define MCI_RXACTIVEMASK (1 << 13) 142 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 143 #define MCI_RXFIFOHALFFULLMASK (1 << 15) 144 #define MCI_TXFIFOFULLMASK (1 << 16) 145 #define MCI_RXFIFOFULLMASK (1 << 17) 146 #define MCI_TXFIFOEMPTYMASK (1 << 18) 147 #define MCI_RXFIFOEMPTYMASK (1 << 19) 148 #define MCI_TXDATAAVLBLMASK (1 << 20) 149 #define MCI_RXDATAAVLBLMASK (1 << 21) 150 /* Extended status bits for the ST Micro variants */ 151 #define MCI_ST_SDIOITMASK (1 << 22) 152 #define MCI_ST_CEATAENDMASK (1 << 23) 153 #define MCI_ST_BUSYEND (1 << 24) 154 155 #define MMCIMASK1 0x040 156 #define MMCIFIFOCNT 0x048 157 #define MMCIFIFO 0x080 /* to 0x0bc */ 158 159 #define MCI_IRQENABLE \ 160 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 161 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 162 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) 163 164 /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 165 #define MCI_IRQ1MASK \ 166 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 167 MCI_TXFIFOHALFEMPTYMASK) 168 169 #define NR_SG 128 170 171 struct clk; 172 struct variant_data; 173 struct dma_chan; 174 175 struct mmci_host_next { 176 struct dma_async_tx_descriptor *dma_desc; 177 struct dma_chan *dma_chan; 178 s32 cookie; 179 }; 180 181 struct mmci_host { 182 phys_addr_t phybase; 183 void __iomem *base; 184 struct mmc_request *mrq; 185 struct mmc_command *cmd; 186 struct mmc_data *data; 187 struct mmc_host *mmc; 188 struct clk *clk; 189 bool singleirq; 190 191 spinlock_t lock; 192 193 unsigned int mclk; 194 unsigned int cclk; 195 u32 pwr_reg; 196 u32 pwr_reg_add; 197 u32 clk_reg; 198 u32 datactrl_reg; 199 u32 busy_status; 200 bool vqmmc_enabled; 201 struct mmci_platform_data *plat; 202 struct variant_data *variant; 203 204 u8 hw_designer; 205 u8 hw_revision:4; 206 207 struct timer_list timer; 208 unsigned int oldstat; 209 210 /* pio stuff */ 211 struct sg_mapping_iter sg_miter; 212 unsigned int size; 213 214 #ifdef CONFIG_DMA_ENGINE 215 /* DMA stuff */ 216 struct dma_chan *dma_current; 217 struct dma_chan *dma_rx_channel; 218 struct dma_chan *dma_tx_channel; 219 struct dma_async_tx_descriptor *dma_desc_current; 220 struct mmci_host_next next_data; 221 222 #define dma_inprogress(host) ((host)->dma_current) 223 #else 224 #define dma_inprogress(host) (0) 225 #endif 226 }; 227 228