1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 */ 7 #define MMCIPOWER 0x000 8 #define MCI_PWR_OFF 0x00 9 #define MCI_PWR_UP 0x02 10 #define MCI_PWR_ON 0x03 11 #define MCI_OD (1 << 6) 12 #define MCI_ROD (1 << 7) 13 /* 14 * The ST Micro version does not have ROD and reuse the voltage registers for 15 * direction settings. 16 */ 17 #define MCI_ST_DATA2DIREN (1 << 2) 18 #define MCI_ST_CMDDIREN (1 << 3) 19 #define MCI_ST_DATA0DIREN (1 << 4) 20 #define MCI_ST_DATA31DIREN (1 << 5) 21 #define MCI_ST_FBCLKEN (1 << 7) 22 #define MCI_ST_DATA74DIREN (1 << 8) 23 /* 24 * The STM32 sdmmc does not have PWR_UP/OD/ROD 25 * and uses the power register for 26 */ 27 #define MCI_STM32_PWR_CYC 0x02 28 #define MCI_STM32_VSWITCH BIT(2) 29 #define MCI_STM32_VSWITCHEN BIT(3) 30 #define MCI_STM32_DIRPOL BIT(4) 31 32 #define MMCICLOCK 0x004 33 #define MCI_CLK_ENABLE (1 << 8) 34 #define MCI_CLK_PWRSAVE (1 << 9) 35 #define MCI_CLK_BYPASS (1 << 10) 36 #define MCI_4BIT_BUS (1 << 11) 37 /* 38 * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 39 * supported in ST Micro U300 and Ux500 versions 40 */ 41 #define MCI_ST_8BIT_BUS (1 << 12) 42 #define MCI_ST_U300_HWFCEN (1 << 13) 43 #define MCI_ST_UX500_NEG_EDGE (1 << 13) 44 #define MCI_ST_UX500_HWFCEN (1 << 14) 45 #define MCI_ST_UX500_CLK_INV (1 << 15) 46 /* Modified PL180 on Versatile Express platform */ 47 #define MCI_ARM_HWFCEN (1 << 12) 48 49 /* Modified on Qualcomm Integrations */ 50 #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) 51 #define MCI_QCOM_CLK_FLOWENA BIT(12) 52 #define MCI_QCOM_CLK_INVERTOUT BIT(13) 53 54 /* select in latch data and command in */ 55 #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) 56 #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) 57 58 /* Modified on STM32 sdmmc */ 59 #define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0) 60 #define MCI_STM32_CLK_WIDEBUS_4 BIT(14) 61 #define MCI_STM32_CLK_WIDEBUS_8 BIT(15) 62 #define MCI_STM32_CLK_NEGEDGE BIT(16) 63 #define MCI_STM32_CLK_HWFCEN BIT(17) 64 #define MCI_STM32_CLK_DDR BIT(18) 65 #define MCI_STM32_CLK_BUSSPEED BIT(19) 66 #define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20) 67 #define MCI_STM32_CLK_SELCK (0 << 20) 68 #define MCI_STM32_CLK_SELCKIN (1 << 20) 69 #define MCI_STM32_CLK_SELFBCK (2 << 20) 70 71 #define MMCIARGUMENT 0x008 72 73 /* The command register controls the Command Path State Machine (CPSM) */ 74 #define MMCICOMMAND 0x00c 75 #define MCI_CPSM_RESPONSE BIT(6) 76 #define MCI_CPSM_LONGRSP BIT(7) 77 #define MCI_CPSM_INTERRUPT BIT(8) 78 #define MCI_CPSM_PENDING BIT(9) 79 #define MCI_CPSM_ENABLE BIT(10) 80 /* Command register flag extenstions in the ST Micro versions */ 81 #define MCI_CPSM_ST_SDIO_SUSP BIT(11) 82 #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) 83 #define MCI_CPSM_ST_NIEN BIT(13) 84 #define MCI_CPSM_ST_CE_ATACMD BIT(14) 85 /* Command register flag extensions in the Qualcomm versions */ 86 #define MCI_CPSM_QCOM_PROGENA BIT(11) 87 #define MCI_CPSM_QCOM_DATCMD BIT(12) 88 #define MCI_CPSM_QCOM_MCIABORT BIT(13) 89 #define MCI_CPSM_QCOM_CCSENABLE BIT(14) 90 #define MCI_CPSM_QCOM_CCSDISABLE BIT(15) 91 #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16) 92 #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21) 93 /* Command register in STM32 sdmmc versions */ 94 #define MCI_CPSM_STM32_CMDTRANS BIT(6) 95 #define MCI_CPSM_STM32_CMDSTOP BIT(7) 96 #define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8) 97 #define MCI_CPSM_STM32_NORSP (0 << 8) 98 #define MCI_CPSM_STM32_SRSP_CRC (1 << 8) 99 #define MCI_CPSM_STM32_SRSP (2 << 8) 100 #define MCI_CPSM_STM32_LRSP_CRC (3 << 8) 101 #define MCI_CPSM_STM32_ENABLE BIT(12) 102 103 #define MMCIRESPCMD 0x010 104 #define MMCIRESPONSE0 0x014 105 #define MMCIRESPONSE1 0x018 106 #define MMCIRESPONSE2 0x01c 107 #define MMCIRESPONSE3 0x020 108 #define MMCIDATATIMER 0x024 109 #define MMCIDATALENGTH 0x028 110 111 /* The data control register controls the Data Path State Machine (DPSM) */ 112 #define MMCIDATACTRL 0x02c 113 #define MCI_DPSM_ENABLE BIT(0) 114 #define MCI_DPSM_DIRECTION BIT(1) 115 #define MCI_DPSM_MODE BIT(2) 116 #define MCI_DPSM_DMAENABLE BIT(3) 117 #define MCI_DPSM_BLOCKSIZE BIT(4) 118 /* Control register extensions in the ST Micro U300 and Ux500 versions */ 119 #define MCI_DPSM_ST_RWSTART BIT(8) 120 #define MCI_DPSM_ST_RWSTOP BIT(9) 121 #define MCI_DPSM_ST_RWMOD BIT(10) 122 #define MCI_DPSM_ST_SDIOEN BIT(11) 123 /* Control register extensions in the ST Micro Ux500 versions */ 124 #define MCI_DPSM_ST_DMAREQCTL BIT(12) 125 #define MCI_DPSM_ST_DBOOTMODEEN BIT(13) 126 #define MCI_DPSM_ST_BUSYMODE BIT(14) 127 #define MCI_DPSM_ST_DDRMODE BIT(15) 128 /* Control register extensions in the Qualcomm versions */ 129 #define MCI_DPSM_QCOM_DATA_PEND BIT(17) 130 #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) 131 /* Control register extensions in STM32 versions */ 132 #define MCI_DPSM_STM32_MODE_BLOCK (0 << 2) 133 #define MCI_DPSM_STM32_MODE_SDIO (1 << 2) 134 #define MCI_DPSM_STM32_MODE_STREAM (2 << 2) 135 #define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2) 136 137 #define MMCIDATACNT 0x030 138 #define MMCISTATUS 0x034 139 #define MCI_CMDCRCFAIL (1 << 0) 140 #define MCI_DATACRCFAIL (1 << 1) 141 #define MCI_CMDTIMEOUT (1 << 2) 142 #define MCI_DATATIMEOUT (1 << 3) 143 #define MCI_TXUNDERRUN (1 << 4) 144 #define MCI_RXOVERRUN (1 << 5) 145 #define MCI_CMDRESPEND (1 << 6) 146 #define MCI_CMDSENT (1 << 7) 147 #define MCI_DATAEND (1 << 8) 148 #define MCI_STARTBITERR (1 << 9) 149 #define MCI_DATABLOCKEND (1 << 10) 150 #define MCI_CMDACTIVE (1 << 11) 151 #define MCI_TXACTIVE (1 << 12) 152 #define MCI_RXACTIVE (1 << 13) 153 #define MCI_TXFIFOHALFEMPTY (1 << 14) 154 #define MCI_RXFIFOHALFFULL (1 << 15) 155 #define MCI_TXFIFOFULL (1 << 16) 156 #define MCI_RXFIFOFULL (1 << 17) 157 #define MCI_TXFIFOEMPTY (1 << 18) 158 #define MCI_RXFIFOEMPTY (1 << 19) 159 #define MCI_TXDATAAVLBL (1 << 20) 160 #define MCI_RXDATAAVLBL (1 << 21) 161 /* Extended status bits for the ST Micro variants */ 162 #define MCI_ST_SDIOIT (1 << 22) 163 #define MCI_ST_CEATAEND (1 << 23) 164 #define MCI_ST_CARDBUSY (1 << 24) 165 /* Extended status bits for the STM32 variants */ 166 #define MCI_STM32_BUSYD0 BIT(20) 167 #define MCI_STM32_BUSYD0END BIT(21) 168 #define MCI_STM32_VSWEND BIT(25) 169 170 #define MMCICLEAR 0x038 171 #define MCI_CMDCRCFAILCLR (1 << 0) 172 #define MCI_DATACRCFAILCLR (1 << 1) 173 #define MCI_CMDTIMEOUTCLR (1 << 2) 174 #define MCI_DATATIMEOUTCLR (1 << 3) 175 #define MCI_TXUNDERRUNCLR (1 << 4) 176 #define MCI_RXOVERRUNCLR (1 << 5) 177 #define MCI_CMDRESPENDCLR (1 << 6) 178 #define MCI_CMDSENTCLR (1 << 7) 179 #define MCI_DATAENDCLR (1 << 8) 180 #define MCI_STARTBITERRCLR (1 << 9) 181 #define MCI_DATABLOCKENDCLR (1 << 10) 182 /* Extended status bits for the ST Micro variants */ 183 #define MCI_ST_SDIOITC (1 << 22) 184 #define MCI_ST_CEATAENDC (1 << 23) 185 #define MCI_ST_BUSYENDC (1 << 24) 186 /* Extended clear bits for the STM32 variants */ 187 #define MCI_STM32_VSWENDC BIT(25) 188 #define MCI_STM32_CKSTOPC BIT(26) 189 190 #define MMCIMASK0 0x03c 191 #define MCI_CMDCRCFAILMASK (1 << 0) 192 #define MCI_DATACRCFAILMASK (1 << 1) 193 #define MCI_CMDTIMEOUTMASK (1 << 2) 194 #define MCI_DATATIMEOUTMASK (1 << 3) 195 #define MCI_TXUNDERRUNMASK (1 << 4) 196 #define MCI_RXOVERRUNMASK (1 << 5) 197 #define MCI_CMDRESPENDMASK (1 << 6) 198 #define MCI_CMDSENTMASK (1 << 7) 199 #define MCI_DATAENDMASK (1 << 8) 200 #define MCI_STARTBITERRMASK (1 << 9) 201 #define MCI_DATABLOCKENDMASK (1 << 10) 202 #define MCI_CMDACTIVEMASK (1 << 11) 203 #define MCI_TXACTIVEMASK (1 << 12) 204 #define MCI_RXACTIVEMASK (1 << 13) 205 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 206 #define MCI_RXFIFOHALFFULLMASK (1 << 15) 207 #define MCI_TXFIFOFULLMASK (1 << 16) 208 #define MCI_RXFIFOFULLMASK (1 << 17) 209 #define MCI_TXFIFOEMPTYMASK (1 << 18) 210 #define MCI_RXFIFOEMPTYMASK (1 << 19) 211 #define MCI_TXDATAAVLBLMASK (1 << 20) 212 #define MCI_RXDATAAVLBLMASK (1 << 21) 213 /* Extended status bits for the ST Micro variants */ 214 #define MCI_ST_SDIOITMASK (1 << 22) 215 #define MCI_ST_CEATAENDMASK (1 << 23) 216 #define MCI_ST_BUSYENDMASK (1 << 24) 217 /* Extended status bits for the STM32 variants */ 218 #define MCI_STM32_BUSYD0ENDMASK BIT(21) 219 220 #define MMCIMASK1 0x040 221 222 /* STM32 sdmmc data FIFO threshold register */ 223 #define MMCI_STM32_FIFOTHRR 0x044 224 #define MMCI_STM32_THR_MASK GENMASK(3, 0) 225 226 #define MMCIFIFOCNT 0x048 227 #define MMCIFIFO 0x080 /* to 0x0bc */ 228 229 /* STM32 sdmmc registers for IDMA (Internal DMA) */ 230 #define MMCI_STM32_IDMACTRLR 0x050 231 #define MMCI_STM32_IDMAEN BIT(0) 232 #define MMCI_STM32_IDMALLIEN BIT(1) 233 234 #define MMCI_STM32_IDMABSIZER 0x054 235 236 #define MMCI_STM32_IDMABASE0R 0x058 237 238 #define MMCI_STM32_IDMALAR 0x64 239 #define MMCI_STM32_IDMALA_MASK GENMASK(13, 0) 240 #define MMCI_STM32_ABR BIT(29) 241 #define MMCI_STM32_ULS BIT(30) 242 #define MMCI_STM32_ULA BIT(31) 243 244 #define MMCI_STM32_IDMABAR 0x68 245 246 #define MCI_IRQENABLE \ 247 (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \ 248 MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \ 249 MCI_CMDRESPENDMASK | MCI_CMDSENTMASK) 250 251 /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 252 #define MCI_IRQ_PIO_MASK \ 253 (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 254 MCI_TXFIFOHALFEMPTYMASK) 255 256 #define MCI_IRQ_PIO_STM32_MASK \ 257 (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK) 258 259 #define NR_SG 128 260 261 #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain" 262 263 struct clk; 264 struct dma_chan; 265 struct mmci_host; 266 267 /** 268 * enum mmci_busy_state - enumerate the busy detect wait states 269 * 270 * This is used for the state machine waiting for different busy detect 271 * interrupts on hardware that fire a single IRQ for start and end of 272 * the busy detect phase on DAT0. 273 */ 274 enum mmci_busy_state { 275 MMCI_BUSY_WAITING_FOR_START_IRQ, 276 MMCI_BUSY_WAITING_FOR_END_IRQ, 277 MMCI_BUSY_DONE, 278 }; 279 280 /** 281 * struct variant_data - MMCI variant-specific quirks 282 * @clkreg: default value for MCICLOCK register 283 * @clkreg_enable: enable value for MMCICLOCK register 284 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 285 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 286 * @cmdreg_cpsm_enable: enable value for CPSM 287 * @cmdreg_lrsp_crc: enable value for long response with crc 288 * @cmdreg_srsp_crc: enable value for short response with crc 289 * @cmdreg_srsp: enable value for short response without crc 290 * @cmdreg_stop: enable value for stop and abort transmission 291 * @datalength_bits: number of bits in the MMCIDATALENGTH register 292 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 293 * is asserted (likewise for RX) 294 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 295 * is asserted (likewise for RX) 296 * @data_cmd_enable: enable value for data commands. 297 * @st_sdio: enable ST specific SDIO logic 298 * @st_clkdiv: true if using a ST-specific clock divider algorithm 299 * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm 300 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 301 * @datactrl_mask_sdio: SDIO enable mask in datactrl register 302 * @datactrl_blocksz: block size in power of two 303 * @datactrl_any_blocksz: true if block any block sizes are accepted by 304 * hardware, such as with some SDIO traffic that send 305 * odd packets. 306 * @dma_power_of_2: DMA only works with blocks that are a power of 2. 307 * @datactrl_first: true if data must be setup before send command 308 * @datacnt_useless: true if you could not use datacnt register to read 309 * remaining data 310 * @pwrreg_powerup: power up value for MMCIPOWER register 311 * @f_max: maximum clk frequency supported by the controller. 312 * @signal_direction: input/out direction of bus signals can be indicated 313 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 314 * @busy_detect: true if the variant supports busy detection on DAT0. 315 * @busy_timeout: true if the variant starts data timer when the DPSM 316 * enter in Wait_R or Busy state. 317 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 318 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 319 * indicating that the card is busy 320 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 321 * getting busy end detection interrupts 322 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 323 * @explicit_mclk_control: enable explicit mclk control in driver. 324 * @qcom_fifo: enables qcom specific fifo pio read logic. 325 * @qcom_dml: enables qcom specific dma glue for dma transfers. 326 * @reversed_irq_handling: handle data irq before cmd irq. 327 * @mmcimask1: true if variant have a MMCIMASK1 register. 328 * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask 329 * register 330 * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS 331 * register. 332 * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register 333 * @dma_lli: true if variant has dma link list feature. 334 * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size. 335 */ 336 struct variant_data { 337 unsigned int clkreg; 338 unsigned int clkreg_enable; 339 unsigned int clkreg_8bit_bus_enable; 340 unsigned int clkreg_neg_edge_enable; 341 unsigned int cmdreg_cpsm_enable; 342 unsigned int cmdreg_lrsp_crc; 343 unsigned int cmdreg_srsp_crc; 344 unsigned int cmdreg_srsp; 345 unsigned int cmdreg_stop; 346 unsigned int datalength_bits; 347 unsigned int fifosize; 348 unsigned int fifohalfsize; 349 unsigned int data_cmd_enable; 350 unsigned int datactrl_mask_ddrmode; 351 unsigned int datactrl_mask_sdio; 352 unsigned int datactrl_blocksz; 353 u8 datactrl_any_blocksz:1; 354 u8 dma_power_of_2:1; 355 u8 datactrl_first:1; 356 u8 datacnt_useless:1; 357 u8 st_sdio:1; 358 u8 st_clkdiv:1; 359 u8 stm32_clkdiv:1; 360 u32 pwrreg_powerup; 361 u32 f_max; 362 u8 signal_direction:1; 363 u8 pwrreg_clkgate:1; 364 u8 busy_detect:1; 365 u8 busy_timeout:1; 366 u32 busy_dpsm_flag; 367 u32 busy_detect_flag; 368 u32 busy_detect_mask; 369 u8 pwrreg_nopower:1; 370 u8 explicit_mclk_control:1; 371 u8 qcom_fifo:1; 372 u8 qcom_dml:1; 373 u8 reversed_irq_handling:1; 374 u8 mmcimask1:1; 375 unsigned int irq_pio_mask; 376 u32 start_err; 377 u32 opendrain; 378 u8 dma_lli:1; 379 u32 stm32_idmabsize_mask; 380 u32 stm32_idmabsize_align; 381 void (*init)(struct mmci_host *host); 382 }; 383 384 /* mmci variant callbacks */ 385 struct mmci_host_ops { 386 int (*validate_data)(struct mmci_host *host, struct mmc_data *data); 387 int (*prep_data)(struct mmci_host *host, struct mmc_data *data, 388 bool next); 389 void (*unprep_data)(struct mmci_host *host, struct mmc_data *data, 390 int err); 391 u32 (*get_datactrl_cfg)(struct mmci_host *host); 392 void (*get_next_data)(struct mmci_host *host, struct mmc_data *data); 393 int (*dma_setup)(struct mmci_host *host); 394 void (*dma_release)(struct mmci_host *host); 395 int (*dma_start)(struct mmci_host *host, unsigned int *datactrl); 396 void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data); 397 void (*dma_error)(struct mmci_host *host); 398 void (*set_clkreg)(struct mmci_host *host, unsigned int desired); 399 void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr); 400 bool (*busy_complete)(struct mmci_host *host, struct mmc_command *cmd, u32 status, u32 err_msk); 401 void (*pre_sig_volt_switch)(struct mmci_host *host); 402 int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios); 403 }; 404 405 struct mmci_host { 406 phys_addr_t phybase; 407 void __iomem *base; 408 struct mmc_request *mrq; 409 struct mmc_command *cmd; 410 struct mmc_command stop_abort; 411 struct mmc_data *data; 412 struct mmc_host *mmc; 413 struct clk *clk; 414 u8 singleirq:1; 415 416 struct reset_control *rst; 417 418 spinlock_t lock; 419 420 unsigned int mclk; 421 /* cached value of requested clk in set_ios */ 422 unsigned int clock_cache; 423 unsigned int cclk; 424 u32 pwr_reg; 425 u32 pwr_reg_add; 426 u32 clk_reg; 427 u32 clk_reg_add; 428 u32 datactrl_reg; 429 enum mmci_busy_state busy_state; 430 u32 busy_status; 431 u32 mask1_reg; 432 u8 vqmmc_enabled:1; 433 struct mmci_platform_data *plat; 434 struct mmc_host_ops *mmc_ops; 435 struct mmci_host_ops *ops; 436 struct variant_data *variant; 437 void *variant_priv; 438 struct pinctrl *pinctrl; 439 struct pinctrl_state *pins_opendrain; 440 441 u8 hw_designer; 442 u8 hw_revision:4; 443 444 struct timer_list timer; 445 unsigned int oldstat; 446 u32 irq_action; 447 448 /* pio stuff */ 449 struct sg_mapping_iter sg_miter; 450 unsigned int size; 451 int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain); 452 453 u8 use_dma:1; 454 u8 dma_in_progress:1; 455 void *dma_priv; 456 457 s32 next_cookie; 458 struct delayed_work ux500_busy_timeout_work; 459 }; 460 461 #define dma_inprogress(host) ((host)->dma_in_progress) 462 463 void mmci_write_clkreg(struct mmci_host *host, u32 clk); 464 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr); 465 466 static inline u32 mmci_dctrl_blksz(struct mmci_host *host) 467 { 468 return (ffs(host->data->blksz) - 1) << 4; 469 } 470 471 #ifdef CONFIG_DMA_ENGINE 472 int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 473 bool next); 474 void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data, 475 int err); 476 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data); 477 int mmci_dmae_setup(struct mmci_host *host); 478 void mmci_dmae_release(struct mmci_host *host); 479 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl); 480 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data); 481 void mmci_dmae_error(struct mmci_host *host); 482 #endif 483 484 #ifdef CONFIG_MMC_QCOM_DML 485 void qcom_variant_init(struct mmci_host *host); 486 #else 487 static inline void qcom_variant_init(struct mmci_host *host) {} 488 #endif 489 490 #ifdef CONFIG_MMC_STM32_SDMMC 491 void sdmmc_variant_init(struct mmci_host *host); 492 #else 493 static inline void sdmmc_variant_init(struct mmci_host *host) {} 494 #endif 495