1 /* 2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #define MMCIPOWER 0x000 11 #define MCI_PWR_OFF 0x00 12 #define MCI_PWR_UP 0x02 13 #define MCI_PWR_ON 0x03 14 #define MCI_DATA2DIREN (1 << 2) 15 #define MCI_CMDDIREN (1 << 3) 16 #define MCI_DATA0DIREN (1 << 4) 17 #define MCI_DATA31DIREN (1 << 5) 18 #define MCI_OD (1 << 6) 19 #define MCI_ROD (1 << 7) 20 /* The ST Micro version does not have ROD */ 21 #define MCI_FBCLKEN (1 << 7) 22 #define MCI_DATA74DIREN (1 << 8) 23 24 #define MMCICLOCK 0x004 25 #define MCI_CLK_ENABLE (1 << 8) 26 #define MCI_CLK_PWRSAVE (1 << 9) 27 #define MCI_CLK_BYPASS (1 << 10) 28 #define MCI_4BIT_BUS (1 << 11) 29 /* 8bit wide buses supported in ST Micro versions */ 30 #define MCI_ST_8BIT_BUS (1 << 12) 31 /* HW flow control on the ST Micro version */ 32 #define MCI_ST_FCEN (1 << 13) 33 34 #define MMCIARGUMENT 0x008 35 #define MMCICOMMAND 0x00c 36 #define MCI_CPSM_RESPONSE (1 << 6) 37 #define MCI_CPSM_LONGRSP (1 << 7) 38 #define MCI_CPSM_INTERRUPT (1 << 8) 39 #define MCI_CPSM_PENDING (1 << 9) 40 #define MCI_CPSM_ENABLE (1 << 10) 41 #define MCI_SDIO_SUSP (1 << 11) 42 #define MCI_ENCMD_COMPL (1 << 12) 43 #define MCI_NIEN (1 << 13) 44 #define MCI_CE_ATACMD (1 << 14) 45 46 #define MMCIRESPCMD 0x010 47 #define MMCIRESPONSE0 0x014 48 #define MMCIRESPONSE1 0x018 49 #define MMCIRESPONSE2 0x01c 50 #define MMCIRESPONSE3 0x020 51 #define MMCIDATATIMER 0x024 52 #define MMCIDATALENGTH 0x028 53 #define MMCIDATACTRL 0x02c 54 #define MCI_DPSM_ENABLE (1 << 0) 55 #define MCI_DPSM_DIRECTION (1 << 1) 56 #define MCI_DPSM_MODE (1 << 2) 57 #define MCI_DPSM_DMAENABLE (1 << 3) 58 #define MCI_DPSM_BLOCKSIZE (1 << 4) 59 #define MCI_DPSM_RWSTART (1 << 8) 60 #define MCI_DPSM_RWSTOP (1 << 9) 61 #define MCI_DPSM_RWMOD (1 << 10) 62 #define MCI_DPSM_SDIOEN (1 << 11) 63 64 #define MMCIDATACNT 0x030 65 #define MMCISTATUS 0x034 66 #define MCI_CMDCRCFAIL (1 << 0) 67 #define MCI_DATACRCFAIL (1 << 1) 68 #define MCI_CMDTIMEOUT (1 << 2) 69 #define MCI_DATATIMEOUT (1 << 3) 70 #define MCI_TXUNDERRUN (1 << 4) 71 #define MCI_RXOVERRUN (1 << 5) 72 #define MCI_CMDRESPEND (1 << 6) 73 #define MCI_CMDSENT (1 << 7) 74 #define MCI_DATAEND (1 << 8) 75 #define MCI_DATABLOCKEND (1 << 10) 76 #define MCI_CMDACTIVE (1 << 11) 77 #define MCI_TXACTIVE (1 << 12) 78 #define MCI_RXACTIVE (1 << 13) 79 #define MCI_TXFIFOHALFEMPTY (1 << 14) 80 #define MCI_RXFIFOHALFFULL (1 << 15) 81 #define MCI_TXFIFOFULL (1 << 16) 82 #define MCI_RXFIFOFULL (1 << 17) 83 #define MCI_TXFIFOEMPTY (1 << 18) 84 #define MCI_RXFIFOEMPTY (1 << 19) 85 #define MCI_TXDATAAVLBL (1 << 20) 86 #define MCI_RXDATAAVLBL (1 << 21) 87 #define MCI_SDIOIT (1 << 22) 88 #define MCI_CEATAEND (1 << 23) 89 90 #define MMCICLEAR 0x038 91 #define MCI_CMDCRCFAILCLR (1 << 0) 92 #define MCI_DATACRCFAILCLR (1 << 1) 93 #define MCI_CMDTIMEOUTCLR (1 << 2) 94 #define MCI_DATATIMEOUTCLR (1 << 3) 95 #define MCI_TXUNDERRUNCLR (1 << 4) 96 #define MCI_RXOVERRUNCLR (1 << 5) 97 #define MCI_CMDRESPENDCLR (1 << 6) 98 #define MCI_CMDSENTCLR (1 << 7) 99 #define MCI_DATAENDCLR (1 << 8) 100 #define MCI_DATABLOCKENDCLR (1 << 10) 101 #define MCI_SDIOITC (1 << 22) 102 #define MCI_CEATAENDC (1 << 23) 103 104 #define MMCIMASK0 0x03c 105 #define MCI_CMDCRCFAILMASK (1 << 0) 106 #define MCI_DATACRCFAILMASK (1 << 1) 107 #define MCI_CMDTIMEOUTMASK (1 << 2) 108 #define MCI_DATATIMEOUTMASK (1 << 3) 109 #define MCI_TXUNDERRUNMASK (1 << 4) 110 #define MCI_RXOVERRUNMASK (1 << 5) 111 #define MCI_CMDRESPENDMASK (1 << 6) 112 #define MCI_CMDSENTMASK (1 << 7) 113 #define MCI_DATAENDMASK (1 << 8) 114 #define MCI_DATABLOCKENDMASK (1 << 10) 115 #define MCI_CMDACTIVEMASK (1 << 11) 116 #define MCI_TXACTIVEMASK (1 << 12) 117 #define MCI_RXACTIVEMASK (1 << 13) 118 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 119 #define MCI_RXFIFOHALFFULLMASK (1 << 15) 120 #define MCI_TXFIFOFULLMASK (1 << 16) 121 #define MCI_RXFIFOFULLMASK (1 << 17) 122 #define MCI_TXFIFOEMPTYMASK (1 << 18) 123 #define MCI_RXFIFOEMPTYMASK (1 << 19) 124 #define MCI_TXDATAAVLBLMASK (1 << 20) 125 #define MCI_RXDATAAVLBLMASK (1 << 21) 126 #define MCI_SDIOITMASK (1 << 22) 127 #define MCI_CEATAENDMASK (1 << 23) 128 129 #define MMCIMASK1 0x040 130 #define MMCIFIFOCNT 0x048 131 #define MMCIFIFO 0x080 /* to 0x0bc */ 132 133 #define MCI_IRQENABLE \ 134 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 135 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 136 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK) 137 138 /* 139 * The size of the FIFO in bytes. 140 */ 141 #define MCI_FIFOSIZE (16*4) 142 143 #define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) 144 145 #define NR_SG 16 146 147 struct clk; 148 149 struct mmci_host { 150 void __iomem *base; 151 struct mmc_request *mrq; 152 struct mmc_command *cmd; 153 struct mmc_data *data; 154 struct mmc_host *mmc; 155 struct clk *clk; 156 int gpio_cd; 157 int gpio_wp; 158 159 unsigned int data_xfered; 160 161 spinlock_t lock; 162 163 unsigned int mclk; 164 unsigned int cclk; 165 u32 pwr; 166 struct mmci_platform_data *plat; 167 168 u8 hw_designer; 169 u8 hw_revision:4; 170 171 struct timer_list timer; 172 unsigned int oldstat; 173 174 unsigned int sg_len; 175 176 /* pio stuff */ 177 struct scatterlist *sg_ptr; 178 unsigned int sg_off; 179 unsigned int size; 180 struct regulator *vcc; 181 }; 182 183 static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 184 { 185 /* 186 * Ideally, we want the higher levels to pass us a scatter list. 187 */ 188 host->sg_len = data->sg_len; 189 host->sg_ptr = data->sg; 190 host->sg_off = 0; 191 } 192 193 static inline int mmci_next_sg(struct mmci_host *host) 194 { 195 host->sg_ptr++; 196 host->sg_off = 0; 197 return --host->sg_len; 198 } 199 200 static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags) 201 { 202 struct scatterlist *sg = host->sg_ptr; 203 204 local_irq_save(*flags); 205 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 206 } 207 208 static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags) 209 { 210 kunmap_atomic(buffer, KM_BIO_SRC_IRQ); 211 local_irq_restore(*flags); 212 } 213