11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #define MMCIPOWER 0x000 111c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 121c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 131c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 141c6a0718SPierre Ossman #define MCI_OD (1 << 6) 151c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 164593df29SUlf Hansson /* 174593df29SUlf Hansson * The ST Micro version does not have ROD and reuse the voltage registers for 184593df29SUlf Hansson * direction settings. 194593df29SUlf Hansson */ 204593df29SUlf Hansson #define MCI_ST_DATA2DIREN (1 << 2) 214593df29SUlf Hansson #define MCI_ST_CMDDIREN (1 << 3) 224593df29SUlf Hansson #define MCI_ST_DATA0DIREN (1 << 4) 234593df29SUlf Hansson #define MCI_ST_DATA31DIREN (1 << 5) 244593df29SUlf Hansson #define MCI_ST_FBCLKEN (1 << 7) 254593df29SUlf Hansson #define MCI_ST_DATA74DIREN (1 << 8) 261c6a0718SPierre Ossman 271c6a0718SPierre Ossman #define MMCICLOCK 0x004 281c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 291c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 301c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 31771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 3249ac215eSLinus Walleij /* 3349ac215eSLinus Walleij * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 3449ac215eSLinus Walleij * supported in ST Micro U300 and Ux500 versions 3549ac215eSLinus Walleij */ 36771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 3749ac215eSLinus Walleij #define MCI_ST_U300_HWFCEN (1 << 13) 3849ac215eSLinus Walleij #define MCI_ST_UX500_NEG_EDGE (1 << 13) 3949ac215eSLinus Walleij #define MCI_ST_UX500_HWFCEN (1 << 14) 4049ac215eSLinus Walleij #define MCI_ST_UX500_CLK_INV (1 << 15) 413a37298aSPawel Moll /* Modified PL180 on Versatile Express platform */ 423a37298aSPawel Moll #define MCI_ARM_HWFCEN (1 << 12) 431c6a0718SPierre Ossman 449681a4e8SSrinivas Kandagatla /* Modified on Qualcomm Integrations */ 459681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) 469681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_FLOWENA BIT(12) 479681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_INVERTOUT BIT(13) 489681a4e8SSrinivas Kandagatla 499681a4e8SSrinivas Kandagatla /* select in latch data and command in */ 509681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) 519681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) 529681a4e8SSrinivas Kandagatla 531c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 541c6a0718SPierre Ossman 555db3eee7SLinus Walleij /* The command register controls the Command Path State Machine (CPSM) */ 565db3eee7SLinus Walleij #define MMCICOMMAND 0x00c 575db3eee7SLinus Walleij #define MCI_CPSM_RESPONSE BIT(6) 585db3eee7SLinus Walleij #define MCI_CPSM_LONGRSP BIT(7) 595db3eee7SLinus Walleij #define MCI_CPSM_INTERRUPT BIT(8) 605db3eee7SLinus Walleij #define MCI_CPSM_PENDING BIT(9) 615db3eee7SLinus Walleij #define MCI_CPSM_ENABLE BIT(10) 625db3eee7SLinus Walleij /* Command register flag extenstions in the ST Micro versions */ 635db3eee7SLinus Walleij #define MCI_CPSM_ST_SDIO_SUSP BIT(11) 645db3eee7SLinus Walleij #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) 655db3eee7SLinus Walleij #define MCI_CPSM_ST_NIEN BIT(13) 665db3eee7SLinus Walleij #define MCI_CPSM_ST_CE_ATACMD BIT(14) 675db3eee7SLinus Walleij /* Command register flag extensions in the Qualcomm versions */ 685db3eee7SLinus Walleij #define MCI_CPSM_QCOM_PROGENA BIT(11) 695db3eee7SLinus Walleij #define MCI_CPSM_QCOM_DATCMD BIT(12) 705db3eee7SLinus Walleij #define MCI_CPSM_QCOM_MCIABORT BIT(13) 715db3eee7SLinus Walleij #define MCI_CPSM_QCOM_CCSENABLE BIT(14) 725db3eee7SLinus Walleij #define MCI_CPSM_QCOM_CCSDISABLE BIT(15) 735db3eee7SLinus Walleij #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16) 745db3eee7SLinus Walleij #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21) 759681a4e8SSrinivas Kandagatla 761c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 771c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 781c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 791c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 801c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 811c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 821c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 835db3eee7SLinus Walleij 845db3eee7SLinus Walleij /* The data control register controls the Data Path State Machine (DPSM) */ 851c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 865db3eee7SLinus Walleij #define MCI_DPSM_ENABLE BIT(0) 875db3eee7SLinus Walleij #define MCI_DPSM_DIRECTION BIT(1) 885db3eee7SLinus Walleij #define MCI_DPSM_MODE BIT(2) 895db3eee7SLinus Walleij #define MCI_DPSM_DMAENABLE BIT(3) 905db3eee7SLinus Walleij #define MCI_DPSM_BLOCKSIZE BIT(4) 91725343faSLinus Walleij /* Control register extensions in the ST Micro U300 and Ux500 versions */ 925db3eee7SLinus Walleij #define MCI_DPSM_ST_RWSTART BIT(8) 935db3eee7SLinus Walleij #define MCI_DPSM_ST_RWSTOP BIT(9) 945db3eee7SLinus Walleij #define MCI_DPSM_ST_RWMOD BIT(10) 955db3eee7SLinus Walleij #define MCI_DPSM_ST_SDIOEN BIT(11) 96725343faSLinus Walleij /* Control register extensions in the ST Micro Ux500 versions */ 975db3eee7SLinus Walleij #define MCI_DPSM_ST_DMAREQCTL BIT(12) 985db3eee7SLinus Walleij #define MCI_DPSM_ST_DBOOTMODEEN BIT(13) 995db3eee7SLinus Walleij #define MCI_DPSM_ST_BUSYMODE BIT(14) 1005db3eee7SLinus Walleij #define MCI_DPSM_ST_DDRMODE BIT(15) 1015db3eee7SLinus Walleij /* Control register extensions in the Qualcomm versions */ 1025db3eee7SLinus Walleij #define MCI_DPSM_QCOM_DATA_PEND BIT(17) 1035db3eee7SLinus Walleij #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) 1041c6a0718SPierre Ossman 1051c6a0718SPierre Ossman #define MMCIDATACNT 0x030 1061c6a0718SPierre Ossman #define MMCISTATUS 0x034 1071c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 1081c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 1091c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 1101c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 1111c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 1121c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 1131c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 1141c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 1151c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 116757df746SLinus Walleij #define MCI_STARTBITERR (1 << 9) 1171c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 1181c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 1191c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 1201c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 1211c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 1221c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 1231c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 1241c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 1251c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 1261c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 1271c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 1281c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 12949ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 13049ac215eSLinus Walleij #define MCI_ST_SDIOIT (1 << 22) 13149ac215eSLinus Walleij #define MCI_ST_CEATAEND (1 << 23) 13201259620SUlf Hansson #define MCI_ST_CARDBUSY (1 << 24) 1331c6a0718SPierre Ossman 1341c6a0718SPierre Ossman #define MMCICLEAR 0x038 1351c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 1361c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 1371c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 1381c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 1391c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 1401c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 1411c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 1421c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 1431c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 144757df746SLinus Walleij #define MCI_STARTBITERRCLR (1 << 9) 1451c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 14649ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 14749ac215eSLinus Walleij #define MCI_ST_SDIOITC (1 << 22) 14849ac215eSLinus Walleij #define MCI_ST_CEATAENDC (1 << 23) 14901259620SUlf Hansson #define MCI_ST_BUSYENDC (1 << 24) 1501c6a0718SPierre Ossman 1511c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1521c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1531c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1541c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1551c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1561c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1571c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1581c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1591c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1601c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 161757df746SLinus Walleij #define MCI_STARTBITERRMASK (1 << 9) 1621c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1631c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1641c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 1651c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 1661c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 1671c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 1681c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 1691c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 1701c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 1711c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 1721c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 1731c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 17449ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 17549ac215eSLinus Walleij #define MCI_ST_SDIOITMASK (1 << 22) 17649ac215eSLinus Walleij #define MCI_ST_CEATAENDMASK (1 << 23) 17749adc0caSLinus Walleij #define MCI_ST_BUSYENDMASK (1 << 24) 1781c6a0718SPierre Ossman 1791c6a0718SPierre Ossman #define MMCIMASK1 0x040 1801c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 1811c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 1821c6a0718SPierre Ossman 1831c6a0718SPierre Ossman #define MCI_IRQENABLE \ 1841c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \ 1851c6a0718SPierre Ossman MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \ 186daf9713cSLudovic Barre MCI_CMDRESPENDMASK | MCI_CMDSENTMASK) 1871c6a0718SPierre Ossman 1882686b4b4SLinus Walleij /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 1892686b4b4SLinus Walleij #define MCI_IRQ1MASK \ 1902686b4b4SLinus Walleij (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 1912686b4b4SLinus Walleij MCI_TXFIFOHALFEMPTYMASK) 1922686b4b4SLinus Walleij 193859dd55dSUlf Hansson #define NR_SG 128 1941c6a0718SPierre Ossman 195f9bb304cSPatrice Chotard #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain" 196f9bb304cSPatrice Chotard 1971c6a0718SPierre Ossman struct clk; 198c8ebae37SRussell King struct dma_chan; 199ed9067fdSUlf Hansson struct mmci_host; 200ed9067fdSUlf Hansson 201ed9067fdSUlf Hansson /** 202ed9067fdSUlf Hansson * struct variant_data - MMCI variant-specific quirks 203ed9067fdSUlf Hansson * @clkreg: default value for MCICLOCK register 204ed9067fdSUlf Hansson * @clkreg_enable: enable value for MMCICLOCK register 205ed9067fdSUlf Hansson * @clkreg_8bit_bus_enable: enable value for 8 bit bus 206ed9067fdSUlf Hansson * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 207ed9067fdSUlf Hansson * @datalength_bits: number of bits in the MMCIDATALENGTH register 208ed9067fdSUlf Hansson * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 209ed9067fdSUlf Hansson * is asserted (likewise for RX) 210ed9067fdSUlf Hansson * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 211ed9067fdSUlf Hansson * is asserted (likewise for RX) 212ed9067fdSUlf Hansson * @data_cmd_enable: enable value for data commands. 213ed9067fdSUlf Hansson * @st_sdio: enable ST specific SDIO logic 214ed9067fdSUlf Hansson * @st_clkdiv: true if using a ST-specific clock divider algorithm 215ed9067fdSUlf Hansson * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 216ed9067fdSUlf Hansson * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 217ed9067fdSUlf Hansson * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 218ed9067fdSUlf Hansson * register 219ed9067fdSUlf Hansson * @datactrl_mask_sdio: SDIO enable mask in datactrl register 220c931d495SLudovic Barre * @datactrl_blksz: block size in power of two 221ed9067fdSUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 222ed9067fdSUlf Hansson * @f_max: maximum clk frequency supported by the controller. 223ed9067fdSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 224ed9067fdSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 225ed9067fdSUlf Hansson * @busy_detect: true if the variant supports busy detection on DAT0. 226ed9067fdSUlf Hansson * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 227ed9067fdSUlf Hansson * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 228ed9067fdSUlf Hansson * indicating that the card is busy 229ed9067fdSUlf Hansson * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 230ed9067fdSUlf Hansson * getting busy end detection interrupts 231ed9067fdSUlf Hansson * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 232ed9067fdSUlf Hansson * @explicit_mclk_control: enable explicit mclk control in driver. 233ed9067fdSUlf Hansson * @qcom_fifo: enables qcom specific fifo pio read logic. 234ed9067fdSUlf Hansson * @qcom_dml: enables qcom specific dma glue for dma transfers. 235ed9067fdSUlf Hansson * @reversed_irq_handling: handle data irq before cmd irq. 236ed9067fdSUlf Hansson * @mmcimask1: true if variant have a MMCIMASK1 register. 237ed9067fdSUlf Hansson * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS 238ed9067fdSUlf Hansson * register. 239ed9067fdSUlf Hansson * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register 240ed9067fdSUlf Hansson */ 241ed9067fdSUlf Hansson struct variant_data { 242ed9067fdSUlf Hansson unsigned int clkreg; 243ed9067fdSUlf Hansson unsigned int clkreg_enable; 244ed9067fdSUlf Hansson unsigned int clkreg_8bit_bus_enable; 245ed9067fdSUlf Hansson unsigned int clkreg_neg_edge_enable; 246ed9067fdSUlf Hansson unsigned int datalength_bits; 247ed9067fdSUlf Hansson unsigned int fifosize; 248ed9067fdSUlf Hansson unsigned int fifohalfsize; 249ed9067fdSUlf Hansson unsigned int data_cmd_enable; 250ed9067fdSUlf Hansson unsigned int datactrl_mask_ddrmode; 251ed9067fdSUlf Hansson unsigned int datactrl_mask_sdio; 252c931d495SLudovic Barre unsigned int datactrl_blocksz; 25319a25d57SLudovic Barre u8 st_sdio:1; 25419a25d57SLudovic Barre u8 st_clkdiv:1; 25519a25d57SLudovic Barre u8 blksz_datactrl16:1; 25619a25d57SLudovic Barre u8 blksz_datactrl4:1; 257ed9067fdSUlf Hansson u32 pwrreg_powerup; 258ed9067fdSUlf Hansson u32 f_max; 25919a25d57SLudovic Barre u8 signal_direction:1; 26019a25d57SLudovic Barre u8 pwrreg_clkgate:1; 26119a25d57SLudovic Barre u8 busy_detect:1; 262ed9067fdSUlf Hansson u32 busy_dpsm_flag; 263ed9067fdSUlf Hansson u32 busy_detect_flag; 264ed9067fdSUlf Hansson u32 busy_detect_mask; 26519a25d57SLudovic Barre u8 pwrreg_nopower:1; 26619a25d57SLudovic Barre u8 explicit_mclk_control:1; 26719a25d57SLudovic Barre u8 qcom_fifo:1; 26819a25d57SLudovic Barre u8 qcom_dml:1; 26919a25d57SLudovic Barre u8 reversed_irq_handling:1; 27019a25d57SLudovic Barre u8 mmcimask1:1; 271ed9067fdSUlf Hansson u32 start_err; 272ed9067fdSUlf Hansson u32 opendrain; 273ed9067fdSUlf Hansson void (*init)(struct mmci_host *host); 274ed9067fdSUlf Hansson }; 275ed9067fdSUlf Hansson 276ed9067fdSUlf Hansson /* mmci variant callbacks */ 277ed9067fdSUlf Hansson struct mmci_host_ops { 278e0da1721SLudovic Barre int (*validate_data)(struct mmci_host *host, struct mmc_data *data); 27947983510SLudovic Barre int (*prep_data)(struct mmci_host *host, struct mmc_data *data, 28047983510SLudovic Barre bool next); 28147983510SLudovic Barre void (*unprep_data)(struct mmci_host *host, struct mmc_data *data, 28247983510SLudovic Barre int err); 28302769968SLudovic Barre void (*get_next_data)(struct mmci_host *host, struct mmc_data *data); 284c3647fdcSLudovic Barre int (*dma_setup)(struct mmci_host *host); 285c3647fdcSLudovic Barre void (*dma_release)(struct mmci_host *host); 286135ea30eSLudovic Barre int (*dma_start)(struct mmci_host *host, unsigned int *datactrl); 2875a9f10c3SLudovic Barre void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data); 288cfccc6acSLudovic Barre void (*dma_error)(struct mmci_host *host); 289cd3ee8c5SLudovic Barre void (*set_clkreg)(struct mmci_host *host, unsigned int desired); 290cd3ee8c5SLudovic Barre void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr); 291ed9067fdSUlf Hansson }; 2921c6a0718SPierre Ossman 2931c6a0718SPierre Ossman struct mmci_host { 294c8ebae37SRussell King phys_addr_t phybase; 2951c6a0718SPierre Ossman void __iomem *base; 2961c6a0718SPierre Ossman struct mmc_request *mrq; 2971c6a0718SPierre Ossman struct mmc_command *cmd; 2981c6a0718SPierre Ossman struct mmc_data *data; 2991c6a0718SPierre Ossman struct mmc_host *mmc; 3001c6a0718SPierre Ossman struct clk *clk; 30119a25d57SLudovic Barre u8 singleirq:1; 3021c6a0718SPierre Ossman 3031c6a0718SPierre Ossman spinlock_t lock; 3041c6a0718SPierre Ossman 3051c6a0718SPierre Ossman unsigned int mclk; 3063f4e6f7bSSrinivas Kandagatla /* cached value of requested clk in set_ios */ 3073f4e6f7bSSrinivas Kandagatla unsigned int clock_cache; 3081c6a0718SPierre Ossman unsigned int cclk; 3097437cfa5SUlf Hansson u32 pwr_reg; 3104593df29SUlf Hansson u32 pwr_reg_add; 3117437cfa5SUlf Hansson u32 clk_reg; 3129cc639a2SUlf Hansson u32 datactrl_reg; 3138d94b54dSUlf Hansson u32 busy_status; 3146ea9cdf3SPatrice Chotard u32 mask1_reg; 31519a25d57SLudovic Barre u8 vqmmc_enabled:1; 3166ef297f8SLinus Walleij struct mmci_platform_data *plat; 317ed9067fdSUlf Hansson struct mmci_host_ops *ops; 3184956e109SRabin Vincent struct variant_data *variant; 319f9bb304cSPatrice Chotard struct pinctrl *pinctrl; 320f9bb304cSPatrice Chotard struct pinctrl_state *pins_default; 321f9bb304cSPatrice Chotard struct pinctrl_state *pins_opendrain; 3221c6a0718SPierre Ossman 323cc30d60eSLinus Walleij u8 hw_designer; 324cc30d60eSLinus Walleij u8 hw_revision:4; 325cc30d60eSLinus Walleij 3261c6a0718SPierre Ossman struct timer_list timer; 3271c6a0718SPierre Ossman unsigned int oldstat; 3281c6a0718SPierre Ossman 3291c6a0718SPierre Ossman /* pio stuff */ 3304ce1d6cbSRabin Vincent struct sg_mapping_iter sg_miter; 3311c6a0718SPierre Ossman unsigned int size; 3329c34b73dSSrinivas Kandagatla int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain); 333c8ebae37SRussell King 334c3647fdcSLudovic Barre u8 use_dma:1; 33519a25d57SLudovic Barre u8 dma_in_progress:1; 336a813f2a2SLudovic Barre void *dma_priv; 337a813f2a2SLudovic Barre 338a813f2a2SLudovic Barre s32 next_cookie; 339a813f2a2SLudovic Barre }; 340c8ebae37SRussell King 341e13934bdSLinus Walleij #define dma_inprogress(host) ((host)->dma_in_progress) 3421c6a0718SPierre Ossman 343cd3ee8c5SLudovic Barre void mmci_write_clkreg(struct mmci_host *host, u32 clk); 344cd3ee8c5SLudovic Barre void mmci_write_pwrreg(struct mmci_host *host, u32 pwr); 345cd3ee8c5SLudovic Barre 34647983510SLudovic Barre int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 34747983510SLudovic Barre bool next); 34847983510SLudovic Barre void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data, 34947983510SLudovic Barre int err); 35002769968SLudovic Barre void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data); 351c3647fdcSLudovic Barre int mmci_dmae_setup(struct mmci_host *host); 352c3647fdcSLudovic Barre void mmci_dmae_release(struct mmci_host *host); 353135ea30eSLudovic Barre int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl); 3545a9f10c3SLudovic Barre void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data); 355cfccc6acSLudovic Barre void mmci_dmae_error(struct mmci_host *host); 356