11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #define MMCIPOWER 0x000 111c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 121c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 131c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 14cc30d60eSLinus Walleij #define MCI_DATA2DIREN (1 << 2) 15cc30d60eSLinus Walleij #define MCI_CMDDIREN (1 << 3) 16cc30d60eSLinus Walleij #define MCI_DATA0DIREN (1 << 4) 17cc30d60eSLinus Walleij #define MCI_DATA31DIREN (1 << 5) 181c6a0718SPierre Ossman #define MCI_OD (1 << 6) 191c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 20cc30d60eSLinus Walleij /* The ST Micro version does not have ROD */ 21cc30d60eSLinus Walleij #define MCI_FBCLKEN (1 << 7) 22cc30d60eSLinus Walleij #define MCI_DATA74DIREN (1 << 8) 231c6a0718SPierre Ossman 241c6a0718SPierre Ossman #define MMCICLOCK 0x004 251c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 261c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 271c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 28771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 29771dc157SLinus Walleij /* 8bit wide buses supported in ST Micro versions */ 30771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 311c6a0718SPierre Ossman 321c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 331c6a0718SPierre Ossman #define MMCICOMMAND 0x00c 341c6a0718SPierre Ossman #define MCI_CPSM_RESPONSE (1 << 6) 351c6a0718SPierre Ossman #define MCI_CPSM_LONGRSP (1 << 7) 361c6a0718SPierre Ossman #define MCI_CPSM_INTERRUPT (1 << 8) 371c6a0718SPierre Ossman #define MCI_CPSM_PENDING (1 << 9) 381c6a0718SPierre Ossman #define MCI_CPSM_ENABLE (1 << 10) 39cc30d60eSLinus Walleij #define MCI_SDIO_SUSP (1 << 11) 40cc30d60eSLinus Walleij #define MCI_ENCMD_COMPL (1 << 12) 41cc30d60eSLinus Walleij #define MCI_NIEN (1 << 13) 42cc30d60eSLinus Walleij #define MCI_CE_ATACMD (1 << 14) 431c6a0718SPierre Ossman 441c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 451c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 461c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 471c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 481c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 491c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 501c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 511c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 521c6a0718SPierre Ossman #define MCI_DPSM_ENABLE (1 << 0) 531c6a0718SPierre Ossman #define MCI_DPSM_DIRECTION (1 << 1) 541c6a0718SPierre Ossman #define MCI_DPSM_MODE (1 << 2) 551c6a0718SPierre Ossman #define MCI_DPSM_DMAENABLE (1 << 3) 56cc30d60eSLinus Walleij #define MCI_DPSM_BLOCKSIZE (1 << 4) 57725343faSLinus Walleij /* Control register extensions in the ST Micro U300 and Ux500 versions */ 58725343faSLinus Walleij #define MCI_ST_DPSM_RWSTART (1 << 8) 59725343faSLinus Walleij #define MCI_ST_DPSM_RWSTOP (1 << 9) 60725343faSLinus Walleij #define MCI_ST_DPSM_RWMOD (1 << 10) 61725343faSLinus Walleij #define MCI_ST_DPSM_SDIOEN (1 << 11) 62725343faSLinus Walleij /* Control register extensions in the ST Micro Ux500 versions */ 63725343faSLinus Walleij #define MCI_ST_DPSM_DMAREQCTL (1 << 12) 64725343faSLinus Walleij #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) 65725343faSLinus Walleij #define MCI_ST_DPSM_BUSYMODE (1 << 14) 66725343faSLinus Walleij #define MCI_ST_DPSM_DDRMODE (1 << 15) 671c6a0718SPierre Ossman 681c6a0718SPierre Ossman #define MMCIDATACNT 0x030 691c6a0718SPierre Ossman #define MMCISTATUS 0x034 701c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 711c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 721c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 731c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 741c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 751c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 761c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 771c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 781c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 791c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 801c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 811c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 821c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 831c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 841c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 851c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 861c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 871c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 881c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 891c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 901c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 91cc30d60eSLinus Walleij #define MCI_SDIOIT (1 << 22) 92cc30d60eSLinus Walleij #define MCI_CEATAEND (1 << 23) 931c6a0718SPierre Ossman 941c6a0718SPierre Ossman #define MMCICLEAR 0x038 951c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 961c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 971c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 981c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 991c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 1001c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 1011c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 1021c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 1031c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 1041c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 105cc30d60eSLinus Walleij #define MCI_SDIOITC (1 << 22) 106cc30d60eSLinus Walleij #define MCI_CEATAENDC (1 << 23) 1071c6a0718SPierre Ossman 1081c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1091c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1101c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1111c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1121c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1131c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1141c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1151c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1161c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1171c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 1181c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1191c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1201c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 1211c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 1221c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 1231c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 1241c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 1251c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 1261c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 1271c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 1281c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 1291c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 130cc30d60eSLinus Walleij #define MCI_SDIOITMASK (1 << 22) 131cc30d60eSLinus Walleij #define MCI_CEATAENDMASK (1 << 23) 1321c6a0718SPierre Ossman 1331c6a0718SPierre Ossman #define MMCIMASK1 0x040 1341c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 1351c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 1361c6a0718SPierre Ossman 1371c6a0718SPierre Ossman #define MCI_IRQENABLE \ 1381c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 1391c6a0718SPierre Ossman MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 1408cb28155SLinus Walleij MCI_CMDRESPENDMASK|MCI_CMDSENTMASK) 1411c6a0718SPierre Ossman 1422686b4b4SLinus Walleij /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 1432686b4b4SLinus Walleij #define MCI_IRQ1MASK \ 1442686b4b4SLinus Walleij (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 1452686b4b4SLinus Walleij MCI_TXFIFOHALFEMPTYMASK) 1462686b4b4SLinus Walleij 1471c6a0718SPierre Ossman #define NR_SG 16 1481c6a0718SPierre Ossman 1491c6a0718SPierre Ossman struct clk; 1504956e109SRabin Vincent struct variant_data; 151c8ebae37SRussell King struct dma_chan; 1521c6a0718SPierre Ossman 1531c6a0718SPierre Ossman struct mmci_host { 154c8ebae37SRussell King phys_addr_t phybase; 1551c6a0718SPierre Ossman void __iomem *base; 1561c6a0718SPierre Ossman struct mmc_request *mrq; 1571c6a0718SPierre Ossman struct mmc_command *cmd; 1581c6a0718SPierre Ossman struct mmc_data *data; 1591c6a0718SPierre Ossman struct mmc_host *mmc; 1601c6a0718SPierre Ossman struct clk *clk; 16189001446SRussell King int gpio_cd; 16289001446SRussell King int gpio_wp; 163148b8b39SRabin Vincent int gpio_cd_irq; 1642686b4b4SLinus Walleij bool singleirq; 1651c6a0718SPierre Ossman 1661c6a0718SPierre Ossman spinlock_t lock; 1671c6a0718SPierre Ossman 1681c6a0718SPierre Ossman unsigned int mclk; 1691c6a0718SPierre Ossman unsigned int cclk; 1701c6a0718SPierre Ossman u32 pwr; 1716ef297f8SLinus Walleij struct mmci_platform_data *plat; 1724956e109SRabin Vincent struct variant_data *variant; 1731c6a0718SPierre Ossman 174cc30d60eSLinus Walleij u8 hw_designer; 175cc30d60eSLinus Walleij u8 hw_revision:4; 176cc30d60eSLinus Walleij 1771c6a0718SPierre Ossman struct timer_list timer; 1781c6a0718SPierre Ossman unsigned int oldstat; 1791c6a0718SPierre Ossman 1801c6a0718SPierre Ossman /* pio stuff */ 1814ce1d6cbSRabin Vincent struct sg_mapping_iter sg_miter; 1821c6a0718SPierre Ossman unsigned int size; 18334e84f39SLinus Walleij struct regulator *vcc; 184c8ebae37SRussell King 185c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 186c8ebae37SRussell King /* DMA stuff */ 187c8ebae37SRussell King struct dma_chan *dma_current; 188c8ebae37SRussell King struct dma_chan *dma_rx_channel; 189c8ebae37SRussell King struct dma_chan *dma_tx_channel; 190c8ebae37SRussell King 191c8ebae37SRussell King #define dma_inprogress(host) ((host)->dma_current) 192c8ebae37SRussell King #else 193c8ebae37SRussell King #define dma_inprogress(host) (0) 194c8ebae37SRussell King #endif 1951c6a0718SPierre Ossman }; 1961c6a0718SPierre Ossman 197