11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #define MMCIPOWER 0x000 111c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 121c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 131c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 141c6a0718SPierre Ossman #define MCI_OD (1 << 6) 151c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 1649ac215eSLinus Walleij /* 1749ac215eSLinus Walleij * The ST Micro version does not have ROD and reuse the voltage registers 1849ac215eSLinus Walleij * for direction settings 1949ac215eSLinus Walleij */ 2049ac215eSLinus Walleij #define MCI_ST_DATA2DIREN (1 << 2) 2149ac215eSLinus Walleij #define MCI_ST_CMDDIREN (1 << 3) 2249ac215eSLinus Walleij #define MCI_ST_DATA0DIREN (1 << 4) 2349ac215eSLinus Walleij #define MCI_ST_DATA31DIREN (1 << 5) 2449ac215eSLinus Walleij #define MCI_ST_FBCLKEN (1 << 7) 2549ac215eSLinus Walleij #define MCI_ST_DATA74DIREN (1 << 8) 261c6a0718SPierre Ossman 271c6a0718SPierre Ossman #define MMCICLOCK 0x004 281c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 291c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 301c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 31771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 3249ac215eSLinus Walleij /* 3349ac215eSLinus Walleij * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 3449ac215eSLinus Walleij * supported in ST Micro U300 and Ux500 versions 3549ac215eSLinus Walleij */ 36771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 3749ac215eSLinus Walleij #define MCI_ST_U300_HWFCEN (1 << 13) 3849ac215eSLinus Walleij #define MCI_ST_UX500_NEG_EDGE (1 << 13) 3949ac215eSLinus Walleij #define MCI_ST_UX500_HWFCEN (1 << 14) 4049ac215eSLinus Walleij #define MCI_ST_UX500_CLK_INV (1 << 15) 411c6a0718SPierre Ossman 421c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 431c6a0718SPierre Ossman #define MMCICOMMAND 0x00c 441c6a0718SPierre Ossman #define MCI_CPSM_RESPONSE (1 << 6) 451c6a0718SPierre Ossman #define MCI_CPSM_LONGRSP (1 << 7) 461c6a0718SPierre Ossman #define MCI_CPSM_INTERRUPT (1 << 8) 471c6a0718SPierre Ossman #define MCI_CPSM_PENDING (1 << 9) 481c6a0718SPierre Ossman #define MCI_CPSM_ENABLE (1 << 10) 49cc30d60eSLinus Walleij #define MCI_SDIO_SUSP (1 << 11) 50cc30d60eSLinus Walleij #define MCI_ENCMD_COMPL (1 << 12) 51cc30d60eSLinus Walleij #define MCI_NIEN (1 << 13) 52cc30d60eSLinus Walleij #define MCI_CE_ATACMD (1 << 14) 531c6a0718SPierre Ossman 541c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 551c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 561c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 571c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 581c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 591c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 601c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 611c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 621c6a0718SPierre Ossman #define MCI_DPSM_ENABLE (1 << 0) 631c6a0718SPierre Ossman #define MCI_DPSM_DIRECTION (1 << 1) 641c6a0718SPierre Ossman #define MCI_DPSM_MODE (1 << 2) 651c6a0718SPierre Ossman #define MCI_DPSM_DMAENABLE (1 << 3) 66cc30d60eSLinus Walleij #define MCI_DPSM_BLOCKSIZE (1 << 4) 67725343faSLinus Walleij /* Control register extensions in the ST Micro U300 and Ux500 versions */ 68725343faSLinus Walleij #define MCI_ST_DPSM_RWSTART (1 << 8) 69725343faSLinus Walleij #define MCI_ST_DPSM_RWSTOP (1 << 9) 70725343faSLinus Walleij #define MCI_ST_DPSM_RWMOD (1 << 10) 71725343faSLinus Walleij #define MCI_ST_DPSM_SDIOEN (1 << 11) 72725343faSLinus Walleij /* Control register extensions in the ST Micro Ux500 versions */ 73725343faSLinus Walleij #define MCI_ST_DPSM_DMAREQCTL (1 << 12) 74725343faSLinus Walleij #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) 75725343faSLinus Walleij #define MCI_ST_DPSM_BUSYMODE (1 << 14) 76725343faSLinus Walleij #define MCI_ST_DPSM_DDRMODE (1 << 15) 771c6a0718SPierre Ossman 781c6a0718SPierre Ossman #define MMCIDATACNT 0x030 791c6a0718SPierre Ossman #define MMCISTATUS 0x034 801c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 811c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 821c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 831c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 841c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 851c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 861c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 871c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 881c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 89757df746SLinus Walleij #define MCI_STARTBITERR (1 << 9) 901c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 911c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 921c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 931c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 941c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 951c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 961c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 971c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 981c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 991c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 1001c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 1011c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 10249ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 10349ac215eSLinus Walleij #define MCI_ST_SDIOIT (1 << 22) 10449ac215eSLinus Walleij #define MCI_ST_CEATAEND (1 << 23) 1051c6a0718SPierre Ossman 1061c6a0718SPierre Ossman #define MMCICLEAR 0x038 1071c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 1081c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 1091c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 1101c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 1111c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 1121c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 1131c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 1141c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 1151c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 116757df746SLinus Walleij #define MCI_STARTBITERRCLR (1 << 9) 1171c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 11849ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 11949ac215eSLinus Walleij #define MCI_ST_SDIOITC (1 << 22) 12049ac215eSLinus Walleij #define MCI_ST_CEATAENDC (1 << 23) 1211c6a0718SPierre Ossman 1221c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1231c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1241c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1251c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1261c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1271c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1281c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1291c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1301c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1311c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 132757df746SLinus Walleij #define MCI_STARTBITERRMASK (1 << 9) 1331c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1341c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1351c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 1361c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 1371c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 1381c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 1391c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 1401c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 1411c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 1421c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 1431c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 1441c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 14549ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 14649ac215eSLinus Walleij #define MCI_ST_SDIOITMASK (1 << 22) 14749ac215eSLinus Walleij #define MCI_ST_CEATAENDMASK (1 << 23) 1481c6a0718SPierre Ossman 1491c6a0718SPierre Ossman #define MMCIMASK1 0x040 1501c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 1511c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 1521c6a0718SPierre Ossman 1531c6a0718SPierre Ossman #define MCI_IRQENABLE \ 1541c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 1551c6a0718SPierre Ossman MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 156757df746SLinus Walleij MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) 1571c6a0718SPierre Ossman 1582686b4b4SLinus Walleij /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 1592686b4b4SLinus Walleij #define MCI_IRQ1MASK \ 1602686b4b4SLinus Walleij (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 1612686b4b4SLinus Walleij MCI_TXFIFOHALFEMPTYMASK) 1622686b4b4SLinus Walleij 163859dd55dSUlf Hansson #define NR_SG 128 1641c6a0718SPierre Ossman 1651c6a0718SPierre Ossman struct clk; 1664956e109SRabin Vincent struct variant_data; 167c8ebae37SRussell King struct dma_chan; 1681c6a0718SPierre Ossman 16958c7ccbfSPer Forlin struct mmci_host_next { 17058c7ccbfSPer Forlin struct dma_async_tx_descriptor *dma_desc; 17158c7ccbfSPer Forlin struct dma_chan *dma_chan; 17258c7ccbfSPer Forlin s32 cookie; 17358c7ccbfSPer Forlin }; 17458c7ccbfSPer Forlin 1751c6a0718SPierre Ossman struct mmci_host { 176c8ebae37SRussell King phys_addr_t phybase; 1771c6a0718SPierre Ossman void __iomem *base; 1781c6a0718SPierre Ossman struct mmc_request *mrq; 1791c6a0718SPierre Ossman struct mmc_command *cmd; 1801c6a0718SPierre Ossman struct mmc_data *data; 1811c6a0718SPierre Ossman struct mmc_host *mmc; 1821c6a0718SPierre Ossman struct clk *clk; 18389001446SRussell King int gpio_cd; 18489001446SRussell King int gpio_wp; 185148b8b39SRabin Vincent int gpio_cd_irq; 1862686b4b4SLinus Walleij bool singleirq; 1871c6a0718SPierre Ossman 1881c6a0718SPierre Ossman spinlock_t lock; 1891c6a0718SPierre Ossman 1901c6a0718SPierre Ossman unsigned int mclk; 1911c6a0718SPierre Ossman unsigned int cclk; 1921c6a0718SPierre Ossman u32 pwr; 1936ef297f8SLinus Walleij struct mmci_platform_data *plat; 1944956e109SRabin Vincent struct variant_data *variant; 1951c6a0718SPierre Ossman 196cc30d60eSLinus Walleij u8 hw_designer; 197cc30d60eSLinus Walleij u8 hw_revision:4; 198cc30d60eSLinus Walleij 1991c6a0718SPierre Ossman struct timer_list timer; 2001c6a0718SPierre Ossman unsigned int oldstat; 2011c6a0718SPierre Ossman 2021c6a0718SPierre Ossman /* pio stuff */ 2034ce1d6cbSRabin Vincent struct sg_mapping_iter sg_miter; 2041c6a0718SPierre Ossman unsigned int size; 20534e84f39SLinus Walleij struct regulator *vcc; 206c8ebae37SRussell King 207c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 208c8ebae37SRussell King /* DMA stuff */ 209c8ebae37SRussell King struct dma_chan *dma_current; 210c8ebae37SRussell King struct dma_chan *dma_rx_channel; 211c8ebae37SRussell King struct dma_chan *dma_tx_channel; 21258c7ccbfSPer Forlin struct dma_async_tx_descriptor *dma_desc_current; 21358c7ccbfSPer Forlin struct mmci_host_next next_data; 214c8ebae37SRussell King 215c8ebae37SRussell King #define dma_inprogress(host) ((host)->dma_current) 216c8ebae37SRussell King #else 217c8ebae37SRussell King #define dma_inprogress(host) (0) 218c8ebae37SRussell King #endif 2191c6a0718SPierre Ossman }; 2201c6a0718SPierre Ossman 221