11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #define MMCIPOWER 0x000 111c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 121c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 131c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 14cc30d60eSLinus Walleij #define MCI_DATA2DIREN (1 << 2) 15cc30d60eSLinus Walleij #define MCI_CMDDIREN (1 << 3) 16cc30d60eSLinus Walleij #define MCI_DATA0DIREN (1 << 4) 17cc30d60eSLinus Walleij #define MCI_DATA31DIREN (1 << 5) 181c6a0718SPierre Ossman #define MCI_OD (1 << 6) 191c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 20cc30d60eSLinus Walleij /* The ST Micro version does not have ROD */ 21cc30d60eSLinus Walleij #define MCI_FBCLKEN (1 << 7) 22cc30d60eSLinus Walleij #define MCI_DATA74DIREN (1 << 8) 231c6a0718SPierre Ossman 241c6a0718SPierre Ossman #define MMCICLOCK 0x004 251c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 261c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 271c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 28771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 29771dc157SLinus Walleij /* 8bit wide buses supported in ST Micro versions */ 30771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 31cc30d60eSLinus Walleij /* HW flow control on the ST Micro version */ 32771dc157SLinus Walleij #define MCI_ST_FCEN (1 << 13) 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 351c6a0718SPierre Ossman #define MMCICOMMAND 0x00c 361c6a0718SPierre Ossman #define MCI_CPSM_RESPONSE (1 << 6) 371c6a0718SPierre Ossman #define MCI_CPSM_LONGRSP (1 << 7) 381c6a0718SPierre Ossman #define MCI_CPSM_INTERRUPT (1 << 8) 391c6a0718SPierre Ossman #define MCI_CPSM_PENDING (1 << 9) 401c6a0718SPierre Ossman #define MCI_CPSM_ENABLE (1 << 10) 41cc30d60eSLinus Walleij #define MCI_SDIO_SUSP (1 << 11) 42cc30d60eSLinus Walleij #define MCI_ENCMD_COMPL (1 << 12) 43cc30d60eSLinus Walleij #define MCI_NIEN (1 << 13) 44cc30d60eSLinus Walleij #define MCI_CE_ATACMD (1 << 14) 451c6a0718SPierre Ossman 461c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 471c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 481c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 491c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 501c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 511c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 521c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 531c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 541c6a0718SPierre Ossman #define MCI_DPSM_ENABLE (1 << 0) 551c6a0718SPierre Ossman #define MCI_DPSM_DIRECTION (1 << 1) 561c6a0718SPierre Ossman #define MCI_DPSM_MODE (1 << 2) 571c6a0718SPierre Ossman #define MCI_DPSM_DMAENABLE (1 << 3) 58cc30d60eSLinus Walleij #define MCI_DPSM_BLOCKSIZE (1 << 4) 59cc30d60eSLinus Walleij #define MCI_DPSM_RWSTART (1 << 8) 60cc30d60eSLinus Walleij #define MCI_DPSM_RWSTOP (1 << 9) 61cc30d60eSLinus Walleij #define MCI_DPSM_RWMOD (1 << 10) 62cc30d60eSLinus Walleij #define MCI_DPSM_SDIOEN (1 << 11) 631c6a0718SPierre Ossman 641c6a0718SPierre Ossman #define MMCIDATACNT 0x030 651c6a0718SPierre Ossman #define MMCISTATUS 0x034 661c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 671c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 681c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 691c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 701c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 711c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 721c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 731c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 741c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 751c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 761c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 771c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 781c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 791c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 801c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 811c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 821c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 831c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 841c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 851c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 861c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 87cc30d60eSLinus Walleij #define MCI_SDIOIT (1 << 22) 88cc30d60eSLinus Walleij #define MCI_CEATAEND (1 << 23) 891c6a0718SPierre Ossman 901c6a0718SPierre Ossman #define MMCICLEAR 0x038 911c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 921c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 931c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 941c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 951c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 961c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 971c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 981c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 991c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 1001c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 101cc30d60eSLinus Walleij #define MCI_SDIOITC (1 << 22) 102cc30d60eSLinus Walleij #define MCI_CEATAENDC (1 << 23) 1031c6a0718SPierre Ossman 1041c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1051c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1061c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1071c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1081c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1091c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1101c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1111c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1121c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1131c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 1141c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1151c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1161c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 1171c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 1181c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 1191c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 1201c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 1211c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 1221c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 1231c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 1241c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 1251c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 126cc30d60eSLinus Walleij #define MCI_SDIOITMASK (1 << 22) 127cc30d60eSLinus Walleij #define MCI_CEATAENDMASK (1 << 23) 1281c6a0718SPierre Ossman 1291c6a0718SPierre Ossman #define MMCIMASK1 0x040 1301c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 1311c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 1321c6a0718SPierre Ossman 1331c6a0718SPierre Ossman #define MCI_IRQENABLE \ 1341c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 1351c6a0718SPierre Ossman MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 1361c6a0718SPierre Ossman MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK) 1371c6a0718SPierre Ossman 1381c6a0718SPierre Ossman /* 1391c6a0718SPierre Ossman * The size of the FIFO in bytes. 1401c6a0718SPierre Ossman */ 1411c6a0718SPierre Ossman #define MCI_FIFOSIZE (16*4) 1421c6a0718SPierre Ossman 1431c6a0718SPierre Ossman #define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2) 1441c6a0718SPierre Ossman 1451c6a0718SPierre Ossman #define NR_SG 16 1461c6a0718SPierre Ossman 1471c6a0718SPierre Ossman struct clk; 1481c6a0718SPierre Ossman 1491c6a0718SPierre Ossman struct mmci_host { 1501c6a0718SPierre Ossman void __iomem *base; 1511c6a0718SPierre Ossman struct mmc_request *mrq; 1521c6a0718SPierre Ossman struct mmc_command *cmd; 1531c6a0718SPierre Ossman struct mmc_data *data; 1541c6a0718SPierre Ossman struct mmc_host *mmc; 1551c6a0718SPierre Ossman struct clk *clk; 15689001446SRussell King int gpio_cd; 15789001446SRussell King int gpio_wp; 1581c6a0718SPierre Ossman 1591c6a0718SPierre Ossman unsigned int data_xfered; 1601c6a0718SPierre Ossman 1611c6a0718SPierre Ossman spinlock_t lock; 1621c6a0718SPierre Ossman 1631c6a0718SPierre Ossman unsigned int mclk; 1641c6a0718SPierre Ossman unsigned int cclk; 1651c6a0718SPierre Ossman u32 pwr; 1666ef297f8SLinus Walleij struct mmci_platform_data *plat; 1671c6a0718SPierre Ossman 168cc30d60eSLinus Walleij u8 hw_designer; 169cc30d60eSLinus Walleij u8 hw_revision:4; 170cc30d60eSLinus Walleij 1711c6a0718SPierre Ossman struct timer_list timer; 1721c6a0718SPierre Ossman unsigned int oldstat; 1731c6a0718SPierre Ossman 1741c6a0718SPierre Ossman unsigned int sg_len; 1751c6a0718SPierre Ossman 1761c6a0718SPierre Ossman /* pio stuff */ 1771c6a0718SPierre Ossman struct scatterlist *sg_ptr; 1781c6a0718SPierre Ossman unsigned int sg_off; 1791c6a0718SPierre Ossman unsigned int size; 18034e84f39SLinus Walleij struct regulator *vcc; 1811c6a0718SPierre Ossman }; 1821c6a0718SPierre Ossman 1831c6a0718SPierre Ossman static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 1841c6a0718SPierre Ossman { 1851c6a0718SPierre Ossman /* 1861c6a0718SPierre Ossman * Ideally, we want the higher levels to pass us a scatter list. 1871c6a0718SPierre Ossman */ 1881c6a0718SPierre Ossman host->sg_len = data->sg_len; 1891c6a0718SPierre Ossman host->sg_ptr = data->sg; 1901c6a0718SPierre Ossman host->sg_off = 0; 1911c6a0718SPierre Ossman } 1921c6a0718SPierre Ossman 1931c6a0718SPierre Ossman static inline int mmci_next_sg(struct mmci_host *host) 1941c6a0718SPierre Ossman { 1951c6a0718SPierre Ossman host->sg_ptr++; 1961c6a0718SPierre Ossman host->sg_off = 0; 1971c6a0718SPierre Ossman return --host->sg_len; 1981c6a0718SPierre Ossman } 1991c6a0718SPierre Ossman 2001c6a0718SPierre Ossman static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags) 2011c6a0718SPierre Ossman { 2021c6a0718SPierre Ossman struct scatterlist *sg = host->sg_ptr; 2031c6a0718SPierre Ossman 2041c6a0718SPierre Ossman local_irq_save(*flags); 2054e017764SEmil Medve return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 2061c6a0718SPierre Ossman } 2071c6a0718SPierre Ossman 2081c6a0718SPierre Ossman static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags) 2091c6a0718SPierre Ossman { 2101c6a0718SPierre Ossman kunmap_atomic(buffer, KM_BIO_SRC_IRQ); 2111c6a0718SPierre Ossman local_irq_restore(*flags); 2121c6a0718SPierre Ossman } 213