1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21c6a0718SPierre Ossman /* 370f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 41c6a0718SPierre Ossman * 51c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 61c6a0718SPierre Ossman */ 71c6a0718SPierre Ossman #define MMCIPOWER 0x000 81c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 91c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 101c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 111c6a0718SPierre Ossman #define MCI_OD (1 << 6) 121c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 134593df29SUlf Hansson /* 144593df29SUlf Hansson * The ST Micro version does not have ROD and reuse the voltage registers for 154593df29SUlf Hansson * direction settings. 164593df29SUlf Hansson */ 174593df29SUlf Hansson #define MCI_ST_DATA2DIREN (1 << 2) 184593df29SUlf Hansson #define MCI_ST_CMDDIREN (1 << 3) 194593df29SUlf Hansson #define MCI_ST_DATA0DIREN (1 << 4) 204593df29SUlf Hansson #define MCI_ST_DATA31DIREN (1 << 5) 214593df29SUlf Hansson #define MCI_ST_FBCLKEN (1 << 7) 224593df29SUlf Hansson #define MCI_ST_DATA74DIREN (1 << 8) 23f3f64334SLudovic Barre /* 24f3f64334SLudovic Barre * The STM32 sdmmc does not have PWR_UP/OD/ROD 25f3f64334SLudovic Barre * and uses the power register for 26f3f64334SLudovic Barre */ 27f3f64334SLudovic Barre #define MCI_STM32_PWR_CYC 0x02 28f3f64334SLudovic Barre #define MCI_STM32_VSWITCH BIT(2) 29f3f64334SLudovic Barre #define MCI_STM32_VSWITCHEN BIT(3) 30f3f64334SLudovic Barre #define MCI_STM32_DIRPOL BIT(4) 311c6a0718SPierre Ossman 321c6a0718SPierre Ossman #define MMCICLOCK 0x004 331c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 341c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 351c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 36771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 3749ac215eSLinus Walleij /* 3849ac215eSLinus Walleij * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 3949ac215eSLinus Walleij * supported in ST Micro U300 and Ux500 versions 4049ac215eSLinus Walleij */ 41771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 4249ac215eSLinus Walleij #define MCI_ST_U300_HWFCEN (1 << 13) 4349ac215eSLinus Walleij #define MCI_ST_UX500_NEG_EDGE (1 << 13) 4449ac215eSLinus Walleij #define MCI_ST_UX500_HWFCEN (1 << 14) 4549ac215eSLinus Walleij #define MCI_ST_UX500_CLK_INV (1 << 15) 463a37298aSPawel Moll /* Modified PL180 on Versatile Express platform */ 473a37298aSPawel Moll #define MCI_ARM_HWFCEN (1 << 12) 481c6a0718SPierre Ossman 499681a4e8SSrinivas Kandagatla /* Modified on Qualcomm Integrations */ 509681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) 519681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_FLOWENA BIT(12) 529681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_INVERTOUT BIT(13) 539681a4e8SSrinivas Kandagatla 549681a4e8SSrinivas Kandagatla /* select in latch data and command in */ 559681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) 569681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) 579681a4e8SSrinivas Kandagatla 58f3f64334SLudovic Barre /* Modified on STM32 sdmmc */ 59f3f64334SLudovic Barre #define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0) 60f3f64334SLudovic Barre #define MCI_STM32_CLK_WIDEBUS_4 BIT(14) 61f3f64334SLudovic Barre #define MCI_STM32_CLK_WIDEBUS_8 BIT(15) 62f3f64334SLudovic Barre #define MCI_STM32_CLK_NEGEDGE BIT(16) 63f3f64334SLudovic Barre #define MCI_STM32_CLK_HWFCEN BIT(17) 64f3f64334SLudovic Barre #define MCI_STM32_CLK_DDR BIT(18) 65f3f64334SLudovic Barre #define MCI_STM32_CLK_BUSSPEED BIT(19) 66f3f64334SLudovic Barre #define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20) 67f3f64334SLudovic Barre #define MCI_STM32_CLK_SELCK (0 << 20) 68f3f64334SLudovic Barre #define MCI_STM32_CLK_SELCKIN (1 << 20) 69f3f64334SLudovic Barre #define MCI_STM32_CLK_SELFBCK (2 << 20) 70f3f64334SLudovic Barre 711c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 721c6a0718SPierre Ossman 735db3eee7SLinus Walleij /* The command register controls the Command Path State Machine (CPSM) */ 745db3eee7SLinus Walleij #define MMCICOMMAND 0x00c 755db3eee7SLinus Walleij #define MCI_CPSM_RESPONSE BIT(6) 765db3eee7SLinus Walleij #define MCI_CPSM_LONGRSP BIT(7) 775db3eee7SLinus Walleij #define MCI_CPSM_INTERRUPT BIT(8) 785db3eee7SLinus Walleij #define MCI_CPSM_PENDING BIT(9) 795db3eee7SLinus Walleij #define MCI_CPSM_ENABLE BIT(10) 805db3eee7SLinus Walleij /* Command register flag extenstions in the ST Micro versions */ 815db3eee7SLinus Walleij #define MCI_CPSM_ST_SDIO_SUSP BIT(11) 825db3eee7SLinus Walleij #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) 835db3eee7SLinus Walleij #define MCI_CPSM_ST_NIEN BIT(13) 845db3eee7SLinus Walleij #define MCI_CPSM_ST_CE_ATACMD BIT(14) 855db3eee7SLinus Walleij /* Command register flag extensions in the Qualcomm versions */ 865db3eee7SLinus Walleij #define MCI_CPSM_QCOM_PROGENA BIT(11) 875db3eee7SLinus Walleij #define MCI_CPSM_QCOM_DATCMD BIT(12) 885db3eee7SLinus Walleij #define MCI_CPSM_QCOM_MCIABORT BIT(13) 895db3eee7SLinus Walleij #define MCI_CPSM_QCOM_CCSENABLE BIT(14) 905db3eee7SLinus Walleij #define MCI_CPSM_QCOM_CCSDISABLE BIT(15) 915db3eee7SLinus Walleij #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16) 925db3eee7SLinus Walleij #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21) 93f3f64334SLudovic Barre /* Command register in STM32 sdmmc versions */ 94f3f64334SLudovic Barre #define MCI_CPSM_STM32_CMDTRANS BIT(6) 95f3f64334SLudovic Barre #define MCI_CPSM_STM32_CMDSTOP BIT(7) 96f3f64334SLudovic Barre #define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8) 97f3f64334SLudovic Barre #define MCI_CPSM_STM32_NORSP (0 << 8) 98f3f64334SLudovic Barre #define MCI_CPSM_STM32_SRSP_CRC (1 << 8) 99f3f64334SLudovic Barre #define MCI_CPSM_STM32_SRSP (2 << 8) 100f3f64334SLudovic Barre #define MCI_CPSM_STM32_LRSP_CRC (3 << 8) 101f3f64334SLudovic Barre #define MCI_CPSM_STM32_ENABLE BIT(12) 1029681a4e8SSrinivas Kandagatla 1031c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 1041c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 1051c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 1061c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 1071c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 1081c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 1091c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 1105db3eee7SLinus Walleij 1115db3eee7SLinus Walleij /* The data control register controls the Data Path State Machine (DPSM) */ 1121c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 1135db3eee7SLinus Walleij #define MCI_DPSM_ENABLE BIT(0) 1145db3eee7SLinus Walleij #define MCI_DPSM_DIRECTION BIT(1) 1155db3eee7SLinus Walleij #define MCI_DPSM_MODE BIT(2) 1165db3eee7SLinus Walleij #define MCI_DPSM_DMAENABLE BIT(3) 1175db3eee7SLinus Walleij #define MCI_DPSM_BLOCKSIZE BIT(4) 118725343faSLinus Walleij /* Control register extensions in the ST Micro U300 and Ux500 versions */ 1195db3eee7SLinus Walleij #define MCI_DPSM_ST_RWSTART BIT(8) 1205db3eee7SLinus Walleij #define MCI_DPSM_ST_RWSTOP BIT(9) 1215db3eee7SLinus Walleij #define MCI_DPSM_ST_RWMOD BIT(10) 1225db3eee7SLinus Walleij #define MCI_DPSM_ST_SDIOEN BIT(11) 123725343faSLinus Walleij /* Control register extensions in the ST Micro Ux500 versions */ 1245db3eee7SLinus Walleij #define MCI_DPSM_ST_DMAREQCTL BIT(12) 1255db3eee7SLinus Walleij #define MCI_DPSM_ST_DBOOTMODEEN BIT(13) 1265db3eee7SLinus Walleij #define MCI_DPSM_ST_BUSYMODE BIT(14) 1275db3eee7SLinus Walleij #define MCI_DPSM_ST_DDRMODE BIT(15) 1285db3eee7SLinus Walleij /* Control register extensions in the Qualcomm versions */ 1295db3eee7SLinus Walleij #define MCI_DPSM_QCOM_DATA_PEND BIT(17) 1305db3eee7SLinus Walleij #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) 1318372f9d0SLudovic Barre /* Control register extensions in STM32 versions */ 1328372f9d0SLudovic Barre #define MCI_DPSM_STM32_MODE_BLOCK (0 << 2) 1338372f9d0SLudovic Barre #define MCI_DPSM_STM32_MODE_SDIO (1 << 2) 1348372f9d0SLudovic Barre #define MCI_DPSM_STM32_MODE_STREAM (2 << 2) 1358372f9d0SLudovic Barre #define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2) 1361c6a0718SPierre Ossman 1371c6a0718SPierre Ossman #define MMCIDATACNT 0x030 1381c6a0718SPierre Ossman #define MMCISTATUS 0x034 1391c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 1401c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 1411c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 1421c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 1431c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 1441c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 1451c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 1461c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 1471c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 148757df746SLinus Walleij #define MCI_STARTBITERR (1 << 9) 1491c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 1501c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 1511c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 1521c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 1531c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 1541c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 1551c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 1561c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 1571c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 1581c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 1591c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 1601c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 16149ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 16249ac215eSLinus Walleij #define MCI_ST_SDIOIT (1 << 22) 16349ac215eSLinus Walleij #define MCI_ST_CEATAEND (1 << 23) 16401259620SUlf Hansson #define MCI_ST_CARDBUSY (1 << 24) 165f3f64334SLudovic Barre /* Extended status bits for the STM32 variants */ 166f3f64334SLudovic Barre #define MCI_STM32_BUSYD0 BIT(20) 1670e68de6aSLudovic Barre #define MCI_STM32_BUSYD0END BIT(21) 1681c6a0718SPierre Ossman 1691c6a0718SPierre Ossman #define MMCICLEAR 0x038 1701c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 1711c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 1721c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 1731c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 1741c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 1751c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 1761c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 1771c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 1781c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 179757df746SLinus Walleij #define MCI_STARTBITERRCLR (1 << 9) 1801c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 18149ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 18249ac215eSLinus Walleij #define MCI_ST_SDIOITC (1 << 22) 18349ac215eSLinus Walleij #define MCI_ST_CEATAENDC (1 << 23) 18401259620SUlf Hansson #define MCI_ST_BUSYENDC (1 << 24) 1851c6a0718SPierre Ossman 1861c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1871c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1881c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1891c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1901c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1911c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1921c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1931c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1941c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1951c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 196757df746SLinus Walleij #define MCI_STARTBITERRMASK (1 << 9) 1971c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1981c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1991c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 2001c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 2011c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 2021c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 2031c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 2041c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 2051c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 2061c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 2071c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 2081c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 20949ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 21049ac215eSLinus Walleij #define MCI_ST_SDIOITMASK (1 << 22) 21149ac215eSLinus Walleij #define MCI_ST_CEATAENDMASK (1 << 23) 21249adc0caSLinus Walleij #define MCI_ST_BUSYENDMASK (1 << 24) 213f3f64334SLudovic Barre /* Extended status bits for the STM32 variants */ 214f3f64334SLudovic Barre #define MCI_STM32_BUSYD0ENDMASK BIT(21) 2151c6a0718SPierre Ossman 2161c6a0718SPierre Ossman #define MMCIMASK1 0x040 2171c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 2181c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 2191c6a0718SPierre Ossman 220f3f64334SLudovic Barre /* STM32 sdmmc registers for IDMA (Internal DMA) */ 221f3f64334SLudovic Barre #define MMCI_STM32_IDMACTRLR 0x050 222f3f64334SLudovic Barre #define MMCI_STM32_IDMAEN BIT(0) 223f3f64334SLudovic Barre #define MMCI_STM32_IDMALLIEN BIT(1) 224f3f64334SLudovic Barre 225f3f64334SLudovic Barre #define MMCI_STM32_IDMABSIZER 0x054 226f3f64334SLudovic Barre #define MMCI_STM32_IDMABNDT_SHIFT 5 227f3f64334SLudovic Barre #define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5) 228f3f64334SLudovic Barre 229f3f64334SLudovic Barre #define MMCI_STM32_IDMABASE0R 0x058 230f3f64334SLudovic Barre 231f3f64334SLudovic Barre #define MMCI_STM32_IDMALAR 0x64 232f3f64334SLudovic Barre #define MMCI_STM32_IDMALA_MASK GENMASK(13, 0) 233f3f64334SLudovic Barre #define MMCI_STM32_ABR BIT(29) 234f3f64334SLudovic Barre #define MMCI_STM32_ULS BIT(30) 235f3f64334SLudovic Barre #define MMCI_STM32_ULA BIT(31) 236f3f64334SLudovic Barre 237f3f64334SLudovic Barre #define MMCI_STM32_IDMABAR 0x68 238f3f64334SLudovic Barre 2391c6a0718SPierre Ossman #define MCI_IRQENABLE \ 2401c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \ 2411c6a0718SPierre Ossman MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \ 242daf9713cSLudovic Barre MCI_CMDRESPENDMASK | MCI_CMDSENTMASK) 2431c6a0718SPierre Ossman 2442686b4b4SLinus Walleij /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 24559db5e2dSLudovic Barre #define MCI_IRQ_PIO_MASK \ 2462686b4b4SLinus Walleij (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 2472686b4b4SLinus Walleij MCI_TXFIFOHALFEMPTYMASK) 2482686b4b4SLinus Walleij 249f3f64334SLudovic Barre #define MCI_IRQ_PIO_STM32_MASK \ 250f3f64334SLudovic Barre (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK) 251f3f64334SLudovic Barre 252859dd55dSUlf Hansson #define NR_SG 128 2531c6a0718SPierre Ossman 254f9bb304cSPatrice Chotard #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain" 255f9bb304cSPatrice Chotard 2561c6a0718SPierre Ossman struct clk; 257c8ebae37SRussell King struct dma_chan; 258ed9067fdSUlf Hansson struct mmci_host; 259ed9067fdSUlf Hansson 260ed9067fdSUlf Hansson /** 261ed9067fdSUlf Hansson * struct variant_data - MMCI variant-specific quirks 262ed9067fdSUlf Hansson * @clkreg: default value for MCICLOCK register 263ed9067fdSUlf Hansson * @clkreg_enable: enable value for MMCICLOCK register 264ed9067fdSUlf Hansson * @clkreg_8bit_bus_enable: enable value for 8 bit bus 265ed9067fdSUlf Hansson * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 2660f244804SLudovic Barre * @cmdreg_cpsm_enable: enable value for CPSM 2670f244804SLudovic Barre * @cmdreg_lrsp_crc: enable value for long response with crc 2680f244804SLudovic Barre * @cmdreg_srsp_crc: enable value for short response with crc 2690f244804SLudovic Barre * @cmdreg_srsp: enable value for short response without crc 270c8073e52SLudovic Barre * @cmdreg_stop: enable value for stop and abort transmission 271ed9067fdSUlf Hansson * @datalength_bits: number of bits in the MMCIDATALENGTH register 272ed9067fdSUlf Hansson * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 273ed9067fdSUlf Hansson * is asserted (likewise for RX) 274ed9067fdSUlf Hansson * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 275ed9067fdSUlf Hansson * is asserted (likewise for RX) 276ed9067fdSUlf Hansson * @data_cmd_enable: enable value for data commands. 277ed9067fdSUlf Hansson * @st_sdio: enable ST specific SDIO logic 278ed9067fdSUlf Hansson * @st_clkdiv: true if using a ST-specific clock divider algorithm 27900e930d8SLudovic Barre * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm 280ed9067fdSUlf Hansson * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 281ed9067fdSUlf Hansson * @datactrl_mask_sdio: SDIO enable mask in datactrl register 2822253ed4bSLinus Walleij * @datactrl_blocksz: block size in power of two 2832253ed4bSLinus Walleij * @datactrl_any_blocksz: true if block any block sizes are accepted by 2842253ed4bSLinus Walleij * hardware, such as with some SDIO traffic that send 2852253ed4bSLinus Walleij * odd packets. 2862253ed4bSLinus Walleij * @dma_power_of_2: DMA only works with blocks that are a power of 2. 287d2141547SLudovic Barre * @datactrl_first: true if data must be setup before send command 288b79220b3SLudovic Barre * @datacnt_useless: true if you could not use datacnt register to read 289b79220b3SLudovic Barre * remaining data 290ed9067fdSUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 291ed9067fdSUlf Hansson * @f_max: maximum clk frequency supported by the controller. 292ed9067fdSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 293ed9067fdSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 294ed9067fdSUlf Hansson * @busy_detect: true if the variant supports busy detection on DAT0. 2958266c585SLudovic Barre * @busy_timeout: true if the variant starts data timer when the DPSM 2968266c585SLudovic Barre * enter in Wait_R or Busy state. 297ed9067fdSUlf Hansson * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 298ed9067fdSUlf Hansson * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 299ed9067fdSUlf Hansson * indicating that the card is busy 300ed9067fdSUlf Hansson * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 301ed9067fdSUlf Hansson * getting busy end detection interrupts 302ed9067fdSUlf Hansson * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 303ed9067fdSUlf Hansson * @explicit_mclk_control: enable explicit mclk control in driver. 304ed9067fdSUlf Hansson * @qcom_fifo: enables qcom specific fifo pio read logic. 305ed9067fdSUlf Hansson * @qcom_dml: enables qcom specific dma glue for dma transfers. 306ed9067fdSUlf Hansson * @reversed_irq_handling: handle data irq before cmd irq. 307ed9067fdSUlf Hansson * @mmcimask1: true if variant have a MMCIMASK1 register. 30859db5e2dSLudovic Barre * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask 30959db5e2dSLudovic Barre * register 310ed9067fdSUlf Hansson * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS 311ed9067fdSUlf Hansson * register. 312ed9067fdSUlf Hansson * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register 31346b723ddSLudovic Barre * @dma_lli: true if variant has dma link list feature. 31446b723ddSLudovic Barre * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size. 315ed9067fdSUlf Hansson */ 316ed9067fdSUlf Hansson struct variant_data { 317ed9067fdSUlf Hansson unsigned int clkreg; 318ed9067fdSUlf Hansson unsigned int clkreg_enable; 319ed9067fdSUlf Hansson unsigned int clkreg_8bit_bus_enable; 320ed9067fdSUlf Hansson unsigned int clkreg_neg_edge_enable; 3210f244804SLudovic Barre unsigned int cmdreg_cpsm_enable; 3220f244804SLudovic Barre unsigned int cmdreg_lrsp_crc; 3230f244804SLudovic Barre unsigned int cmdreg_srsp_crc; 3240f244804SLudovic Barre unsigned int cmdreg_srsp; 325c8073e52SLudovic Barre unsigned int cmdreg_stop; 326ed9067fdSUlf Hansson unsigned int datalength_bits; 327ed9067fdSUlf Hansson unsigned int fifosize; 328ed9067fdSUlf Hansson unsigned int fifohalfsize; 329ed9067fdSUlf Hansson unsigned int data_cmd_enable; 330ed9067fdSUlf Hansson unsigned int datactrl_mask_ddrmode; 331ed9067fdSUlf Hansson unsigned int datactrl_mask_sdio; 332c931d495SLudovic Barre unsigned int datactrl_blocksz; 3332253ed4bSLinus Walleij u8 datactrl_any_blocksz:1; 3342253ed4bSLinus Walleij u8 dma_power_of_2:1; 335d2141547SLudovic Barre u8 datactrl_first:1; 336b79220b3SLudovic Barre u8 datacnt_useless:1; 33719a25d57SLudovic Barre u8 st_sdio:1; 33819a25d57SLudovic Barre u8 st_clkdiv:1; 33900e930d8SLudovic Barre u8 stm32_clkdiv:1; 340ed9067fdSUlf Hansson u32 pwrreg_powerup; 341ed9067fdSUlf Hansson u32 f_max; 34219a25d57SLudovic Barre u8 signal_direction:1; 34319a25d57SLudovic Barre u8 pwrreg_clkgate:1; 34419a25d57SLudovic Barre u8 busy_detect:1; 3458266c585SLudovic Barre u8 busy_timeout:1; 346ed9067fdSUlf Hansson u32 busy_dpsm_flag; 347ed9067fdSUlf Hansson u32 busy_detect_flag; 348ed9067fdSUlf Hansson u32 busy_detect_mask; 34919a25d57SLudovic Barre u8 pwrreg_nopower:1; 35019a25d57SLudovic Barre u8 explicit_mclk_control:1; 35119a25d57SLudovic Barre u8 qcom_fifo:1; 35219a25d57SLudovic Barre u8 qcom_dml:1; 35319a25d57SLudovic Barre u8 reversed_irq_handling:1; 35419a25d57SLudovic Barre u8 mmcimask1:1; 35559db5e2dSLudovic Barre unsigned int irq_pio_mask; 356ed9067fdSUlf Hansson u32 start_err; 357ed9067fdSUlf Hansson u32 opendrain; 35846b723ddSLudovic Barre u8 dma_lli:1; 35946b723ddSLudovic Barre u32 stm32_idmabsize_mask; 360ed9067fdSUlf Hansson void (*init)(struct mmci_host *host); 361ed9067fdSUlf Hansson }; 362ed9067fdSUlf Hansson 363ed9067fdSUlf Hansson /* mmci variant callbacks */ 364ed9067fdSUlf Hansson struct mmci_host_ops { 365e0da1721SLudovic Barre int (*validate_data)(struct mmci_host *host, struct mmc_data *data); 36647983510SLudovic Barre int (*prep_data)(struct mmci_host *host, struct mmc_data *data, 36747983510SLudovic Barre bool next); 36847983510SLudovic Barre void (*unprep_data)(struct mmci_host *host, struct mmc_data *data, 36947983510SLudovic Barre int err); 3700732ea75SLudovic Barre u32 (*get_datactrl_cfg)(struct mmci_host *host); 37102769968SLudovic Barre void (*get_next_data)(struct mmci_host *host, struct mmc_data *data); 372c3647fdcSLudovic Barre int (*dma_setup)(struct mmci_host *host); 373c3647fdcSLudovic Barre void (*dma_release)(struct mmci_host *host); 374135ea30eSLudovic Barre int (*dma_start)(struct mmci_host *host, unsigned int *datactrl); 3755a9f10c3SLudovic Barre void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data); 376cfccc6acSLudovic Barre void (*dma_error)(struct mmci_host *host); 377cd3ee8c5SLudovic Barre void (*set_clkreg)(struct mmci_host *host, unsigned int desired); 378cd3ee8c5SLudovic Barre void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr); 379cb0335b7SLudovic Barre bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk); 38075773165SLudovic Barre void (*pre_sig_volt_switch)(struct mmci_host *host); 38175773165SLudovic Barre int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios); 382ed9067fdSUlf Hansson }; 3831c6a0718SPierre Ossman 3841c6a0718SPierre Ossman struct mmci_host { 385c8ebae37SRussell King phys_addr_t phybase; 3861c6a0718SPierre Ossman void __iomem *base; 3871c6a0718SPierre Ossman struct mmc_request *mrq; 3881c6a0718SPierre Ossman struct mmc_command *cmd; 389e9968c6fSUlf Hansson struct mmc_command stop_abort; 3901c6a0718SPierre Ossman struct mmc_data *data; 3911c6a0718SPierre Ossman struct mmc_host *mmc; 3921c6a0718SPierre Ossman struct clk *clk; 39319a25d57SLudovic Barre u8 singleirq:1; 3941c6a0718SPierre Ossman 39515878e58SLudovic Barre struct reset_control *rst; 39615878e58SLudovic Barre 3971c6a0718SPierre Ossman spinlock_t lock; 3981c6a0718SPierre Ossman 3991c6a0718SPierre Ossman unsigned int mclk; 4003f4e6f7bSSrinivas Kandagatla /* cached value of requested clk in set_ios */ 4013f4e6f7bSSrinivas Kandagatla unsigned int clock_cache; 4021c6a0718SPierre Ossman unsigned int cclk; 4037437cfa5SUlf Hansson u32 pwr_reg; 4044593df29SUlf Hansson u32 pwr_reg_add; 4057437cfa5SUlf Hansson u32 clk_reg; 40646b723ddSLudovic Barre u32 clk_reg_add; 4079cc639a2SUlf Hansson u32 datactrl_reg; 4088d94b54dSUlf Hansson u32 busy_status; 4096ea9cdf3SPatrice Chotard u32 mask1_reg; 41019a25d57SLudovic Barre u8 vqmmc_enabled:1; 4116ef297f8SLinus Walleij struct mmci_platform_data *plat; 4127b9716a0SLudovic Barre struct mmc_host_ops *mmc_ops; 413ed9067fdSUlf Hansson struct mmci_host_ops *ops; 4144956e109SRabin Vincent struct variant_data *variant; 41531b963e1SLudovic Barre void *variant_priv; 416f9bb304cSPatrice Chotard struct pinctrl *pinctrl; 417f9bb304cSPatrice Chotard struct pinctrl_state *pins_opendrain; 4181c6a0718SPierre Ossman 419cc30d60eSLinus Walleij u8 hw_designer; 420cc30d60eSLinus Walleij u8 hw_revision:4; 421cc30d60eSLinus Walleij 4221c6a0718SPierre Ossman struct timer_list timer; 4231c6a0718SPierre Ossman unsigned int oldstat; 424ee157abeSLudovic Barre u32 irq_action; 4251c6a0718SPierre Ossman 4261c6a0718SPierre Ossman /* pio stuff */ 4274ce1d6cbSRabin Vincent struct sg_mapping_iter sg_miter; 4281c6a0718SPierre Ossman unsigned int size; 4299c34b73dSSrinivas Kandagatla int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain); 430c8ebae37SRussell King 431c3647fdcSLudovic Barre u8 use_dma:1; 43219a25d57SLudovic Barre u8 dma_in_progress:1; 433a813f2a2SLudovic Barre void *dma_priv; 434a813f2a2SLudovic Barre 435a813f2a2SLudovic Barre s32 next_cookie; 436a813f2a2SLudovic Barre }; 437c8ebae37SRussell King 438e13934bdSLinus Walleij #define dma_inprogress(host) ((host)->dma_in_progress) 4391c6a0718SPierre Ossman 440cd3ee8c5SLudovic Barre void mmci_write_clkreg(struct mmci_host *host, u32 clk); 441cd3ee8c5SLudovic Barre void mmci_write_pwrreg(struct mmci_host *host, u32 pwr); 442cd3ee8c5SLudovic Barre 4430732ea75SLudovic Barre static inline u32 mmci_dctrl_blksz(struct mmci_host *host) 4440732ea75SLudovic Barre { 4450732ea75SLudovic Barre return (ffs(host->data->blksz) - 1) << 4; 4460732ea75SLudovic Barre } 4470732ea75SLudovic Barre 4486aa35ce7SUlf Hansson #ifdef CONFIG_DMA_ENGINE 44947983510SLudovic Barre int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 45047983510SLudovic Barre bool next); 45147983510SLudovic Barre void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data, 45247983510SLudovic Barre int err); 45302769968SLudovic Barre void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data); 454c3647fdcSLudovic Barre int mmci_dmae_setup(struct mmci_host *host); 455c3647fdcSLudovic Barre void mmci_dmae_release(struct mmci_host *host); 456135ea30eSLudovic Barre int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl); 4575a9f10c3SLudovic Barre void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data); 458cfccc6acSLudovic Barre void mmci_dmae_error(struct mmci_host *host); 4596aa35ce7SUlf Hansson #endif 460f7f3e7daSUlf Hansson 461f7f3e7daSUlf Hansson #ifdef CONFIG_MMC_QCOM_DML 462f7f3e7daSUlf Hansson void qcom_variant_init(struct mmci_host *host); 463f7f3e7daSUlf Hansson #else 464f7f3e7daSUlf Hansson static inline void qcom_variant_init(struct mmci_host *host) {} 465f7f3e7daSUlf Hansson #endif 46662e546beSUlf Hansson 46762e546beSUlf Hansson #ifdef CONFIG_MMC_STM32_SDMMC 46862e546beSUlf Hansson void sdmmc_variant_init(struct mmci_host *host); 46962e546beSUlf Hansson #else 47062e546beSUlf Hansson static inline void sdmmc_variant_init(struct mmci_host *host) {} 47162e546beSUlf Hansson #endif 472