11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #define MMCIPOWER 0x000 111c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 121c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 131c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 141c6a0718SPierre Ossman #define MCI_OD (1 << 6) 151c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 164593df29SUlf Hansson /* 174593df29SUlf Hansson * The ST Micro version does not have ROD and reuse the voltage registers for 184593df29SUlf Hansson * direction settings. 194593df29SUlf Hansson */ 204593df29SUlf Hansson #define MCI_ST_DATA2DIREN (1 << 2) 214593df29SUlf Hansson #define MCI_ST_CMDDIREN (1 << 3) 224593df29SUlf Hansson #define MCI_ST_DATA0DIREN (1 << 4) 234593df29SUlf Hansson #define MCI_ST_DATA31DIREN (1 << 5) 244593df29SUlf Hansson #define MCI_ST_FBCLKEN (1 << 7) 254593df29SUlf Hansson #define MCI_ST_DATA74DIREN (1 << 8) 261c6a0718SPierre Ossman 271c6a0718SPierre Ossman #define MMCICLOCK 0x004 281c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 291c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 301c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 31771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 3249ac215eSLinus Walleij /* 3349ac215eSLinus Walleij * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 3449ac215eSLinus Walleij * supported in ST Micro U300 and Ux500 versions 3549ac215eSLinus Walleij */ 36771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 3749ac215eSLinus Walleij #define MCI_ST_U300_HWFCEN (1 << 13) 3849ac215eSLinus Walleij #define MCI_ST_UX500_NEG_EDGE (1 << 13) 3949ac215eSLinus Walleij #define MCI_ST_UX500_HWFCEN (1 << 14) 4049ac215eSLinus Walleij #define MCI_ST_UX500_CLK_INV (1 << 15) 413a37298aSPawel Moll /* Modified PL180 on Versatile Express platform */ 423a37298aSPawel Moll #define MCI_ARM_HWFCEN (1 << 12) 431c6a0718SPierre Ossman 441c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 451c6a0718SPierre Ossman #define MMCICOMMAND 0x00c 461c6a0718SPierre Ossman #define MCI_CPSM_RESPONSE (1 << 6) 471c6a0718SPierre Ossman #define MCI_CPSM_LONGRSP (1 << 7) 481c6a0718SPierre Ossman #define MCI_CPSM_INTERRUPT (1 << 8) 491c6a0718SPierre Ossman #define MCI_CPSM_PENDING (1 << 9) 501c6a0718SPierre Ossman #define MCI_CPSM_ENABLE (1 << 10) 51dfdf5f63SLinus Walleij /* Argument flag extenstions in the ST Micro versions */ 52dfdf5f63SLinus Walleij #define MCI_ST_SDIO_SUSP (1 << 11) 53dfdf5f63SLinus Walleij #define MCI_ST_ENCMD_COMPL (1 << 12) 54dfdf5f63SLinus Walleij #define MCI_ST_NIEN (1 << 13) 55dfdf5f63SLinus Walleij #define MCI_ST_CE_ATACMD (1 << 14) 561c6a0718SPierre Ossman 571c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 581c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 591c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 601c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 611c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 621c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 631c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 641c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 651c6a0718SPierre Ossman #define MCI_DPSM_ENABLE (1 << 0) 661c6a0718SPierre Ossman #define MCI_DPSM_DIRECTION (1 << 1) 671c6a0718SPierre Ossman #define MCI_DPSM_MODE (1 << 2) 681c6a0718SPierre Ossman #define MCI_DPSM_DMAENABLE (1 << 3) 69cc30d60eSLinus Walleij #define MCI_DPSM_BLOCKSIZE (1 << 4) 70725343faSLinus Walleij /* Control register extensions in the ST Micro U300 and Ux500 versions */ 71725343faSLinus Walleij #define MCI_ST_DPSM_RWSTART (1 << 8) 72725343faSLinus Walleij #define MCI_ST_DPSM_RWSTOP (1 << 9) 73725343faSLinus Walleij #define MCI_ST_DPSM_RWMOD (1 << 10) 74725343faSLinus Walleij #define MCI_ST_DPSM_SDIOEN (1 << 11) 75725343faSLinus Walleij /* Control register extensions in the ST Micro Ux500 versions */ 76725343faSLinus Walleij #define MCI_ST_DPSM_DMAREQCTL (1 << 12) 77725343faSLinus Walleij #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) 78725343faSLinus Walleij #define MCI_ST_DPSM_BUSYMODE (1 << 14) 79725343faSLinus Walleij #define MCI_ST_DPSM_DDRMODE (1 << 15) 801c6a0718SPierre Ossman 811c6a0718SPierre Ossman #define MMCIDATACNT 0x030 821c6a0718SPierre Ossman #define MMCISTATUS 0x034 831c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 841c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 851c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 861c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 871c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 881c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 891c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 901c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 911c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 92757df746SLinus Walleij #define MCI_STARTBITERR (1 << 9) 931c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 941c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 951c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 961c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 971c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 981c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 991c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 1001c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 1011c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 1021c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 1031c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 1041c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 10549ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 10649ac215eSLinus Walleij #define MCI_ST_SDIOIT (1 << 22) 10749ac215eSLinus Walleij #define MCI_ST_CEATAEND (1 << 23) 10801259620SUlf Hansson #define MCI_ST_CARDBUSY (1 << 24) 1091c6a0718SPierre Ossman 1101c6a0718SPierre Ossman #define MMCICLEAR 0x038 1111c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 1121c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 1131c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 1141c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 1151c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 1161c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 1171c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 1181c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 1191c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 120757df746SLinus Walleij #define MCI_STARTBITERRCLR (1 << 9) 1211c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 12249ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 12349ac215eSLinus Walleij #define MCI_ST_SDIOITC (1 << 22) 12449ac215eSLinus Walleij #define MCI_ST_CEATAENDC (1 << 23) 12501259620SUlf Hansson #define MCI_ST_BUSYENDC (1 << 24) 1261c6a0718SPierre Ossman 1271c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1281c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1291c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1301c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1311c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1321c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1331c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1341c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1351c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1361c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 137757df746SLinus Walleij #define MCI_STARTBITERRMASK (1 << 9) 1381c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1391c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1401c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 1411c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 1421c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 1431c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 1441c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 1451c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 1461c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 1471c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 1481c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 1491c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 15049ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 15149ac215eSLinus Walleij #define MCI_ST_SDIOITMASK (1 << 22) 15249ac215eSLinus Walleij #define MCI_ST_CEATAENDMASK (1 << 23) 1538d94b54dSUlf Hansson #define MCI_ST_BUSYEND (1 << 24) 1541c6a0718SPierre Ossman 1551c6a0718SPierre Ossman #define MMCIMASK1 0x040 1561c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 1571c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 1581c6a0718SPierre Ossman 1591c6a0718SPierre Ossman #define MCI_IRQENABLE \ 1601c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ 1611c6a0718SPierre Ossman MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ 162757df746SLinus Walleij MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) 1631c6a0718SPierre Ossman 1642686b4b4SLinus Walleij /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 1652686b4b4SLinus Walleij #define MCI_IRQ1MASK \ 1662686b4b4SLinus Walleij (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 1672686b4b4SLinus Walleij MCI_TXFIFOHALFEMPTYMASK) 1682686b4b4SLinus Walleij 169859dd55dSUlf Hansson #define NR_SG 128 1701c6a0718SPierre Ossman 1711c6a0718SPierre Ossman struct clk; 1724956e109SRabin Vincent struct variant_data; 173c8ebae37SRussell King struct dma_chan; 1741c6a0718SPierre Ossman 17558c7ccbfSPer Forlin struct mmci_host_next { 17658c7ccbfSPer Forlin struct dma_async_tx_descriptor *dma_desc; 17758c7ccbfSPer Forlin struct dma_chan *dma_chan; 17858c7ccbfSPer Forlin s32 cookie; 17958c7ccbfSPer Forlin }; 18058c7ccbfSPer Forlin 1811c6a0718SPierre Ossman struct mmci_host { 182c8ebae37SRussell King phys_addr_t phybase; 1831c6a0718SPierre Ossman void __iomem *base; 1841c6a0718SPierre Ossman struct mmc_request *mrq; 1851c6a0718SPierre Ossman struct mmc_command *cmd; 1861c6a0718SPierre Ossman struct mmc_data *data; 1871c6a0718SPierre Ossman struct mmc_host *mmc; 1881c6a0718SPierre Ossman struct clk *clk; 1892686b4b4SLinus Walleij bool singleirq; 1901c6a0718SPierre Ossman 1911c6a0718SPierre Ossman spinlock_t lock; 1921c6a0718SPierre Ossman 1931c6a0718SPierre Ossman unsigned int mclk; 1941c6a0718SPierre Ossman unsigned int cclk; 1957437cfa5SUlf Hansson u32 pwr_reg; 1964593df29SUlf Hansson u32 pwr_reg_add; 1977437cfa5SUlf Hansson u32 clk_reg; 1989cc639a2SUlf Hansson u32 datactrl_reg; 1998d94b54dSUlf Hansson u32 busy_status; 2007c0136efSUlf Hansson bool vqmmc_enabled; 2016ef297f8SLinus Walleij struct mmci_platform_data *plat; 2024956e109SRabin Vincent struct variant_data *variant; 2031c6a0718SPierre Ossman 204cc30d60eSLinus Walleij u8 hw_designer; 205cc30d60eSLinus Walleij u8 hw_revision:4; 206cc30d60eSLinus Walleij 2071c6a0718SPierre Ossman struct timer_list timer; 2081c6a0718SPierre Ossman unsigned int oldstat; 2091c6a0718SPierre Ossman 2101c6a0718SPierre Ossman /* pio stuff */ 2114ce1d6cbSRabin Vincent struct sg_mapping_iter sg_miter; 2121c6a0718SPierre Ossman unsigned int size; 213c8ebae37SRussell King 214c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 215c8ebae37SRussell King /* DMA stuff */ 216c8ebae37SRussell King struct dma_chan *dma_current; 217c8ebae37SRussell King struct dma_chan *dma_rx_channel; 218c8ebae37SRussell King struct dma_chan *dma_tx_channel; 21958c7ccbfSPer Forlin struct dma_async_tx_descriptor *dma_desc_current; 22058c7ccbfSPer Forlin struct mmci_host_next next_data; 221c8ebae37SRussell King 222c8ebae37SRussell King #define dma_inprogress(host) ((host)->dma_current) 223c8ebae37SRussell King #else 224c8ebae37SRussell King #define dma_inprogress(host) (0) 225c8ebae37SRussell King #endif 2261c6a0718SPierre Ossman }; 2271c6a0718SPierre Ossman 228