11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 51c6a0718SPierre Ossman * 61c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 71c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 81c6a0718SPierre Ossman * published by the Free Software Foundation. 91c6a0718SPierre Ossman */ 101c6a0718SPierre Ossman #define MMCIPOWER 0x000 111c6a0718SPierre Ossman #define MCI_PWR_OFF 0x00 121c6a0718SPierre Ossman #define MCI_PWR_UP 0x02 131c6a0718SPierre Ossman #define MCI_PWR_ON 0x03 141c6a0718SPierre Ossman #define MCI_OD (1 << 6) 151c6a0718SPierre Ossman #define MCI_ROD (1 << 7) 164593df29SUlf Hansson /* 174593df29SUlf Hansson * The ST Micro version does not have ROD and reuse the voltage registers for 184593df29SUlf Hansson * direction settings. 194593df29SUlf Hansson */ 204593df29SUlf Hansson #define MCI_ST_DATA2DIREN (1 << 2) 214593df29SUlf Hansson #define MCI_ST_CMDDIREN (1 << 3) 224593df29SUlf Hansson #define MCI_ST_DATA0DIREN (1 << 4) 234593df29SUlf Hansson #define MCI_ST_DATA31DIREN (1 << 5) 244593df29SUlf Hansson #define MCI_ST_FBCLKEN (1 << 7) 254593df29SUlf Hansson #define MCI_ST_DATA74DIREN (1 << 8) 26f3f64334SLudovic Barre /* 27f3f64334SLudovic Barre * The STM32 sdmmc does not have PWR_UP/OD/ROD 28f3f64334SLudovic Barre * and uses the power register for 29f3f64334SLudovic Barre */ 30f3f64334SLudovic Barre #define MCI_STM32_PWR_CYC 0x02 31f3f64334SLudovic Barre #define MCI_STM32_VSWITCH BIT(2) 32f3f64334SLudovic Barre #define MCI_STM32_VSWITCHEN BIT(3) 33f3f64334SLudovic Barre #define MCI_STM32_DIRPOL BIT(4) 341c6a0718SPierre Ossman 351c6a0718SPierre Ossman #define MMCICLOCK 0x004 361c6a0718SPierre Ossman #define MCI_CLK_ENABLE (1 << 8) 371c6a0718SPierre Ossman #define MCI_CLK_PWRSAVE (1 << 9) 381c6a0718SPierre Ossman #define MCI_CLK_BYPASS (1 << 10) 39771dc157SLinus Walleij #define MCI_4BIT_BUS (1 << 11) 4049ac215eSLinus Walleij /* 4149ac215eSLinus Walleij * 8bit wide buses, hardware flow contronl, negative edges and clock inversion 4249ac215eSLinus Walleij * supported in ST Micro U300 and Ux500 versions 4349ac215eSLinus Walleij */ 44771dc157SLinus Walleij #define MCI_ST_8BIT_BUS (1 << 12) 4549ac215eSLinus Walleij #define MCI_ST_U300_HWFCEN (1 << 13) 4649ac215eSLinus Walleij #define MCI_ST_UX500_NEG_EDGE (1 << 13) 4749ac215eSLinus Walleij #define MCI_ST_UX500_HWFCEN (1 << 14) 4849ac215eSLinus Walleij #define MCI_ST_UX500_CLK_INV (1 << 15) 493a37298aSPawel Moll /* Modified PL180 on Versatile Express platform */ 503a37298aSPawel Moll #define MCI_ARM_HWFCEN (1 << 12) 511c6a0718SPierre Ossman 529681a4e8SSrinivas Kandagatla /* Modified on Qualcomm Integrations */ 539681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) 549681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_FLOWENA BIT(12) 559681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_INVERTOUT BIT(13) 569681a4e8SSrinivas Kandagatla 579681a4e8SSrinivas Kandagatla /* select in latch data and command in */ 589681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_SELECT_IN_FBCLK BIT(15) 599681a4e8SSrinivas Kandagatla #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15)) 609681a4e8SSrinivas Kandagatla 61f3f64334SLudovic Barre /* Modified on STM32 sdmmc */ 62f3f64334SLudovic Barre #define MCI_STM32_CLK_CLKDIV_MSK GENMASK(9, 0) 63f3f64334SLudovic Barre #define MCI_STM32_CLK_WIDEBUS_4 BIT(14) 64f3f64334SLudovic Barre #define MCI_STM32_CLK_WIDEBUS_8 BIT(15) 65f3f64334SLudovic Barre #define MCI_STM32_CLK_NEGEDGE BIT(16) 66f3f64334SLudovic Barre #define MCI_STM32_CLK_HWFCEN BIT(17) 67f3f64334SLudovic Barre #define MCI_STM32_CLK_DDR BIT(18) 68f3f64334SLudovic Barre #define MCI_STM32_CLK_BUSSPEED BIT(19) 69f3f64334SLudovic Barre #define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20) 70f3f64334SLudovic Barre #define MCI_STM32_CLK_SELCK (0 << 20) 71f3f64334SLudovic Barre #define MCI_STM32_CLK_SELCKIN (1 << 20) 72f3f64334SLudovic Barre #define MCI_STM32_CLK_SELFBCK (2 << 20) 73f3f64334SLudovic Barre 741c6a0718SPierre Ossman #define MMCIARGUMENT 0x008 751c6a0718SPierre Ossman 765db3eee7SLinus Walleij /* The command register controls the Command Path State Machine (CPSM) */ 775db3eee7SLinus Walleij #define MMCICOMMAND 0x00c 785db3eee7SLinus Walleij #define MCI_CPSM_RESPONSE BIT(6) 795db3eee7SLinus Walleij #define MCI_CPSM_LONGRSP BIT(7) 805db3eee7SLinus Walleij #define MCI_CPSM_INTERRUPT BIT(8) 815db3eee7SLinus Walleij #define MCI_CPSM_PENDING BIT(9) 825db3eee7SLinus Walleij #define MCI_CPSM_ENABLE BIT(10) 835db3eee7SLinus Walleij /* Command register flag extenstions in the ST Micro versions */ 845db3eee7SLinus Walleij #define MCI_CPSM_ST_SDIO_SUSP BIT(11) 855db3eee7SLinus Walleij #define MCI_CPSM_ST_ENCMD_COMPL BIT(12) 865db3eee7SLinus Walleij #define MCI_CPSM_ST_NIEN BIT(13) 875db3eee7SLinus Walleij #define MCI_CPSM_ST_CE_ATACMD BIT(14) 885db3eee7SLinus Walleij /* Command register flag extensions in the Qualcomm versions */ 895db3eee7SLinus Walleij #define MCI_CPSM_QCOM_PROGENA BIT(11) 905db3eee7SLinus Walleij #define MCI_CPSM_QCOM_DATCMD BIT(12) 915db3eee7SLinus Walleij #define MCI_CPSM_QCOM_MCIABORT BIT(13) 925db3eee7SLinus Walleij #define MCI_CPSM_QCOM_CCSENABLE BIT(14) 935db3eee7SLinus Walleij #define MCI_CPSM_QCOM_CCSDISABLE BIT(15) 945db3eee7SLinus Walleij #define MCI_CPSM_QCOM_AUTO_CMD19 BIT(16) 955db3eee7SLinus Walleij #define MCI_CPSM_QCOM_AUTO_CMD21 BIT(21) 96f3f64334SLudovic Barre /* Command register in STM32 sdmmc versions */ 97f3f64334SLudovic Barre #define MCI_CPSM_STM32_CMDTRANS BIT(6) 98f3f64334SLudovic Barre #define MCI_CPSM_STM32_CMDSTOP BIT(7) 99f3f64334SLudovic Barre #define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8) 100f3f64334SLudovic Barre #define MCI_CPSM_STM32_NORSP (0 << 8) 101f3f64334SLudovic Barre #define MCI_CPSM_STM32_SRSP_CRC (1 << 8) 102f3f64334SLudovic Barre #define MCI_CPSM_STM32_SRSP (2 << 8) 103f3f64334SLudovic Barre #define MCI_CPSM_STM32_LRSP_CRC (3 << 8) 104f3f64334SLudovic Barre #define MCI_CPSM_STM32_ENABLE BIT(12) 1059681a4e8SSrinivas Kandagatla 1061c6a0718SPierre Ossman #define MMCIRESPCMD 0x010 1071c6a0718SPierre Ossman #define MMCIRESPONSE0 0x014 1081c6a0718SPierre Ossman #define MMCIRESPONSE1 0x018 1091c6a0718SPierre Ossman #define MMCIRESPONSE2 0x01c 1101c6a0718SPierre Ossman #define MMCIRESPONSE3 0x020 1111c6a0718SPierre Ossman #define MMCIDATATIMER 0x024 1121c6a0718SPierre Ossman #define MMCIDATALENGTH 0x028 1135db3eee7SLinus Walleij 1145db3eee7SLinus Walleij /* The data control register controls the Data Path State Machine (DPSM) */ 1151c6a0718SPierre Ossman #define MMCIDATACTRL 0x02c 1165db3eee7SLinus Walleij #define MCI_DPSM_ENABLE BIT(0) 1175db3eee7SLinus Walleij #define MCI_DPSM_DIRECTION BIT(1) 1185db3eee7SLinus Walleij #define MCI_DPSM_MODE BIT(2) 1195db3eee7SLinus Walleij #define MCI_DPSM_DMAENABLE BIT(3) 1205db3eee7SLinus Walleij #define MCI_DPSM_BLOCKSIZE BIT(4) 121725343faSLinus Walleij /* Control register extensions in the ST Micro U300 and Ux500 versions */ 1225db3eee7SLinus Walleij #define MCI_DPSM_ST_RWSTART BIT(8) 1235db3eee7SLinus Walleij #define MCI_DPSM_ST_RWSTOP BIT(9) 1245db3eee7SLinus Walleij #define MCI_DPSM_ST_RWMOD BIT(10) 1255db3eee7SLinus Walleij #define MCI_DPSM_ST_SDIOEN BIT(11) 126725343faSLinus Walleij /* Control register extensions in the ST Micro Ux500 versions */ 1275db3eee7SLinus Walleij #define MCI_DPSM_ST_DMAREQCTL BIT(12) 1285db3eee7SLinus Walleij #define MCI_DPSM_ST_DBOOTMODEEN BIT(13) 1295db3eee7SLinus Walleij #define MCI_DPSM_ST_BUSYMODE BIT(14) 1305db3eee7SLinus Walleij #define MCI_DPSM_ST_DDRMODE BIT(15) 1315db3eee7SLinus Walleij /* Control register extensions in the Qualcomm versions */ 1325db3eee7SLinus Walleij #define MCI_DPSM_QCOM_DATA_PEND BIT(17) 1335db3eee7SLinus Walleij #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) 1341c6a0718SPierre Ossman 1351c6a0718SPierre Ossman #define MMCIDATACNT 0x030 1361c6a0718SPierre Ossman #define MMCISTATUS 0x034 1371c6a0718SPierre Ossman #define MCI_CMDCRCFAIL (1 << 0) 1381c6a0718SPierre Ossman #define MCI_DATACRCFAIL (1 << 1) 1391c6a0718SPierre Ossman #define MCI_CMDTIMEOUT (1 << 2) 1401c6a0718SPierre Ossman #define MCI_DATATIMEOUT (1 << 3) 1411c6a0718SPierre Ossman #define MCI_TXUNDERRUN (1 << 4) 1421c6a0718SPierre Ossman #define MCI_RXOVERRUN (1 << 5) 1431c6a0718SPierre Ossman #define MCI_CMDRESPEND (1 << 6) 1441c6a0718SPierre Ossman #define MCI_CMDSENT (1 << 7) 1451c6a0718SPierre Ossman #define MCI_DATAEND (1 << 8) 146757df746SLinus Walleij #define MCI_STARTBITERR (1 << 9) 1471c6a0718SPierre Ossman #define MCI_DATABLOCKEND (1 << 10) 1481c6a0718SPierre Ossman #define MCI_CMDACTIVE (1 << 11) 1491c6a0718SPierre Ossman #define MCI_TXACTIVE (1 << 12) 1501c6a0718SPierre Ossman #define MCI_RXACTIVE (1 << 13) 1511c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTY (1 << 14) 1521c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULL (1 << 15) 1531c6a0718SPierre Ossman #define MCI_TXFIFOFULL (1 << 16) 1541c6a0718SPierre Ossman #define MCI_RXFIFOFULL (1 << 17) 1551c6a0718SPierre Ossman #define MCI_TXFIFOEMPTY (1 << 18) 1561c6a0718SPierre Ossman #define MCI_RXFIFOEMPTY (1 << 19) 1571c6a0718SPierre Ossman #define MCI_TXDATAAVLBL (1 << 20) 1581c6a0718SPierre Ossman #define MCI_RXDATAAVLBL (1 << 21) 15949ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 16049ac215eSLinus Walleij #define MCI_ST_SDIOIT (1 << 22) 16149ac215eSLinus Walleij #define MCI_ST_CEATAEND (1 << 23) 16201259620SUlf Hansson #define MCI_ST_CARDBUSY (1 << 24) 163f3f64334SLudovic Barre /* Extended status bits for the STM32 variants */ 164f3f64334SLudovic Barre #define MCI_STM32_BUSYD0 BIT(20) 1651c6a0718SPierre Ossman 1661c6a0718SPierre Ossman #define MMCICLEAR 0x038 1671c6a0718SPierre Ossman #define MCI_CMDCRCFAILCLR (1 << 0) 1681c6a0718SPierre Ossman #define MCI_DATACRCFAILCLR (1 << 1) 1691c6a0718SPierre Ossman #define MCI_CMDTIMEOUTCLR (1 << 2) 1701c6a0718SPierre Ossman #define MCI_DATATIMEOUTCLR (1 << 3) 1711c6a0718SPierre Ossman #define MCI_TXUNDERRUNCLR (1 << 4) 1721c6a0718SPierre Ossman #define MCI_RXOVERRUNCLR (1 << 5) 1731c6a0718SPierre Ossman #define MCI_CMDRESPENDCLR (1 << 6) 1741c6a0718SPierre Ossman #define MCI_CMDSENTCLR (1 << 7) 1751c6a0718SPierre Ossman #define MCI_DATAENDCLR (1 << 8) 176757df746SLinus Walleij #define MCI_STARTBITERRCLR (1 << 9) 1771c6a0718SPierre Ossman #define MCI_DATABLOCKENDCLR (1 << 10) 17849ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 17949ac215eSLinus Walleij #define MCI_ST_SDIOITC (1 << 22) 18049ac215eSLinus Walleij #define MCI_ST_CEATAENDC (1 << 23) 18101259620SUlf Hansson #define MCI_ST_BUSYENDC (1 << 24) 1821c6a0718SPierre Ossman 1831c6a0718SPierre Ossman #define MMCIMASK0 0x03c 1841c6a0718SPierre Ossman #define MCI_CMDCRCFAILMASK (1 << 0) 1851c6a0718SPierre Ossman #define MCI_DATACRCFAILMASK (1 << 1) 1861c6a0718SPierre Ossman #define MCI_CMDTIMEOUTMASK (1 << 2) 1871c6a0718SPierre Ossman #define MCI_DATATIMEOUTMASK (1 << 3) 1881c6a0718SPierre Ossman #define MCI_TXUNDERRUNMASK (1 << 4) 1891c6a0718SPierre Ossman #define MCI_RXOVERRUNMASK (1 << 5) 1901c6a0718SPierre Ossman #define MCI_CMDRESPENDMASK (1 << 6) 1911c6a0718SPierre Ossman #define MCI_CMDSENTMASK (1 << 7) 1921c6a0718SPierre Ossman #define MCI_DATAENDMASK (1 << 8) 193757df746SLinus Walleij #define MCI_STARTBITERRMASK (1 << 9) 1941c6a0718SPierre Ossman #define MCI_DATABLOCKENDMASK (1 << 10) 1951c6a0718SPierre Ossman #define MCI_CMDACTIVEMASK (1 << 11) 1961c6a0718SPierre Ossman #define MCI_TXACTIVEMASK (1 << 12) 1971c6a0718SPierre Ossman #define MCI_RXACTIVEMASK (1 << 13) 1981c6a0718SPierre Ossman #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) 1991c6a0718SPierre Ossman #define MCI_RXFIFOHALFFULLMASK (1 << 15) 2001c6a0718SPierre Ossman #define MCI_TXFIFOFULLMASK (1 << 16) 2011c6a0718SPierre Ossman #define MCI_RXFIFOFULLMASK (1 << 17) 2021c6a0718SPierre Ossman #define MCI_TXFIFOEMPTYMASK (1 << 18) 2031c6a0718SPierre Ossman #define MCI_RXFIFOEMPTYMASK (1 << 19) 2041c6a0718SPierre Ossman #define MCI_TXDATAAVLBLMASK (1 << 20) 2051c6a0718SPierre Ossman #define MCI_RXDATAAVLBLMASK (1 << 21) 20649ac215eSLinus Walleij /* Extended status bits for the ST Micro variants */ 20749ac215eSLinus Walleij #define MCI_ST_SDIOITMASK (1 << 22) 20849ac215eSLinus Walleij #define MCI_ST_CEATAENDMASK (1 << 23) 20949adc0caSLinus Walleij #define MCI_ST_BUSYENDMASK (1 << 24) 210f3f64334SLudovic Barre /* Extended status bits for the STM32 variants */ 211f3f64334SLudovic Barre #define MCI_STM32_BUSYD0ENDMASK BIT(21) 2121c6a0718SPierre Ossman 2131c6a0718SPierre Ossman #define MMCIMASK1 0x040 2141c6a0718SPierre Ossman #define MMCIFIFOCNT 0x048 2151c6a0718SPierre Ossman #define MMCIFIFO 0x080 /* to 0x0bc */ 2161c6a0718SPierre Ossman 217f3f64334SLudovic Barre /* STM32 sdmmc registers for IDMA (Internal DMA) */ 218f3f64334SLudovic Barre #define MMCI_STM32_IDMACTRLR 0x050 219f3f64334SLudovic Barre #define MMCI_STM32_IDMAEN BIT(0) 220f3f64334SLudovic Barre #define MMCI_STM32_IDMALLIEN BIT(1) 221f3f64334SLudovic Barre 222f3f64334SLudovic Barre #define MMCI_STM32_IDMABSIZER 0x054 223f3f64334SLudovic Barre #define MMCI_STM32_IDMABNDT_SHIFT 5 224f3f64334SLudovic Barre #define MMCI_STM32_IDMABNDT_MASK GENMASK(12, 5) 225f3f64334SLudovic Barre 226f3f64334SLudovic Barre #define MMCI_STM32_IDMABASE0R 0x058 227f3f64334SLudovic Barre 228f3f64334SLudovic Barre #define MMCI_STM32_IDMALAR 0x64 229f3f64334SLudovic Barre #define MMCI_STM32_IDMALA_MASK GENMASK(13, 0) 230f3f64334SLudovic Barre #define MMCI_STM32_ABR BIT(29) 231f3f64334SLudovic Barre #define MMCI_STM32_ULS BIT(30) 232f3f64334SLudovic Barre #define MMCI_STM32_ULA BIT(31) 233f3f64334SLudovic Barre 234f3f64334SLudovic Barre #define MMCI_STM32_IDMABAR 0x68 235f3f64334SLudovic Barre 2361c6a0718SPierre Ossman #define MCI_IRQENABLE \ 2371c6a0718SPierre Ossman (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \ 2381c6a0718SPierre Ossman MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK | \ 239daf9713cSLudovic Barre MCI_CMDRESPENDMASK | MCI_CMDSENTMASK) 2401c6a0718SPierre Ossman 2412686b4b4SLinus Walleij /* These interrupts are directed to IRQ1 when two IRQ lines are available */ 24259db5e2dSLudovic Barre #define MCI_IRQ_PIO_MASK \ 2432686b4b4SLinus Walleij (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ 2442686b4b4SLinus Walleij MCI_TXFIFOHALFEMPTYMASK) 2452686b4b4SLinus Walleij 246f3f64334SLudovic Barre #define MCI_IRQ_PIO_STM32_MASK \ 247f3f64334SLudovic Barre (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK) 248f3f64334SLudovic Barre 249859dd55dSUlf Hansson #define NR_SG 128 2501c6a0718SPierre Ossman 251f9bb304cSPatrice Chotard #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain" 252f9bb304cSPatrice Chotard 2531c6a0718SPierre Ossman struct clk; 254c8ebae37SRussell King struct dma_chan; 255ed9067fdSUlf Hansson struct mmci_host; 256ed9067fdSUlf Hansson 257ed9067fdSUlf Hansson /** 258ed9067fdSUlf Hansson * struct variant_data - MMCI variant-specific quirks 259ed9067fdSUlf Hansson * @clkreg: default value for MCICLOCK register 260ed9067fdSUlf Hansson * @clkreg_enable: enable value for MMCICLOCK register 261ed9067fdSUlf Hansson * @clkreg_8bit_bus_enable: enable value for 8 bit bus 262ed9067fdSUlf Hansson * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 2630f244804SLudovic Barre * @cmdreg_cpsm_enable: enable value for CPSM 2640f244804SLudovic Barre * @cmdreg_lrsp_crc: enable value for long response with crc 2650f244804SLudovic Barre * @cmdreg_srsp_crc: enable value for short response with crc 2660f244804SLudovic Barre * @cmdreg_srsp: enable value for short response without crc 267c8073e52SLudovic Barre * @cmdreg_stop: enable value for stop and abort transmission 268ed9067fdSUlf Hansson * @datalength_bits: number of bits in the MMCIDATALENGTH register 269ed9067fdSUlf Hansson * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 270ed9067fdSUlf Hansson * is asserted (likewise for RX) 271ed9067fdSUlf Hansson * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 272ed9067fdSUlf Hansson * is asserted (likewise for RX) 273ed9067fdSUlf Hansson * @data_cmd_enable: enable value for data commands. 274ed9067fdSUlf Hansson * @st_sdio: enable ST specific SDIO logic 275ed9067fdSUlf Hansson * @st_clkdiv: true if using a ST-specific clock divider algorithm 27600e930d8SLudovic Barre * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm 277ed9067fdSUlf Hansson * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 278ed9067fdSUlf Hansson * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 279ed9067fdSUlf Hansson * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 280ed9067fdSUlf Hansson * register 281ed9067fdSUlf Hansson * @datactrl_mask_sdio: SDIO enable mask in datactrl register 282c931d495SLudovic Barre * @datactrl_blksz: block size in power of two 2839b279941SLudovic Barre * @datactrl_dpsm_enable: enable value for DPSM 284d2141547SLudovic Barre * @datactrl_first: true if data must be setup before send command 285b79220b3SLudovic Barre * @datacnt_useless: true if you could not use datacnt register to read 286b79220b3SLudovic Barre * remaining data 287ed9067fdSUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 288ed9067fdSUlf Hansson * @f_max: maximum clk frequency supported by the controller. 289ed9067fdSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 290ed9067fdSUlf Hansson * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 291ed9067fdSUlf Hansson * @busy_detect: true if the variant supports busy detection on DAT0. 292ed9067fdSUlf Hansson * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 293ed9067fdSUlf Hansson * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 294ed9067fdSUlf Hansson * indicating that the card is busy 295ed9067fdSUlf Hansson * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 296ed9067fdSUlf Hansson * getting busy end detection interrupts 297ed9067fdSUlf Hansson * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 298ed9067fdSUlf Hansson * @explicit_mclk_control: enable explicit mclk control in driver. 299ed9067fdSUlf Hansson * @qcom_fifo: enables qcom specific fifo pio read logic. 300ed9067fdSUlf Hansson * @qcom_dml: enables qcom specific dma glue for dma transfers. 301ed9067fdSUlf Hansson * @reversed_irq_handling: handle data irq before cmd irq. 302ed9067fdSUlf Hansson * @mmcimask1: true if variant have a MMCIMASK1 register. 30359db5e2dSLudovic Barre * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask 30459db5e2dSLudovic Barre * register 305ed9067fdSUlf Hansson * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS 306ed9067fdSUlf Hansson * register. 307ed9067fdSUlf Hansson * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register 30846b723ddSLudovic Barre * @dma_lli: true if variant has dma link list feature. 30946b723ddSLudovic Barre * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size. 310ed9067fdSUlf Hansson */ 311ed9067fdSUlf Hansson struct variant_data { 312ed9067fdSUlf Hansson unsigned int clkreg; 313ed9067fdSUlf Hansson unsigned int clkreg_enable; 314ed9067fdSUlf Hansson unsigned int clkreg_8bit_bus_enable; 315ed9067fdSUlf Hansson unsigned int clkreg_neg_edge_enable; 3160f244804SLudovic Barre unsigned int cmdreg_cpsm_enable; 3170f244804SLudovic Barre unsigned int cmdreg_lrsp_crc; 3180f244804SLudovic Barre unsigned int cmdreg_srsp_crc; 3190f244804SLudovic Barre unsigned int cmdreg_srsp; 320c8073e52SLudovic Barre unsigned int cmdreg_stop; 321ed9067fdSUlf Hansson unsigned int datalength_bits; 322ed9067fdSUlf Hansson unsigned int fifosize; 323ed9067fdSUlf Hansson unsigned int fifohalfsize; 324ed9067fdSUlf Hansson unsigned int data_cmd_enable; 325ed9067fdSUlf Hansson unsigned int datactrl_mask_ddrmode; 326ed9067fdSUlf Hansson unsigned int datactrl_mask_sdio; 327c931d495SLudovic Barre unsigned int datactrl_blocksz; 3289b279941SLudovic Barre unsigned int datactrl_dpsm_enable; 329d2141547SLudovic Barre u8 datactrl_first:1; 330b79220b3SLudovic Barre u8 datacnt_useless:1; 33119a25d57SLudovic Barre u8 st_sdio:1; 33219a25d57SLudovic Barre u8 st_clkdiv:1; 33300e930d8SLudovic Barre u8 stm32_clkdiv:1; 33419a25d57SLudovic Barre u8 blksz_datactrl16:1; 33519a25d57SLudovic Barre u8 blksz_datactrl4:1; 336ed9067fdSUlf Hansson u32 pwrreg_powerup; 337ed9067fdSUlf Hansson u32 f_max; 33819a25d57SLudovic Barre u8 signal_direction:1; 33919a25d57SLudovic Barre u8 pwrreg_clkgate:1; 34019a25d57SLudovic Barre u8 busy_detect:1; 341ed9067fdSUlf Hansson u32 busy_dpsm_flag; 342ed9067fdSUlf Hansson u32 busy_detect_flag; 343ed9067fdSUlf Hansson u32 busy_detect_mask; 34419a25d57SLudovic Barre u8 pwrreg_nopower:1; 34519a25d57SLudovic Barre u8 explicit_mclk_control:1; 34619a25d57SLudovic Barre u8 qcom_fifo:1; 34719a25d57SLudovic Barre u8 qcom_dml:1; 34819a25d57SLudovic Barre u8 reversed_irq_handling:1; 34919a25d57SLudovic Barre u8 mmcimask1:1; 35059db5e2dSLudovic Barre unsigned int irq_pio_mask; 351ed9067fdSUlf Hansson u32 start_err; 352ed9067fdSUlf Hansson u32 opendrain; 35346b723ddSLudovic Barre u8 dma_lli:1; 35446b723ddSLudovic Barre u32 stm32_idmabsize_mask; 355ed9067fdSUlf Hansson void (*init)(struct mmci_host *host); 356ed9067fdSUlf Hansson }; 357ed9067fdSUlf Hansson 358ed9067fdSUlf Hansson /* mmci variant callbacks */ 359ed9067fdSUlf Hansson struct mmci_host_ops { 360e0da1721SLudovic Barre int (*validate_data)(struct mmci_host *host, struct mmc_data *data); 36147983510SLudovic Barre int (*prep_data)(struct mmci_host *host, struct mmc_data *data, 36247983510SLudovic Barre bool next); 36347983510SLudovic Barre void (*unprep_data)(struct mmci_host *host, struct mmc_data *data, 36447983510SLudovic Barre int err); 3650732ea75SLudovic Barre u32 (*get_datactrl_cfg)(struct mmci_host *host); 36602769968SLudovic Barre void (*get_next_data)(struct mmci_host *host, struct mmc_data *data); 367c3647fdcSLudovic Barre int (*dma_setup)(struct mmci_host *host); 368c3647fdcSLudovic Barre void (*dma_release)(struct mmci_host *host); 369135ea30eSLudovic Barre int (*dma_start)(struct mmci_host *host, unsigned int *datactrl); 3705a9f10c3SLudovic Barre void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data); 371cfccc6acSLudovic Barre void (*dma_error)(struct mmci_host *host); 372cd3ee8c5SLudovic Barre void (*set_clkreg)(struct mmci_host *host, unsigned int desired); 373cd3ee8c5SLudovic Barre void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr); 374ed9067fdSUlf Hansson }; 3751c6a0718SPierre Ossman 3761c6a0718SPierre Ossman struct mmci_host { 377c8ebae37SRussell King phys_addr_t phybase; 3781c6a0718SPierre Ossman void __iomem *base; 3791c6a0718SPierre Ossman struct mmc_request *mrq; 3801c6a0718SPierre Ossman struct mmc_command *cmd; 381e9968c6fSUlf Hansson struct mmc_command stop_abort; 3821c6a0718SPierre Ossman struct mmc_data *data; 3831c6a0718SPierre Ossman struct mmc_host *mmc; 3841c6a0718SPierre Ossman struct clk *clk; 38519a25d57SLudovic Barre u8 singleirq:1; 3861c6a0718SPierre Ossman 38715878e58SLudovic Barre struct reset_control *rst; 38815878e58SLudovic Barre 3891c6a0718SPierre Ossman spinlock_t lock; 3901c6a0718SPierre Ossman 3911c6a0718SPierre Ossman unsigned int mclk; 3923f4e6f7bSSrinivas Kandagatla /* cached value of requested clk in set_ios */ 3933f4e6f7bSSrinivas Kandagatla unsigned int clock_cache; 3941c6a0718SPierre Ossman unsigned int cclk; 3957437cfa5SUlf Hansson u32 pwr_reg; 3964593df29SUlf Hansson u32 pwr_reg_add; 3977437cfa5SUlf Hansson u32 clk_reg; 39846b723ddSLudovic Barre u32 clk_reg_add; 3999cc639a2SUlf Hansson u32 datactrl_reg; 4008d94b54dSUlf Hansson u32 busy_status; 4016ea9cdf3SPatrice Chotard u32 mask1_reg; 40219a25d57SLudovic Barre u8 vqmmc_enabled:1; 4036ef297f8SLinus Walleij struct mmci_platform_data *plat; 404ed9067fdSUlf Hansson struct mmci_host_ops *ops; 4054956e109SRabin Vincent struct variant_data *variant; 406f9bb304cSPatrice Chotard struct pinctrl *pinctrl; 407f9bb304cSPatrice Chotard struct pinctrl_state *pins_default; 408f9bb304cSPatrice Chotard struct pinctrl_state *pins_opendrain; 4091c6a0718SPierre Ossman 410cc30d60eSLinus Walleij u8 hw_designer; 411cc30d60eSLinus Walleij u8 hw_revision:4; 412cc30d60eSLinus Walleij 4131c6a0718SPierre Ossman struct timer_list timer; 4141c6a0718SPierre Ossman unsigned int oldstat; 4151c6a0718SPierre Ossman 4161c6a0718SPierre Ossman /* pio stuff */ 4174ce1d6cbSRabin Vincent struct sg_mapping_iter sg_miter; 4181c6a0718SPierre Ossman unsigned int size; 4199c34b73dSSrinivas Kandagatla int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain); 420c8ebae37SRussell King 421c3647fdcSLudovic Barre u8 use_dma:1; 42219a25d57SLudovic Barre u8 dma_in_progress:1; 423a813f2a2SLudovic Barre void *dma_priv; 424a813f2a2SLudovic Barre 425a813f2a2SLudovic Barre s32 next_cookie; 426a813f2a2SLudovic Barre }; 427c8ebae37SRussell King 428e13934bdSLinus Walleij #define dma_inprogress(host) ((host)->dma_in_progress) 4291c6a0718SPierre Ossman 430cd3ee8c5SLudovic Barre void mmci_write_clkreg(struct mmci_host *host, u32 clk); 431cd3ee8c5SLudovic Barre void mmci_write_pwrreg(struct mmci_host *host, u32 pwr); 432cd3ee8c5SLudovic Barre 4330732ea75SLudovic Barre static inline u32 mmci_dctrl_blksz(struct mmci_host *host) 4340732ea75SLudovic Barre { 4350732ea75SLudovic Barre return (ffs(host->data->blksz) - 1) << 4; 4360732ea75SLudovic Barre } 4370732ea75SLudovic Barre 4386aa35ce7SUlf Hansson #ifdef CONFIG_DMA_ENGINE 43947983510SLudovic Barre int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 44047983510SLudovic Barre bool next); 44147983510SLudovic Barre void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data, 44247983510SLudovic Barre int err); 44302769968SLudovic Barre void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data); 444c3647fdcSLudovic Barre int mmci_dmae_setup(struct mmci_host *host); 445c3647fdcSLudovic Barre void mmci_dmae_release(struct mmci_host *host); 446135ea30eSLudovic Barre int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl); 4475a9f10c3SLudovic Barre void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data); 448cfccc6acSLudovic Barre void mmci_dmae_error(struct mmci_host *host); 4496aa35ce7SUlf Hansson #endif 450f7f3e7daSUlf Hansson 451f7f3e7daSUlf Hansson #ifdef CONFIG_MMC_QCOM_DML 452f7f3e7daSUlf Hansson void qcom_variant_init(struct mmci_host *host); 453f7f3e7daSUlf Hansson #else 454f7f3e7daSUlf Hansson static inline void qcom_variant_init(struct mmci_host *host) {} 455f7f3e7daSUlf Hansson #endif 45662e546beSUlf Hansson 45762e546beSUlf Hansson #ifdef CONFIG_MMC_STM32_SDMMC 45862e546beSUlf Hansson void sdmmc_variant_init(struct mmci_host *host); 45962e546beSUlf Hansson #else 46062e546beSUlf Hansson static inline void sdmmc_variant_init(struct mmci_host *host) {} 46162e546beSUlf Hansson #endif 462