1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/amba/mmci.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/types.h> 39 #include <linux/pinctrl/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 #include "mmci_qcom_dml.h" 46 47 #define DRIVER_NAME "mmci-pl18x" 48 49 static unsigned int fmax = 515633; 50 51 /** 52 * struct variant_data - MMCI variant-specific quirks 53 * @clkreg: default value for MCICLOCK register 54 * @clkreg_enable: enable value for MMCICLOCK register 55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 57 * @datalength_bits: number of bits in the MMCIDATALENGTH register 58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 59 * is asserted (likewise for RX) 60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 61 * is asserted (likewise for RX) 62 * @data_cmd_enable: enable value for data commands. 63 * @st_sdio: enable ST specific SDIO logic 64 * @st_clkdiv: true if using a ST-specific clock divider algorithm 65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 68 * register 69 * @datactrl_mask_sdio: SDIO enable mask in datactrl register 70 * @pwrreg_powerup: power up value for MMCIPOWER register 71 * @f_max: maximum clk frequency supported by the controller. 72 * @signal_direction: input/out direction of bus signals can be indicated 73 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 74 * @busy_detect: true if the variant supports busy detection on DAT0. 75 * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM 76 * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register 77 * indicating that the card is busy 78 * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for 79 * getting busy end detection interrupts 80 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 81 * @explicit_mclk_control: enable explicit mclk control in driver. 82 * @qcom_fifo: enables qcom specific fifo pio read logic. 83 * @qcom_dml: enables qcom specific dma glue for dma transfers. 84 * @reversed_irq_handling: handle data irq before cmd irq. 85 */ 86 struct variant_data { 87 unsigned int clkreg; 88 unsigned int clkreg_enable; 89 unsigned int clkreg_8bit_bus_enable; 90 unsigned int clkreg_neg_edge_enable; 91 unsigned int datalength_bits; 92 unsigned int fifosize; 93 unsigned int fifohalfsize; 94 unsigned int data_cmd_enable; 95 unsigned int datactrl_mask_ddrmode; 96 unsigned int datactrl_mask_sdio; 97 bool st_sdio; 98 bool st_clkdiv; 99 bool blksz_datactrl16; 100 bool blksz_datactrl4; 101 u32 pwrreg_powerup; 102 u32 f_max; 103 bool signal_direction; 104 bool pwrreg_clkgate; 105 bool busy_detect; 106 u32 busy_dpsm_flag; 107 u32 busy_detect_flag; 108 u32 busy_detect_mask; 109 bool pwrreg_nopower; 110 bool explicit_mclk_control; 111 bool qcom_fifo; 112 bool qcom_dml; 113 bool reversed_irq_handling; 114 }; 115 116 static struct variant_data variant_arm = { 117 .fifosize = 16 * 4, 118 .fifohalfsize = 8 * 4, 119 .datalength_bits = 16, 120 .pwrreg_powerup = MCI_PWR_UP, 121 .f_max = 100000000, 122 .reversed_irq_handling = true, 123 }; 124 125 static struct variant_data variant_arm_extended_fifo = { 126 .fifosize = 128 * 4, 127 .fifohalfsize = 64 * 4, 128 .datalength_bits = 16, 129 .pwrreg_powerup = MCI_PWR_UP, 130 .f_max = 100000000, 131 }; 132 133 static struct variant_data variant_arm_extended_fifo_hwfc = { 134 .fifosize = 128 * 4, 135 .fifohalfsize = 64 * 4, 136 .clkreg_enable = MCI_ARM_HWFCEN, 137 .datalength_bits = 16, 138 .pwrreg_powerup = MCI_PWR_UP, 139 .f_max = 100000000, 140 }; 141 142 static struct variant_data variant_u300 = { 143 .fifosize = 16 * 4, 144 .fifohalfsize = 8 * 4, 145 .clkreg_enable = MCI_ST_U300_HWFCEN, 146 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 147 .datalength_bits = 16, 148 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 149 .st_sdio = true, 150 .pwrreg_powerup = MCI_PWR_ON, 151 .f_max = 100000000, 152 .signal_direction = true, 153 .pwrreg_clkgate = true, 154 .pwrreg_nopower = true, 155 }; 156 157 static struct variant_data variant_nomadik = { 158 .fifosize = 16 * 4, 159 .fifohalfsize = 8 * 4, 160 .clkreg = MCI_CLK_ENABLE, 161 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 162 .datalength_bits = 24, 163 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 164 .st_sdio = true, 165 .st_clkdiv = true, 166 .pwrreg_powerup = MCI_PWR_ON, 167 .f_max = 100000000, 168 .signal_direction = true, 169 .pwrreg_clkgate = true, 170 .pwrreg_nopower = true, 171 }; 172 173 static struct variant_data variant_ux500 = { 174 .fifosize = 30 * 4, 175 .fifohalfsize = 8 * 4, 176 .clkreg = MCI_CLK_ENABLE, 177 .clkreg_enable = MCI_ST_UX500_HWFCEN, 178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 180 .datalength_bits = 24, 181 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 182 .st_sdio = true, 183 .st_clkdiv = true, 184 .pwrreg_powerup = MCI_PWR_ON, 185 .f_max = 100000000, 186 .signal_direction = true, 187 .pwrreg_clkgate = true, 188 .busy_detect = true, 189 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 190 .busy_detect_flag = MCI_ST_CARDBUSY, 191 .busy_detect_mask = MCI_ST_BUSYENDMASK, 192 .pwrreg_nopower = true, 193 }; 194 195 static struct variant_data variant_ux500v2 = { 196 .fifosize = 30 * 4, 197 .fifohalfsize = 8 * 4, 198 .clkreg = MCI_CLK_ENABLE, 199 .clkreg_enable = MCI_ST_UX500_HWFCEN, 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 202 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 203 .datalength_bits = 24, 204 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 205 .st_sdio = true, 206 .st_clkdiv = true, 207 .blksz_datactrl16 = true, 208 .pwrreg_powerup = MCI_PWR_ON, 209 .f_max = 100000000, 210 .signal_direction = true, 211 .pwrreg_clkgate = true, 212 .busy_detect = true, 213 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 214 .busy_detect_flag = MCI_ST_CARDBUSY, 215 .busy_detect_mask = MCI_ST_BUSYENDMASK, 216 .pwrreg_nopower = true, 217 }; 218 219 static struct variant_data variant_qcom = { 220 .fifosize = 16 * 4, 221 .fifohalfsize = 8 * 4, 222 .clkreg = MCI_CLK_ENABLE, 223 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 224 MCI_QCOM_CLK_SELECT_IN_FBCLK, 225 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 226 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 227 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 228 .blksz_datactrl4 = true, 229 .datalength_bits = 24, 230 .pwrreg_powerup = MCI_PWR_UP, 231 .f_max = 208000000, 232 .explicit_mclk_control = true, 233 .qcom_fifo = true, 234 .qcom_dml = true, 235 }; 236 237 /* Busy detection for the ST Micro variant */ 238 static int mmci_card_busy(struct mmc_host *mmc) 239 { 240 struct mmci_host *host = mmc_priv(mmc); 241 unsigned long flags; 242 int busy = 0; 243 244 spin_lock_irqsave(&host->lock, flags); 245 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 246 busy = 1; 247 spin_unlock_irqrestore(&host->lock, flags); 248 249 return busy; 250 } 251 252 /* 253 * Validate mmc prerequisites 254 */ 255 static int mmci_validate_data(struct mmci_host *host, 256 struct mmc_data *data) 257 { 258 if (!data) 259 return 0; 260 261 if (!is_power_of_2(data->blksz)) { 262 dev_err(mmc_dev(host->mmc), 263 "unsupported block size (%d bytes)\n", data->blksz); 264 return -EINVAL; 265 } 266 267 return 0; 268 } 269 270 static void mmci_reg_delay(struct mmci_host *host) 271 { 272 /* 273 * According to the spec, at least three feedback clock cycles 274 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 275 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 276 * Worst delay time during card init is at 100 kHz => 30 us. 277 * Worst delay time when up and running is at 25 MHz => 120 ns. 278 */ 279 if (host->cclk < 25000000) 280 udelay(30); 281 else 282 ndelay(120); 283 } 284 285 /* 286 * This must be called with host->lock held 287 */ 288 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 289 { 290 if (host->clk_reg != clk) { 291 host->clk_reg = clk; 292 writel(clk, host->base + MMCICLOCK); 293 } 294 } 295 296 /* 297 * This must be called with host->lock held 298 */ 299 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 300 { 301 if (host->pwr_reg != pwr) { 302 host->pwr_reg = pwr; 303 writel(pwr, host->base + MMCIPOWER); 304 } 305 } 306 307 /* 308 * This must be called with host->lock held 309 */ 310 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 311 { 312 /* Keep busy mode in DPSM if enabled */ 313 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 314 315 if (host->datactrl_reg != datactrl) { 316 host->datactrl_reg = datactrl; 317 writel(datactrl, host->base + MMCIDATACTRL); 318 } 319 } 320 321 /* 322 * This must be called with host->lock held 323 */ 324 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 325 { 326 struct variant_data *variant = host->variant; 327 u32 clk = variant->clkreg; 328 329 /* Make sure cclk reflects the current calculated clock */ 330 host->cclk = 0; 331 332 if (desired) { 333 if (variant->explicit_mclk_control) { 334 host->cclk = host->mclk; 335 } else if (desired >= host->mclk) { 336 clk = MCI_CLK_BYPASS; 337 if (variant->st_clkdiv) 338 clk |= MCI_ST_UX500_NEG_EDGE; 339 host->cclk = host->mclk; 340 } else if (variant->st_clkdiv) { 341 /* 342 * DB8500 TRM says f = mclk / (clkdiv + 2) 343 * => clkdiv = (mclk / f) - 2 344 * Round the divider up so we don't exceed the max 345 * frequency 346 */ 347 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 348 if (clk >= 256) 349 clk = 255; 350 host->cclk = host->mclk / (clk + 2); 351 } else { 352 /* 353 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 354 * => clkdiv = mclk / (2 * f) - 1 355 */ 356 clk = host->mclk / (2 * desired) - 1; 357 if (clk >= 256) 358 clk = 255; 359 host->cclk = host->mclk / (2 * (clk + 1)); 360 } 361 362 clk |= variant->clkreg_enable; 363 clk |= MCI_CLK_ENABLE; 364 /* This hasn't proven to be worthwhile */ 365 /* clk |= MCI_CLK_PWRSAVE; */ 366 } 367 368 /* Set actual clock for debug */ 369 host->mmc->actual_clock = host->cclk; 370 371 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 372 clk |= MCI_4BIT_BUS; 373 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 374 clk |= variant->clkreg_8bit_bus_enable; 375 376 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 377 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 378 clk |= variant->clkreg_neg_edge_enable; 379 380 mmci_write_clkreg(host, clk); 381 } 382 383 static void 384 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 385 { 386 writel(0, host->base + MMCICOMMAND); 387 388 BUG_ON(host->data); 389 390 host->mrq = NULL; 391 host->cmd = NULL; 392 393 mmc_request_done(host->mmc, mrq); 394 } 395 396 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 397 { 398 void __iomem *base = host->base; 399 400 if (host->singleirq) { 401 unsigned int mask0 = readl(base + MMCIMASK0); 402 403 mask0 &= ~MCI_IRQ1MASK; 404 mask0 |= mask; 405 406 writel(mask0, base + MMCIMASK0); 407 } 408 409 writel(mask, base + MMCIMASK1); 410 } 411 412 static void mmci_stop_data(struct mmci_host *host) 413 { 414 mmci_write_datactrlreg(host, 0); 415 mmci_set_mask1(host, 0); 416 host->data = NULL; 417 } 418 419 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 420 { 421 unsigned int flags = SG_MITER_ATOMIC; 422 423 if (data->flags & MMC_DATA_READ) 424 flags |= SG_MITER_TO_SG; 425 else 426 flags |= SG_MITER_FROM_SG; 427 428 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 429 } 430 431 /* 432 * All the DMA operation mode stuff goes inside this ifdef. 433 * This assumes that you have a generic DMA device interface, 434 * no custom DMA interfaces are supported. 435 */ 436 #ifdef CONFIG_DMA_ENGINE 437 static void mmci_dma_setup(struct mmci_host *host) 438 { 439 const char *rxname, *txname; 440 struct variant_data *variant = host->variant; 441 442 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 443 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 444 445 /* initialize pre request cookie */ 446 host->next_data.cookie = 1; 447 448 /* 449 * If only an RX channel is specified, the driver will 450 * attempt to use it bidirectionally, however if it is 451 * is specified but cannot be located, DMA will be disabled. 452 */ 453 if (host->dma_rx_channel && !host->dma_tx_channel) 454 host->dma_tx_channel = host->dma_rx_channel; 455 456 if (host->dma_rx_channel) 457 rxname = dma_chan_name(host->dma_rx_channel); 458 else 459 rxname = "none"; 460 461 if (host->dma_tx_channel) 462 txname = dma_chan_name(host->dma_tx_channel); 463 else 464 txname = "none"; 465 466 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 467 rxname, txname); 468 469 /* 470 * Limit the maximum segment size in any SG entry according to 471 * the parameters of the DMA engine device. 472 */ 473 if (host->dma_tx_channel) { 474 struct device *dev = host->dma_tx_channel->device->dev; 475 unsigned int max_seg_size = dma_get_max_seg_size(dev); 476 477 if (max_seg_size < host->mmc->max_seg_size) 478 host->mmc->max_seg_size = max_seg_size; 479 } 480 if (host->dma_rx_channel) { 481 struct device *dev = host->dma_rx_channel->device->dev; 482 unsigned int max_seg_size = dma_get_max_seg_size(dev); 483 484 if (max_seg_size < host->mmc->max_seg_size) 485 host->mmc->max_seg_size = max_seg_size; 486 } 487 488 if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) 489 if (dml_hw_init(host, host->mmc->parent->of_node)) 490 variant->qcom_dml = false; 491 } 492 493 /* 494 * This is used in or so inline it 495 * so it can be discarded. 496 */ 497 static inline void mmci_dma_release(struct mmci_host *host) 498 { 499 if (host->dma_rx_channel) 500 dma_release_channel(host->dma_rx_channel); 501 if (host->dma_tx_channel) 502 dma_release_channel(host->dma_tx_channel); 503 host->dma_rx_channel = host->dma_tx_channel = NULL; 504 } 505 506 static void mmci_dma_data_error(struct mmci_host *host) 507 { 508 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 509 dmaengine_terminate_all(host->dma_current); 510 host->dma_in_progress = false; 511 host->dma_current = NULL; 512 host->dma_desc_current = NULL; 513 host->data->host_cookie = 0; 514 } 515 516 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 517 { 518 struct dma_chan *chan; 519 enum dma_data_direction dir; 520 521 if (data->flags & MMC_DATA_READ) { 522 dir = DMA_FROM_DEVICE; 523 chan = host->dma_rx_channel; 524 } else { 525 dir = DMA_TO_DEVICE; 526 chan = host->dma_tx_channel; 527 } 528 529 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 530 } 531 532 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 533 { 534 u32 status; 535 int i; 536 537 /* Wait up to 1ms for the DMA to complete */ 538 for (i = 0; ; i++) { 539 status = readl(host->base + MMCISTATUS); 540 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 541 break; 542 udelay(10); 543 } 544 545 /* 546 * Check to see whether we still have some data left in the FIFO - 547 * this catches DMA controllers which are unable to monitor the 548 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 549 * contiguous buffers. On TX, we'll get a FIFO underrun error. 550 */ 551 if (status & MCI_RXDATAAVLBLMASK) { 552 mmci_dma_data_error(host); 553 if (!data->error) 554 data->error = -EIO; 555 } 556 557 if (!data->host_cookie) 558 mmci_dma_unmap(host, data); 559 560 /* 561 * Use of DMA with scatter-gather is impossible. 562 * Give up with DMA and switch back to PIO mode. 563 */ 564 if (status & MCI_RXDATAAVLBLMASK) { 565 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 566 mmci_dma_release(host); 567 } 568 569 host->dma_in_progress = false; 570 host->dma_current = NULL; 571 host->dma_desc_current = NULL; 572 } 573 574 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 575 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 576 struct dma_chan **dma_chan, 577 struct dma_async_tx_descriptor **dma_desc) 578 { 579 struct variant_data *variant = host->variant; 580 struct dma_slave_config conf = { 581 .src_addr = host->phybase + MMCIFIFO, 582 .dst_addr = host->phybase + MMCIFIFO, 583 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 584 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 585 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 586 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 587 .device_fc = false, 588 }; 589 struct dma_chan *chan; 590 struct dma_device *device; 591 struct dma_async_tx_descriptor *desc; 592 enum dma_data_direction buffer_dirn; 593 int nr_sg; 594 unsigned long flags = DMA_CTRL_ACK; 595 596 if (data->flags & MMC_DATA_READ) { 597 conf.direction = DMA_DEV_TO_MEM; 598 buffer_dirn = DMA_FROM_DEVICE; 599 chan = host->dma_rx_channel; 600 } else { 601 conf.direction = DMA_MEM_TO_DEV; 602 buffer_dirn = DMA_TO_DEVICE; 603 chan = host->dma_tx_channel; 604 } 605 606 /* If there's no DMA channel, fall back to PIO */ 607 if (!chan) 608 return -EINVAL; 609 610 /* If less than or equal to the fifo size, don't bother with DMA */ 611 if (data->blksz * data->blocks <= variant->fifosize) 612 return -EINVAL; 613 614 device = chan->device; 615 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 616 if (nr_sg == 0) 617 return -EINVAL; 618 619 if (host->variant->qcom_dml) 620 flags |= DMA_PREP_INTERRUPT; 621 622 dmaengine_slave_config(chan, &conf); 623 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 624 conf.direction, flags); 625 if (!desc) 626 goto unmap_exit; 627 628 *dma_chan = chan; 629 *dma_desc = desc; 630 631 return 0; 632 633 unmap_exit: 634 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 635 return -ENOMEM; 636 } 637 638 static inline int mmci_dma_prep_data(struct mmci_host *host, 639 struct mmc_data *data) 640 { 641 /* Check if next job is already prepared. */ 642 if (host->dma_current && host->dma_desc_current) 643 return 0; 644 645 /* No job were prepared thus do it now. */ 646 return __mmci_dma_prep_data(host, data, &host->dma_current, 647 &host->dma_desc_current); 648 } 649 650 static inline int mmci_dma_prep_next(struct mmci_host *host, 651 struct mmc_data *data) 652 { 653 struct mmci_host_next *nd = &host->next_data; 654 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 655 } 656 657 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 658 { 659 int ret; 660 struct mmc_data *data = host->data; 661 662 ret = mmci_dma_prep_data(host, host->data); 663 if (ret) 664 return ret; 665 666 /* Okay, go for it. */ 667 dev_vdbg(mmc_dev(host->mmc), 668 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 669 data->sg_len, data->blksz, data->blocks, data->flags); 670 host->dma_in_progress = true; 671 dmaengine_submit(host->dma_desc_current); 672 dma_async_issue_pending(host->dma_current); 673 674 if (host->variant->qcom_dml) 675 dml_start_xfer(host, data); 676 677 datactrl |= MCI_DPSM_DMAENABLE; 678 679 /* Trigger the DMA transfer */ 680 mmci_write_datactrlreg(host, datactrl); 681 682 /* 683 * Let the MMCI say when the data is ended and it's time 684 * to fire next DMA request. When that happens, MMCI will 685 * call mmci_data_end() 686 */ 687 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 688 host->base + MMCIMASK0); 689 return 0; 690 } 691 692 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 693 { 694 struct mmci_host_next *next = &host->next_data; 695 696 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 697 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 698 699 host->dma_desc_current = next->dma_desc; 700 host->dma_current = next->dma_chan; 701 next->dma_desc = NULL; 702 next->dma_chan = NULL; 703 } 704 705 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 706 { 707 struct mmci_host *host = mmc_priv(mmc); 708 struct mmc_data *data = mrq->data; 709 struct mmci_host_next *nd = &host->next_data; 710 711 if (!data) 712 return; 713 714 BUG_ON(data->host_cookie); 715 716 if (mmci_validate_data(host, data)) 717 return; 718 719 if (!mmci_dma_prep_next(host, data)) 720 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 721 } 722 723 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 724 int err) 725 { 726 struct mmci_host *host = mmc_priv(mmc); 727 struct mmc_data *data = mrq->data; 728 729 if (!data || !data->host_cookie) 730 return; 731 732 mmci_dma_unmap(host, data); 733 734 if (err) { 735 struct mmci_host_next *next = &host->next_data; 736 struct dma_chan *chan; 737 if (data->flags & MMC_DATA_READ) 738 chan = host->dma_rx_channel; 739 else 740 chan = host->dma_tx_channel; 741 dmaengine_terminate_all(chan); 742 743 if (host->dma_desc_current == next->dma_desc) 744 host->dma_desc_current = NULL; 745 746 if (host->dma_current == next->dma_chan) { 747 host->dma_in_progress = false; 748 host->dma_current = NULL; 749 } 750 751 next->dma_desc = NULL; 752 next->dma_chan = NULL; 753 data->host_cookie = 0; 754 } 755 } 756 757 #else 758 /* Blank functions if the DMA engine is not available */ 759 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 760 { 761 } 762 static inline void mmci_dma_setup(struct mmci_host *host) 763 { 764 } 765 766 static inline void mmci_dma_release(struct mmci_host *host) 767 { 768 } 769 770 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 771 { 772 } 773 774 static inline void mmci_dma_finalize(struct mmci_host *host, 775 struct mmc_data *data) 776 { 777 } 778 779 static inline void mmci_dma_data_error(struct mmci_host *host) 780 { 781 } 782 783 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 784 { 785 return -ENOSYS; 786 } 787 788 #define mmci_pre_request NULL 789 #define mmci_post_request NULL 790 791 #endif 792 793 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 794 { 795 struct variant_data *variant = host->variant; 796 unsigned int datactrl, timeout, irqmask; 797 unsigned long long clks; 798 void __iomem *base; 799 int blksz_bits; 800 801 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 802 data->blksz, data->blocks, data->flags); 803 804 host->data = data; 805 host->size = data->blksz * data->blocks; 806 data->bytes_xfered = 0; 807 808 clks = (unsigned long long)data->timeout_ns * host->cclk; 809 do_div(clks, NSEC_PER_SEC); 810 811 timeout = data->timeout_clks + (unsigned int)clks; 812 813 base = host->base; 814 writel(timeout, base + MMCIDATATIMER); 815 writel(host->size, base + MMCIDATALENGTH); 816 817 blksz_bits = ffs(data->blksz) - 1; 818 BUG_ON(1 << blksz_bits != data->blksz); 819 820 if (variant->blksz_datactrl16) 821 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 822 else if (variant->blksz_datactrl4) 823 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 824 else 825 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 826 827 if (data->flags & MMC_DATA_READ) 828 datactrl |= MCI_DPSM_DIRECTION; 829 830 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 831 u32 clk; 832 833 datactrl |= variant->datactrl_mask_sdio; 834 835 /* 836 * The ST Micro variant for SDIO small write transfers 837 * needs to have clock H/W flow control disabled, 838 * otherwise the transfer will not start. The threshold 839 * depends on the rate of MCLK. 840 */ 841 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 842 (host->size < 8 || 843 (host->size <= 8 && host->mclk > 50000000))) 844 clk = host->clk_reg & ~variant->clkreg_enable; 845 else 846 clk = host->clk_reg | variant->clkreg_enable; 847 848 mmci_write_clkreg(host, clk); 849 } 850 851 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 852 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 853 datactrl |= variant->datactrl_mask_ddrmode; 854 855 /* 856 * Attempt to use DMA operation mode, if this 857 * should fail, fall back to PIO mode 858 */ 859 if (!mmci_dma_start_data(host, datactrl)) 860 return; 861 862 /* IRQ mode, map the SG list for CPU reading/writing */ 863 mmci_init_sg(host, data); 864 865 if (data->flags & MMC_DATA_READ) { 866 irqmask = MCI_RXFIFOHALFFULLMASK; 867 868 /* 869 * If we have less than the fifo 'half-full' threshold to 870 * transfer, trigger a PIO interrupt as soon as any data 871 * is available. 872 */ 873 if (host->size < variant->fifohalfsize) 874 irqmask |= MCI_RXDATAAVLBLMASK; 875 } else { 876 /* 877 * We don't actually need to include "FIFO empty" here 878 * since its implicit in "FIFO half empty". 879 */ 880 irqmask = MCI_TXFIFOHALFEMPTYMASK; 881 } 882 883 mmci_write_datactrlreg(host, datactrl); 884 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 885 mmci_set_mask1(host, irqmask); 886 } 887 888 static void 889 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 890 { 891 void __iomem *base = host->base; 892 893 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 894 cmd->opcode, cmd->arg, cmd->flags); 895 896 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 897 writel(0, base + MMCICOMMAND); 898 mmci_reg_delay(host); 899 } 900 901 c |= cmd->opcode | MCI_CPSM_ENABLE; 902 if (cmd->flags & MMC_RSP_PRESENT) { 903 if (cmd->flags & MMC_RSP_136) 904 c |= MCI_CPSM_LONGRSP; 905 c |= MCI_CPSM_RESPONSE; 906 } 907 if (/*interrupt*/0) 908 c |= MCI_CPSM_INTERRUPT; 909 910 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 911 c |= host->variant->data_cmd_enable; 912 913 host->cmd = cmd; 914 915 writel(cmd->arg, base + MMCIARGUMENT); 916 writel(c, base + MMCICOMMAND); 917 } 918 919 static void 920 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 921 unsigned int status) 922 { 923 /* Make sure we have data to handle */ 924 if (!data) 925 return; 926 927 /* First check for errors */ 928 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 929 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 930 u32 remain, success; 931 932 /* Terminate the DMA transfer */ 933 if (dma_inprogress(host)) { 934 mmci_dma_data_error(host); 935 mmci_dma_unmap(host, data); 936 } 937 938 /* 939 * Calculate how far we are into the transfer. Note that 940 * the data counter gives the number of bytes transferred 941 * on the MMC bus, not on the host side. On reads, this 942 * can be as much as a FIFO-worth of data ahead. This 943 * matters for FIFO overruns only. 944 */ 945 remain = readl(host->base + MMCIDATACNT); 946 success = data->blksz * data->blocks - remain; 947 948 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 949 status, success); 950 if (status & MCI_DATACRCFAIL) { 951 /* Last block was not successful */ 952 success -= 1; 953 data->error = -EILSEQ; 954 } else if (status & MCI_DATATIMEOUT) { 955 data->error = -ETIMEDOUT; 956 } else if (status & MCI_STARTBITERR) { 957 data->error = -ECOMM; 958 } else if (status & MCI_TXUNDERRUN) { 959 data->error = -EIO; 960 } else if (status & MCI_RXOVERRUN) { 961 if (success > host->variant->fifosize) 962 success -= host->variant->fifosize; 963 else 964 success = 0; 965 data->error = -EIO; 966 } 967 data->bytes_xfered = round_down(success, data->blksz); 968 } 969 970 if (status & MCI_DATABLOCKEND) 971 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 972 973 if (status & MCI_DATAEND || data->error) { 974 if (dma_inprogress(host)) 975 mmci_dma_finalize(host, data); 976 mmci_stop_data(host); 977 978 if (!data->error) 979 /* The error clause is handled above, success! */ 980 data->bytes_xfered = data->blksz * data->blocks; 981 982 if (!data->stop || host->mrq->sbc) { 983 mmci_request_end(host, data->mrq); 984 } else { 985 mmci_start_command(host, data->stop, 0); 986 } 987 } 988 } 989 990 static void 991 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 992 unsigned int status) 993 { 994 void __iomem *base = host->base; 995 bool sbc; 996 997 if (!cmd) 998 return; 999 1000 sbc = (cmd == host->mrq->sbc); 1001 1002 /* 1003 * We need to be one of these interrupts to be considered worth 1004 * handling. Note that we tag on any latent IRQs postponed 1005 * due to waiting for busy status. 1006 */ 1007 if (!((status|host->busy_status) & 1008 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1009 return; 1010 1011 /* 1012 * ST Micro variant: handle busy detection. 1013 */ 1014 if (host->variant->busy_detect) { 1015 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1016 1017 /* We are busy with a command, return */ 1018 if (host->busy_status && 1019 (status & host->variant->busy_detect_flag)) 1020 return; 1021 1022 /* 1023 * We were not busy, but we now got a busy response on 1024 * something that was not an error, and we double-check 1025 * that the special busy status bit is still set before 1026 * proceeding. 1027 */ 1028 if (!host->busy_status && busy_resp && 1029 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1030 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1031 1032 /* Clear the busy start IRQ */ 1033 writel(host->variant->busy_detect_mask, 1034 host->base + MMCICLEAR); 1035 1036 /* Unmask the busy end IRQ */ 1037 writel(readl(base + MMCIMASK0) | 1038 host->variant->busy_detect_mask, 1039 base + MMCIMASK0); 1040 /* 1041 * Now cache the last response status code (until 1042 * the busy bit goes low), and return. 1043 */ 1044 host->busy_status = 1045 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1046 return; 1047 } 1048 1049 /* 1050 * At this point we are not busy with a command, we have 1051 * not received a new busy request, clear and mask the busy 1052 * end IRQ and fall through to process the IRQ. 1053 */ 1054 if (host->busy_status) { 1055 1056 writel(host->variant->busy_detect_mask, 1057 host->base + MMCICLEAR); 1058 1059 writel(readl(base + MMCIMASK0) & 1060 ~host->variant->busy_detect_mask, 1061 base + MMCIMASK0); 1062 host->busy_status = 0; 1063 } 1064 } 1065 1066 host->cmd = NULL; 1067 1068 if (status & MCI_CMDTIMEOUT) { 1069 cmd->error = -ETIMEDOUT; 1070 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1071 cmd->error = -EILSEQ; 1072 } else { 1073 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1074 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1075 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1076 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1077 } 1078 1079 if ((!sbc && !cmd->data) || cmd->error) { 1080 if (host->data) { 1081 /* Terminate the DMA transfer */ 1082 if (dma_inprogress(host)) { 1083 mmci_dma_data_error(host); 1084 mmci_dma_unmap(host, host->data); 1085 } 1086 mmci_stop_data(host); 1087 } 1088 mmci_request_end(host, host->mrq); 1089 } else if (sbc) { 1090 mmci_start_command(host, host->mrq->cmd, 0); 1091 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 1092 mmci_start_data(host, cmd->data); 1093 } 1094 } 1095 1096 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1097 { 1098 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1099 } 1100 1101 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1102 { 1103 /* 1104 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1105 * from the fifo range should be used 1106 */ 1107 if (status & MCI_RXFIFOHALFFULL) 1108 return host->variant->fifohalfsize; 1109 else if (status & MCI_RXDATAAVLBL) 1110 return 4; 1111 1112 return 0; 1113 } 1114 1115 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1116 { 1117 void __iomem *base = host->base; 1118 char *ptr = buffer; 1119 u32 status = readl(host->base + MMCISTATUS); 1120 int host_remain = host->size; 1121 1122 do { 1123 int count = host->get_rx_fifocnt(host, status, host_remain); 1124 1125 if (count > remain) 1126 count = remain; 1127 1128 if (count <= 0) 1129 break; 1130 1131 /* 1132 * SDIO especially may want to send something that is 1133 * not divisible by 4 (as opposed to card sectors 1134 * etc). Therefore make sure to always read the last bytes 1135 * while only doing full 32-bit reads towards the FIFO. 1136 */ 1137 if (unlikely(count & 0x3)) { 1138 if (count < 4) { 1139 unsigned char buf[4]; 1140 ioread32_rep(base + MMCIFIFO, buf, 1); 1141 memcpy(ptr, buf, count); 1142 } else { 1143 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1144 count &= ~0x3; 1145 } 1146 } else { 1147 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1148 } 1149 1150 ptr += count; 1151 remain -= count; 1152 host_remain -= count; 1153 1154 if (remain == 0) 1155 break; 1156 1157 status = readl(base + MMCISTATUS); 1158 } while (status & MCI_RXDATAAVLBL); 1159 1160 return ptr - buffer; 1161 } 1162 1163 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1164 { 1165 struct variant_data *variant = host->variant; 1166 void __iomem *base = host->base; 1167 char *ptr = buffer; 1168 1169 do { 1170 unsigned int count, maxcnt; 1171 1172 maxcnt = status & MCI_TXFIFOEMPTY ? 1173 variant->fifosize : variant->fifohalfsize; 1174 count = min(remain, maxcnt); 1175 1176 /* 1177 * SDIO especially may want to send something that is 1178 * not divisible by 4 (as opposed to card sectors 1179 * etc), and the FIFO only accept full 32-bit writes. 1180 * So compensate by adding +3 on the count, a single 1181 * byte become a 32bit write, 7 bytes will be two 1182 * 32bit writes etc. 1183 */ 1184 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1185 1186 ptr += count; 1187 remain -= count; 1188 1189 if (remain == 0) 1190 break; 1191 1192 status = readl(base + MMCISTATUS); 1193 } while (status & MCI_TXFIFOHALFEMPTY); 1194 1195 return ptr - buffer; 1196 } 1197 1198 /* 1199 * PIO data transfer IRQ handler. 1200 */ 1201 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1202 { 1203 struct mmci_host *host = dev_id; 1204 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1205 struct variant_data *variant = host->variant; 1206 void __iomem *base = host->base; 1207 unsigned long flags; 1208 u32 status; 1209 1210 status = readl(base + MMCISTATUS); 1211 1212 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1213 1214 local_irq_save(flags); 1215 1216 do { 1217 unsigned int remain, len; 1218 char *buffer; 1219 1220 /* 1221 * For write, we only need to test the half-empty flag 1222 * here - if the FIFO is completely empty, then by 1223 * definition it is more than half empty. 1224 * 1225 * For read, check for data available. 1226 */ 1227 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1228 break; 1229 1230 if (!sg_miter_next(sg_miter)) 1231 break; 1232 1233 buffer = sg_miter->addr; 1234 remain = sg_miter->length; 1235 1236 len = 0; 1237 if (status & MCI_RXACTIVE) 1238 len = mmci_pio_read(host, buffer, remain); 1239 if (status & MCI_TXACTIVE) 1240 len = mmci_pio_write(host, buffer, remain, status); 1241 1242 sg_miter->consumed = len; 1243 1244 host->size -= len; 1245 remain -= len; 1246 1247 if (remain) 1248 break; 1249 1250 status = readl(base + MMCISTATUS); 1251 } while (1); 1252 1253 sg_miter_stop(sg_miter); 1254 1255 local_irq_restore(flags); 1256 1257 /* 1258 * If we have less than the fifo 'half-full' threshold to transfer, 1259 * trigger a PIO interrupt as soon as any data is available. 1260 */ 1261 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1262 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1263 1264 /* 1265 * If we run out of data, disable the data IRQs; this 1266 * prevents a race where the FIFO becomes empty before 1267 * the chip itself has disabled the data path, and 1268 * stops us racing with our data end IRQ. 1269 */ 1270 if (host->size == 0) { 1271 mmci_set_mask1(host, 0); 1272 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1273 } 1274 1275 return IRQ_HANDLED; 1276 } 1277 1278 /* 1279 * Handle completion of command and data transfers. 1280 */ 1281 static irqreturn_t mmci_irq(int irq, void *dev_id) 1282 { 1283 struct mmci_host *host = dev_id; 1284 u32 status; 1285 int ret = 0; 1286 1287 spin_lock(&host->lock); 1288 1289 do { 1290 status = readl(host->base + MMCISTATUS); 1291 1292 if (host->singleirq) { 1293 if (status & readl(host->base + MMCIMASK1)) 1294 mmci_pio_irq(irq, dev_id); 1295 1296 status &= ~MCI_IRQ1MASK; 1297 } 1298 1299 /* 1300 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1301 * enabled) in mmci_cmd_irq() function where ST Micro busy 1302 * detection variant is handled. Considering the HW seems to be 1303 * triggering the IRQ on both edges while monitoring DAT0 for 1304 * busy completion and that same status bit is used to monitor 1305 * start and end of busy detection, special care must be taken 1306 * to make sure that both start and end interrupts are always 1307 * cleared one after the other. 1308 */ 1309 status &= readl(host->base + MMCIMASK0); 1310 if (host->variant->busy_detect) 1311 writel(status & ~host->variant->busy_detect_mask, 1312 host->base + MMCICLEAR); 1313 else 1314 writel(status, host->base + MMCICLEAR); 1315 1316 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1317 1318 if (host->variant->reversed_irq_handling) { 1319 mmci_data_irq(host, host->data, status); 1320 mmci_cmd_irq(host, host->cmd, status); 1321 } else { 1322 mmci_cmd_irq(host, host->cmd, status); 1323 mmci_data_irq(host, host->data, status); 1324 } 1325 1326 /* 1327 * Don't poll for busy completion in irq context. 1328 */ 1329 if (host->variant->busy_detect && host->busy_status) 1330 status &= ~host->variant->busy_detect_flag; 1331 1332 ret = 1; 1333 } while (status); 1334 1335 spin_unlock(&host->lock); 1336 1337 return IRQ_RETVAL(ret); 1338 } 1339 1340 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1341 { 1342 struct mmci_host *host = mmc_priv(mmc); 1343 unsigned long flags; 1344 1345 WARN_ON(host->mrq != NULL); 1346 1347 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1348 if (mrq->cmd->error) { 1349 mmc_request_done(mmc, mrq); 1350 return; 1351 } 1352 1353 spin_lock_irqsave(&host->lock, flags); 1354 1355 host->mrq = mrq; 1356 1357 if (mrq->data) 1358 mmci_get_next_data(host, mrq->data); 1359 1360 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1361 mmci_start_data(host, mrq->data); 1362 1363 if (mrq->sbc) 1364 mmci_start_command(host, mrq->sbc, 0); 1365 else 1366 mmci_start_command(host, mrq->cmd, 0); 1367 1368 spin_unlock_irqrestore(&host->lock, flags); 1369 } 1370 1371 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1372 { 1373 struct mmci_host *host = mmc_priv(mmc); 1374 struct variant_data *variant = host->variant; 1375 u32 pwr = 0; 1376 unsigned long flags; 1377 int ret; 1378 1379 if (host->plat->ios_handler && 1380 host->plat->ios_handler(mmc_dev(mmc), ios)) 1381 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1382 1383 switch (ios->power_mode) { 1384 case MMC_POWER_OFF: 1385 if (!IS_ERR(mmc->supply.vmmc)) 1386 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1387 1388 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1389 regulator_disable(mmc->supply.vqmmc); 1390 host->vqmmc_enabled = false; 1391 } 1392 1393 break; 1394 case MMC_POWER_UP: 1395 if (!IS_ERR(mmc->supply.vmmc)) 1396 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1397 1398 /* 1399 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1400 * and instead uses MCI_PWR_ON so apply whatever value is 1401 * configured in the variant data. 1402 */ 1403 pwr |= variant->pwrreg_powerup; 1404 1405 break; 1406 case MMC_POWER_ON: 1407 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1408 ret = regulator_enable(mmc->supply.vqmmc); 1409 if (ret < 0) 1410 dev_err(mmc_dev(mmc), 1411 "failed to enable vqmmc regulator\n"); 1412 else 1413 host->vqmmc_enabled = true; 1414 } 1415 1416 pwr |= MCI_PWR_ON; 1417 break; 1418 } 1419 1420 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1421 /* 1422 * The ST Micro variant has some additional bits 1423 * indicating signal direction for the signals in 1424 * the SD/MMC bus and feedback-clock usage. 1425 */ 1426 pwr |= host->pwr_reg_add; 1427 1428 if (ios->bus_width == MMC_BUS_WIDTH_4) 1429 pwr &= ~MCI_ST_DATA74DIREN; 1430 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1431 pwr &= (~MCI_ST_DATA74DIREN & 1432 ~MCI_ST_DATA31DIREN & 1433 ~MCI_ST_DATA2DIREN); 1434 } 1435 1436 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1437 if (host->hw_designer != AMBA_VENDOR_ST) 1438 pwr |= MCI_ROD; 1439 else { 1440 /* 1441 * The ST Micro variant use the ROD bit for something 1442 * else and only has OD (Open Drain). 1443 */ 1444 pwr |= MCI_OD; 1445 } 1446 } 1447 1448 /* 1449 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1450 * gating the clock, the MCI_PWR_ON bit is cleared. 1451 */ 1452 if (!ios->clock && variant->pwrreg_clkgate) 1453 pwr &= ~MCI_PWR_ON; 1454 1455 if (host->variant->explicit_mclk_control && 1456 ios->clock != host->clock_cache) { 1457 ret = clk_set_rate(host->clk, ios->clock); 1458 if (ret < 0) 1459 dev_err(mmc_dev(host->mmc), 1460 "Error setting clock rate (%d)\n", ret); 1461 else 1462 host->mclk = clk_get_rate(host->clk); 1463 } 1464 host->clock_cache = ios->clock; 1465 1466 spin_lock_irqsave(&host->lock, flags); 1467 1468 mmci_set_clkreg(host, ios->clock); 1469 mmci_write_pwrreg(host, pwr); 1470 mmci_reg_delay(host); 1471 1472 spin_unlock_irqrestore(&host->lock, flags); 1473 } 1474 1475 static int mmci_get_cd(struct mmc_host *mmc) 1476 { 1477 struct mmci_host *host = mmc_priv(mmc); 1478 struct mmci_platform_data *plat = host->plat; 1479 unsigned int status = mmc_gpio_get_cd(mmc); 1480 1481 if (status == -ENOSYS) { 1482 if (!plat->status) 1483 return 1; /* Assume always present */ 1484 1485 status = plat->status(mmc_dev(host->mmc)); 1486 } 1487 return status; 1488 } 1489 1490 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1491 { 1492 int ret = 0; 1493 1494 if (!IS_ERR(mmc->supply.vqmmc)) { 1495 1496 switch (ios->signal_voltage) { 1497 case MMC_SIGNAL_VOLTAGE_330: 1498 ret = regulator_set_voltage(mmc->supply.vqmmc, 1499 2700000, 3600000); 1500 break; 1501 case MMC_SIGNAL_VOLTAGE_180: 1502 ret = regulator_set_voltage(mmc->supply.vqmmc, 1503 1700000, 1950000); 1504 break; 1505 case MMC_SIGNAL_VOLTAGE_120: 1506 ret = regulator_set_voltage(mmc->supply.vqmmc, 1507 1100000, 1300000); 1508 break; 1509 } 1510 1511 if (ret) 1512 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1513 } 1514 1515 return ret; 1516 } 1517 1518 static struct mmc_host_ops mmci_ops = { 1519 .request = mmci_request, 1520 .pre_req = mmci_pre_request, 1521 .post_req = mmci_post_request, 1522 .set_ios = mmci_set_ios, 1523 .get_ro = mmc_gpio_get_ro, 1524 .get_cd = mmci_get_cd, 1525 .start_signal_voltage_switch = mmci_sig_volt_switch, 1526 }; 1527 1528 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1529 { 1530 struct mmci_host *host = mmc_priv(mmc); 1531 int ret = mmc_of_parse(mmc); 1532 1533 if (ret) 1534 return ret; 1535 1536 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1537 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1538 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1539 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1540 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1541 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1542 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1543 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1544 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1545 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1546 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1547 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1548 1549 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1550 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1551 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1552 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1553 1554 return 0; 1555 } 1556 1557 static int mmci_probe(struct amba_device *dev, 1558 const struct amba_id *id) 1559 { 1560 struct mmci_platform_data *plat = dev->dev.platform_data; 1561 struct device_node *np = dev->dev.of_node; 1562 struct variant_data *variant = id->data; 1563 struct mmci_host *host; 1564 struct mmc_host *mmc; 1565 int ret; 1566 1567 /* Must have platform data or Device Tree. */ 1568 if (!plat && !np) { 1569 dev_err(&dev->dev, "No plat data or DT found\n"); 1570 return -EINVAL; 1571 } 1572 1573 if (!plat) { 1574 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1575 if (!plat) 1576 return -ENOMEM; 1577 } 1578 1579 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1580 if (!mmc) 1581 return -ENOMEM; 1582 1583 ret = mmci_of_parse(np, mmc); 1584 if (ret) 1585 goto host_free; 1586 1587 host = mmc_priv(mmc); 1588 host->mmc = mmc; 1589 1590 host->hw_designer = amba_manf(dev); 1591 host->hw_revision = amba_rev(dev); 1592 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1593 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1594 1595 host->clk = devm_clk_get(&dev->dev, NULL); 1596 if (IS_ERR(host->clk)) { 1597 ret = PTR_ERR(host->clk); 1598 goto host_free; 1599 } 1600 1601 ret = clk_prepare_enable(host->clk); 1602 if (ret) 1603 goto host_free; 1604 1605 if (variant->qcom_fifo) 1606 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1607 else 1608 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1609 1610 host->plat = plat; 1611 host->variant = variant; 1612 host->mclk = clk_get_rate(host->clk); 1613 /* 1614 * According to the spec, mclk is max 100 MHz, 1615 * so we try to adjust the clock down to this, 1616 * (if possible). 1617 */ 1618 if (host->mclk > variant->f_max) { 1619 ret = clk_set_rate(host->clk, variant->f_max); 1620 if (ret < 0) 1621 goto clk_disable; 1622 host->mclk = clk_get_rate(host->clk); 1623 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1624 host->mclk); 1625 } 1626 1627 host->phybase = dev->res.start; 1628 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1629 if (IS_ERR(host->base)) { 1630 ret = PTR_ERR(host->base); 1631 goto clk_disable; 1632 } 1633 1634 /* 1635 * The ARM and ST versions of the block have slightly different 1636 * clock divider equations which means that the minimum divider 1637 * differs too. 1638 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1639 */ 1640 if (variant->st_clkdiv) 1641 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1642 else if (variant->explicit_mclk_control) 1643 mmc->f_min = clk_round_rate(host->clk, 100000); 1644 else 1645 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1646 /* 1647 * If no maximum operating frequency is supplied, fall back to use 1648 * the module parameter, which has a (low) default value in case it 1649 * is not specified. Either value must not exceed the clock rate into 1650 * the block, of course. 1651 */ 1652 if (mmc->f_max) 1653 mmc->f_max = variant->explicit_mclk_control ? 1654 min(variant->f_max, mmc->f_max) : 1655 min(host->mclk, mmc->f_max); 1656 else 1657 mmc->f_max = variant->explicit_mclk_control ? 1658 fmax : min(host->mclk, fmax); 1659 1660 1661 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1662 1663 /* Get regulators and the supported OCR mask */ 1664 ret = mmc_regulator_get_supply(mmc); 1665 if (ret == -EPROBE_DEFER) 1666 goto clk_disable; 1667 1668 if (!mmc->ocr_avail) 1669 mmc->ocr_avail = plat->ocr_mask; 1670 else if (plat->ocr_mask) 1671 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1672 1673 /* DT takes precedence over platform data. */ 1674 if (!np) { 1675 if (!plat->cd_invert) 1676 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1677 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1678 } 1679 1680 /* We support these capabilities. */ 1681 mmc->caps |= MMC_CAP_CMD23; 1682 1683 /* 1684 * Enable busy detection. 1685 */ 1686 if (variant->busy_detect) { 1687 mmci_ops.card_busy = mmci_card_busy; 1688 /* 1689 * Not all variants have a flag to enable busy detection 1690 * in the DPSM, but if they do, set it here. 1691 */ 1692 if (variant->busy_dpsm_flag) 1693 mmci_write_datactrlreg(host, 1694 host->variant->busy_dpsm_flag); 1695 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1696 mmc->max_busy_timeout = 0; 1697 } 1698 1699 mmc->ops = &mmci_ops; 1700 1701 /* We support these PM capabilities. */ 1702 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1703 1704 /* 1705 * We can do SGIO 1706 */ 1707 mmc->max_segs = NR_SG; 1708 1709 /* 1710 * Since only a certain number of bits are valid in the data length 1711 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1712 * single request. 1713 */ 1714 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1715 1716 /* 1717 * Set the maximum segment size. Since we aren't doing DMA 1718 * (yet) we are only limited by the data length register. 1719 */ 1720 mmc->max_seg_size = mmc->max_req_size; 1721 1722 /* 1723 * Block size can be up to 2048 bytes, but must be a power of two. 1724 */ 1725 mmc->max_blk_size = 1 << 11; 1726 1727 /* 1728 * Limit the number of blocks transferred so that we don't overflow 1729 * the maximum request size. 1730 */ 1731 mmc->max_blk_count = mmc->max_req_size >> 11; 1732 1733 spin_lock_init(&host->lock); 1734 1735 writel(0, host->base + MMCIMASK0); 1736 writel(0, host->base + MMCIMASK1); 1737 writel(0xfff, host->base + MMCICLEAR); 1738 1739 /* 1740 * If: 1741 * - not using DT but using a descriptor table, or 1742 * - using a table of descriptors ALONGSIDE DT, or 1743 * look up these descriptors named "cd" and "wp" right here, fail 1744 * silently of these do not exist and proceed to try platform data 1745 */ 1746 if (!np) { 1747 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1748 if (ret < 0) { 1749 if (ret == -EPROBE_DEFER) 1750 goto clk_disable; 1751 else if (gpio_is_valid(plat->gpio_cd)) { 1752 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1753 if (ret) 1754 goto clk_disable; 1755 } 1756 } 1757 1758 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1759 if (ret < 0) { 1760 if (ret == -EPROBE_DEFER) 1761 goto clk_disable; 1762 else if (gpio_is_valid(plat->gpio_wp)) { 1763 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1764 if (ret) 1765 goto clk_disable; 1766 } 1767 } 1768 } 1769 1770 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1771 DRIVER_NAME " (cmd)", host); 1772 if (ret) 1773 goto clk_disable; 1774 1775 if (!dev->irq[1]) 1776 host->singleirq = true; 1777 else { 1778 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1779 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1780 if (ret) 1781 goto clk_disable; 1782 } 1783 1784 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1785 1786 amba_set_drvdata(dev, mmc); 1787 1788 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1789 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1790 amba_rev(dev), (unsigned long long)dev->res.start, 1791 dev->irq[0], dev->irq[1]); 1792 1793 mmci_dma_setup(host); 1794 1795 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1796 pm_runtime_use_autosuspend(&dev->dev); 1797 1798 mmc_add_host(mmc); 1799 1800 pm_runtime_put(&dev->dev); 1801 return 0; 1802 1803 clk_disable: 1804 clk_disable_unprepare(host->clk); 1805 host_free: 1806 mmc_free_host(mmc); 1807 return ret; 1808 } 1809 1810 static int mmci_remove(struct amba_device *dev) 1811 { 1812 struct mmc_host *mmc = amba_get_drvdata(dev); 1813 1814 if (mmc) { 1815 struct mmci_host *host = mmc_priv(mmc); 1816 1817 /* 1818 * Undo pm_runtime_put() in probe. We use the _sync 1819 * version here so that we can access the primecell. 1820 */ 1821 pm_runtime_get_sync(&dev->dev); 1822 1823 mmc_remove_host(mmc); 1824 1825 writel(0, host->base + MMCIMASK0); 1826 writel(0, host->base + MMCIMASK1); 1827 1828 writel(0, host->base + MMCICOMMAND); 1829 writel(0, host->base + MMCIDATACTRL); 1830 1831 mmci_dma_release(host); 1832 clk_disable_unprepare(host->clk); 1833 mmc_free_host(mmc); 1834 } 1835 1836 return 0; 1837 } 1838 1839 #ifdef CONFIG_PM 1840 static void mmci_save(struct mmci_host *host) 1841 { 1842 unsigned long flags; 1843 1844 spin_lock_irqsave(&host->lock, flags); 1845 1846 writel(0, host->base + MMCIMASK0); 1847 if (host->variant->pwrreg_nopower) { 1848 writel(0, host->base + MMCIDATACTRL); 1849 writel(0, host->base + MMCIPOWER); 1850 writel(0, host->base + MMCICLOCK); 1851 } 1852 mmci_reg_delay(host); 1853 1854 spin_unlock_irqrestore(&host->lock, flags); 1855 } 1856 1857 static void mmci_restore(struct mmci_host *host) 1858 { 1859 unsigned long flags; 1860 1861 spin_lock_irqsave(&host->lock, flags); 1862 1863 if (host->variant->pwrreg_nopower) { 1864 writel(host->clk_reg, host->base + MMCICLOCK); 1865 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1866 writel(host->pwr_reg, host->base + MMCIPOWER); 1867 } 1868 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1869 mmci_reg_delay(host); 1870 1871 spin_unlock_irqrestore(&host->lock, flags); 1872 } 1873 1874 static int mmci_runtime_suspend(struct device *dev) 1875 { 1876 struct amba_device *adev = to_amba_device(dev); 1877 struct mmc_host *mmc = amba_get_drvdata(adev); 1878 1879 if (mmc) { 1880 struct mmci_host *host = mmc_priv(mmc); 1881 pinctrl_pm_select_sleep_state(dev); 1882 mmci_save(host); 1883 clk_disable_unprepare(host->clk); 1884 } 1885 1886 return 0; 1887 } 1888 1889 static int mmci_runtime_resume(struct device *dev) 1890 { 1891 struct amba_device *adev = to_amba_device(dev); 1892 struct mmc_host *mmc = amba_get_drvdata(adev); 1893 1894 if (mmc) { 1895 struct mmci_host *host = mmc_priv(mmc); 1896 clk_prepare_enable(host->clk); 1897 mmci_restore(host); 1898 pinctrl_pm_select_default_state(dev); 1899 } 1900 1901 return 0; 1902 } 1903 #endif 1904 1905 static const struct dev_pm_ops mmci_dev_pm_ops = { 1906 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1907 pm_runtime_force_resume) 1908 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1909 }; 1910 1911 static struct amba_id mmci_ids[] = { 1912 { 1913 .id = 0x00041180, 1914 .mask = 0xff0fffff, 1915 .data = &variant_arm, 1916 }, 1917 { 1918 .id = 0x01041180, 1919 .mask = 0xff0fffff, 1920 .data = &variant_arm_extended_fifo, 1921 }, 1922 { 1923 .id = 0x02041180, 1924 .mask = 0xff0fffff, 1925 .data = &variant_arm_extended_fifo_hwfc, 1926 }, 1927 { 1928 .id = 0x00041181, 1929 .mask = 0x000fffff, 1930 .data = &variant_arm, 1931 }, 1932 /* ST Micro variants */ 1933 { 1934 .id = 0x00180180, 1935 .mask = 0x00ffffff, 1936 .data = &variant_u300, 1937 }, 1938 { 1939 .id = 0x10180180, 1940 .mask = 0xf0ffffff, 1941 .data = &variant_nomadik, 1942 }, 1943 { 1944 .id = 0x00280180, 1945 .mask = 0x00ffffff, 1946 .data = &variant_nomadik, 1947 }, 1948 { 1949 .id = 0x00480180, 1950 .mask = 0xf0ffffff, 1951 .data = &variant_ux500, 1952 }, 1953 { 1954 .id = 0x10480180, 1955 .mask = 0xf0ffffff, 1956 .data = &variant_ux500v2, 1957 }, 1958 /* Qualcomm variants */ 1959 { 1960 .id = 0x00051180, 1961 .mask = 0x000fffff, 1962 .data = &variant_qcom, 1963 }, 1964 { 0, 0 }, 1965 }; 1966 1967 MODULE_DEVICE_TABLE(amba, mmci_ids); 1968 1969 static struct amba_driver mmci_driver = { 1970 .drv = { 1971 .name = DRIVER_NAME, 1972 .pm = &mmci_dev_pm_ops, 1973 }, 1974 .probe = mmci_probe, 1975 .remove = mmci_remove, 1976 .id_table = mmci_ids, 1977 }; 1978 1979 module_amba_driver(mmci_driver); 1980 1981 module_param(fmax, uint, 0444); 1982 1983 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1984 MODULE_LICENSE("GPL"); 1985