1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/of.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/gpio/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 static void mmci_variant_init(struct mmci_host *host); 49 static void ux500_variant_init(struct mmci_host *host); 50 static void ux500v2_variant_init(struct mmci_host *host); 51 52 static unsigned int fmax = 515633; 53 54 static struct variant_data variant_arm = { 55 .fifosize = 16 * 4, 56 .fifohalfsize = 8 * 4, 57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 60 .cmdreg_srsp = MCI_CPSM_RESPONSE, 61 .datalength_bits = 16, 62 .datactrl_blocksz = 11, 63 .pwrreg_powerup = MCI_PWR_UP, 64 .f_max = 100000000, 65 .reversed_irq_handling = true, 66 .mmcimask1 = true, 67 .irq_pio_mask = MCI_IRQ_PIO_MASK, 68 .start_err = MCI_STARTBITERR, 69 .opendrain = MCI_ROD, 70 .init = mmci_variant_init, 71 }; 72 73 static struct variant_data variant_arm_extended_fifo = { 74 .fifosize = 128 * 4, 75 .fifohalfsize = 64 * 4, 76 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 77 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 78 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 79 .cmdreg_srsp = MCI_CPSM_RESPONSE, 80 .datalength_bits = 16, 81 .datactrl_blocksz = 11, 82 .pwrreg_powerup = MCI_PWR_UP, 83 .f_max = 100000000, 84 .mmcimask1 = true, 85 .irq_pio_mask = MCI_IRQ_PIO_MASK, 86 .start_err = MCI_STARTBITERR, 87 .opendrain = MCI_ROD, 88 .init = mmci_variant_init, 89 }; 90 91 static struct variant_data variant_arm_extended_fifo_hwfc = { 92 .fifosize = 128 * 4, 93 .fifohalfsize = 64 * 4, 94 .clkreg_enable = MCI_ARM_HWFCEN, 95 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 96 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 97 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 98 .cmdreg_srsp = MCI_CPSM_RESPONSE, 99 .datalength_bits = 16, 100 .datactrl_blocksz = 11, 101 .pwrreg_powerup = MCI_PWR_UP, 102 .f_max = 100000000, 103 .mmcimask1 = true, 104 .irq_pio_mask = MCI_IRQ_PIO_MASK, 105 .start_err = MCI_STARTBITERR, 106 .opendrain = MCI_ROD, 107 .init = mmci_variant_init, 108 }; 109 110 static struct variant_data variant_u300 = { 111 .fifosize = 16 * 4, 112 .fifohalfsize = 8 * 4, 113 .clkreg_enable = MCI_ST_U300_HWFCEN, 114 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 115 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 116 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 117 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 118 .cmdreg_srsp = MCI_CPSM_RESPONSE, 119 .datalength_bits = 16, 120 .datactrl_blocksz = 11, 121 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 122 .st_sdio = true, 123 .pwrreg_powerup = MCI_PWR_ON, 124 .f_max = 100000000, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128 .mmcimask1 = true, 129 .irq_pio_mask = MCI_IRQ_PIO_MASK, 130 .start_err = MCI_STARTBITERR, 131 .opendrain = MCI_OD, 132 .init = mmci_variant_init, 133 }; 134 135 static struct variant_data variant_nomadik = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg = MCI_CLK_ENABLE, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 141 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 142 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 143 .cmdreg_srsp = MCI_CPSM_RESPONSE, 144 .datalength_bits = 24, 145 .datactrl_blocksz = 11, 146 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 147 .st_sdio = true, 148 .st_clkdiv = true, 149 .pwrreg_powerup = MCI_PWR_ON, 150 .f_max = 100000000, 151 .signal_direction = true, 152 .pwrreg_clkgate = true, 153 .pwrreg_nopower = true, 154 .mmcimask1 = true, 155 .irq_pio_mask = MCI_IRQ_PIO_MASK, 156 .start_err = MCI_STARTBITERR, 157 .opendrain = MCI_OD, 158 .init = mmci_variant_init, 159 }; 160 161 static struct variant_data variant_ux500 = { 162 .fifosize = 30 * 4, 163 .fifohalfsize = 8 * 4, 164 .clkreg = MCI_CLK_ENABLE, 165 .clkreg_enable = MCI_ST_UX500_HWFCEN, 166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 168 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 169 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 170 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 171 .cmdreg_srsp = MCI_CPSM_RESPONSE, 172 .datalength_bits = 24, 173 .datactrl_blocksz = 11, 174 .datactrl_any_blocksz = true, 175 .dma_power_of_2 = true, 176 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 177 .st_sdio = true, 178 .st_clkdiv = true, 179 .pwrreg_powerup = MCI_PWR_ON, 180 .f_max = 100000000, 181 .signal_direction = true, 182 .pwrreg_clkgate = true, 183 .busy_detect = true, 184 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 185 .busy_detect_flag = MCI_ST_CARDBUSY, 186 .busy_detect_mask = MCI_ST_BUSYENDMASK, 187 .pwrreg_nopower = true, 188 .mmcimask1 = true, 189 .irq_pio_mask = MCI_IRQ_PIO_MASK, 190 .start_err = MCI_STARTBITERR, 191 .opendrain = MCI_OD, 192 .init = ux500_variant_init, 193 }; 194 195 static struct variant_data variant_ux500v2 = { 196 .fifosize = 30 * 4, 197 .fifohalfsize = 8 * 4, 198 .clkreg = MCI_CLK_ENABLE, 199 .clkreg_enable = MCI_ST_UX500_HWFCEN, 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 202 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 203 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 204 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 205 .cmdreg_srsp = MCI_CPSM_RESPONSE, 206 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 207 .datalength_bits = 24, 208 .datactrl_blocksz = 11, 209 .datactrl_any_blocksz = true, 210 .dma_power_of_2 = true, 211 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 212 .st_sdio = true, 213 .st_clkdiv = true, 214 .pwrreg_powerup = MCI_PWR_ON, 215 .f_max = 100000000, 216 .signal_direction = true, 217 .pwrreg_clkgate = true, 218 .busy_detect = true, 219 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 220 .busy_detect_flag = MCI_ST_CARDBUSY, 221 .busy_detect_mask = MCI_ST_BUSYENDMASK, 222 .pwrreg_nopower = true, 223 .mmcimask1 = true, 224 .irq_pio_mask = MCI_IRQ_PIO_MASK, 225 .start_err = MCI_STARTBITERR, 226 .opendrain = MCI_OD, 227 .init = ux500v2_variant_init, 228 }; 229 230 static struct variant_data variant_stm32 = { 231 .fifosize = 32 * 4, 232 .fifohalfsize = 8 * 4, 233 .clkreg = MCI_CLK_ENABLE, 234 .clkreg_enable = MCI_ST_UX500_HWFCEN, 235 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 236 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 237 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 238 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 239 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 240 .cmdreg_srsp = MCI_CPSM_RESPONSE, 241 .irq_pio_mask = MCI_IRQ_PIO_MASK, 242 .datalength_bits = 24, 243 .datactrl_blocksz = 11, 244 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 245 .st_sdio = true, 246 .st_clkdiv = true, 247 .pwrreg_powerup = MCI_PWR_ON, 248 .f_max = 48000000, 249 .pwrreg_clkgate = true, 250 .pwrreg_nopower = true, 251 .init = mmci_variant_init, 252 }; 253 254 static struct variant_data variant_stm32_sdmmc = { 255 .fifosize = 16 * 4, 256 .fifohalfsize = 8 * 4, 257 .f_max = 208000000, 258 .stm32_clkdiv = true, 259 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 260 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 261 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 262 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 263 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 264 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 265 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 266 .datactrl_first = true, 267 .datacnt_useless = true, 268 .datalength_bits = 25, 269 .datactrl_blocksz = 14, 270 .datactrl_any_blocksz = true, 271 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 272 .stm32_idmabsize_mask = GENMASK(12, 5), 273 .stm32_idmabsize_align = BIT(5), 274 .busy_timeout = true, 275 .busy_detect = true, 276 .busy_detect_flag = MCI_STM32_BUSYD0, 277 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 278 .init = sdmmc_variant_init, 279 }; 280 281 static struct variant_data variant_stm32_sdmmcv2 = { 282 .fifosize = 16 * 4, 283 .fifohalfsize = 8 * 4, 284 .f_max = 267000000, 285 .stm32_clkdiv = true, 286 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 287 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 288 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 289 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 290 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 291 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 292 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 293 .datactrl_first = true, 294 .datacnt_useless = true, 295 .datalength_bits = 25, 296 .datactrl_blocksz = 14, 297 .datactrl_any_blocksz = true, 298 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 299 .stm32_idmabsize_mask = GENMASK(16, 5), 300 .stm32_idmabsize_align = BIT(5), 301 .dma_lli = true, 302 .busy_timeout = true, 303 .busy_detect = true, 304 .busy_detect_flag = MCI_STM32_BUSYD0, 305 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 306 .init = sdmmc_variant_init, 307 }; 308 309 static struct variant_data variant_stm32_sdmmcv3 = { 310 .fifosize = 256 * 4, 311 .fifohalfsize = 128 * 4, 312 .f_max = 267000000, 313 .stm32_clkdiv = true, 314 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 315 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 316 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 317 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 318 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 319 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 320 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 321 .datactrl_first = true, 322 .datacnt_useless = true, 323 .datalength_bits = 25, 324 .datactrl_blocksz = 14, 325 .datactrl_any_blocksz = true, 326 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 327 .stm32_idmabsize_mask = GENMASK(16, 6), 328 .stm32_idmabsize_align = BIT(6), 329 .dma_lli = true, 330 .busy_timeout = true, 331 .busy_detect = true, 332 .busy_detect_flag = MCI_STM32_BUSYD0, 333 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 334 .init = sdmmc_variant_init, 335 }; 336 337 static struct variant_data variant_qcom = { 338 .fifosize = 16 * 4, 339 .fifohalfsize = 8 * 4, 340 .clkreg = MCI_CLK_ENABLE, 341 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 342 MCI_QCOM_CLK_SELECT_IN_FBCLK, 343 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 344 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 345 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 346 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 347 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 348 .cmdreg_srsp = MCI_CPSM_RESPONSE, 349 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 350 .datalength_bits = 24, 351 .datactrl_blocksz = 11, 352 .datactrl_any_blocksz = true, 353 .pwrreg_powerup = MCI_PWR_UP, 354 .f_max = 208000000, 355 .explicit_mclk_control = true, 356 .qcom_fifo = true, 357 .qcom_dml = true, 358 .mmcimask1 = true, 359 .irq_pio_mask = MCI_IRQ_PIO_MASK, 360 .start_err = MCI_STARTBITERR, 361 .opendrain = MCI_ROD, 362 .init = qcom_variant_init, 363 }; 364 365 /* Busy detection for the ST Micro variant */ 366 static int mmci_card_busy(struct mmc_host *mmc) 367 { 368 struct mmci_host *host = mmc_priv(mmc); 369 unsigned long flags; 370 int busy = 0; 371 372 spin_lock_irqsave(&host->lock, flags); 373 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 374 busy = 1; 375 spin_unlock_irqrestore(&host->lock, flags); 376 377 return busy; 378 } 379 380 static void mmci_reg_delay(struct mmci_host *host) 381 { 382 /* 383 * According to the spec, at least three feedback clock cycles 384 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 385 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 386 * Worst delay time during card init is at 100 kHz => 30 us. 387 * Worst delay time when up and running is at 25 MHz => 120 ns. 388 */ 389 if (host->cclk < 25000000) 390 udelay(30); 391 else 392 ndelay(120); 393 } 394 395 /* 396 * This must be called with host->lock held 397 */ 398 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 399 { 400 if (host->clk_reg != clk) { 401 host->clk_reg = clk; 402 writel(clk, host->base + MMCICLOCK); 403 } 404 } 405 406 /* 407 * This must be called with host->lock held 408 */ 409 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 410 { 411 if (host->pwr_reg != pwr) { 412 host->pwr_reg = pwr; 413 writel(pwr, host->base + MMCIPOWER); 414 } 415 } 416 417 /* 418 * This must be called with host->lock held 419 */ 420 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 421 { 422 /* Keep busy mode in DPSM if enabled */ 423 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 424 425 if (host->datactrl_reg != datactrl) { 426 host->datactrl_reg = datactrl; 427 writel(datactrl, host->base + MMCIDATACTRL); 428 } 429 } 430 431 /* 432 * This must be called with host->lock held 433 */ 434 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 435 { 436 struct variant_data *variant = host->variant; 437 u32 clk = variant->clkreg; 438 439 /* Make sure cclk reflects the current calculated clock */ 440 host->cclk = 0; 441 442 if (desired) { 443 if (variant->explicit_mclk_control) { 444 host->cclk = host->mclk; 445 } else if (desired >= host->mclk) { 446 clk = MCI_CLK_BYPASS; 447 if (variant->st_clkdiv) 448 clk |= MCI_ST_UX500_NEG_EDGE; 449 host->cclk = host->mclk; 450 } else if (variant->st_clkdiv) { 451 /* 452 * DB8500 TRM says f = mclk / (clkdiv + 2) 453 * => clkdiv = (mclk / f) - 2 454 * Round the divider up so we don't exceed the max 455 * frequency 456 */ 457 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 458 if (clk >= 256) 459 clk = 255; 460 host->cclk = host->mclk / (clk + 2); 461 } else { 462 /* 463 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 464 * => clkdiv = mclk / (2 * f) - 1 465 */ 466 clk = host->mclk / (2 * desired) - 1; 467 if (clk >= 256) 468 clk = 255; 469 host->cclk = host->mclk / (2 * (clk + 1)); 470 } 471 472 clk |= variant->clkreg_enable; 473 clk |= MCI_CLK_ENABLE; 474 /* This hasn't proven to be worthwhile */ 475 /* clk |= MCI_CLK_PWRSAVE; */ 476 } 477 478 /* Set actual clock for debug */ 479 host->mmc->actual_clock = host->cclk; 480 481 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 482 clk |= MCI_4BIT_BUS; 483 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 484 clk |= variant->clkreg_8bit_bus_enable; 485 486 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 487 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 488 clk |= variant->clkreg_neg_edge_enable; 489 490 mmci_write_clkreg(host, clk); 491 } 492 493 static void mmci_dma_release(struct mmci_host *host) 494 { 495 if (host->ops && host->ops->dma_release) 496 host->ops->dma_release(host); 497 498 host->use_dma = false; 499 } 500 501 static void mmci_dma_setup(struct mmci_host *host) 502 { 503 if (!host->ops || !host->ops->dma_setup) 504 return; 505 506 if (host->ops->dma_setup(host)) 507 return; 508 509 /* initialize pre request cookie */ 510 host->next_cookie = 1; 511 512 host->use_dma = true; 513 } 514 515 /* 516 * Validate mmc prerequisites 517 */ 518 static int mmci_validate_data(struct mmci_host *host, 519 struct mmc_data *data) 520 { 521 struct variant_data *variant = host->variant; 522 523 if (!data) 524 return 0; 525 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { 526 dev_err(mmc_dev(host->mmc), 527 "unsupported block size (%d bytes)\n", data->blksz); 528 return -EINVAL; 529 } 530 531 if (host->ops && host->ops->validate_data) 532 return host->ops->validate_data(host, data); 533 534 return 0; 535 } 536 537 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 538 { 539 int err; 540 541 if (!host->ops || !host->ops->prep_data) 542 return 0; 543 544 err = host->ops->prep_data(host, data, next); 545 546 if (next && !err) 547 data->host_cookie = ++host->next_cookie < 0 ? 548 1 : host->next_cookie; 549 550 return err; 551 } 552 553 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 554 int err) 555 { 556 if (host->ops && host->ops->unprep_data) 557 host->ops->unprep_data(host, data, err); 558 559 data->host_cookie = 0; 560 } 561 562 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 563 { 564 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 565 566 if (host->ops && host->ops->get_next_data) 567 host->ops->get_next_data(host, data); 568 } 569 570 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 571 { 572 struct mmc_data *data = host->data; 573 int ret; 574 575 if (!host->use_dma) 576 return -EINVAL; 577 578 ret = mmci_prep_data(host, data, false); 579 if (ret) 580 return ret; 581 582 if (!host->ops || !host->ops->dma_start) 583 return -EINVAL; 584 585 /* Okay, go for it. */ 586 dev_vdbg(mmc_dev(host->mmc), 587 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 588 data->sg_len, data->blksz, data->blocks, data->flags); 589 590 ret = host->ops->dma_start(host, &datactrl); 591 if (ret) 592 return ret; 593 594 /* Trigger the DMA transfer */ 595 mmci_write_datactrlreg(host, datactrl); 596 597 /* 598 * Let the MMCI say when the data is ended and it's time 599 * to fire next DMA request. When that happens, MMCI will 600 * call mmci_data_end() 601 */ 602 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 603 host->base + MMCIMASK0); 604 return 0; 605 } 606 607 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 608 { 609 if (!host->use_dma) 610 return; 611 612 if (host->ops && host->ops->dma_finalize) 613 host->ops->dma_finalize(host, data); 614 } 615 616 static void mmci_dma_error(struct mmci_host *host) 617 { 618 if (!host->use_dma) 619 return; 620 621 if (host->ops && host->ops->dma_error) 622 host->ops->dma_error(host); 623 } 624 625 static void 626 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 627 { 628 writel(0, host->base + MMCICOMMAND); 629 630 BUG_ON(host->data); 631 632 host->mrq = NULL; 633 host->cmd = NULL; 634 635 mmc_request_done(host->mmc, mrq); 636 } 637 638 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 639 { 640 void __iomem *base = host->base; 641 struct variant_data *variant = host->variant; 642 643 if (host->singleirq) { 644 unsigned int mask0 = readl(base + MMCIMASK0); 645 646 mask0 &= ~variant->irq_pio_mask; 647 mask0 |= mask; 648 649 writel(mask0, base + MMCIMASK0); 650 } 651 652 if (variant->mmcimask1) 653 writel(mask, base + MMCIMASK1); 654 655 host->mask1_reg = mask; 656 } 657 658 static void mmci_stop_data(struct mmci_host *host) 659 { 660 mmci_write_datactrlreg(host, 0); 661 mmci_set_mask1(host, 0); 662 host->data = NULL; 663 } 664 665 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 666 { 667 unsigned int flags = SG_MITER_ATOMIC; 668 669 if (data->flags & MMC_DATA_READ) 670 flags |= SG_MITER_TO_SG; 671 else 672 flags |= SG_MITER_FROM_SG; 673 674 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 675 } 676 677 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 678 { 679 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 680 } 681 682 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 683 { 684 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 685 } 686 687 static void ux500_busy_clear_mask_done(struct mmci_host *host) 688 { 689 void __iomem *base = host->base; 690 691 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 692 writel(readl(base + MMCIMASK0) & 693 ~host->variant->busy_detect_mask, base + MMCIMASK0); 694 host->busy_state = MMCI_BUSY_DONE; 695 host->busy_status = 0; 696 } 697 698 /* 699 * ux500_busy_complete() - this will wait until the busy status 700 * goes off, saving any status that occur in the meantime into 701 * host->busy_status until we know the card is not busy any more. 702 * The function returns true when the busy detection is ended 703 * and we should continue processing the command. 704 * 705 * The Ux500 typically fires two IRQs over a busy cycle like this: 706 * 707 * DAT0 busy +-----------------+ 708 * | | 709 * DAT0 not busy ----+ +-------- 710 * 711 * ^ ^ 712 * | | 713 * IRQ1 IRQ2 714 */ 715 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 716 { 717 void __iomem *base = host->base; 718 int retries = 10; 719 720 if (status & err_msk) { 721 /* Stop any ongoing busy detection if an error occurs */ 722 ux500_busy_clear_mask_done(host); 723 goto out_ret_state; 724 } 725 726 /* 727 * The state transitions are encoded in a state machine crossing 728 * the edges in this switch statement. 729 */ 730 switch (host->busy_state) { 731 732 /* 733 * Before unmasking for the busy end IRQ, confirm that the 734 * command was sent successfully. To keep track of having a 735 * command in-progress, waiting for busy signaling to end, 736 * store the status in host->busy_status. 737 * 738 * Note that, the card may need a couple of clock cycles before 739 * it starts signaling busy on DAT0, hence re-read the 740 * MMCISTATUS register here, to allow the busy bit to be set. 741 */ 742 case MMCI_BUSY_DONE: 743 /* 744 * Save the first status register read to be sure to catch 745 * all bits that may be lost will retrying. If the command 746 * is still busy this will result in assigning 0 to 747 * host->busy_status, which is what it should be in IDLE. 748 */ 749 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 750 while (retries) { 751 status = readl(base + MMCISTATUS); 752 /* Keep accumulating status bits */ 753 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 754 if (status & host->variant->busy_detect_flag) { 755 writel(readl(base + MMCIMASK0) | 756 host->variant->busy_detect_mask, 757 base + MMCIMASK0); 758 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; 759 goto out_ret_state; 760 } 761 retries--; 762 } 763 dev_dbg(mmc_dev(host->mmc), "no busy signalling in time\n"); 764 ux500_busy_clear_mask_done(host); 765 break; 766 767 /* 768 * If there is a command in-progress that has been successfully 769 * sent, then bail out if busy status is set and wait for the 770 * busy end IRQ. 771 * 772 * Note that, the HW triggers an IRQ on both edges while 773 * monitoring DAT0 for busy completion, but there is only one 774 * status bit in MMCISTATUS for the busy state. Therefore 775 * both the start and the end interrupts needs to be cleared, 776 * one after the other. So, clear the busy start IRQ here. 777 */ 778 case MMCI_BUSY_WAITING_FOR_START_IRQ: 779 if (status & host->variant->busy_detect_flag) { 780 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 781 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 782 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ; 783 } else { 784 dev_dbg(mmc_dev(host->mmc), 785 "lost busy status when waiting for busy start IRQ\n"); 786 ux500_busy_clear_mask_done(host); 787 } 788 break; 789 790 case MMCI_BUSY_WAITING_FOR_END_IRQ: 791 if (!(status & host->variant->busy_detect_flag)) { 792 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 793 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 794 ux500_busy_clear_mask_done(host); 795 } else { 796 dev_dbg(mmc_dev(host->mmc), 797 "busy status still asserted when handling busy end IRQ - will keep waiting\n"); 798 } 799 break; 800 801 default: 802 dev_dbg(mmc_dev(host->mmc), "fell through on state %d\n", 803 host->busy_state); 804 break; 805 } 806 807 out_ret_state: 808 return (host->busy_state == MMCI_BUSY_DONE); 809 } 810 811 /* 812 * All the DMA operation mode stuff goes inside this ifdef. 813 * This assumes that you have a generic DMA device interface, 814 * no custom DMA interfaces are supported. 815 */ 816 #ifdef CONFIG_DMA_ENGINE 817 struct mmci_dmae_next { 818 struct dma_async_tx_descriptor *desc; 819 struct dma_chan *chan; 820 }; 821 822 struct mmci_dmae_priv { 823 struct dma_chan *cur; 824 struct dma_chan *rx_channel; 825 struct dma_chan *tx_channel; 826 struct dma_async_tx_descriptor *desc_current; 827 struct mmci_dmae_next next_data; 828 }; 829 830 int mmci_dmae_setup(struct mmci_host *host) 831 { 832 const char *rxname, *txname; 833 struct mmci_dmae_priv *dmae; 834 835 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 836 if (!dmae) 837 return -ENOMEM; 838 839 host->dma_priv = dmae; 840 841 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); 842 if (IS_ERR(dmae->rx_channel)) { 843 int ret = PTR_ERR(dmae->rx_channel); 844 dmae->rx_channel = NULL; 845 return ret; 846 } 847 848 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); 849 if (IS_ERR(dmae->tx_channel)) { 850 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) 851 dev_warn(mmc_dev(host->mmc), 852 "Deferred probe for TX channel ignored\n"); 853 dmae->tx_channel = NULL; 854 } 855 856 /* 857 * If only an RX channel is specified, the driver will 858 * attempt to use it bidirectionally, however if it 859 * is specified but cannot be located, DMA will be disabled. 860 */ 861 if (dmae->rx_channel && !dmae->tx_channel) 862 dmae->tx_channel = dmae->rx_channel; 863 864 if (dmae->rx_channel) 865 rxname = dma_chan_name(dmae->rx_channel); 866 else 867 rxname = "none"; 868 869 if (dmae->tx_channel) 870 txname = dma_chan_name(dmae->tx_channel); 871 else 872 txname = "none"; 873 874 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 875 rxname, txname); 876 877 /* 878 * Limit the maximum segment size in any SG entry according to 879 * the parameters of the DMA engine device. 880 */ 881 if (dmae->tx_channel) { 882 struct device *dev = dmae->tx_channel->device->dev; 883 unsigned int max_seg_size = dma_get_max_seg_size(dev); 884 885 if (max_seg_size < host->mmc->max_seg_size) 886 host->mmc->max_seg_size = max_seg_size; 887 } 888 if (dmae->rx_channel) { 889 struct device *dev = dmae->rx_channel->device->dev; 890 unsigned int max_seg_size = dma_get_max_seg_size(dev); 891 892 if (max_seg_size < host->mmc->max_seg_size) 893 host->mmc->max_seg_size = max_seg_size; 894 } 895 896 if (!dmae->tx_channel || !dmae->rx_channel) { 897 mmci_dmae_release(host); 898 return -EINVAL; 899 } 900 901 return 0; 902 } 903 904 /* 905 * This is used in or so inline it 906 * so it can be discarded. 907 */ 908 void mmci_dmae_release(struct mmci_host *host) 909 { 910 struct mmci_dmae_priv *dmae = host->dma_priv; 911 912 if (dmae->rx_channel) 913 dma_release_channel(dmae->rx_channel); 914 if (dmae->tx_channel) 915 dma_release_channel(dmae->tx_channel); 916 dmae->rx_channel = dmae->tx_channel = NULL; 917 } 918 919 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 920 { 921 struct mmci_dmae_priv *dmae = host->dma_priv; 922 struct dma_chan *chan; 923 924 if (data->flags & MMC_DATA_READ) 925 chan = dmae->rx_channel; 926 else 927 chan = dmae->tx_channel; 928 929 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 930 mmc_get_dma_dir(data)); 931 } 932 933 void mmci_dmae_error(struct mmci_host *host) 934 { 935 struct mmci_dmae_priv *dmae = host->dma_priv; 936 937 if (!dma_inprogress(host)) 938 return; 939 940 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 941 dmaengine_terminate_all(dmae->cur); 942 host->dma_in_progress = false; 943 dmae->cur = NULL; 944 dmae->desc_current = NULL; 945 host->data->host_cookie = 0; 946 947 mmci_dma_unmap(host, host->data); 948 } 949 950 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 951 { 952 struct mmci_dmae_priv *dmae = host->dma_priv; 953 u32 status; 954 int i; 955 956 if (!dma_inprogress(host)) 957 return; 958 959 /* Wait up to 1ms for the DMA to complete */ 960 for (i = 0; ; i++) { 961 status = readl(host->base + MMCISTATUS); 962 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 963 break; 964 udelay(10); 965 } 966 967 /* 968 * Check to see whether we still have some data left in the FIFO - 969 * this catches DMA controllers which are unable to monitor the 970 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 971 * contiguous buffers. On TX, we'll get a FIFO underrun error. 972 */ 973 if (status & MCI_RXDATAAVLBLMASK) { 974 mmci_dma_error(host); 975 if (!data->error) 976 data->error = -EIO; 977 } else if (!data->host_cookie) { 978 mmci_dma_unmap(host, data); 979 } 980 981 /* 982 * Use of DMA with scatter-gather is impossible. 983 * Give up with DMA and switch back to PIO mode. 984 */ 985 if (status & MCI_RXDATAAVLBLMASK) { 986 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 987 mmci_dma_release(host); 988 } 989 990 host->dma_in_progress = false; 991 dmae->cur = NULL; 992 dmae->desc_current = NULL; 993 } 994 995 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 996 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 997 struct dma_chan **dma_chan, 998 struct dma_async_tx_descriptor **dma_desc) 999 { 1000 struct mmci_dmae_priv *dmae = host->dma_priv; 1001 struct variant_data *variant = host->variant; 1002 struct dma_slave_config conf = { 1003 .src_addr = host->phybase + MMCIFIFO, 1004 .dst_addr = host->phybase + MMCIFIFO, 1005 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1006 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1007 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 1008 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 1009 .device_fc = false, 1010 }; 1011 struct dma_chan *chan; 1012 struct dma_device *device; 1013 struct dma_async_tx_descriptor *desc; 1014 int nr_sg; 1015 unsigned long flags = DMA_CTRL_ACK; 1016 1017 if (data->flags & MMC_DATA_READ) { 1018 conf.direction = DMA_DEV_TO_MEM; 1019 chan = dmae->rx_channel; 1020 } else { 1021 conf.direction = DMA_MEM_TO_DEV; 1022 chan = dmae->tx_channel; 1023 } 1024 1025 /* If there's no DMA channel, fall back to PIO */ 1026 if (!chan) 1027 return -EINVAL; 1028 1029 /* If less than or equal to the fifo size, don't bother with DMA */ 1030 if (data->blksz * data->blocks <= variant->fifosize) 1031 return -EINVAL; 1032 1033 /* 1034 * This is necessary to get SDIO working on the Ux500. We do not yet 1035 * know if this is a bug in: 1036 * - The Ux500 DMA controller (DMA40) 1037 * - The MMCI DMA interface on the Ux500 1038 * some power of two blocks (such as 64 bytes) are sent regularly 1039 * during SDIO traffic and those work fine so for these we enable DMA 1040 * transfers. 1041 */ 1042 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) 1043 return -EINVAL; 1044 1045 device = chan->device; 1046 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 1047 mmc_get_dma_dir(data)); 1048 if (nr_sg == 0) 1049 return -EINVAL; 1050 1051 if (host->variant->qcom_dml) 1052 flags |= DMA_PREP_INTERRUPT; 1053 1054 dmaengine_slave_config(chan, &conf); 1055 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 1056 conf.direction, flags); 1057 if (!desc) 1058 goto unmap_exit; 1059 1060 *dma_chan = chan; 1061 *dma_desc = desc; 1062 1063 return 0; 1064 1065 unmap_exit: 1066 dma_unmap_sg(device->dev, data->sg, data->sg_len, 1067 mmc_get_dma_dir(data)); 1068 return -ENOMEM; 1069 } 1070 1071 int mmci_dmae_prep_data(struct mmci_host *host, 1072 struct mmc_data *data, 1073 bool next) 1074 { 1075 struct mmci_dmae_priv *dmae = host->dma_priv; 1076 struct mmci_dmae_next *nd = &dmae->next_data; 1077 1078 if (!host->use_dma) 1079 return -EINVAL; 1080 1081 if (next) 1082 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 1083 /* Check if next job is already prepared. */ 1084 if (dmae->cur && dmae->desc_current) 1085 return 0; 1086 1087 /* No job were prepared thus do it now. */ 1088 return _mmci_dmae_prep_data(host, data, &dmae->cur, 1089 &dmae->desc_current); 1090 } 1091 1092 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 1093 { 1094 struct mmci_dmae_priv *dmae = host->dma_priv; 1095 int ret; 1096 1097 host->dma_in_progress = true; 1098 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); 1099 if (ret < 0) { 1100 host->dma_in_progress = false; 1101 return ret; 1102 } 1103 dma_async_issue_pending(dmae->cur); 1104 1105 *datactrl |= MCI_DPSM_DMAENABLE; 1106 1107 return 0; 1108 } 1109 1110 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 1111 { 1112 struct mmci_dmae_priv *dmae = host->dma_priv; 1113 struct mmci_dmae_next *next = &dmae->next_data; 1114 1115 if (!host->use_dma) 1116 return; 1117 1118 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 1119 1120 dmae->desc_current = next->desc; 1121 dmae->cur = next->chan; 1122 next->desc = NULL; 1123 next->chan = NULL; 1124 } 1125 1126 void mmci_dmae_unprep_data(struct mmci_host *host, 1127 struct mmc_data *data, int err) 1128 1129 { 1130 struct mmci_dmae_priv *dmae = host->dma_priv; 1131 1132 if (!host->use_dma) 1133 return; 1134 1135 mmci_dma_unmap(host, data); 1136 1137 if (err) { 1138 struct mmci_dmae_next *next = &dmae->next_data; 1139 struct dma_chan *chan; 1140 if (data->flags & MMC_DATA_READ) 1141 chan = dmae->rx_channel; 1142 else 1143 chan = dmae->tx_channel; 1144 dmaengine_terminate_all(chan); 1145 1146 if (dmae->desc_current == next->desc) 1147 dmae->desc_current = NULL; 1148 1149 if (dmae->cur == next->chan) { 1150 host->dma_in_progress = false; 1151 dmae->cur = NULL; 1152 } 1153 1154 next->desc = NULL; 1155 next->chan = NULL; 1156 } 1157 } 1158 1159 static struct mmci_host_ops mmci_variant_ops = { 1160 .prep_data = mmci_dmae_prep_data, 1161 .unprep_data = mmci_dmae_unprep_data, 1162 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1163 .get_next_data = mmci_dmae_get_next_data, 1164 .dma_setup = mmci_dmae_setup, 1165 .dma_release = mmci_dmae_release, 1166 .dma_start = mmci_dmae_start, 1167 .dma_finalize = mmci_dmae_finalize, 1168 .dma_error = mmci_dmae_error, 1169 }; 1170 #else 1171 static struct mmci_host_ops mmci_variant_ops = { 1172 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1173 }; 1174 #endif 1175 1176 static void mmci_variant_init(struct mmci_host *host) 1177 { 1178 host->ops = &mmci_variant_ops; 1179 } 1180 1181 static void ux500_variant_init(struct mmci_host *host) 1182 { 1183 host->ops = &mmci_variant_ops; 1184 host->ops->busy_complete = ux500_busy_complete; 1185 } 1186 1187 static void ux500v2_variant_init(struct mmci_host *host) 1188 { 1189 host->ops = &mmci_variant_ops; 1190 host->ops->busy_complete = ux500_busy_complete; 1191 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1192 } 1193 1194 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1195 { 1196 struct mmci_host *host = mmc_priv(mmc); 1197 struct mmc_data *data = mrq->data; 1198 1199 if (!data) 1200 return; 1201 1202 WARN_ON(data->host_cookie); 1203 1204 if (mmci_validate_data(host, data)) 1205 return; 1206 1207 mmci_prep_data(host, data, true); 1208 } 1209 1210 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1211 int err) 1212 { 1213 struct mmci_host *host = mmc_priv(mmc); 1214 struct mmc_data *data = mrq->data; 1215 1216 if (!data || !data->host_cookie) 1217 return; 1218 1219 mmci_unprep_data(host, data, err); 1220 } 1221 1222 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1223 { 1224 struct variant_data *variant = host->variant; 1225 unsigned int datactrl, timeout, irqmask; 1226 unsigned long long clks; 1227 void __iomem *base; 1228 1229 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1230 data->blksz, data->blocks, data->flags); 1231 1232 host->data = data; 1233 host->size = data->blksz * data->blocks; 1234 data->bytes_xfered = 0; 1235 1236 clks = (unsigned long long)data->timeout_ns * host->cclk; 1237 do_div(clks, NSEC_PER_SEC); 1238 1239 timeout = data->timeout_clks + (unsigned int)clks; 1240 1241 base = host->base; 1242 writel(timeout, base + MMCIDATATIMER); 1243 writel(host->size, base + MMCIDATALENGTH); 1244 1245 datactrl = host->ops->get_datactrl_cfg(host); 1246 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1247 1248 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1249 u32 clk; 1250 1251 datactrl |= variant->datactrl_mask_sdio; 1252 1253 /* 1254 * The ST Micro variant for SDIO small write transfers 1255 * needs to have clock H/W flow control disabled, 1256 * otherwise the transfer will not start. The threshold 1257 * depends on the rate of MCLK. 1258 */ 1259 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1260 (host->size < 8 || 1261 (host->size <= 8 && host->mclk > 50000000))) 1262 clk = host->clk_reg & ~variant->clkreg_enable; 1263 else 1264 clk = host->clk_reg | variant->clkreg_enable; 1265 1266 mmci_write_clkreg(host, clk); 1267 } 1268 1269 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1270 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1271 datactrl |= variant->datactrl_mask_ddrmode; 1272 1273 /* 1274 * Attempt to use DMA operation mode, if this 1275 * should fail, fall back to PIO mode 1276 */ 1277 if (!mmci_dma_start(host, datactrl)) 1278 return; 1279 1280 /* IRQ mode, map the SG list for CPU reading/writing */ 1281 mmci_init_sg(host, data); 1282 1283 if (data->flags & MMC_DATA_READ) { 1284 irqmask = MCI_RXFIFOHALFFULLMASK; 1285 1286 /* 1287 * If we have less than the fifo 'half-full' threshold to 1288 * transfer, trigger a PIO interrupt as soon as any data 1289 * is available. 1290 */ 1291 if (host->size < variant->fifohalfsize) 1292 irqmask |= MCI_RXDATAAVLBLMASK; 1293 } else { 1294 /* 1295 * We don't actually need to include "FIFO empty" here 1296 * since its implicit in "FIFO half empty". 1297 */ 1298 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1299 } 1300 1301 mmci_write_datactrlreg(host, datactrl); 1302 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1303 mmci_set_mask1(host, irqmask); 1304 } 1305 1306 static void 1307 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1308 { 1309 void __iomem *base = host->base; 1310 unsigned long long clks; 1311 1312 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1313 cmd->opcode, cmd->arg, cmd->flags); 1314 1315 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1316 writel(0, base + MMCICOMMAND); 1317 mmci_reg_delay(host); 1318 } 1319 1320 if (host->variant->cmdreg_stop && 1321 cmd->opcode == MMC_STOP_TRANSMISSION) 1322 c |= host->variant->cmdreg_stop; 1323 1324 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1325 if (cmd->flags & MMC_RSP_PRESENT) { 1326 if (cmd->flags & MMC_RSP_136) 1327 c |= host->variant->cmdreg_lrsp_crc; 1328 else if (cmd->flags & MMC_RSP_CRC) 1329 c |= host->variant->cmdreg_srsp_crc; 1330 else 1331 c |= host->variant->cmdreg_srsp; 1332 } 1333 1334 host->busy_status = 0; 1335 host->busy_state = MMCI_BUSY_DONE; 1336 1337 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1338 if (!cmd->busy_timeout) 1339 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1340 1341 if (cmd->busy_timeout > host->mmc->max_busy_timeout) 1342 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; 1343 else 1344 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1345 1346 do_div(clks, MSEC_PER_SEC); 1347 writel_relaxed(clks, host->base + MMCIDATATIMER); 1348 } 1349 1350 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) 1351 host->ops->pre_sig_volt_switch(host); 1352 1353 if (/*interrupt*/0) 1354 c |= MCI_CPSM_INTERRUPT; 1355 1356 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1357 c |= host->variant->data_cmd_enable; 1358 1359 host->cmd = cmd; 1360 1361 writel(cmd->arg, base + MMCIARGUMENT); 1362 writel(c, base + MMCICOMMAND); 1363 } 1364 1365 static void mmci_stop_command(struct mmci_host *host) 1366 { 1367 host->stop_abort.error = 0; 1368 mmci_start_command(host, &host->stop_abort, 0); 1369 } 1370 1371 static void 1372 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1373 unsigned int status) 1374 { 1375 unsigned int status_err; 1376 1377 /* Make sure we have data to handle */ 1378 if (!data) 1379 return; 1380 1381 /* First check for errors */ 1382 status_err = status & (host->variant->start_err | 1383 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1384 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1385 1386 if (status_err) { 1387 u32 remain, success; 1388 1389 /* Terminate the DMA transfer */ 1390 mmci_dma_error(host); 1391 1392 /* 1393 * Calculate how far we are into the transfer. Note that 1394 * the data counter gives the number of bytes transferred 1395 * on the MMC bus, not on the host side. On reads, this 1396 * can be as much as a FIFO-worth of data ahead. This 1397 * matters for FIFO overruns only. 1398 */ 1399 if (!host->variant->datacnt_useless) { 1400 remain = readl(host->base + MMCIDATACNT); 1401 success = data->blksz * data->blocks - remain; 1402 } else { 1403 success = 0; 1404 } 1405 1406 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1407 status_err, success); 1408 if (status_err & MCI_DATACRCFAIL) { 1409 /* Last block was not successful */ 1410 success -= 1; 1411 data->error = -EILSEQ; 1412 } else if (status_err & MCI_DATATIMEOUT) { 1413 data->error = -ETIMEDOUT; 1414 } else if (status_err & MCI_STARTBITERR) { 1415 data->error = -ECOMM; 1416 } else if (status_err & MCI_TXUNDERRUN) { 1417 data->error = -EIO; 1418 } else if (status_err & MCI_RXOVERRUN) { 1419 if (success > host->variant->fifosize) 1420 success -= host->variant->fifosize; 1421 else 1422 success = 0; 1423 data->error = -EIO; 1424 } 1425 data->bytes_xfered = round_down(success, data->blksz); 1426 } 1427 1428 if (status & MCI_DATABLOCKEND) 1429 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1430 1431 if (status & MCI_DATAEND || data->error) { 1432 mmci_dma_finalize(host, data); 1433 1434 mmci_stop_data(host); 1435 1436 if (!data->error) 1437 /* The error clause is handled above, success! */ 1438 data->bytes_xfered = data->blksz * data->blocks; 1439 1440 if (!data->stop) { 1441 if (host->variant->cmdreg_stop && data->error) 1442 mmci_stop_command(host); 1443 else 1444 mmci_request_end(host, data->mrq); 1445 } else if (host->mrq->sbc && !data->error) { 1446 mmci_request_end(host, data->mrq); 1447 } else { 1448 mmci_start_command(host, data->stop, 0); 1449 } 1450 } 1451 } 1452 1453 static void 1454 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1455 unsigned int status) 1456 { 1457 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1458 void __iomem *base = host->base; 1459 bool sbc, busy_resp; 1460 1461 if (!cmd) 1462 return; 1463 1464 sbc = (cmd == host->mrq->sbc); 1465 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1466 1467 /* 1468 * We need to be one of these interrupts to be considered worth 1469 * handling. Note that we tag on any latent IRQs postponed 1470 * due to waiting for busy status. 1471 */ 1472 if (host->variant->busy_timeout && busy_resp) 1473 err_msk |= MCI_DATATIMEOUT; 1474 1475 if (!((status | host->busy_status) & 1476 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1477 return; 1478 1479 /* Handle busy detection on DAT0 if the variant supports it. */ 1480 if (busy_resp && host->variant->busy_detect) 1481 if (!host->ops->busy_complete(host, status, err_msk)) 1482 return; 1483 1484 host->cmd = NULL; 1485 1486 if (status & MCI_CMDTIMEOUT) { 1487 cmd->error = -ETIMEDOUT; 1488 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1489 cmd->error = -EILSEQ; 1490 } else if (host->variant->busy_timeout && busy_resp && 1491 status & MCI_DATATIMEOUT) { 1492 cmd->error = -ETIMEDOUT; 1493 /* 1494 * This will wake up mmci_irq_thread() which will issue 1495 * a hardware reset of the MMCI block. 1496 */ 1497 host->irq_action = IRQ_WAKE_THREAD; 1498 } else { 1499 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1500 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1501 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1502 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1503 } 1504 1505 if ((!sbc && !cmd->data) || cmd->error) { 1506 if (host->data) { 1507 /* Terminate the DMA transfer */ 1508 mmci_dma_error(host); 1509 1510 mmci_stop_data(host); 1511 if (host->variant->cmdreg_stop && cmd->error) { 1512 mmci_stop_command(host); 1513 return; 1514 } 1515 } 1516 1517 if (host->irq_action != IRQ_WAKE_THREAD) 1518 mmci_request_end(host, host->mrq); 1519 1520 } else if (sbc) { 1521 mmci_start_command(host, host->mrq->cmd, 0); 1522 } else if (!host->variant->datactrl_first && 1523 !(cmd->data->flags & MMC_DATA_READ)) { 1524 mmci_start_data(host, cmd->data); 1525 } 1526 } 1527 1528 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1529 { 1530 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1531 } 1532 1533 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1534 { 1535 /* 1536 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1537 * from the fifo range should be used 1538 */ 1539 if (status & MCI_RXFIFOHALFFULL) 1540 return host->variant->fifohalfsize; 1541 else if (status & MCI_RXDATAAVLBL) 1542 return 4; 1543 1544 return 0; 1545 } 1546 1547 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1548 { 1549 void __iomem *base = host->base; 1550 char *ptr = buffer; 1551 u32 status = readl(host->base + MMCISTATUS); 1552 int host_remain = host->size; 1553 1554 do { 1555 int count = host->get_rx_fifocnt(host, status, host_remain); 1556 1557 if (count > remain) 1558 count = remain; 1559 1560 if (count <= 0) 1561 break; 1562 1563 /* 1564 * SDIO especially may want to send something that is 1565 * not divisible by 4 (as opposed to card sectors 1566 * etc). Therefore make sure to always read the last bytes 1567 * while only doing full 32-bit reads towards the FIFO. 1568 */ 1569 if (unlikely(count & 0x3)) { 1570 if (count < 4) { 1571 unsigned char buf[4]; 1572 ioread32_rep(base + MMCIFIFO, buf, 1); 1573 memcpy(ptr, buf, count); 1574 } else { 1575 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1576 count &= ~0x3; 1577 } 1578 } else { 1579 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1580 } 1581 1582 ptr += count; 1583 remain -= count; 1584 host_remain -= count; 1585 1586 if (remain == 0) 1587 break; 1588 1589 status = readl(base + MMCISTATUS); 1590 } while (status & MCI_RXDATAAVLBL); 1591 1592 return ptr - buffer; 1593 } 1594 1595 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1596 { 1597 struct variant_data *variant = host->variant; 1598 void __iomem *base = host->base; 1599 char *ptr = buffer; 1600 1601 do { 1602 unsigned int count, maxcnt; 1603 1604 maxcnt = status & MCI_TXFIFOEMPTY ? 1605 variant->fifosize : variant->fifohalfsize; 1606 count = min(remain, maxcnt); 1607 1608 /* 1609 * SDIO especially may want to send something that is 1610 * not divisible by 4 (as opposed to card sectors 1611 * etc), and the FIFO only accept full 32-bit writes. 1612 * So compensate by adding +3 on the count, a single 1613 * byte become a 32bit write, 7 bytes will be two 1614 * 32bit writes etc. 1615 */ 1616 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1617 1618 ptr += count; 1619 remain -= count; 1620 1621 if (remain == 0) 1622 break; 1623 1624 status = readl(base + MMCISTATUS); 1625 } while (status & MCI_TXFIFOHALFEMPTY); 1626 1627 return ptr - buffer; 1628 } 1629 1630 /* 1631 * PIO data transfer IRQ handler. 1632 */ 1633 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1634 { 1635 struct mmci_host *host = dev_id; 1636 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1637 struct variant_data *variant = host->variant; 1638 void __iomem *base = host->base; 1639 u32 status; 1640 1641 status = readl(base + MMCISTATUS); 1642 1643 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1644 1645 do { 1646 unsigned int remain, len; 1647 char *buffer; 1648 1649 /* 1650 * For write, we only need to test the half-empty flag 1651 * here - if the FIFO is completely empty, then by 1652 * definition it is more than half empty. 1653 * 1654 * For read, check for data available. 1655 */ 1656 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1657 break; 1658 1659 if (!sg_miter_next(sg_miter)) 1660 break; 1661 1662 buffer = sg_miter->addr; 1663 remain = sg_miter->length; 1664 1665 len = 0; 1666 if (status & MCI_RXACTIVE) 1667 len = mmci_pio_read(host, buffer, remain); 1668 if (status & MCI_TXACTIVE) 1669 len = mmci_pio_write(host, buffer, remain, status); 1670 1671 sg_miter->consumed = len; 1672 1673 host->size -= len; 1674 remain -= len; 1675 1676 if (remain) 1677 break; 1678 1679 status = readl(base + MMCISTATUS); 1680 } while (1); 1681 1682 sg_miter_stop(sg_miter); 1683 1684 /* 1685 * If we have less than the fifo 'half-full' threshold to transfer, 1686 * trigger a PIO interrupt as soon as any data is available. 1687 */ 1688 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1689 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1690 1691 /* 1692 * If we run out of data, disable the data IRQs; this 1693 * prevents a race where the FIFO becomes empty before 1694 * the chip itself has disabled the data path, and 1695 * stops us racing with our data end IRQ. 1696 */ 1697 if (host->size == 0) { 1698 mmci_set_mask1(host, 0); 1699 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1700 } 1701 1702 return IRQ_HANDLED; 1703 } 1704 1705 /* 1706 * Handle completion of command and data transfers. 1707 */ 1708 static irqreturn_t mmci_irq(int irq, void *dev_id) 1709 { 1710 struct mmci_host *host = dev_id; 1711 u32 status; 1712 1713 spin_lock(&host->lock); 1714 host->irq_action = IRQ_HANDLED; 1715 1716 do { 1717 status = readl(host->base + MMCISTATUS); 1718 if (!status) 1719 break; 1720 1721 if (host->singleirq) { 1722 if (status & host->mask1_reg) 1723 mmci_pio_irq(irq, dev_id); 1724 1725 status &= ~host->variant->irq_pio_mask; 1726 } 1727 1728 /* 1729 * Busy detection is managed by mmci_cmd_irq(), including to 1730 * clear the corresponding IRQ. 1731 */ 1732 status &= readl(host->base + MMCIMASK0); 1733 if (host->variant->busy_detect) 1734 writel(status & ~host->variant->busy_detect_mask, 1735 host->base + MMCICLEAR); 1736 else 1737 writel(status, host->base + MMCICLEAR); 1738 1739 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1740 1741 if (host->variant->reversed_irq_handling) { 1742 mmci_data_irq(host, host->data, status); 1743 mmci_cmd_irq(host, host->cmd, status); 1744 } else { 1745 mmci_cmd_irq(host, host->cmd, status); 1746 mmci_data_irq(host, host->data, status); 1747 } 1748 1749 /* 1750 * Busy detection has been handled by mmci_cmd_irq() above. 1751 * Clear the status bit to prevent polling in IRQ context. 1752 */ 1753 if (host->variant->busy_detect_flag) 1754 status &= ~host->variant->busy_detect_flag; 1755 1756 } while (status); 1757 1758 spin_unlock(&host->lock); 1759 1760 return host->irq_action; 1761 } 1762 1763 /* 1764 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. 1765 * 1766 * A reset is needed for some variants, where a datatimeout for a R1B request 1767 * causes the DPSM to stay busy (non-functional). 1768 */ 1769 static irqreturn_t mmci_irq_thread(int irq, void *dev_id) 1770 { 1771 struct mmci_host *host = dev_id; 1772 unsigned long flags; 1773 1774 if (host->rst) { 1775 reset_control_assert(host->rst); 1776 udelay(2); 1777 reset_control_deassert(host->rst); 1778 } 1779 1780 spin_lock_irqsave(&host->lock, flags); 1781 writel(host->clk_reg, host->base + MMCICLOCK); 1782 writel(host->pwr_reg, host->base + MMCIPOWER); 1783 writel(MCI_IRQENABLE | host->variant->start_err, 1784 host->base + MMCIMASK0); 1785 1786 host->irq_action = IRQ_HANDLED; 1787 mmci_request_end(host, host->mrq); 1788 spin_unlock_irqrestore(&host->lock, flags); 1789 1790 return host->irq_action; 1791 } 1792 1793 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1794 { 1795 struct mmci_host *host = mmc_priv(mmc); 1796 unsigned long flags; 1797 1798 WARN_ON(host->mrq != NULL); 1799 1800 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1801 if (mrq->cmd->error) { 1802 mmc_request_done(mmc, mrq); 1803 return; 1804 } 1805 1806 spin_lock_irqsave(&host->lock, flags); 1807 1808 host->mrq = mrq; 1809 1810 if (mrq->data) 1811 mmci_get_next_data(host, mrq->data); 1812 1813 if (mrq->data && 1814 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1815 mmci_start_data(host, mrq->data); 1816 1817 if (mrq->sbc) 1818 mmci_start_command(host, mrq->sbc, 0); 1819 else 1820 mmci_start_command(host, mrq->cmd, 0); 1821 1822 spin_unlock_irqrestore(&host->lock, flags); 1823 } 1824 1825 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1826 { 1827 struct mmci_host *host = mmc_priv(mmc); 1828 u32 max_busy_timeout = 0; 1829 1830 if (!host->variant->busy_detect) 1831 return; 1832 1833 if (host->variant->busy_timeout && mmc->actual_clock) 1834 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, 1835 MSEC_PER_SEC); 1836 1837 mmc->max_busy_timeout = max_busy_timeout; 1838 } 1839 1840 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1841 { 1842 struct mmci_host *host = mmc_priv(mmc); 1843 struct variant_data *variant = host->variant; 1844 u32 pwr = 0; 1845 unsigned long flags; 1846 int ret; 1847 1848 switch (ios->power_mode) { 1849 case MMC_POWER_OFF: 1850 if (!IS_ERR(mmc->supply.vmmc)) 1851 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1852 1853 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1854 regulator_disable(mmc->supply.vqmmc); 1855 host->vqmmc_enabled = false; 1856 } 1857 1858 break; 1859 case MMC_POWER_UP: 1860 if (!IS_ERR(mmc->supply.vmmc)) 1861 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1862 1863 /* 1864 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1865 * and instead uses MCI_PWR_ON so apply whatever value is 1866 * configured in the variant data. 1867 */ 1868 pwr |= variant->pwrreg_powerup; 1869 1870 break; 1871 case MMC_POWER_ON: 1872 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1873 ret = regulator_enable(mmc->supply.vqmmc); 1874 if (ret < 0) 1875 dev_err(mmc_dev(mmc), 1876 "failed to enable vqmmc regulator\n"); 1877 else 1878 host->vqmmc_enabled = true; 1879 } 1880 1881 pwr |= MCI_PWR_ON; 1882 break; 1883 } 1884 1885 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1886 /* 1887 * The ST Micro variant has some additional bits 1888 * indicating signal direction for the signals in 1889 * the SD/MMC bus and feedback-clock usage. 1890 */ 1891 pwr |= host->pwr_reg_add; 1892 1893 if (ios->bus_width == MMC_BUS_WIDTH_4) 1894 pwr &= ~MCI_ST_DATA74DIREN; 1895 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1896 pwr &= (~MCI_ST_DATA74DIREN & 1897 ~MCI_ST_DATA31DIREN & 1898 ~MCI_ST_DATA2DIREN); 1899 } 1900 1901 if (variant->opendrain) { 1902 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1903 pwr |= variant->opendrain; 1904 } else { 1905 /* 1906 * If the variant cannot configure the pads by its own, then we 1907 * expect the pinctrl to be able to do that for us 1908 */ 1909 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1910 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1911 else 1912 pinctrl_select_default_state(mmc_dev(mmc)); 1913 } 1914 1915 /* 1916 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1917 * gating the clock, the MCI_PWR_ON bit is cleared. 1918 */ 1919 if (!ios->clock && variant->pwrreg_clkgate) 1920 pwr &= ~MCI_PWR_ON; 1921 1922 if (host->variant->explicit_mclk_control && 1923 ios->clock != host->clock_cache) { 1924 ret = clk_set_rate(host->clk, ios->clock); 1925 if (ret < 0) 1926 dev_err(mmc_dev(host->mmc), 1927 "Error setting clock rate (%d)\n", ret); 1928 else 1929 host->mclk = clk_get_rate(host->clk); 1930 } 1931 host->clock_cache = ios->clock; 1932 1933 spin_lock_irqsave(&host->lock, flags); 1934 1935 if (host->ops && host->ops->set_clkreg) 1936 host->ops->set_clkreg(host, ios->clock); 1937 else 1938 mmci_set_clkreg(host, ios->clock); 1939 1940 mmci_set_max_busy_timeout(mmc); 1941 1942 if (host->ops && host->ops->set_pwrreg) 1943 host->ops->set_pwrreg(host, pwr); 1944 else 1945 mmci_write_pwrreg(host, pwr); 1946 1947 mmci_reg_delay(host); 1948 1949 spin_unlock_irqrestore(&host->lock, flags); 1950 } 1951 1952 static int mmci_get_cd(struct mmc_host *mmc) 1953 { 1954 struct mmci_host *host = mmc_priv(mmc); 1955 struct mmci_platform_data *plat = host->plat; 1956 unsigned int status = mmc_gpio_get_cd(mmc); 1957 1958 if (status == -ENOSYS) { 1959 if (!plat->status) 1960 return 1; /* Assume always present */ 1961 1962 status = plat->status(mmc_dev(host->mmc)); 1963 } 1964 return status; 1965 } 1966 1967 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1968 { 1969 struct mmci_host *host = mmc_priv(mmc); 1970 int ret; 1971 1972 ret = mmc_regulator_set_vqmmc(mmc, ios); 1973 1974 if (!ret && host->ops && host->ops->post_sig_volt_switch) 1975 ret = host->ops->post_sig_volt_switch(host, ios); 1976 else if (ret) 1977 ret = 0; 1978 1979 if (ret < 0) 1980 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1981 1982 return ret; 1983 } 1984 1985 static struct mmc_host_ops mmci_ops = { 1986 .request = mmci_request, 1987 .pre_req = mmci_pre_request, 1988 .post_req = mmci_post_request, 1989 .set_ios = mmci_set_ios, 1990 .get_ro = mmc_gpio_get_ro, 1991 .get_cd = mmci_get_cd, 1992 .start_signal_voltage_switch = mmci_sig_volt_switch, 1993 }; 1994 1995 static void mmci_probe_level_translator(struct mmc_host *mmc) 1996 { 1997 struct device *dev = mmc_dev(mmc); 1998 struct mmci_host *host = mmc_priv(mmc); 1999 struct gpio_desc *cmd_gpio; 2000 struct gpio_desc *ck_gpio; 2001 struct gpio_desc *ckin_gpio; 2002 int clk_hi, clk_lo; 2003 2004 /* 2005 * Assume the level translator is present if st,use-ckin is set. 2006 * This is to cater for DTs which do not implement this test. 2007 */ 2008 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 2009 2010 cmd_gpio = gpiod_get(dev, "st,cmd", GPIOD_OUT_HIGH); 2011 if (IS_ERR(cmd_gpio)) 2012 goto exit_cmd; 2013 2014 ck_gpio = gpiod_get(dev, "st,ck", GPIOD_OUT_HIGH); 2015 if (IS_ERR(ck_gpio)) 2016 goto exit_ck; 2017 2018 ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); 2019 if (IS_ERR(ckin_gpio)) 2020 goto exit_ckin; 2021 2022 /* All GPIOs are valid, test whether level translator works */ 2023 2024 /* Sample CKIN */ 2025 clk_hi = !!gpiod_get_value(ckin_gpio); 2026 2027 /* Set CK low */ 2028 gpiod_set_value(ck_gpio, 0); 2029 2030 /* Sample CKIN */ 2031 clk_lo = !!gpiod_get_value(ckin_gpio); 2032 2033 /* Tristate all */ 2034 gpiod_direction_input(cmd_gpio); 2035 gpiod_direction_input(ck_gpio); 2036 2037 /* Level translator is present if CK signal is propagated to CKIN */ 2038 if (!clk_hi || clk_lo) { 2039 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; 2040 dev_warn(dev, 2041 "Level translator inoperable, CK signal not detected on CKIN, disabling.\n"); 2042 } 2043 2044 gpiod_put(ckin_gpio); 2045 2046 exit_ckin: 2047 gpiod_put(ck_gpio); 2048 exit_ck: 2049 gpiod_put(cmd_gpio); 2050 exit_cmd: 2051 pinctrl_select_default_state(dev); 2052 } 2053 2054 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 2055 { 2056 struct mmci_host *host = mmc_priv(mmc); 2057 int ret = mmc_of_parse(mmc); 2058 2059 if (ret) 2060 return ret; 2061 2062 if (of_property_read_bool(np, "st,sig-dir-dat0")) 2063 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 2064 if (of_property_read_bool(np, "st,sig-dir-dat2")) 2065 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 2066 if (of_property_read_bool(np, "st,sig-dir-dat31")) 2067 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 2068 if (of_property_read_bool(np, "st,sig-dir-dat74")) 2069 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 2070 if (of_property_read_bool(np, "st,sig-dir-cmd")) 2071 host->pwr_reg_add |= MCI_ST_CMDDIREN; 2072 if (of_property_read_bool(np, "st,sig-pin-fbclk")) 2073 host->pwr_reg_add |= MCI_ST_FBCLKEN; 2074 if (of_property_read_bool(np, "st,sig-dir")) 2075 host->pwr_reg_add |= MCI_STM32_DIRPOL; 2076 if (of_property_read_bool(np, "st,neg-edge")) 2077 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 2078 if (of_property_read_bool(np, "st,use-ckin")) 2079 mmci_probe_level_translator(mmc); 2080 2081 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) 2082 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 2083 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) 2084 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2085 2086 return 0; 2087 } 2088 2089 static int mmci_probe(struct amba_device *dev, 2090 const struct amba_id *id) 2091 { 2092 struct mmci_platform_data *plat = dev->dev.platform_data; 2093 struct device_node *np = dev->dev.of_node; 2094 struct variant_data *variant = id->data; 2095 struct mmci_host *host; 2096 struct mmc_host *mmc; 2097 int ret; 2098 2099 /* Must have platform data or Device Tree. */ 2100 if (!plat && !np) { 2101 dev_err(&dev->dev, "No plat data or DT found\n"); 2102 return -EINVAL; 2103 } 2104 2105 if (!plat) { 2106 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 2107 if (!plat) 2108 return -ENOMEM; 2109 } 2110 2111 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 2112 if (!mmc) 2113 return -ENOMEM; 2114 2115 host = mmc_priv(mmc); 2116 host->mmc = mmc; 2117 host->mmc_ops = &mmci_ops; 2118 mmc->ops = &mmci_ops; 2119 2120 ret = mmci_of_parse(np, mmc); 2121 if (ret) 2122 goto host_free; 2123 2124 /* 2125 * Some variant (STM32) doesn't have opendrain bit, nevertheless 2126 * pins can be set accordingly using pinctrl 2127 */ 2128 if (!variant->opendrain) { 2129 host->pinctrl = devm_pinctrl_get(&dev->dev); 2130 if (IS_ERR(host->pinctrl)) { 2131 dev_err(&dev->dev, "failed to get pinctrl"); 2132 ret = PTR_ERR(host->pinctrl); 2133 goto host_free; 2134 } 2135 2136 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 2137 MMCI_PINCTRL_STATE_OPENDRAIN); 2138 if (IS_ERR(host->pins_opendrain)) { 2139 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 2140 ret = PTR_ERR(host->pins_opendrain); 2141 goto host_free; 2142 } 2143 } 2144 2145 host->hw_designer = amba_manf(dev); 2146 host->hw_revision = amba_rev(dev); 2147 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 2148 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 2149 2150 host->clk = devm_clk_get(&dev->dev, NULL); 2151 if (IS_ERR(host->clk)) { 2152 ret = PTR_ERR(host->clk); 2153 goto host_free; 2154 } 2155 2156 ret = clk_prepare_enable(host->clk); 2157 if (ret) 2158 goto host_free; 2159 2160 if (variant->qcom_fifo) 2161 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 2162 else 2163 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 2164 2165 host->plat = plat; 2166 host->variant = variant; 2167 host->mclk = clk_get_rate(host->clk); 2168 /* 2169 * According to the spec, mclk is max 100 MHz, 2170 * so we try to adjust the clock down to this, 2171 * (if possible). 2172 */ 2173 if (host->mclk > variant->f_max) { 2174 ret = clk_set_rate(host->clk, variant->f_max); 2175 if (ret < 0) 2176 goto clk_disable; 2177 host->mclk = clk_get_rate(host->clk); 2178 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 2179 host->mclk); 2180 } 2181 2182 host->phybase = dev->res.start; 2183 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 2184 if (IS_ERR(host->base)) { 2185 ret = PTR_ERR(host->base); 2186 goto clk_disable; 2187 } 2188 2189 if (variant->init) 2190 variant->init(host); 2191 2192 /* 2193 * The ARM and ST versions of the block have slightly different 2194 * clock divider equations which means that the minimum divider 2195 * differs too. 2196 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 2197 */ 2198 if (variant->st_clkdiv) 2199 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 2200 else if (variant->stm32_clkdiv) 2201 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 2202 else if (variant->explicit_mclk_control) 2203 mmc->f_min = clk_round_rate(host->clk, 100000); 2204 else 2205 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 2206 /* 2207 * If no maximum operating frequency is supplied, fall back to use 2208 * the module parameter, which has a (low) default value in case it 2209 * is not specified. Either value must not exceed the clock rate into 2210 * the block, of course. 2211 */ 2212 if (mmc->f_max) 2213 mmc->f_max = variant->explicit_mclk_control ? 2214 min(variant->f_max, mmc->f_max) : 2215 min(host->mclk, mmc->f_max); 2216 else 2217 mmc->f_max = variant->explicit_mclk_control ? 2218 fmax : min(host->mclk, fmax); 2219 2220 2221 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 2222 2223 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 2224 if (IS_ERR(host->rst)) { 2225 ret = PTR_ERR(host->rst); 2226 goto clk_disable; 2227 } 2228 ret = reset_control_deassert(host->rst); 2229 if (ret) 2230 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); 2231 2232 /* Get regulators and the supported OCR mask */ 2233 ret = mmc_regulator_get_supply(mmc); 2234 if (ret) 2235 goto clk_disable; 2236 2237 if (!mmc->ocr_avail) 2238 mmc->ocr_avail = plat->ocr_mask; 2239 else if (plat->ocr_mask) 2240 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 2241 2242 /* We support these capabilities. */ 2243 mmc->caps |= MMC_CAP_CMD23; 2244 2245 /* 2246 * Enable busy detection. 2247 */ 2248 if (variant->busy_detect) { 2249 mmci_ops.card_busy = mmci_card_busy; 2250 /* 2251 * Not all variants have a flag to enable busy detection 2252 * in the DPSM, but if they do, set it here. 2253 */ 2254 if (variant->busy_dpsm_flag) 2255 mmci_write_datactrlreg(host, 2256 host->variant->busy_dpsm_flag); 2257 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2258 } 2259 2260 /* Variants with mandatory busy timeout in HW needs R1B responses. */ 2261 if (variant->busy_timeout) 2262 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 2263 2264 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2265 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2266 host->stop_abort.arg = 0; 2267 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2268 2269 /* We support these PM capabilities. */ 2270 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2271 2272 /* 2273 * We can do SGIO 2274 */ 2275 mmc->max_segs = NR_SG; 2276 2277 /* 2278 * Since only a certain number of bits are valid in the data length 2279 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2280 * single request. 2281 */ 2282 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2283 2284 /* 2285 * Set the maximum segment size. Since we aren't doing DMA 2286 * (yet) we are only limited by the data length register. 2287 */ 2288 mmc->max_seg_size = mmc->max_req_size; 2289 2290 /* 2291 * Block size can be up to 2048 bytes, but must be a power of two. 2292 */ 2293 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2294 2295 /* 2296 * Limit the number of blocks transferred so that we don't overflow 2297 * the maximum request size. 2298 */ 2299 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2300 2301 spin_lock_init(&host->lock); 2302 2303 writel(0, host->base + MMCIMASK0); 2304 2305 if (variant->mmcimask1) 2306 writel(0, host->base + MMCIMASK1); 2307 2308 writel(0xfff, host->base + MMCICLEAR); 2309 2310 /* 2311 * If: 2312 * - not using DT but using a descriptor table, or 2313 * - using a table of descriptors ALONGSIDE DT, or 2314 * look up these descriptors named "cd" and "wp" right here, fail 2315 * silently of these do not exist 2316 */ 2317 if (!np) { 2318 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 2319 if (ret == -EPROBE_DEFER) 2320 goto clk_disable; 2321 2322 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 2323 if (ret == -EPROBE_DEFER) 2324 goto clk_disable; 2325 } 2326 2327 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, 2328 mmci_irq_thread, IRQF_SHARED, 2329 DRIVER_NAME " (cmd)", host); 2330 if (ret) 2331 goto clk_disable; 2332 2333 if (!dev->irq[1]) 2334 host->singleirq = true; 2335 else { 2336 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2337 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2338 if (ret) 2339 goto clk_disable; 2340 } 2341 2342 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2343 2344 amba_set_drvdata(dev, mmc); 2345 2346 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2347 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2348 amba_rev(dev), (unsigned long long)dev->res.start, 2349 dev->irq[0], dev->irq[1]); 2350 2351 mmci_dma_setup(host); 2352 2353 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2354 pm_runtime_use_autosuspend(&dev->dev); 2355 2356 ret = mmc_add_host(mmc); 2357 if (ret) 2358 goto clk_disable; 2359 2360 pm_runtime_put(&dev->dev); 2361 return 0; 2362 2363 clk_disable: 2364 clk_disable_unprepare(host->clk); 2365 host_free: 2366 mmc_free_host(mmc); 2367 return ret; 2368 } 2369 2370 static void mmci_remove(struct amba_device *dev) 2371 { 2372 struct mmc_host *mmc = amba_get_drvdata(dev); 2373 2374 if (mmc) { 2375 struct mmci_host *host = mmc_priv(mmc); 2376 struct variant_data *variant = host->variant; 2377 2378 /* 2379 * Undo pm_runtime_put() in probe. We use the _sync 2380 * version here so that we can access the primecell. 2381 */ 2382 pm_runtime_get_sync(&dev->dev); 2383 2384 mmc_remove_host(mmc); 2385 2386 writel(0, host->base + MMCIMASK0); 2387 2388 if (variant->mmcimask1) 2389 writel(0, host->base + MMCIMASK1); 2390 2391 writel(0, host->base + MMCICOMMAND); 2392 writel(0, host->base + MMCIDATACTRL); 2393 2394 mmci_dma_release(host); 2395 clk_disable_unprepare(host->clk); 2396 mmc_free_host(mmc); 2397 } 2398 } 2399 2400 #ifdef CONFIG_PM 2401 static void mmci_save(struct mmci_host *host) 2402 { 2403 unsigned long flags; 2404 2405 spin_lock_irqsave(&host->lock, flags); 2406 2407 writel(0, host->base + MMCIMASK0); 2408 if (host->variant->pwrreg_nopower) { 2409 writel(0, host->base + MMCIDATACTRL); 2410 writel(0, host->base + MMCIPOWER); 2411 writel(0, host->base + MMCICLOCK); 2412 } 2413 mmci_reg_delay(host); 2414 2415 spin_unlock_irqrestore(&host->lock, flags); 2416 } 2417 2418 static void mmci_restore(struct mmci_host *host) 2419 { 2420 unsigned long flags; 2421 2422 spin_lock_irqsave(&host->lock, flags); 2423 2424 if (host->variant->pwrreg_nopower) { 2425 writel(host->clk_reg, host->base + MMCICLOCK); 2426 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2427 writel(host->pwr_reg, host->base + MMCIPOWER); 2428 } 2429 writel(MCI_IRQENABLE | host->variant->start_err, 2430 host->base + MMCIMASK0); 2431 mmci_reg_delay(host); 2432 2433 spin_unlock_irqrestore(&host->lock, flags); 2434 } 2435 2436 static int mmci_runtime_suspend(struct device *dev) 2437 { 2438 struct amba_device *adev = to_amba_device(dev); 2439 struct mmc_host *mmc = amba_get_drvdata(adev); 2440 2441 if (mmc) { 2442 struct mmci_host *host = mmc_priv(mmc); 2443 pinctrl_pm_select_sleep_state(dev); 2444 mmci_save(host); 2445 clk_disable_unprepare(host->clk); 2446 } 2447 2448 return 0; 2449 } 2450 2451 static int mmci_runtime_resume(struct device *dev) 2452 { 2453 struct amba_device *adev = to_amba_device(dev); 2454 struct mmc_host *mmc = amba_get_drvdata(adev); 2455 2456 if (mmc) { 2457 struct mmci_host *host = mmc_priv(mmc); 2458 clk_prepare_enable(host->clk); 2459 mmci_restore(host); 2460 pinctrl_select_default_state(dev); 2461 } 2462 2463 return 0; 2464 } 2465 #endif 2466 2467 static const struct dev_pm_ops mmci_dev_pm_ops = { 2468 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2469 pm_runtime_force_resume) 2470 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2471 }; 2472 2473 static const struct amba_id mmci_ids[] = { 2474 { 2475 .id = 0x00041180, 2476 .mask = 0xff0fffff, 2477 .data = &variant_arm, 2478 }, 2479 { 2480 .id = 0x01041180, 2481 .mask = 0xff0fffff, 2482 .data = &variant_arm_extended_fifo, 2483 }, 2484 { 2485 .id = 0x02041180, 2486 .mask = 0xff0fffff, 2487 .data = &variant_arm_extended_fifo_hwfc, 2488 }, 2489 { 2490 .id = 0x00041181, 2491 .mask = 0x000fffff, 2492 .data = &variant_arm, 2493 }, 2494 /* ST Micro variants */ 2495 { 2496 .id = 0x00180180, 2497 .mask = 0x00ffffff, 2498 .data = &variant_u300, 2499 }, 2500 { 2501 .id = 0x10180180, 2502 .mask = 0xf0ffffff, 2503 .data = &variant_nomadik, 2504 }, 2505 { 2506 .id = 0x00280180, 2507 .mask = 0x00ffffff, 2508 .data = &variant_nomadik, 2509 }, 2510 { 2511 .id = 0x00480180, 2512 .mask = 0xf0ffffff, 2513 .data = &variant_ux500, 2514 }, 2515 { 2516 .id = 0x10480180, 2517 .mask = 0xf0ffffff, 2518 .data = &variant_ux500v2, 2519 }, 2520 { 2521 .id = 0x00880180, 2522 .mask = 0x00ffffff, 2523 .data = &variant_stm32, 2524 }, 2525 { 2526 .id = 0x10153180, 2527 .mask = 0xf0ffffff, 2528 .data = &variant_stm32_sdmmc, 2529 }, 2530 { 2531 .id = 0x00253180, 2532 .mask = 0xf0ffffff, 2533 .data = &variant_stm32_sdmmcv2, 2534 }, 2535 { 2536 .id = 0x20253180, 2537 .mask = 0xf0ffffff, 2538 .data = &variant_stm32_sdmmcv2, 2539 }, 2540 { 2541 .id = 0x00353180, 2542 .mask = 0xf0ffffff, 2543 .data = &variant_stm32_sdmmcv3, 2544 }, 2545 /* Qualcomm variants */ 2546 { 2547 .id = 0x00051180, 2548 .mask = 0x000fffff, 2549 .data = &variant_qcom, 2550 }, 2551 { 0, 0 }, 2552 }; 2553 2554 MODULE_DEVICE_TABLE(amba, mmci_ids); 2555 2556 static struct amba_driver mmci_driver = { 2557 .drv = { 2558 .name = DRIVER_NAME, 2559 .pm = &mmci_dev_pm_ops, 2560 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2561 }, 2562 .probe = mmci_probe, 2563 .remove = mmci_remove, 2564 .id_table = mmci_ids, 2565 }; 2566 2567 module_amba_driver(mmci_driver); 2568 2569 module_param(fmax, uint, 0444); 2570 2571 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2572 MODULE_LICENSE("GPL"); 2573