1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/of.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/gpio/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 static void mmci_variant_init(struct mmci_host *host); 49 static void ux500_variant_init(struct mmci_host *host); 50 static void ux500v2_variant_init(struct mmci_host *host); 51 52 static unsigned int fmax = 515633; 53 54 static struct variant_data variant_arm = { 55 .fifosize = 16 * 4, 56 .fifohalfsize = 8 * 4, 57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 60 .cmdreg_srsp = MCI_CPSM_RESPONSE, 61 .datalength_bits = 16, 62 .datactrl_blocksz = 11, 63 .pwrreg_powerup = MCI_PWR_UP, 64 .f_max = 100000000, 65 .reversed_irq_handling = true, 66 .mmcimask1 = true, 67 .irq_pio_mask = MCI_IRQ_PIO_MASK, 68 .start_err = MCI_STARTBITERR, 69 .opendrain = MCI_ROD, 70 .init = mmci_variant_init, 71 }; 72 73 static struct variant_data variant_arm_extended_fifo = { 74 .fifosize = 128 * 4, 75 .fifohalfsize = 64 * 4, 76 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 77 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 78 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 79 .cmdreg_srsp = MCI_CPSM_RESPONSE, 80 .datalength_bits = 16, 81 .datactrl_blocksz = 11, 82 .pwrreg_powerup = MCI_PWR_UP, 83 .f_max = 100000000, 84 .mmcimask1 = true, 85 .irq_pio_mask = MCI_IRQ_PIO_MASK, 86 .start_err = MCI_STARTBITERR, 87 .opendrain = MCI_ROD, 88 .init = mmci_variant_init, 89 }; 90 91 static struct variant_data variant_arm_extended_fifo_hwfc = { 92 .fifosize = 128 * 4, 93 .fifohalfsize = 64 * 4, 94 .clkreg_enable = MCI_ARM_HWFCEN, 95 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 96 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 97 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 98 .cmdreg_srsp = MCI_CPSM_RESPONSE, 99 .datalength_bits = 16, 100 .datactrl_blocksz = 11, 101 .pwrreg_powerup = MCI_PWR_UP, 102 .f_max = 100000000, 103 .mmcimask1 = true, 104 .irq_pio_mask = MCI_IRQ_PIO_MASK, 105 .start_err = MCI_STARTBITERR, 106 .opendrain = MCI_ROD, 107 .init = mmci_variant_init, 108 }; 109 110 static struct variant_data variant_u300 = { 111 .fifosize = 16 * 4, 112 .fifohalfsize = 8 * 4, 113 .clkreg_enable = MCI_ST_U300_HWFCEN, 114 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 115 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 116 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 117 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 118 .cmdreg_srsp = MCI_CPSM_RESPONSE, 119 .datalength_bits = 16, 120 .datactrl_blocksz = 11, 121 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 122 .st_sdio = true, 123 .pwrreg_powerup = MCI_PWR_ON, 124 .f_max = 100000000, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128 .mmcimask1 = true, 129 .irq_pio_mask = MCI_IRQ_PIO_MASK, 130 .start_err = MCI_STARTBITERR, 131 .opendrain = MCI_OD, 132 .init = mmci_variant_init, 133 }; 134 135 static struct variant_data variant_nomadik = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg = MCI_CLK_ENABLE, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 141 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 142 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 143 .cmdreg_srsp = MCI_CPSM_RESPONSE, 144 .datalength_bits = 24, 145 .datactrl_blocksz = 11, 146 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 147 .st_sdio = true, 148 .st_clkdiv = true, 149 .pwrreg_powerup = MCI_PWR_ON, 150 .f_max = 100000000, 151 .signal_direction = true, 152 .pwrreg_clkgate = true, 153 .pwrreg_nopower = true, 154 .mmcimask1 = true, 155 .irq_pio_mask = MCI_IRQ_PIO_MASK, 156 .start_err = MCI_STARTBITERR, 157 .opendrain = MCI_OD, 158 .init = mmci_variant_init, 159 }; 160 161 static struct variant_data variant_ux500 = { 162 .fifosize = 30 * 4, 163 .fifohalfsize = 8 * 4, 164 .clkreg = MCI_CLK_ENABLE, 165 .clkreg_enable = MCI_ST_UX500_HWFCEN, 166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 168 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 169 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 170 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 171 .cmdreg_srsp = MCI_CPSM_RESPONSE, 172 .datalength_bits = 24, 173 .datactrl_blocksz = 11, 174 .datactrl_any_blocksz = true, 175 .dma_power_of_2 = true, 176 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 177 .st_sdio = true, 178 .st_clkdiv = true, 179 .pwrreg_powerup = MCI_PWR_ON, 180 .f_max = 100000000, 181 .signal_direction = true, 182 .pwrreg_clkgate = true, 183 .busy_detect = true, 184 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 185 .busy_detect_flag = MCI_ST_CARDBUSY, 186 .busy_detect_mask = MCI_ST_BUSYENDMASK, 187 .pwrreg_nopower = true, 188 .mmcimask1 = true, 189 .irq_pio_mask = MCI_IRQ_PIO_MASK, 190 .start_err = MCI_STARTBITERR, 191 .opendrain = MCI_OD, 192 .init = ux500_variant_init, 193 }; 194 195 static struct variant_data variant_ux500v2 = { 196 .fifosize = 30 * 4, 197 .fifohalfsize = 8 * 4, 198 .clkreg = MCI_CLK_ENABLE, 199 .clkreg_enable = MCI_ST_UX500_HWFCEN, 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 202 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 203 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 204 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 205 .cmdreg_srsp = MCI_CPSM_RESPONSE, 206 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 207 .datalength_bits = 24, 208 .datactrl_blocksz = 11, 209 .datactrl_any_blocksz = true, 210 .dma_power_of_2 = true, 211 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 212 .st_sdio = true, 213 .st_clkdiv = true, 214 .pwrreg_powerup = MCI_PWR_ON, 215 .f_max = 100000000, 216 .signal_direction = true, 217 .pwrreg_clkgate = true, 218 .busy_detect = true, 219 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 220 .busy_detect_flag = MCI_ST_CARDBUSY, 221 .busy_detect_mask = MCI_ST_BUSYENDMASK, 222 .pwrreg_nopower = true, 223 .mmcimask1 = true, 224 .irq_pio_mask = MCI_IRQ_PIO_MASK, 225 .start_err = MCI_STARTBITERR, 226 .opendrain = MCI_OD, 227 .init = ux500v2_variant_init, 228 }; 229 230 static struct variant_data variant_stm32 = { 231 .fifosize = 32 * 4, 232 .fifohalfsize = 8 * 4, 233 .clkreg = MCI_CLK_ENABLE, 234 .clkreg_enable = MCI_ST_UX500_HWFCEN, 235 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 236 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 237 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 238 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 239 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 240 .cmdreg_srsp = MCI_CPSM_RESPONSE, 241 .irq_pio_mask = MCI_IRQ_PIO_MASK, 242 .datalength_bits = 24, 243 .datactrl_blocksz = 11, 244 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 245 .st_sdio = true, 246 .st_clkdiv = true, 247 .pwrreg_powerup = MCI_PWR_ON, 248 .f_max = 48000000, 249 .pwrreg_clkgate = true, 250 .pwrreg_nopower = true, 251 .init = mmci_variant_init, 252 }; 253 254 static struct variant_data variant_stm32_sdmmc = { 255 .fifosize = 16 * 4, 256 .fifohalfsize = 8 * 4, 257 .f_max = 208000000, 258 .stm32_clkdiv = true, 259 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 260 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 261 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 262 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 263 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 264 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 265 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 266 .datactrl_first = true, 267 .datacnt_useless = true, 268 .datalength_bits = 25, 269 .datactrl_blocksz = 14, 270 .datactrl_any_blocksz = true, 271 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 272 .stm32_idmabsize_mask = GENMASK(12, 5), 273 .busy_timeout = true, 274 .busy_detect = true, 275 .busy_detect_flag = MCI_STM32_BUSYD0, 276 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 277 .init = sdmmc_variant_init, 278 }; 279 280 static struct variant_data variant_stm32_sdmmcv2 = { 281 .fifosize = 16 * 4, 282 .fifohalfsize = 8 * 4, 283 .f_max = 267000000, 284 .stm32_clkdiv = true, 285 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 286 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 287 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 288 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 289 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 290 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 291 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 292 .datactrl_first = true, 293 .datacnt_useless = true, 294 .datalength_bits = 25, 295 .datactrl_blocksz = 14, 296 .datactrl_any_blocksz = true, 297 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 298 .stm32_idmabsize_mask = GENMASK(16, 5), 299 .dma_lli = true, 300 .busy_timeout = true, 301 .busy_detect = true, 302 .busy_detect_flag = MCI_STM32_BUSYD0, 303 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 304 .init = sdmmc_variant_init, 305 }; 306 307 static struct variant_data variant_qcom = { 308 .fifosize = 16 * 4, 309 .fifohalfsize = 8 * 4, 310 .clkreg = MCI_CLK_ENABLE, 311 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 312 MCI_QCOM_CLK_SELECT_IN_FBCLK, 313 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 314 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 315 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 316 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 317 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 318 .cmdreg_srsp = MCI_CPSM_RESPONSE, 319 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 320 .datalength_bits = 24, 321 .datactrl_blocksz = 11, 322 .datactrl_any_blocksz = true, 323 .pwrreg_powerup = MCI_PWR_UP, 324 .f_max = 208000000, 325 .explicit_mclk_control = true, 326 .qcom_fifo = true, 327 .qcom_dml = true, 328 .mmcimask1 = true, 329 .irq_pio_mask = MCI_IRQ_PIO_MASK, 330 .start_err = MCI_STARTBITERR, 331 .opendrain = MCI_ROD, 332 .init = qcom_variant_init, 333 }; 334 335 /* Busy detection for the ST Micro variant */ 336 static int mmci_card_busy(struct mmc_host *mmc) 337 { 338 struct mmci_host *host = mmc_priv(mmc); 339 unsigned long flags; 340 int busy = 0; 341 342 spin_lock_irqsave(&host->lock, flags); 343 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 344 busy = 1; 345 spin_unlock_irqrestore(&host->lock, flags); 346 347 return busy; 348 } 349 350 static void mmci_reg_delay(struct mmci_host *host) 351 { 352 /* 353 * According to the spec, at least three feedback clock cycles 354 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 355 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 356 * Worst delay time during card init is at 100 kHz => 30 us. 357 * Worst delay time when up and running is at 25 MHz => 120 ns. 358 */ 359 if (host->cclk < 25000000) 360 udelay(30); 361 else 362 ndelay(120); 363 } 364 365 /* 366 * This must be called with host->lock held 367 */ 368 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 369 { 370 if (host->clk_reg != clk) { 371 host->clk_reg = clk; 372 writel(clk, host->base + MMCICLOCK); 373 } 374 } 375 376 /* 377 * This must be called with host->lock held 378 */ 379 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 380 { 381 if (host->pwr_reg != pwr) { 382 host->pwr_reg = pwr; 383 writel(pwr, host->base + MMCIPOWER); 384 } 385 } 386 387 /* 388 * This must be called with host->lock held 389 */ 390 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 391 { 392 /* Keep busy mode in DPSM if enabled */ 393 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 394 395 if (host->datactrl_reg != datactrl) { 396 host->datactrl_reg = datactrl; 397 writel(datactrl, host->base + MMCIDATACTRL); 398 } 399 } 400 401 /* 402 * This must be called with host->lock held 403 */ 404 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 405 { 406 struct variant_data *variant = host->variant; 407 u32 clk = variant->clkreg; 408 409 /* Make sure cclk reflects the current calculated clock */ 410 host->cclk = 0; 411 412 if (desired) { 413 if (variant->explicit_mclk_control) { 414 host->cclk = host->mclk; 415 } else if (desired >= host->mclk) { 416 clk = MCI_CLK_BYPASS; 417 if (variant->st_clkdiv) 418 clk |= MCI_ST_UX500_NEG_EDGE; 419 host->cclk = host->mclk; 420 } else if (variant->st_clkdiv) { 421 /* 422 * DB8500 TRM says f = mclk / (clkdiv + 2) 423 * => clkdiv = (mclk / f) - 2 424 * Round the divider up so we don't exceed the max 425 * frequency 426 */ 427 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 428 if (clk >= 256) 429 clk = 255; 430 host->cclk = host->mclk / (clk + 2); 431 } else { 432 /* 433 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 434 * => clkdiv = mclk / (2 * f) - 1 435 */ 436 clk = host->mclk / (2 * desired) - 1; 437 if (clk >= 256) 438 clk = 255; 439 host->cclk = host->mclk / (2 * (clk + 1)); 440 } 441 442 clk |= variant->clkreg_enable; 443 clk |= MCI_CLK_ENABLE; 444 /* This hasn't proven to be worthwhile */ 445 /* clk |= MCI_CLK_PWRSAVE; */ 446 } 447 448 /* Set actual clock for debug */ 449 host->mmc->actual_clock = host->cclk; 450 451 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 452 clk |= MCI_4BIT_BUS; 453 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 454 clk |= variant->clkreg_8bit_bus_enable; 455 456 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 457 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 458 clk |= variant->clkreg_neg_edge_enable; 459 460 mmci_write_clkreg(host, clk); 461 } 462 463 static void mmci_dma_release(struct mmci_host *host) 464 { 465 if (host->ops && host->ops->dma_release) 466 host->ops->dma_release(host); 467 468 host->use_dma = false; 469 } 470 471 static void mmci_dma_setup(struct mmci_host *host) 472 { 473 if (!host->ops || !host->ops->dma_setup) 474 return; 475 476 if (host->ops->dma_setup(host)) 477 return; 478 479 /* initialize pre request cookie */ 480 host->next_cookie = 1; 481 482 host->use_dma = true; 483 } 484 485 /* 486 * Validate mmc prerequisites 487 */ 488 static int mmci_validate_data(struct mmci_host *host, 489 struct mmc_data *data) 490 { 491 struct variant_data *variant = host->variant; 492 493 if (!data) 494 return 0; 495 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { 496 dev_err(mmc_dev(host->mmc), 497 "unsupported block size (%d bytes)\n", data->blksz); 498 return -EINVAL; 499 } 500 501 if (host->ops && host->ops->validate_data) 502 return host->ops->validate_data(host, data); 503 504 return 0; 505 } 506 507 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 508 { 509 int err; 510 511 if (!host->ops || !host->ops->prep_data) 512 return 0; 513 514 err = host->ops->prep_data(host, data, next); 515 516 if (next && !err) 517 data->host_cookie = ++host->next_cookie < 0 ? 518 1 : host->next_cookie; 519 520 return err; 521 } 522 523 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 524 int err) 525 { 526 if (host->ops && host->ops->unprep_data) 527 host->ops->unprep_data(host, data, err); 528 529 data->host_cookie = 0; 530 } 531 532 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 533 { 534 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 535 536 if (host->ops && host->ops->get_next_data) 537 host->ops->get_next_data(host, data); 538 } 539 540 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 541 { 542 struct mmc_data *data = host->data; 543 int ret; 544 545 if (!host->use_dma) 546 return -EINVAL; 547 548 ret = mmci_prep_data(host, data, false); 549 if (ret) 550 return ret; 551 552 if (!host->ops || !host->ops->dma_start) 553 return -EINVAL; 554 555 /* Okay, go for it. */ 556 dev_vdbg(mmc_dev(host->mmc), 557 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 558 data->sg_len, data->blksz, data->blocks, data->flags); 559 560 ret = host->ops->dma_start(host, &datactrl); 561 if (ret) 562 return ret; 563 564 /* Trigger the DMA transfer */ 565 mmci_write_datactrlreg(host, datactrl); 566 567 /* 568 * Let the MMCI say when the data is ended and it's time 569 * to fire next DMA request. When that happens, MMCI will 570 * call mmci_data_end() 571 */ 572 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 573 host->base + MMCIMASK0); 574 return 0; 575 } 576 577 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 578 { 579 if (!host->use_dma) 580 return; 581 582 if (host->ops && host->ops->dma_finalize) 583 host->ops->dma_finalize(host, data); 584 } 585 586 static void mmci_dma_error(struct mmci_host *host) 587 { 588 if (!host->use_dma) 589 return; 590 591 if (host->ops && host->ops->dma_error) 592 host->ops->dma_error(host); 593 } 594 595 static void 596 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 597 { 598 writel(0, host->base + MMCICOMMAND); 599 600 BUG_ON(host->data); 601 602 host->mrq = NULL; 603 host->cmd = NULL; 604 605 mmc_request_done(host->mmc, mrq); 606 } 607 608 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 609 { 610 void __iomem *base = host->base; 611 struct variant_data *variant = host->variant; 612 613 if (host->singleirq) { 614 unsigned int mask0 = readl(base + MMCIMASK0); 615 616 mask0 &= ~variant->irq_pio_mask; 617 mask0 |= mask; 618 619 writel(mask0, base + MMCIMASK0); 620 } 621 622 if (variant->mmcimask1) 623 writel(mask, base + MMCIMASK1); 624 625 host->mask1_reg = mask; 626 } 627 628 static void mmci_stop_data(struct mmci_host *host) 629 { 630 mmci_write_datactrlreg(host, 0); 631 mmci_set_mask1(host, 0); 632 host->data = NULL; 633 } 634 635 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 636 { 637 unsigned int flags = SG_MITER_ATOMIC; 638 639 if (data->flags & MMC_DATA_READ) 640 flags |= SG_MITER_TO_SG; 641 else 642 flags |= SG_MITER_FROM_SG; 643 644 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 645 } 646 647 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 648 { 649 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 650 } 651 652 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 653 { 654 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 655 } 656 657 /* 658 * ux500_busy_complete() - this will wait until the busy status 659 * goes off, saving any status that occur in the meantime into 660 * host->busy_status until we know the card is not busy any more. 661 * The function returns true when the busy detection is ended 662 * and we should continue processing the command. 663 * 664 * The Ux500 typically fires two IRQs over a busy cycle like this: 665 * 666 * DAT0 busy +-----------------+ 667 * | | 668 * DAT0 not busy ----+ +-------- 669 * 670 * ^ ^ 671 * | | 672 * IRQ1 IRQ2 673 */ 674 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 675 { 676 void __iomem *base = host->base; 677 678 if (status & err_msk) { 679 /* Stop any ongoing busy detection if an error occurs */ 680 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 681 writel(readl(base + MMCIMASK0) & 682 ~host->variant->busy_detect_mask, base + MMCIMASK0); 683 host->busy_status = 0; 684 return true; 685 } 686 687 /* 688 * Before unmasking for the busy end IRQ, confirm that the 689 * command was sent successfully. To keep track of having a 690 * command in-progress, waiting for busy signaling to end, 691 * store the status in host->busy_status. 692 * 693 * Note that, the card may need a couple of clock cycles before 694 * it starts signaling busy on DAT0, hence re-read the 695 * MMCISTATUS register here, to allow the busy bit to be set. 696 * Potentially we may even need to poll the register for a 697 * while, to allow it to be set, but tests indicates that it 698 * isn't needed. 699 */ 700 if (!host->busy_status) { 701 status = readl(base + MMCISTATUS); 702 if (status & host->variant->busy_detect_flag) { 703 writel(readl(base + MMCIMASK0) | 704 host->variant->busy_detect_mask, 705 base + MMCIMASK0); 706 707 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 708 return false; 709 } 710 } 711 712 /* 713 * If there is a command in-progress that has been successfully 714 * sent, then bail out if busy status is set and wait for the 715 * busy end IRQ. 716 * 717 * Note that, the HW triggers an IRQ on both edges while 718 * monitoring DAT0 for busy completion, but there is only one 719 * status bit in MMCISTATUS for the busy state. Therefore 720 * both the start and the end interrupts needs to be cleared, 721 * one after the other. So, clear the busy start IRQ here. 722 */ 723 if (host->busy_status && 724 (status & host->variant->busy_detect_flag)) { 725 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 726 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 727 return false; 728 } 729 730 /* 731 * If there is a command in-progress that has been successfully 732 * sent and the busy bit isn't set, it means we have received 733 * the busy end IRQ. Clear and mask the IRQ, then continue to 734 * process the command. 735 */ 736 if (host->busy_status) { 737 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 738 739 writel(readl(base + MMCIMASK0) & 740 ~host->variant->busy_detect_mask, base + MMCIMASK0); 741 host->busy_status = 0; 742 } 743 744 return true; 745 } 746 747 /* 748 * All the DMA operation mode stuff goes inside this ifdef. 749 * This assumes that you have a generic DMA device interface, 750 * no custom DMA interfaces are supported. 751 */ 752 #ifdef CONFIG_DMA_ENGINE 753 struct mmci_dmae_next { 754 struct dma_async_tx_descriptor *desc; 755 struct dma_chan *chan; 756 }; 757 758 struct mmci_dmae_priv { 759 struct dma_chan *cur; 760 struct dma_chan *rx_channel; 761 struct dma_chan *tx_channel; 762 struct dma_async_tx_descriptor *desc_current; 763 struct mmci_dmae_next next_data; 764 }; 765 766 int mmci_dmae_setup(struct mmci_host *host) 767 { 768 const char *rxname, *txname; 769 struct mmci_dmae_priv *dmae; 770 771 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 772 if (!dmae) 773 return -ENOMEM; 774 775 host->dma_priv = dmae; 776 777 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); 778 if (IS_ERR(dmae->rx_channel)) { 779 int ret = PTR_ERR(dmae->rx_channel); 780 dmae->rx_channel = NULL; 781 return ret; 782 } 783 784 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); 785 if (IS_ERR(dmae->tx_channel)) { 786 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) 787 dev_warn(mmc_dev(host->mmc), 788 "Deferred probe for TX channel ignored\n"); 789 dmae->tx_channel = NULL; 790 } 791 792 /* 793 * If only an RX channel is specified, the driver will 794 * attempt to use it bidirectionally, however if it 795 * is specified but cannot be located, DMA will be disabled. 796 */ 797 if (dmae->rx_channel && !dmae->tx_channel) 798 dmae->tx_channel = dmae->rx_channel; 799 800 if (dmae->rx_channel) 801 rxname = dma_chan_name(dmae->rx_channel); 802 else 803 rxname = "none"; 804 805 if (dmae->tx_channel) 806 txname = dma_chan_name(dmae->tx_channel); 807 else 808 txname = "none"; 809 810 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 811 rxname, txname); 812 813 /* 814 * Limit the maximum segment size in any SG entry according to 815 * the parameters of the DMA engine device. 816 */ 817 if (dmae->tx_channel) { 818 struct device *dev = dmae->tx_channel->device->dev; 819 unsigned int max_seg_size = dma_get_max_seg_size(dev); 820 821 if (max_seg_size < host->mmc->max_seg_size) 822 host->mmc->max_seg_size = max_seg_size; 823 } 824 if (dmae->rx_channel) { 825 struct device *dev = dmae->rx_channel->device->dev; 826 unsigned int max_seg_size = dma_get_max_seg_size(dev); 827 828 if (max_seg_size < host->mmc->max_seg_size) 829 host->mmc->max_seg_size = max_seg_size; 830 } 831 832 if (!dmae->tx_channel || !dmae->rx_channel) { 833 mmci_dmae_release(host); 834 return -EINVAL; 835 } 836 837 return 0; 838 } 839 840 /* 841 * This is used in or so inline it 842 * so it can be discarded. 843 */ 844 void mmci_dmae_release(struct mmci_host *host) 845 { 846 struct mmci_dmae_priv *dmae = host->dma_priv; 847 848 if (dmae->rx_channel) 849 dma_release_channel(dmae->rx_channel); 850 if (dmae->tx_channel) 851 dma_release_channel(dmae->tx_channel); 852 dmae->rx_channel = dmae->tx_channel = NULL; 853 } 854 855 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 856 { 857 struct mmci_dmae_priv *dmae = host->dma_priv; 858 struct dma_chan *chan; 859 860 if (data->flags & MMC_DATA_READ) 861 chan = dmae->rx_channel; 862 else 863 chan = dmae->tx_channel; 864 865 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 866 mmc_get_dma_dir(data)); 867 } 868 869 void mmci_dmae_error(struct mmci_host *host) 870 { 871 struct mmci_dmae_priv *dmae = host->dma_priv; 872 873 if (!dma_inprogress(host)) 874 return; 875 876 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 877 dmaengine_terminate_all(dmae->cur); 878 host->dma_in_progress = false; 879 dmae->cur = NULL; 880 dmae->desc_current = NULL; 881 host->data->host_cookie = 0; 882 883 mmci_dma_unmap(host, host->data); 884 } 885 886 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 887 { 888 struct mmci_dmae_priv *dmae = host->dma_priv; 889 u32 status; 890 int i; 891 892 if (!dma_inprogress(host)) 893 return; 894 895 /* Wait up to 1ms for the DMA to complete */ 896 for (i = 0; ; i++) { 897 status = readl(host->base + MMCISTATUS); 898 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 899 break; 900 udelay(10); 901 } 902 903 /* 904 * Check to see whether we still have some data left in the FIFO - 905 * this catches DMA controllers which are unable to monitor the 906 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 907 * contiguous buffers. On TX, we'll get a FIFO underrun error. 908 */ 909 if (status & MCI_RXDATAAVLBLMASK) { 910 mmci_dma_error(host); 911 if (!data->error) 912 data->error = -EIO; 913 } else if (!data->host_cookie) { 914 mmci_dma_unmap(host, data); 915 } 916 917 /* 918 * Use of DMA with scatter-gather is impossible. 919 * Give up with DMA and switch back to PIO mode. 920 */ 921 if (status & MCI_RXDATAAVLBLMASK) { 922 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 923 mmci_dma_release(host); 924 } 925 926 host->dma_in_progress = false; 927 dmae->cur = NULL; 928 dmae->desc_current = NULL; 929 } 930 931 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 932 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 933 struct dma_chan **dma_chan, 934 struct dma_async_tx_descriptor **dma_desc) 935 { 936 struct mmci_dmae_priv *dmae = host->dma_priv; 937 struct variant_data *variant = host->variant; 938 struct dma_slave_config conf = { 939 .src_addr = host->phybase + MMCIFIFO, 940 .dst_addr = host->phybase + MMCIFIFO, 941 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 942 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 943 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 944 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 945 .device_fc = false, 946 }; 947 struct dma_chan *chan; 948 struct dma_device *device; 949 struct dma_async_tx_descriptor *desc; 950 int nr_sg; 951 unsigned long flags = DMA_CTRL_ACK; 952 953 if (data->flags & MMC_DATA_READ) { 954 conf.direction = DMA_DEV_TO_MEM; 955 chan = dmae->rx_channel; 956 } else { 957 conf.direction = DMA_MEM_TO_DEV; 958 chan = dmae->tx_channel; 959 } 960 961 /* If there's no DMA channel, fall back to PIO */ 962 if (!chan) 963 return -EINVAL; 964 965 /* If less than or equal to the fifo size, don't bother with DMA */ 966 if (data->blksz * data->blocks <= variant->fifosize) 967 return -EINVAL; 968 969 /* 970 * This is necessary to get SDIO working on the Ux500. We do not yet 971 * know if this is a bug in: 972 * - The Ux500 DMA controller (DMA40) 973 * - The MMCI DMA interface on the Ux500 974 * some power of two blocks (such as 64 bytes) are sent regularly 975 * during SDIO traffic and those work fine so for these we enable DMA 976 * transfers. 977 */ 978 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) 979 return -EINVAL; 980 981 device = chan->device; 982 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 983 mmc_get_dma_dir(data)); 984 if (nr_sg == 0) 985 return -EINVAL; 986 987 if (host->variant->qcom_dml) 988 flags |= DMA_PREP_INTERRUPT; 989 990 dmaengine_slave_config(chan, &conf); 991 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 992 conf.direction, flags); 993 if (!desc) 994 goto unmap_exit; 995 996 *dma_chan = chan; 997 *dma_desc = desc; 998 999 return 0; 1000 1001 unmap_exit: 1002 dma_unmap_sg(device->dev, data->sg, data->sg_len, 1003 mmc_get_dma_dir(data)); 1004 return -ENOMEM; 1005 } 1006 1007 int mmci_dmae_prep_data(struct mmci_host *host, 1008 struct mmc_data *data, 1009 bool next) 1010 { 1011 struct mmci_dmae_priv *dmae = host->dma_priv; 1012 struct mmci_dmae_next *nd = &dmae->next_data; 1013 1014 if (!host->use_dma) 1015 return -EINVAL; 1016 1017 if (next) 1018 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 1019 /* Check if next job is already prepared. */ 1020 if (dmae->cur && dmae->desc_current) 1021 return 0; 1022 1023 /* No job were prepared thus do it now. */ 1024 return _mmci_dmae_prep_data(host, data, &dmae->cur, 1025 &dmae->desc_current); 1026 } 1027 1028 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 1029 { 1030 struct mmci_dmae_priv *dmae = host->dma_priv; 1031 int ret; 1032 1033 host->dma_in_progress = true; 1034 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); 1035 if (ret < 0) { 1036 host->dma_in_progress = false; 1037 return ret; 1038 } 1039 dma_async_issue_pending(dmae->cur); 1040 1041 *datactrl |= MCI_DPSM_DMAENABLE; 1042 1043 return 0; 1044 } 1045 1046 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 1047 { 1048 struct mmci_dmae_priv *dmae = host->dma_priv; 1049 struct mmci_dmae_next *next = &dmae->next_data; 1050 1051 if (!host->use_dma) 1052 return; 1053 1054 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 1055 1056 dmae->desc_current = next->desc; 1057 dmae->cur = next->chan; 1058 next->desc = NULL; 1059 next->chan = NULL; 1060 } 1061 1062 void mmci_dmae_unprep_data(struct mmci_host *host, 1063 struct mmc_data *data, int err) 1064 1065 { 1066 struct mmci_dmae_priv *dmae = host->dma_priv; 1067 1068 if (!host->use_dma) 1069 return; 1070 1071 mmci_dma_unmap(host, data); 1072 1073 if (err) { 1074 struct mmci_dmae_next *next = &dmae->next_data; 1075 struct dma_chan *chan; 1076 if (data->flags & MMC_DATA_READ) 1077 chan = dmae->rx_channel; 1078 else 1079 chan = dmae->tx_channel; 1080 dmaengine_terminate_all(chan); 1081 1082 if (dmae->desc_current == next->desc) 1083 dmae->desc_current = NULL; 1084 1085 if (dmae->cur == next->chan) { 1086 host->dma_in_progress = false; 1087 dmae->cur = NULL; 1088 } 1089 1090 next->desc = NULL; 1091 next->chan = NULL; 1092 } 1093 } 1094 1095 static struct mmci_host_ops mmci_variant_ops = { 1096 .prep_data = mmci_dmae_prep_data, 1097 .unprep_data = mmci_dmae_unprep_data, 1098 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1099 .get_next_data = mmci_dmae_get_next_data, 1100 .dma_setup = mmci_dmae_setup, 1101 .dma_release = mmci_dmae_release, 1102 .dma_start = mmci_dmae_start, 1103 .dma_finalize = mmci_dmae_finalize, 1104 .dma_error = mmci_dmae_error, 1105 }; 1106 #else 1107 static struct mmci_host_ops mmci_variant_ops = { 1108 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1109 }; 1110 #endif 1111 1112 static void mmci_variant_init(struct mmci_host *host) 1113 { 1114 host->ops = &mmci_variant_ops; 1115 } 1116 1117 static void ux500_variant_init(struct mmci_host *host) 1118 { 1119 host->ops = &mmci_variant_ops; 1120 host->ops->busy_complete = ux500_busy_complete; 1121 } 1122 1123 static void ux500v2_variant_init(struct mmci_host *host) 1124 { 1125 host->ops = &mmci_variant_ops; 1126 host->ops->busy_complete = ux500_busy_complete; 1127 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1128 } 1129 1130 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1131 { 1132 struct mmci_host *host = mmc_priv(mmc); 1133 struct mmc_data *data = mrq->data; 1134 1135 if (!data) 1136 return; 1137 1138 WARN_ON(data->host_cookie); 1139 1140 if (mmci_validate_data(host, data)) 1141 return; 1142 1143 mmci_prep_data(host, data, true); 1144 } 1145 1146 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1147 int err) 1148 { 1149 struct mmci_host *host = mmc_priv(mmc); 1150 struct mmc_data *data = mrq->data; 1151 1152 if (!data || !data->host_cookie) 1153 return; 1154 1155 mmci_unprep_data(host, data, err); 1156 } 1157 1158 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1159 { 1160 struct variant_data *variant = host->variant; 1161 unsigned int datactrl, timeout, irqmask; 1162 unsigned long long clks; 1163 void __iomem *base; 1164 1165 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1166 data->blksz, data->blocks, data->flags); 1167 1168 host->data = data; 1169 host->size = data->blksz * data->blocks; 1170 data->bytes_xfered = 0; 1171 1172 clks = (unsigned long long)data->timeout_ns * host->cclk; 1173 do_div(clks, NSEC_PER_SEC); 1174 1175 timeout = data->timeout_clks + (unsigned int)clks; 1176 1177 base = host->base; 1178 writel(timeout, base + MMCIDATATIMER); 1179 writel(host->size, base + MMCIDATALENGTH); 1180 1181 datactrl = host->ops->get_datactrl_cfg(host); 1182 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1183 1184 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1185 u32 clk; 1186 1187 datactrl |= variant->datactrl_mask_sdio; 1188 1189 /* 1190 * The ST Micro variant for SDIO small write transfers 1191 * needs to have clock H/W flow control disabled, 1192 * otherwise the transfer will not start. The threshold 1193 * depends on the rate of MCLK. 1194 */ 1195 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1196 (host->size < 8 || 1197 (host->size <= 8 && host->mclk > 50000000))) 1198 clk = host->clk_reg & ~variant->clkreg_enable; 1199 else 1200 clk = host->clk_reg | variant->clkreg_enable; 1201 1202 mmci_write_clkreg(host, clk); 1203 } 1204 1205 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1206 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1207 datactrl |= variant->datactrl_mask_ddrmode; 1208 1209 /* 1210 * Attempt to use DMA operation mode, if this 1211 * should fail, fall back to PIO mode 1212 */ 1213 if (!mmci_dma_start(host, datactrl)) 1214 return; 1215 1216 /* IRQ mode, map the SG list for CPU reading/writing */ 1217 mmci_init_sg(host, data); 1218 1219 if (data->flags & MMC_DATA_READ) { 1220 irqmask = MCI_RXFIFOHALFFULLMASK; 1221 1222 /* 1223 * If we have less than the fifo 'half-full' threshold to 1224 * transfer, trigger a PIO interrupt as soon as any data 1225 * is available. 1226 */ 1227 if (host->size < variant->fifohalfsize) 1228 irqmask |= MCI_RXDATAAVLBLMASK; 1229 } else { 1230 /* 1231 * We don't actually need to include "FIFO empty" here 1232 * since its implicit in "FIFO half empty". 1233 */ 1234 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1235 } 1236 1237 mmci_write_datactrlreg(host, datactrl); 1238 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1239 mmci_set_mask1(host, irqmask); 1240 } 1241 1242 static void 1243 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1244 { 1245 void __iomem *base = host->base; 1246 unsigned long long clks; 1247 1248 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1249 cmd->opcode, cmd->arg, cmd->flags); 1250 1251 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1252 writel(0, base + MMCICOMMAND); 1253 mmci_reg_delay(host); 1254 } 1255 1256 if (host->variant->cmdreg_stop && 1257 cmd->opcode == MMC_STOP_TRANSMISSION) 1258 c |= host->variant->cmdreg_stop; 1259 1260 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1261 if (cmd->flags & MMC_RSP_PRESENT) { 1262 if (cmd->flags & MMC_RSP_136) 1263 c |= host->variant->cmdreg_lrsp_crc; 1264 else if (cmd->flags & MMC_RSP_CRC) 1265 c |= host->variant->cmdreg_srsp_crc; 1266 else 1267 c |= host->variant->cmdreg_srsp; 1268 } 1269 1270 host->busy_status = 0; 1271 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1272 if (!cmd->busy_timeout) 1273 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1274 1275 if (cmd->busy_timeout > host->mmc->max_busy_timeout) 1276 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; 1277 else 1278 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1279 1280 do_div(clks, MSEC_PER_SEC); 1281 writel_relaxed(clks, host->base + MMCIDATATIMER); 1282 } 1283 1284 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) 1285 host->ops->pre_sig_volt_switch(host); 1286 1287 if (/*interrupt*/0) 1288 c |= MCI_CPSM_INTERRUPT; 1289 1290 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1291 c |= host->variant->data_cmd_enable; 1292 1293 host->cmd = cmd; 1294 1295 writel(cmd->arg, base + MMCIARGUMENT); 1296 writel(c, base + MMCICOMMAND); 1297 } 1298 1299 static void mmci_stop_command(struct mmci_host *host) 1300 { 1301 host->stop_abort.error = 0; 1302 mmci_start_command(host, &host->stop_abort, 0); 1303 } 1304 1305 static void 1306 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1307 unsigned int status) 1308 { 1309 unsigned int status_err; 1310 1311 /* Make sure we have data to handle */ 1312 if (!data) 1313 return; 1314 1315 /* First check for errors */ 1316 status_err = status & (host->variant->start_err | 1317 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1318 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1319 1320 if (status_err) { 1321 u32 remain, success; 1322 1323 /* Terminate the DMA transfer */ 1324 mmci_dma_error(host); 1325 1326 /* 1327 * Calculate how far we are into the transfer. Note that 1328 * the data counter gives the number of bytes transferred 1329 * on the MMC bus, not on the host side. On reads, this 1330 * can be as much as a FIFO-worth of data ahead. This 1331 * matters for FIFO overruns only. 1332 */ 1333 if (!host->variant->datacnt_useless) { 1334 remain = readl(host->base + MMCIDATACNT); 1335 success = data->blksz * data->blocks - remain; 1336 } else { 1337 success = 0; 1338 } 1339 1340 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1341 status_err, success); 1342 if (status_err & MCI_DATACRCFAIL) { 1343 /* Last block was not successful */ 1344 success -= 1; 1345 data->error = -EILSEQ; 1346 } else if (status_err & MCI_DATATIMEOUT) { 1347 data->error = -ETIMEDOUT; 1348 } else if (status_err & MCI_STARTBITERR) { 1349 data->error = -ECOMM; 1350 } else if (status_err & MCI_TXUNDERRUN) { 1351 data->error = -EIO; 1352 } else if (status_err & MCI_RXOVERRUN) { 1353 if (success > host->variant->fifosize) 1354 success -= host->variant->fifosize; 1355 else 1356 success = 0; 1357 data->error = -EIO; 1358 } 1359 data->bytes_xfered = round_down(success, data->blksz); 1360 } 1361 1362 if (status & MCI_DATABLOCKEND) 1363 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1364 1365 if (status & MCI_DATAEND || data->error) { 1366 mmci_dma_finalize(host, data); 1367 1368 mmci_stop_data(host); 1369 1370 if (!data->error) 1371 /* The error clause is handled above, success! */ 1372 data->bytes_xfered = data->blksz * data->blocks; 1373 1374 if (!data->stop) { 1375 if (host->variant->cmdreg_stop && data->error) 1376 mmci_stop_command(host); 1377 else 1378 mmci_request_end(host, data->mrq); 1379 } else if (host->mrq->sbc && !data->error) { 1380 mmci_request_end(host, data->mrq); 1381 } else { 1382 mmci_start_command(host, data->stop, 0); 1383 } 1384 } 1385 } 1386 1387 static void 1388 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1389 unsigned int status) 1390 { 1391 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1392 void __iomem *base = host->base; 1393 bool sbc, busy_resp; 1394 1395 if (!cmd) 1396 return; 1397 1398 sbc = (cmd == host->mrq->sbc); 1399 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1400 1401 /* 1402 * We need to be one of these interrupts to be considered worth 1403 * handling. Note that we tag on any latent IRQs postponed 1404 * due to waiting for busy status. 1405 */ 1406 if (host->variant->busy_timeout && busy_resp) 1407 err_msk |= MCI_DATATIMEOUT; 1408 1409 if (!((status | host->busy_status) & 1410 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1411 return; 1412 1413 /* Handle busy detection on DAT0 if the variant supports it. */ 1414 if (busy_resp && host->variant->busy_detect) 1415 if (!host->ops->busy_complete(host, status, err_msk)) 1416 return; 1417 1418 host->cmd = NULL; 1419 1420 if (status & MCI_CMDTIMEOUT) { 1421 cmd->error = -ETIMEDOUT; 1422 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1423 cmd->error = -EILSEQ; 1424 } else if (host->variant->busy_timeout && busy_resp && 1425 status & MCI_DATATIMEOUT) { 1426 cmd->error = -ETIMEDOUT; 1427 /* 1428 * This will wake up mmci_irq_thread() which will issue 1429 * a hardware reset of the MMCI block. 1430 */ 1431 host->irq_action = IRQ_WAKE_THREAD; 1432 } else { 1433 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1434 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1435 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1436 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1437 } 1438 1439 if ((!sbc && !cmd->data) || cmd->error) { 1440 if (host->data) { 1441 /* Terminate the DMA transfer */ 1442 mmci_dma_error(host); 1443 1444 mmci_stop_data(host); 1445 if (host->variant->cmdreg_stop && cmd->error) { 1446 mmci_stop_command(host); 1447 return; 1448 } 1449 } 1450 1451 if (host->irq_action != IRQ_WAKE_THREAD) 1452 mmci_request_end(host, host->mrq); 1453 1454 } else if (sbc) { 1455 mmci_start_command(host, host->mrq->cmd, 0); 1456 } else if (!host->variant->datactrl_first && 1457 !(cmd->data->flags & MMC_DATA_READ)) { 1458 mmci_start_data(host, cmd->data); 1459 } 1460 } 1461 1462 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1463 { 1464 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1465 } 1466 1467 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1468 { 1469 /* 1470 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1471 * from the fifo range should be used 1472 */ 1473 if (status & MCI_RXFIFOHALFFULL) 1474 return host->variant->fifohalfsize; 1475 else if (status & MCI_RXDATAAVLBL) 1476 return 4; 1477 1478 return 0; 1479 } 1480 1481 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1482 { 1483 void __iomem *base = host->base; 1484 char *ptr = buffer; 1485 u32 status = readl(host->base + MMCISTATUS); 1486 int host_remain = host->size; 1487 1488 do { 1489 int count = host->get_rx_fifocnt(host, status, host_remain); 1490 1491 if (count > remain) 1492 count = remain; 1493 1494 if (count <= 0) 1495 break; 1496 1497 /* 1498 * SDIO especially may want to send something that is 1499 * not divisible by 4 (as opposed to card sectors 1500 * etc). Therefore make sure to always read the last bytes 1501 * while only doing full 32-bit reads towards the FIFO. 1502 */ 1503 if (unlikely(count & 0x3)) { 1504 if (count < 4) { 1505 unsigned char buf[4]; 1506 ioread32_rep(base + MMCIFIFO, buf, 1); 1507 memcpy(ptr, buf, count); 1508 } else { 1509 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1510 count &= ~0x3; 1511 } 1512 } else { 1513 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1514 } 1515 1516 ptr += count; 1517 remain -= count; 1518 host_remain -= count; 1519 1520 if (remain == 0) 1521 break; 1522 1523 status = readl(base + MMCISTATUS); 1524 } while (status & MCI_RXDATAAVLBL); 1525 1526 return ptr - buffer; 1527 } 1528 1529 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1530 { 1531 struct variant_data *variant = host->variant; 1532 void __iomem *base = host->base; 1533 char *ptr = buffer; 1534 1535 do { 1536 unsigned int count, maxcnt; 1537 1538 maxcnt = status & MCI_TXFIFOEMPTY ? 1539 variant->fifosize : variant->fifohalfsize; 1540 count = min(remain, maxcnt); 1541 1542 /* 1543 * SDIO especially may want to send something that is 1544 * not divisible by 4 (as opposed to card sectors 1545 * etc), and the FIFO only accept full 32-bit writes. 1546 * So compensate by adding +3 on the count, a single 1547 * byte become a 32bit write, 7 bytes will be two 1548 * 32bit writes etc. 1549 */ 1550 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1551 1552 ptr += count; 1553 remain -= count; 1554 1555 if (remain == 0) 1556 break; 1557 1558 status = readl(base + MMCISTATUS); 1559 } while (status & MCI_TXFIFOHALFEMPTY); 1560 1561 return ptr - buffer; 1562 } 1563 1564 /* 1565 * PIO data transfer IRQ handler. 1566 */ 1567 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1568 { 1569 struct mmci_host *host = dev_id; 1570 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1571 struct variant_data *variant = host->variant; 1572 void __iomem *base = host->base; 1573 u32 status; 1574 1575 status = readl(base + MMCISTATUS); 1576 1577 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1578 1579 do { 1580 unsigned int remain, len; 1581 char *buffer; 1582 1583 /* 1584 * For write, we only need to test the half-empty flag 1585 * here - if the FIFO is completely empty, then by 1586 * definition it is more than half empty. 1587 * 1588 * For read, check for data available. 1589 */ 1590 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1591 break; 1592 1593 if (!sg_miter_next(sg_miter)) 1594 break; 1595 1596 buffer = sg_miter->addr; 1597 remain = sg_miter->length; 1598 1599 len = 0; 1600 if (status & MCI_RXACTIVE) 1601 len = mmci_pio_read(host, buffer, remain); 1602 if (status & MCI_TXACTIVE) 1603 len = mmci_pio_write(host, buffer, remain, status); 1604 1605 sg_miter->consumed = len; 1606 1607 host->size -= len; 1608 remain -= len; 1609 1610 if (remain) 1611 break; 1612 1613 status = readl(base + MMCISTATUS); 1614 } while (1); 1615 1616 sg_miter_stop(sg_miter); 1617 1618 /* 1619 * If we have less than the fifo 'half-full' threshold to transfer, 1620 * trigger a PIO interrupt as soon as any data is available. 1621 */ 1622 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1623 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1624 1625 /* 1626 * If we run out of data, disable the data IRQs; this 1627 * prevents a race where the FIFO becomes empty before 1628 * the chip itself has disabled the data path, and 1629 * stops us racing with our data end IRQ. 1630 */ 1631 if (host->size == 0) { 1632 mmci_set_mask1(host, 0); 1633 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1634 } 1635 1636 return IRQ_HANDLED; 1637 } 1638 1639 /* 1640 * Handle completion of command and data transfers. 1641 */ 1642 static irqreturn_t mmci_irq(int irq, void *dev_id) 1643 { 1644 struct mmci_host *host = dev_id; 1645 u32 status; 1646 1647 spin_lock(&host->lock); 1648 host->irq_action = IRQ_HANDLED; 1649 1650 do { 1651 status = readl(host->base + MMCISTATUS); 1652 if (!status) 1653 break; 1654 1655 if (host->singleirq) { 1656 if (status & host->mask1_reg) 1657 mmci_pio_irq(irq, dev_id); 1658 1659 status &= ~host->variant->irq_pio_mask; 1660 } 1661 1662 /* 1663 * Busy detection is managed by mmci_cmd_irq(), including to 1664 * clear the corresponding IRQ. 1665 */ 1666 status &= readl(host->base + MMCIMASK0); 1667 if (host->variant->busy_detect) 1668 writel(status & ~host->variant->busy_detect_mask, 1669 host->base + MMCICLEAR); 1670 else 1671 writel(status, host->base + MMCICLEAR); 1672 1673 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1674 1675 if (host->variant->reversed_irq_handling) { 1676 mmci_data_irq(host, host->data, status); 1677 mmci_cmd_irq(host, host->cmd, status); 1678 } else { 1679 mmci_cmd_irq(host, host->cmd, status); 1680 mmci_data_irq(host, host->data, status); 1681 } 1682 1683 /* 1684 * Busy detection has been handled by mmci_cmd_irq() above. 1685 * Clear the status bit to prevent polling in IRQ context. 1686 */ 1687 if (host->variant->busy_detect_flag) 1688 status &= ~host->variant->busy_detect_flag; 1689 1690 } while (status); 1691 1692 spin_unlock(&host->lock); 1693 1694 return host->irq_action; 1695 } 1696 1697 /* 1698 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. 1699 * 1700 * A reset is needed for some variants, where a datatimeout for a R1B request 1701 * causes the DPSM to stay busy (non-functional). 1702 */ 1703 static irqreturn_t mmci_irq_thread(int irq, void *dev_id) 1704 { 1705 struct mmci_host *host = dev_id; 1706 unsigned long flags; 1707 1708 if (host->rst) { 1709 reset_control_assert(host->rst); 1710 udelay(2); 1711 reset_control_deassert(host->rst); 1712 } 1713 1714 spin_lock_irqsave(&host->lock, flags); 1715 writel(host->clk_reg, host->base + MMCICLOCK); 1716 writel(host->pwr_reg, host->base + MMCIPOWER); 1717 writel(MCI_IRQENABLE | host->variant->start_err, 1718 host->base + MMCIMASK0); 1719 1720 host->irq_action = IRQ_HANDLED; 1721 mmci_request_end(host, host->mrq); 1722 spin_unlock_irqrestore(&host->lock, flags); 1723 1724 return host->irq_action; 1725 } 1726 1727 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1728 { 1729 struct mmci_host *host = mmc_priv(mmc); 1730 unsigned long flags; 1731 1732 WARN_ON(host->mrq != NULL); 1733 1734 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1735 if (mrq->cmd->error) { 1736 mmc_request_done(mmc, mrq); 1737 return; 1738 } 1739 1740 spin_lock_irqsave(&host->lock, flags); 1741 1742 host->mrq = mrq; 1743 1744 if (mrq->data) 1745 mmci_get_next_data(host, mrq->data); 1746 1747 if (mrq->data && 1748 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1749 mmci_start_data(host, mrq->data); 1750 1751 if (mrq->sbc) 1752 mmci_start_command(host, mrq->sbc, 0); 1753 else 1754 mmci_start_command(host, mrq->cmd, 0); 1755 1756 spin_unlock_irqrestore(&host->lock, flags); 1757 } 1758 1759 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1760 { 1761 struct mmci_host *host = mmc_priv(mmc); 1762 u32 max_busy_timeout = 0; 1763 1764 if (!host->variant->busy_detect) 1765 return; 1766 1767 if (host->variant->busy_timeout && mmc->actual_clock) 1768 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, 1769 MSEC_PER_SEC); 1770 1771 mmc->max_busy_timeout = max_busy_timeout; 1772 } 1773 1774 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1775 { 1776 struct mmci_host *host = mmc_priv(mmc); 1777 struct variant_data *variant = host->variant; 1778 u32 pwr = 0; 1779 unsigned long flags; 1780 int ret; 1781 1782 switch (ios->power_mode) { 1783 case MMC_POWER_OFF: 1784 if (!IS_ERR(mmc->supply.vmmc)) 1785 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1786 1787 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1788 regulator_disable(mmc->supply.vqmmc); 1789 host->vqmmc_enabled = false; 1790 } 1791 1792 break; 1793 case MMC_POWER_UP: 1794 if (!IS_ERR(mmc->supply.vmmc)) 1795 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1796 1797 /* 1798 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1799 * and instead uses MCI_PWR_ON so apply whatever value is 1800 * configured in the variant data. 1801 */ 1802 pwr |= variant->pwrreg_powerup; 1803 1804 break; 1805 case MMC_POWER_ON: 1806 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1807 ret = regulator_enable(mmc->supply.vqmmc); 1808 if (ret < 0) 1809 dev_err(mmc_dev(mmc), 1810 "failed to enable vqmmc regulator\n"); 1811 else 1812 host->vqmmc_enabled = true; 1813 } 1814 1815 pwr |= MCI_PWR_ON; 1816 break; 1817 } 1818 1819 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1820 /* 1821 * The ST Micro variant has some additional bits 1822 * indicating signal direction for the signals in 1823 * the SD/MMC bus and feedback-clock usage. 1824 */ 1825 pwr |= host->pwr_reg_add; 1826 1827 if (ios->bus_width == MMC_BUS_WIDTH_4) 1828 pwr &= ~MCI_ST_DATA74DIREN; 1829 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1830 pwr &= (~MCI_ST_DATA74DIREN & 1831 ~MCI_ST_DATA31DIREN & 1832 ~MCI_ST_DATA2DIREN); 1833 } 1834 1835 if (variant->opendrain) { 1836 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1837 pwr |= variant->opendrain; 1838 } else { 1839 /* 1840 * If the variant cannot configure the pads by its own, then we 1841 * expect the pinctrl to be able to do that for us 1842 */ 1843 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1844 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1845 else 1846 pinctrl_select_default_state(mmc_dev(mmc)); 1847 } 1848 1849 /* 1850 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1851 * gating the clock, the MCI_PWR_ON bit is cleared. 1852 */ 1853 if (!ios->clock && variant->pwrreg_clkgate) 1854 pwr &= ~MCI_PWR_ON; 1855 1856 if (host->variant->explicit_mclk_control && 1857 ios->clock != host->clock_cache) { 1858 ret = clk_set_rate(host->clk, ios->clock); 1859 if (ret < 0) 1860 dev_err(mmc_dev(host->mmc), 1861 "Error setting clock rate (%d)\n", ret); 1862 else 1863 host->mclk = clk_get_rate(host->clk); 1864 } 1865 host->clock_cache = ios->clock; 1866 1867 spin_lock_irqsave(&host->lock, flags); 1868 1869 if (host->ops && host->ops->set_clkreg) 1870 host->ops->set_clkreg(host, ios->clock); 1871 else 1872 mmci_set_clkreg(host, ios->clock); 1873 1874 mmci_set_max_busy_timeout(mmc); 1875 1876 if (host->ops && host->ops->set_pwrreg) 1877 host->ops->set_pwrreg(host, pwr); 1878 else 1879 mmci_write_pwrreg(host, pwr); 1880 1881 mmci_reg_delay(host); 1882 1883 spin_unlock_irqrestore(&host->lock, flags); 1884 } 1885 1886 static int mmci_get_cd(struct mmc_host *mmc) 1887 { 1888 struct mmci_host *host = mmc_priv(mmc); 1889 struct mmci_platform_data *plat = host->plat; 1890 unsigned int status = mmc_gpio_get_cd(mmc); 1891 1892 if (status == -ENOSYS) { 1893 if (!plat->status) 1894 return 1; /* Assume always present */ 1895 1896 status = plat->status(mmc_dev(host->mmc)); 1897 } 1898 return status; 1899 } 1900 1901 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1902 { 1903 struct mmci_host *host = mmc_priv(mmc); 1904 int ret; 1905 1906 ret = mmc_regulator_set_vqmmc(mmc, ios); 1907 1908 if (!ret && host->ops && host->ops->post_sig_volt_switch) 1909 ret = host->ops->post_sig_volt_switch(host, ios); 1910 else if (ret) 1911 ret = 0; 1912 1913 if (ret < 0) 1914 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1915 1916 return ret; 1917 } 1918 1919 static struct mmc_host_ops mmci_ops = { 1920 .request = mmci_request, 1921 .pre_req = mmci_pre_request, 1922 .post_req = mmci_post_request, 1923 .set_ios = mmci_set_ios, 1924 .get_ro = mmc_gpio_get_ro, 1925 .get_cd = mmci_get_cd, 1926 .start_signal_voltage_switch = mmci_sig_volt_switch, 1927 }; 1928 1929 static void mmci_probe_level_translator(struct mmc_host *mmc) 1930 { 1931 struct device *dev = mmc_dev(mmc); 1932 struct mmci_host *host = mmc_priv(mmc); 1933 struct gpio_desc *cmd_gpio; 1934 struct gpio_desc *ck_gpio; 1935 struct gpio_desc *ckin_gpio; 1936 int clk_hi, clk_lo; 1937 1938 /* 1939 * Assume the level translator is present if st,use-ckin is set. 1940 * This is to cater for DTs which do not implement this test. 1941 */ 1942 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1943 1944 cmd_gpio = gpiod_get(dev, "st,cmd", GPIOD_OUT_HIGH); 1945 if (IS_ERR(cmd_gpio)) 1946 goto exit_cmd; 1947 1948 ck_gpio = gpiod_get(dev, "st,ck", GPIOD_OUT_HIGH); 1949 if (IS_ERR(ck_gpio)) 1950 goto exit_ck; 1951 1952 ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); 1953 if (IS_ERR(ckin_gpio)) 1954 goto exit_ckin; 1955 1956 /* All GPIOs are valid, test whether level translator works */ 1957 1958 /* Sample CKIN */ 1959 clk_hi = !!gpiod_get_value(ckin_gpio); 1960 1961 /* Set CK low */ 1962 gpiod_set_value(ck_gpio, 0); 1963 1964 /* Sample CKIN */ 1965 clk_lo = !!gpiod_get_value(ckin_gpio); 1966 1967 /* Tristate all */ 1968 gpiod_direction_input(cmd_gpio); 1969 gpiod_direction_input(ck_gpio); 1970 1971 /* Level translator is present if CK signal is propagated to CKIN */ 1972 if (!clk_hi || clk_lo) { 1973 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; 1974 dev_warn(dev, 1975 "Level translator inoperable, CK signal not detected on CKIN, disabling.\n"); 1976 } 1977 1978 gpiod_put(ckin_gpio); 1979 1980 exit_ckin: 1981 gpiod_put(ck_gpio); 1982 exit_ck: 1983 gpiod_put(cmd_gpio); 1984 exit_cmd: 1985 pinctrl_select_default_state(dev); 1986 } 1987 1988 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1989 { 1990 struct mmci_host *host = mmc_priv(mmc); 1991 int ret = mmc_of_parse(mmc); 1992 1993 if (ret) 1994 return ret; 1995 1996 if (of_property_read_bool(np, "st,sig-dir-dat0")) 1997 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1998 if (of_property_read_bool(np, "st,sig-dir-dat2")) 1999 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 2000 if (of_property_read_bool(np, "st,sig-dir-dat31")) 2001 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 2002 if (of_property_read_bool(np, "st,sig-dir-dat74")) 2003 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 2004 if (of_property_read_bool(np, "st,sig-dir-cmd")) 2005 host->pwr_reg_add |= MCI_ST_CMDDIREN; 2006 if (of_property_read_bool(np, "st,sig-pin-fbclk")) 2007 host->pwr_reg_add |= MCI_ST_FBCLKEN; 2008 if (of_property_read_bool(np, "st,sig-dir")) 2009 host->pwr_reg_add |= MCI_STM32_DIRPOL; 2010 if (of_property_read_bool(np, "st,neg-edge")) 2011 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 2012 if (of_property_read_bool(np, "st,use-ckin")) 2013 mmci_probe_level_translator(mmc); 2014 2015 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) 2016 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 2017 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) 2018 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2019 2020 return 0; 2021 } 2022 2023 static int mmci_probe(struct amba_device *dev, 2024 const struct amba_id *id) 2025 { 2026 struct mmci_platform_data *plat = dev->dev.platform_data; 2027 struct device_node *np = dev->dev.of_node; 2028 struct variant_data *variant = id->data; 2029 struct mmci_host *host; 2030 struct mmc_host *mmc; 2031 int ret; 2032 2033 /* Must have platform data or Device Tree. */ 2034 if (!plat && !np) { 2035 dev_err(&dev->dev, "No plat data or DT found\n"); 2036 return -EINVAL; 2037 } 2038 2039 if (!plat) { 2040 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 2041 if (!plat) 2042 return -ENOMEM; 2043 } 2044 2045 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 2046 if (!mmc) 2047 return -ENOMEM; 2048 2049 host = mmc_priv(mmc); 2050 host->mmc = mmc; 2051 host->mmc_ops = &mmci_ops; 2052 mmc->ops = &mmci_ops; 2053 2054 ret = mmci_of_parse(np, mmc); 2055 if (ret) 2056 goto host_free; 2057 2058 /* 2059 * Some variant (STM32) doesn't have opendrain bit, nevertheless 2060 * pins can be set accordingly using pinctrl 2061 */ 2062 if (!variant->opendrain) { 2063 host->pinctrl = devm_pinctrl_get(&dev->dev); 2064 if (IS_ERR(host->pinctrl)) { 2065 dev_err(&dev->dev, "failed to get pinctrl"); 2066 ret = PTR_ERR(host->pinctrl); 2067 goto host_free; 2068 } 2069 2070 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 2071 MMCI_PINCTRL_STATE_OPENDRAIN); 2072 if (IS_ERR(host->pins_opendrain)) { 2073 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 2074 ret = PTR_ERR(host->pins_opendrain); 2075 goto host_free; 2076 } 2077 } 2078 2079 host->hw_designer = amba_manf(dev); 2080 host->hw_revision = amba_rev(dev); 2081 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 2082 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 2083 2084 host->clk = devm_clk_get(&dev->dev, NULL); 2085 if (IS_ERR(host->clk)) { 2086 ret = PTR_ERR(host->clk); 2087 goto host_free; 2088 } 2089 2090 ret = clk_prepare_enable(host->clk); 2091 if (ret) 2092 goto host_free; 2093 2094 if (variant->qcom_fifo) 2095 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 2096 else 2097 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 2098 2099 host->plat = plat; 2100 host->variant = variant; 2101 host->mclk = clk_get_rate(host->clk); 2102 /* 2103 * According to the spec, mclk is max 100 MHz, 2104 * so we try to adjust the clock down to this, 2105 * (if possible). 2106 */ 2107 if (host->mclk > variant->f_max) { 2108 ret = clk_set_rate(host->clk, variant->f_max); 2109 if (ret < 0) 2110 goto clk_disable; 2111 host->mclk = clk_get_rate(host->clk); 2112 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 2113 host->mclk); 2114 } 2115 2116 host->phybase = dev->res.start; 2117 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 2118 if (IS_ERR(host->base)) { 2119 ret = PTR_ERR(host->base); 2120 goto clk_disable; 2121 } 2122 2123 if (variant->init) 2124 variant->init(host); 2125 2126 /* 2127 * The ARM and ST versions of the block have slightly different 2128 * clock divider equations which means that the minimum divider 2129 * differs too. 2130 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 2131 */ 2132 if (variant->st_clkdiv) 2133 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 2134 else if (variant->stm32_clkdiv) 2135 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 2136 else if (variant->explicit_mclk_control) 2137 mmc->f_min = clk_round_rate(host->clk, 100000); 2138 else 2139 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 2140 /* 2141 * If no maximum operating frequency is supplied, fall back to use 2142 * the module parameter, which has a (low) default value in case it 2143 * is not specified. Either value must not exceed the clock rate into 2144 * the block, of course. 2145 */ 2146 if (mmc->f_max) 2147 mmc->f_max = variant->explicit_mclk_control ? 2148 min(variant->f_max, mmc->f_max) : 2149 min(host->mclk, mmc->f_max); 2150 else 2151 mmc->f_max = variant->explicit_mclk_control ? 2152 fmax : min(host->mclk, fmax); 2153 2154 2155 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 2156 2157 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 2158 if (IS_ERR(host->rst)) { 2159 ret = PTR_ERR(host->rst); 2160 goto clk_disable; 2161 } 2162 ret = reset_control_deassert(host->rst); 2163 if (ret) 2164 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); 2165 2166 /* Get regulators and the supported OCR mask */ 2167 ret = mmc_regulator_get_supply(mmc); 2168 if (ret) 2169 goto clk_disable; 2170 2171 if (!mmc->ocr_avail) 2172 mmc->ocr_avail = plat->ocr_mask; 2173 else if (plat->ocr_mask) 2174 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 2175 2176 /* We support these capabilities. */ 2177 mmc->caps |= MMC_CAP_CMD23; 2178 2179 /* 2180 * Enable busy detection. 2181 */ 2182 if (variant->busy_detect) { 2183 mmci_ops.card_busy = mmci_card_busy; 2184 /* 2185 * Not all variants have a flag to enable busy detection 2186 * in the DPSM, but if they do, set it here. 2187 */ 2188 if (variant->busy_dpsm_flag) 2189 mmci_write_datactrlreg(host, 2190 host->variant->busy_dpsm_flag); 2191 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2192 } 2193 2194 /* Variants with mandatory busy timeout in HW needs R1B responses. */ 2195 if (variant->busy_timeout) 2196 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 2197 2198 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2199 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2200 host->stop_abort.arg = 0; 2201 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2202 2203 /* We support these PM capabilities. */ 2204 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2205 2206 /* 2207 * We can do SGIO 2208 */ 2209 mmc->max_segs = NR_SG; 2210 2211 /* 2212 * Since only a certain number of bits are valid in the data length 2213 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2214 * single request. 2215 */ 2216 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2217 2218 /* 2219 * Set the maximum segment size. Since we aren't doing DMA 2220 * (yet) we are only limited by the data length register. 2221 */ 2222 mmc->max_seg_size = mmc->max_req_size; 2223 2224 /* 2225 * Block size can be up to 2048 bytes, but must be a power of two. 2226 */ 2227 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2228 2229 /* 2230 * Limit the number of blocks transferred so that we don't overflow 2231 * the maximum request size. 2232 */ 2233 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2234 2235 spin_lock_init(&host->lock); 2236 2237 writel(0, host->base + MMCIMASK0); 2238 2239 if (variant->mmcimask1) 2240 writel(0, host->base + MMCIMASK1); 2241 2242 writel(0xfff, host->base + MMCICLEAR); 2243 2244 /* 2245 * If: 2246 * - not using DT but using a descriptor table, or 2247 * - using a table of descriptors ALONGSIDE DT, or 2248 * look up these descriptors named "cd" and "wp" right here, fail 2249 * silently of these do not exist 2250 */ 2251 if (!np) { 2252 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 2253 if (ret == -EPROBE_DEFER) 2254 goto clk_disable; 2255 2256 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 2257 if (ret == -EPROBE_DEFER) 2258 goto clk_disable; 2259 } 2260 2261 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, 2262 mmci_irq_thread, IRQF_SHARED, 2263 DRIVER_NAME " (cmd)", host); 2264 if (ret) 2265 goto clk_disable; 2266 2267 if (!dev->irq[1]) 2268 host->singleirq = true; 2269 else { 2270 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2271 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2272 if (ret) 2273 goto clk_disable; 2274 } 2275 2276 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2277 2278 amba_set_drvdata(dev, mmc); 2279 2280 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2281 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2282 amba_rev(dev), (unsigned long long)dev->res.start, 2283 dev->irq[0], dev->irq[1]); 2284 2285 mmci_dma_setup(host); 2286 2287 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2288 pm_runtime_use_autosuspend(&dev->dev); 2289 2290 ret = mmc_add_host(mmc); 2291 if (ret) 2292 goto clk_disable; 2293 2294 pm_runtime_put(&dev->dev); 2295 return 0; 2296 2297 clk_disable: 2298 clk_disable_unprepare(host->clk); 2299 host_free: 2300 mmc_free_host(mmc); 2301 return ret; 2302 } 2303 2304 static void mmci_remove(struct amba_device *dev) 2305 { 2306 struct mmc_host *mmc = amba_get_drvdata(dev); 2307 2308 if (mmc) { 2309 struct mmci_host *host = mmc_priv(mmc); 2310 struct variant_data *variant = host->variant; 2311 2312 /* 2313 * Undo pm_runtime_put() in probe. We use the _sync 2314 * version here so that we can access the primecell. 2315 */ 2316 pm_runtime_get_sync(&dev->dev); 2317 2318 mmc_remove_host(mmc); 2319 2320 writel(0, host->base + MMCIMASK0); 2321 2322 if (variant->mmcimask1) 2323 writel(0, host->base + MMCIMASK1); 2324 2325 writel(0, host->base + MMCICOMMAND); 2326 writel(0, host->base + MMCIDATACTRL); 2327 2328 mmci_dma_release(host); 2329 clk_disable_unprepare(host->clk); 2330 mmc_free_host(mmc); 2331 } 2332 } 2333 2334 #ifdef CONFIG_PM 2335 static void mmci_save(struct mmci_host *host) 2336 { 2337 unsigned long flags; 2338 2339 spin_lock_irqsave(&host->lock, flags); 2340 2341 writel(0, host->base + MMCIMASK0); 2342 if (host->variant->pwrreg_nopower) { 2343 writel(0, host->base + MMCIDATACTRL); 2344 writel(0, host->base + MMCIPOWER); 2345 writel(0, host->base + MMCICLOCK); 2346 } 2347 mmci_reg_delay(host); 2348 2349 spin_unlock_irqrestore(&host->lock, flags); 2350 } 2351 2352 static void mmci_restore(struct mmci_host *host) 2353 { 2354 unsigned long flags; 2355 2356 spin_lock_irqsave(&host->lock, flags); 2357 2358 if (host->variant->pwrreg_nopower) { 2359 writel(host->clk_reg, host->base + MMCICLOCK); 2360 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2361 writel(host->pwr_reg, host->base + MMCIPOWER); 2362 } 2363 writel(MCI_IRQENABLE | host->variant->start_err, 2364 host->base + MMCIMASK0); 2365 mmci_reg_delay(host); 2366 2367 spin_unlock_irqrestore(&host->lock, flags); 2368 } 2369 2370 static int mmci_runtime_suspend(struct device *dev) 2371 { 2372 struct amba_device *adev = to_amba_device(dev); 2373 struct mmc_host *mmc = amba_get_drvdata(adev); 2374 2375 if (mmc) { 2376 struct mmci_host *host = mmc_priv(mmc); 2377 pinctrl_pm_select_sleep_state(dev); 2378 mmci_save(host); 2379 clk_disable_unprepare(host->clk); 2380 } 2381 2382 return 0; 2383 } 2384 2385 static int mmci_runtime_resume(struct device *dev) 2386 { 2387 struct amba_device *adev = to_amba_device(dev); 2388 struct mmc_host *mmc = amba_get_drvdata(adev); 2389 2390 if (mmc) { 2391 struct mmci_host *host = mmc_priv(mmc); 2392 clk_prepare_enable(host->clk); 2393 mmci_restore(host); 2394 pinctrl_select_default_state(dev); 2395 } 2396 2397 return 0; 2398 } 2399 #endif 2400 2401 static const struct dev_pm_ops mmci_dev_pm_ops = { 2402 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2403 pm_runtime_force_resume) 2404 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2405 }; 2406 2407 static const struct amba_id mmci_ids[] = { 2408 { 2409 .id = 0x00041180, 2410 .mask = 0xff0fffff, 2411 .data = &variant_arm, 2412 }, 2413 { 2414 .id = 0x01041180, 2415 .mask = 0xff0fffff, 2416 .data = &variant_arm_extended_fifo, 2417 }, 2418 { 2419 .id = 0x02041180, 2420 .mask = 0xff0fffff, 2421 .data = &variant_arm_extended_fifo_hwfc, 2422 }, 2423 { 2424 .id = 0x00041181, 2425 .mask = 0x000fffff, 2426 .data = &variant_arm, 2427 }, 2428 /* ST Micro variants */ 2429 { 2430 .id = 0x00180180, 2431 .mask = 0x00ffffff, 2432 .data = &variant_u300, 2433 }, 2434 { 2435 .id = 0x10180180, 2436 .mask = 0xf0ffffff, 2437 .data = &variant_nomadik, 2438 }, 2439 { 2440 .id = 0x00280180, 2441 .mask = 0x00ffffff, 2442 .data = &variant_nomadik, 2443 }, 2444 { 2445 .id = 0x00480180, 2446 .mask = 0xf0ffffff, 2447 .data = &variant_ux500, 2448 }, 2449 { 2450 .id = 0x10480180, 2451 .mask = 0xf0ffffff, 2452 .data = &variant_ux500v2, 2453 }, 2454 { 2455 .id = 0x00880180, 2456 .mask = 0x00ffffff, 2457 .data = &variant_stm32, 2458 }, 2459 { 2460 .id = 0x10153180, 2461 .mask = 0xf0ffffff, 2462 .data = &variant_stm32_sdmmc, 2463 }, 2464 { 2465 .id = 0x00253180, 2466 .mask = 0xf0ffffff, 2467 .data = &variant_stm32_sdmmcv2, 2468 }, 2469 { 2470 .id = 0x20253180, 2471 .mask = 0xf0ffffff, 2472 .data = &variant_stm32_sdmmcv2, 2473 }, 2474 /* Qualcomm variants */ 2475 { 2476 .id = 0x00051180, 2477 .mask = 0x000fffff, 2478 .data = &variant_qcom, 2479 }, 2480 { 0, 0 }, 2481 }; 2482 2483 MODULE_DEVICE_TABLE(amba, mmci_ids); 2484 2485 static struct amba_driver mmci_driver = { 2486 .drv = { 2487 .name = DRIVER_NAME, 2488 .pm = &mmci_dev_pm_ops, 2489 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2490 }, 2491 .probe = mmci_probe, 2492 .remove = mmci_remove, 2493 .id_table = mmci_ids, 2494 }; 2495 2496 module_amba_driver(mmci_driver); 2497 2498 module_param(fmax, uint, 0444); 2499 2500 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2501 MODULE_LICENSE("GPL"); 2502