1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/of.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/gpio/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 static void mmci_variant_init(struct mmci_host *host); 49 static void ux500_variant_init(struct mmci_host *host); 50 static void ux500v2_variant_init(struct mmci_host *host); 51 52 static unsigned int fmax = 515633; 53 54 static struct variant_data variant_arm = { 55 .fifosize = 16 * 4, 56 .fifohalfsize = 8 * 4, 57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 60 .cmdreg_srsp = MCI_CPSM_RESPONSE, 61 .datalength_bits = 16, 62 .datactrl_blocksz = 11, 63 .pwrreg_powerup = MCI_PWR_UP, 64 .f_max = 100000000, 65 .reversed_irq_handling = true, 66 .mmcimask1 = true, 67 .irq_pio_mask = MCI_IRQ_PIO_MASK, 68 .start_err = MCI_STARTBITERR, 69 .opendrain = MCI_ROD, 70 .init = mmci_variant_init, 71 }; 72 73 static struct variant_data variant_arm_extended_fifo = { 74 .fifosize = 128 * 4, 75 .fifohalfsize = 64 * 4, 76 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 77 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 78 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 79 .cmdreg_srsp = MCI_CPSM_RESPONSE, 80 .datalength_bits = 16, 81 .datactrl_blocksz = 11, 82 .pwrreg_powerup = MCI_PWR_UP, 83 .f_max = 100000000, 84 .mmcimask1 = true, 85 .irq_pio_mask = MCI_IRQ_PIO_MASK, 86 .start_err = MCI_STARTBITERR, 87 .opendrain = MCI_ROD, 88 .init = mmci_variant_init, 89 }; 90 91 static struct variant_data variant_arm_extended_fifo_hwfc = { 92 .fifosize = 128 * 4, 93 .fifohalfsize = 64 * 4, 94 .clkreg_enable = MCI_ARM_HWFCEN, 95 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 96 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 97 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 98 .cmdreg_srsp = MCI_CPSM_RESPONSE, 99 .datalength_bits = 16, 100 .datactrl_blocksz = 11, 101 .pwrreg_powerup = MCI_PWR_UP, 102 .f_max = 100000000, 103 .mmcimask1 = true, 104 .irq_pio_mask = MCI_IRQ_PIO_MASK, 105 .start_err = MCI_STARTBITERR, 106 .opendrain = MCI_ROD, 107 .init = mmci_variant_init, 108 }; 109 110 static struct variant_data variant_u300 = { 111 .fifosize = 16 * 4, 112 .fifohalfsize = 8 * 4, 113 .clkreg_enable = MCI_ST_U300_HWFCEN, 114 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 115 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 116 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 117 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 118 .cmdreg_srsp = MCI_CPSM_RESPONSE, 119 .datalength_bits = 16, 120 .datactrl_blocksz = 11, 121 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 122 .st_sdio = true, 123 .pwrreg_powerup = MCI_PWR_ON, 124 .f_max = 100000000, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128 .mmcimask1 = true, 129 .irq_pio_mask = MCI_IRQ_PIO_MASK, 130 .start_err = MCI_STARTBITERR, 131 .opendrain = MCI_OD, 132 .init = mmci_variant_init, 133 }; 134 135 static struct variant_data variant_nomadik = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg = MCI_CLK_ENABLE, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 141 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 142 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 143 .cmdreg_srsp = MCI_CPSM_RESPONSE, 144 .datalength_bits = 24, 145 .datactrl_blocksz = 11, 146 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 147 .st_sdio = true, 148 .st_clkdiv = true, 149 .pwrreg_powerup = MCI_PWR_ON, 150 .f_max = 100000000, 151 .signal_direction = true, 152 .pwrreg_clkgate = true, 153 .pwrreg_nopower = true, 154 .mmcimask1 = true, 155 .irq_pio_mask = MCI_IRQ_PIO_MASK, 156 .start_err = MCI_STARTBITERR, 157 .opendrain = MCI_OD, 158 .init = mmci_variant_init, 159 }; 160 161 static struct variant_data variant_ux500 = { 162 .fifosize = 30 * 4, 163 .fifohalfsize = 8 * 4, 164 .clkreg = MCI_CLK_ENABLE, 165 .clkreg_enable = MCI_ST_UX500_HWFCEN, 166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 168 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 169 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 170 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 171 .cmdreg_srsp = MCI_CPSM_RESPONSE, 172 .datalength_bits = 24, 173 .datactrl_blocksz = 11, 174 .datactrl_any_blocksz = true, 175 .dma_power_of_2 = true, 176 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 177 .st_sdio = true, 178 .st_clkdiv = true, 179 .pwrreg_powerup = MCI_PWR_ON, 180 .f_max = 100000000, 181 .signal_direction = true, 182 .pwrreg_clkgate = true, 183 .busy_detect = true, 184 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 185 .busy_detect_flag = MCI_ST_CARDBUSY, 186 .busy_detect_mask = MCI_ST_BUSYENDMASK, 187 .pwrreg_nopower = true, 188 .mmcimask1 = true, 189 .irq_pio_mask = MCI_IRQ_PIO_MASK, 190 .start_err = MCI_STARTBITERR, 191 .opendrain = MCI_OD, 192 .init = ux500_variant_init, 193 }; 194 195 static struct variant_data variant_ux500v2 = { 196 .fifosize = 30 * 4, 197 .fifohalfsize = 8 * 4, 198 .clkreg = MCI_CLK_ENABLE, 199 .clkreg_enable = MCI_ST_UX500_HWFCEN, 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 202 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 203 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 204 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 205 .cmdreg_srsp = MCI_CPSM_RESPONSE, 206 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 207 .datalength_bits = 24, 208 .datactrl_blocksz = 11, 209 .datactrl_any_blocksz = true, 210 .dma_power_of_2 = true, 211 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 212 .st_sdio = true, 213 .st_clkdiv = true, 214 .pwrreg_powerup = MCI_PWR_ON, 215 .f_max = 100000000, 216 .signal_direction = true, 217 .pwrreg_clkgate = true, 218 .busy_detect = true, 219 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 220 .busy_detect_flag = MCI_ST_CARDBUSY, 221 .busy_detect_mask = MCI_ST_BUSYENDMASK, 222 .pwrreg_nopower = true, 223 .mmcimask1 = true, 224 .irq_pio_mask = MCI_IRQ_PIO_MASK, 225 .start_err = MCI_STARTBITERR, 226 .opendrain = MCI_OD, 227 .init = ux500v2_variant_init, 228 }; 229 230 static struct variant_data variant_stm32 = { 231 .fifosize = 32 * 4, 232 .fifohalfsize = 8 * 4, 233 .clkreg = MCI_CLK_ENABLE, 234 .clkreg_enable = MCI_ST_UX500_HWFCEN, 235 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 236 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 237 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 238 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 239 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 240 .cmdreg_srsp = MCI_CPSM_RESPONSE, 241 .irq_pio_mask = MCI_IRQ_PIO_MASK, 242 .datalength_bits = 24, 243 .datactrl_blocksz = 11, 244 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 245 .st_sdio = true, 246 .st_clkdiv = true, 247 .pwrreg_powerup = MCI_PWR_ON, 248 .f_max = 48000000, 249 .pwrreg_clkgate = true, 250 .pwrreg_nopower = true, 251 .init = mmci_variant_init, 252 }; 253 254 static struct variant_data variant_stm32_sdmmc = { 255 .fifosize = 16 * 4, 256 .fifohalfsize = 8 * 4, 257 .f_max = 208000000, 258 .stm32_clkdiv = true, 259 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 260 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 261 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 262 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 263 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 264 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 265 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 266 .datactrl_first = true, 267 .datacnt_useless = true, 268 .datalength_bits = 25, 269 .datactrl_blocksz = 14, 270 .datactrl_any_blocksz = true, 271 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 272 .stm32_idmabsize_mask = GENMASK(12, 5), 273 .busy_timeout = true, 274 .busy_detect = true, 275 .busy_detect_flag = MCI_STM32_BUSYD0, 276 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 277 .init = sdmmc_variant_init, 278 }; 279 280 static struct variant_data variant_stm32_sdmmcv2 = { 281 .fifosize = 16 * 4, 282 .fifohalfsize = 8 * 4, 283 .f_max = 267000000, 284 .stm32_clkdiv = true, 285 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 286 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 287 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 288 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 289 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 290 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 291 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 292 .datactrl_first = true, 293 .datacnt_useless = true, 294 .datalength_bits = 25, 295 .datactrl_blocksz = 14, 296 .datactrl_any_blocksz = true, 297 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 298 .stm32_idmabsize_mask = GENMASK(16, 5), 299 .dma_lli = true, 300 .busy_timeout = true, 301 .busy_detect = true, 302 .busy_detect_flag = MCI_STM32_BUSYD0, 303 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 304 .init = sdmmc_variant_init, 305 }; 306 307 static struct variant_data variant_qcom = { 308 .fifosize = 16 * 4, 309 .fifohalfsize = 8 * 4, 310 .clkreg = MCI_CLK_ENABLE, 311 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 312 MCI_QCOM_CLK_SELECT_IN_FBCLK, 313 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 314 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 315 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 316 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 317 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 318 .cmdreg_srsp = MCI_CPSM_RESPONSE, 319 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 320 .datalength_bits = 24, 321 .datactrl_blocksz = 11, 322 .datactrl_any_blocksz = true, 323 .pwrreg_powerup = MCI_PWR_UP, 324 .f_max = 208000000, 325 .explicit_mclk_control = true, 326 .qcom_fifo = true, 327 .qcom_dml = true, 328 .mmcimask1 = true, 329 .irq_pio_mask = MCI_IRQ_PIO_MASK, 330 .start_err = MCI_STARTBITERR, 331 .opendrain = MCI_ROD, 332 .init = qcom_variant_init, 333 }; 334 335 /* Busy detection for the ST Micro variant */ 336 static int mmci_card_busy(struct mmc_host *mmc) 337 { 338 struct mmci_host *host = mmc_priv(mmc); 339 unsigned long flags; 340 int busy = 0; 341 342 spin_lock_irqsave(&host->lock, flags); 343 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 344 busy = 1; 345 spin_unlock_irqrestore(&host->lock, flags); 346 347 return busy; 348 } 349 350 static void mmci_reg_delay(struct mmci_host *host) 351 { 352 /* 353 * According to the spec, at least three feedback clock cycles 354 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 355 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 356 * Worst delay time during card init is at 100 kHz => 30 us. 357 * Worst delay time when up and running is at 25 MHz => 120 ns. 358 */ 359 if (host->cclk < 25000000) 360 udelay(30); 361 else 362 ndelay(120); 363 } 364 365 /* 366 * This must be called with host->lock held 367 */ 368 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 369 { 370 if (host->clk_reg != clk) { 371 host->clk_reg = clk; 372 writel(clk, host->base + MMCICLOCK); 373 } 374 } 375 376 /* 377 * This must be called with host->lock held 378 */ 379 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 380 { 381 if (host->pwr_reg != pwr) { 382 host->pwr_reg = pwr; 383 writel(pwr, host->base + MMCIPOWER); 384 } 385 } 386 387 /* 388 * This must be called with host->lock held 389 */ 390 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 391 { 392 /* Keep busy mode in DPSM if enabled */ 393 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 394 395 if (host->datactrl_reg != datactrl) { 396 host->datactrl_reg = datactrl; 397 writel(datactrl, host->base + MMCIDATACTRL); 398 } 399 } 400 401 /* 402 * This must be called with host->lock held 403 */ 404 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 405 { 406 struct variant_data *variant = host->variant; 407 u32 clk = variant->clkreg; 408 409 /* Make sure cclk reflects the current calculated clock */ 410 host->cclk = 0; 411 412 if (desired) { 413 if (variant->explicit_mclk_control) { 414 host->cclk = host->mclk; 415 } else if (desired >= host->mclk) { 416 clk = MCI_CLK_BYPASS; 417 if (variant->st_clkdiv) 418 clk |= MCI_ST_UX500_NEG_EDGE; 419 host->cclk = host->mclk; 420 } else if (variant->st_clkdiv) { 421 /* 422 * DB8500 TRM says f = mclk / (clkdiv + 2) 423 * => clkdiv = (mclk / f) - 2 424 * Round the divider up so we don't exceed the max 425 * frequency 426 */ 427 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 428 if (clk >= 256) 429 clk = 255; 430 host->cclk = host->mclk / (clk + 2); 431 } else { 432 /* 433 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 434 * => clkdiv = mclk / (2 * f) - 1 435 */ 436 clk = host->mclk / (2 * desired) - 1; 437 if (clk >= 256) 438 clk = 255; 439 host->cclk = host->mclk / (2 * (clk + 1)); 440 } 441 442 clk |= variant->clkreg_enable; 443 clk |= MCI_CLK_ENABLE; 444 /* This hasn't proven to be worthwhile */ 445 /* clk |= MCI_CLK_PWRSAVE; */ 446 } 447 448 /* Set actual clock for debug */ 449 host->mmc->actual_clock = host->cclk; 450 451 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 452 clk |= MCI_4BIT_BUS; 453 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 454 clk |= variant->clkreg_8bit_bus_enable; 455 456 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 457 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 458 clk |= variant->clkreg_neg_edge_enable; 459 460 mmci_write_clkreg(host, clk); 461 } 462 463 static void mmci_dma_release(struct mmci_host *host) 464 { 465 if (host->ops && host->ops->dma_release) 466 host->ops->dma_release(host); 467 468 host->use_dma = false; 469 } 470 471 static void mmci_dma_setup(struct mmci_host *host) 472 { 473 if (!host->ops || !host->ops->dma_setup) 474 return; 475 476 if (host->ops->dma_setup(host)) 477 return; 478 479 /* initialize pre request cookie */ 480 host->next_cookie = 1; 481 482 host->use_dma = true; 483 } 484 485 /* 486 * Validate mmc prerequisites 487 */ 488 static int mmci_validate_data(struct mmci_host *host, 489 struct mmc_data *data) 490 { 491 struct variant_data *variant = host->variant; 492 493 if (!data) 494 return 0; 495 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { 496 dev_err(mmc_dev(host->mmc), 497 "unsupported block size (%d bytes)\n", data->blksz); 498 return -EINVAL; 499 } 500 501 if (host->ops && host->ops->validate_data) 502 return host->ops->validate_data(host, data); 503 504 return 0; 505 } 506 507 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 508 { 509 int err; 510 511 if (!host->ops || !host->ops->prep_data) 512 return 0; 513 514 err = host->ops->prep_data(host, data, next); 515 516 if (next && !err) 517 data->host_cookie = ++host->next_cookie < 0 ? 518 1 : host->next_cookie; 519 520 return err; 521 } 522 523 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 524 int err) 525 { 526 if (host->ops && host->ops->unprep_data) 527 host->ops->unprep_data(host, data, err); 528 529 data->host_cookie = 0; 530 } 531 532 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 533 { 534 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 535 536 if (host->ops && host->ops->get_next_data) 537 host->ops->get_next_data(host, data); 538 } 539 540 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 541 { 542 struct mmc_data *data = host->data; 543 int ret; 544 545 if (!host->use_dma) 546 return -EINVAL; 547 548 ret = mmci_prep_data(host, data, false); 549 if (ret) 550 return ret; 551 552 if (!host->ops || !host->ops->dma_start) 553 return -EINVAL; 554 555 /* Okay, go for it. */ 556 dev_vdbg(mmc_dev(host->mmc), 557 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 558 data->sg_len, data->blksz, data->blocks, data->flags); 559 560 ret = host->ops->dma_start(host, &datactrl); 561 if (ret) 562 return ret; 563 564 /* Trigger the DMA transfer */ 565 mmci_write_datactrlreg(host, datactrl); 566 567 /* 568 * Let the MMCI say when the data is ended and it's time 569 * to fire next DMA request. When that happens, MMCI will 570 * call mmci_data_end() 571 */ 572 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 573 host->base + MMCIMASK0); 574 return 0; 575 } 576 577 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 578 { 579 if (!host->use_dma) 580 return; 581 582 if (host->ops && host->ops->dma_finalize) 583 host->ops->dma_finalize(host, data); 584 } 585 586 static void mmci_dma_error(struct mmci_host *host) 587 { 588 if (!host->use_dma) 589 return; 590 591 if (host->ops && host->ops->dma_error) 592 host->ops->dma_error(host); 593 } 594 595 static void 596 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 597 { 598 writel(0, host->base + MMCICOMMAND); 599 600 BUG_ON(host->data); 601 602 host->mrq = NULL; 603 host->cmd = NULL; 604 605 mmc_request_done(host->mmc, mrq); 606 } 607 608 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 609 { 610 void __iomem *base = host->base; 611 struct variant_data *variant = host->variant; 612 613 if (host->singleirq) { 614 unsigned int mask0 = readl(base + MMCIMASK0); 615 616 mask0 &= ~variant->irq_pio_mask; 617 mask0 |= mask; 618 619 writel(mask0, base + MMCIMASK0); 620 } 621 622 if (variant->mmcimask1) 623 writel(mask, base + MMCIMASK1); 624 625 host->mask1_reg = mask; 626 } 627 628 static void mmci_stop_data(struct mmci_host *host) 629 { 630 mmci_write_datactrlreg(host, 0); 631 mmci_set_mask1(host, 0); 632 host->data = NULL; 633 } 634 635 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 636 { 637 unsigned int flags = SG_MITER_ATOMIC; 638 639 if (data->flags & MMC_DATA_READ) 640 flags |= SG_MITER_TO_SG; 641 else 642 flags |= SG_MITER_FROM_SG; 643 644 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 645 } 646 647 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 648 { 649 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 650 } 651 652 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 653 { 654 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 655 } 656 657 /* 658 * ux500_busy_complete() - this will wait until the busy status 659 * goes off, saving any status that occur in the meantime into 660 * host->busy_status until we know the card is not busy any more. 661 * The function returns true when the busy detection is ended 662 * and we should continue processing the command. 663 * 664 * The Ux500 typically fires two IRQs over a busy cycle like this: 665 * 666 * DAT0 busy +-----------------+ 667 * | | 668 * DAT0 not busy ----+ +-------- 669 * 670 * ^ ^ 671 * | | 672 * IRQ1 IRQ2 673 */ 674 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 675 { 676 void __iomem *base = host->base; 677 int retries = 10; 678 679 if (status & err_msk) { 680 /* Stop any ongoing busy detection if an error occurs */ 681 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 682 writel(readl(base + MMCIMASK0) & 683 ~host->variant->busy_detect_mask, base + MMCIMASK0); 684 host->busy_state = MMCI_BUSY_DONE; 685 host->busy_status = 0; 686 goto out_ret_state; 687 } 688 689 /* 690 * The state transitions are encoded in a state machine crossing 691 * the edges in this switch statement. 692 */ 693 switch (host->busy_state) { 694 695 /* 696 * Before unmasking for the busy end IRQ, confirm that the 697 * command was sent successfully. To keep track of having a 698 * command in-progress, waiting for busy signaling to end, 699 * store the status in host->busy_status. 700 * 701 * Note that, the card may need a couple of clock cycles before 702 * it starts signaling busy on DAT0, hence re-read the 703 * MMCISTATUS register here, to allow the busy bit to be set. 704 */ 705 case MMCI_BUSY_DONE: 706 /* 707 * Save the first status register read to be sure to catch 708 * all bits that may be lost will retrying. If the command 709 * is still busy this will result in assigning 0 to 710 * host->busy_status, which is what it should be in IDLE. 711 */ 712 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 713 while (retries) { 714 status = readl(base + MMCISTATUS); 715 /* Keep accumulating status bits */ 716 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 717 if (status & host->variant->busy_detect_flag) { 718 writel(readl(base + MMCIMASK0) | 719 host->variant->busy_detect_mask, 720 base + MMCIMASK0); 721 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; 722 goto out_ret_state; 723 } 724 retries--; 725 } 726 dev_dbg(mmc_dev(host->mmc), "no busy signalling in time\n"); 727 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 728 writel(readl(base + MMCIMASK0) & 729 ~host->variant->busy_detect_mask, base + MMCIMASK0); 730 host->busy_state = MMCI_BUSY_DONE; 731 break; 732 733 /* 734 * If there is a command in-progress that has been successfully 735 * sent, then bail out if busy status is set and wait for the 736 * busy end IRQ. 737 * 738 * Note that, the HW triggers an IRQ on both edges while 739 * monitoring DAT0 for busy completion, but there is only one 740 * status bit in MMCISTATUS for the busy state. Therefore 741 * both the start and the end interrupts needs to be cleared, 742 * one after the other. So, clear the busy start IRQ here. 743 */ 744 case MMCI_BUSY_WAITING_FOR_START_IRQ: 745 if (status & host->variant->busy_detect_flag) { 746 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 747 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 748 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ; 749 } else { 750 dev_dbg(mmc_dev(host->mmc), 751 "lost busy status when waiting for busy start IRQ\n"); 752 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 753 writel(readl(base + MMCIMASK0) & 754 ~host->variant->busy_detect_mask, base + MMCIMASK0); 755 host->busy_state = MMCI_BUSY_DONE; 756 host->busy_status = 0; 757 } 758 break; 759 760 case MMCI_BUSY_WAITING_FOR_END_IRQ: 761 if (!(status & host->variant->busy_detect_flag)) { 762 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 763 host->busy_state = MMCI_BUSY_DONE; 764 } else { 765 dev_dbg(mmc_dev(host->mmc), 766 "busy status still asserted when handling busy end IRQ - will keep waiting\n"); 767 } 768 break; 769 770 default: 771 dev_dbg(mmc_dev(host->mmc), "fell through on state %d\n", 772 host->busy_state); 773 break; 774 } 775 776 out_ret_state: 777 return (host->busy_state == MMCI_BUSY_DONE); 778 } 779 780 /* 781 * All the DMA operation mode stuff goes inside this ifdef. 782 * This assumes that you have a generic DMA device interface, 783 * no custom DMA interfaces are supported. 784 */ 785 #ifdef CONFIG_DMA_ENGINE 786 struct mmci_dmae_next { 787 struct dma_async_tx_descriptor *desc; 788 struct dma_chan *chan; 789 }; 790 791 struct mmci_dmae_priv { 792 struct dma_chan *cur; 793 struct dma_chan *rx_channel; 794 struct dma_chan *tx_channel; 795 struct dma_async_tx_descriptor *desc_current; 796 struct mmci_dmae_next next_data; 797 }; 798 799 int mmci_dmae_setup(struct mmci_host *host) 800 { 801 const char *rxname, *txname; 802 struct mmci_dmae_priv *dmae; 803 804 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 805 if (!dmae) 806 return -ENOMEM; 807 808 host->dma_priv = dmae; 809 810 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); 811 if (IS_ERR(dmae->rx_channel)) { 812 int ret = PTR_ERR(dmae->rx_channel); 813 dmae->rx_channel = NULL; 814 return ret; 815 } 816 817 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); 818 if (IS_ERR(dmae->tx_channel)) { 819 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) 820 dev_warn(mmc_dev(host->mmc), 821 "Deferred probe for TX channel ignored\n"); 822 dmae->tx_channel = NULL; 823 } 824 825 /* 826 * If only an RX channel is specified, the driver will 827 * attempt to use it bidirectionally, however if it 828 * is specified but cannot be located, DMA will be disabled. 829 */ 830 if (dmae->rx_channel && !dmae->tx_channel) 831 dmae->tx_channel = dmae->rx_channel; 832 833 if (dmae->rx_channel) 834 rxname = dma_chan_name(dmae->rx_channel); 835 else 836 rxname = "none"; 837 838 if (dmae->tx_channel) 839 txname = dma_chan_name(dmae->tx_channel); 840 else 841 txname = "none"; 842 843 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 844 rxname, txname); 845 846 /* 847 * Limit the maximum segment size in any SG entry according to 848 * the parameters of the DMA engine device. 849 */ 850 if (dmae->tx_channel) { 851 struct device *dev = dmae->tx_channel->device->dev; 852 unsigned int max_seg_size = dma_get_max_seg_size(dev); 853 854 if (max_seg_size < host->mmc->max_seg_size) 855 host->mmc->max_seg_size = max_seg_size; 856 } 857 if (dmae->rx_channel) { 858 struct device *dev = dmae->rx_channel->device->dev; 859 unsigned int max_seg_size = dma_get_max_seg_size(dev); 860 861 if (max_seg_size < host->mmc->max_seg_size) 862 host->mmc->max_seg_size = max_seg_size; 863 } 864 865 if (!dmae->tx_channel || !dmae->rx_channel) { 866 mmci_dmae_release(host); 867 return -EINVAL; 868 } 869 870 return 0; 871 } 872 873 /* 874 * This is used in or so inline it 875 * so it can be discarded. 876 */ 877 void mmci_dmae_release(struct mmci_host *host) 878 { 879 struct mmci_dmae_priv *dmae = host->dma_priv; 880 881 if (dmae->rx_channel) 882 dma_release_channel(dmae->rx_channel); 883 if (dmae->tx_channel) 884 dma_release_channel(dmae->tx_channel); 885 dmae->rx_channel = dmae->tx_channel = NULL; 886 } 887 888 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 889 { 890 struct mmci_dmae_priv *dmae = host->dma_priv; 891 struct dma_chan *chan; 892 893 if (data->flags & MMC_DATA_READ) 894 chan = dmae->rx_channel; 895 else 896 chan = dmae->tx_channel; 897 898 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 899 mmc_get_dma_dir(data)); 900 } 901 902 void mmci_dmae_error(struct mmci_host *host) 903 { 904 struct mmci_dmae_priv *dmae = host->dma_priv; 905 906 if (!dma_inprogress(host)) 907 return; 908 909 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 910 dmaengine_terminate_all(dmae->cur); 911 host->dma_in_progress = false; 912 dmae->cur = NULL; 913 dmae->desc_current = NULL; 914 host->data->host_cookie = 0; 915 916 mmci_dma_unmap(host, host->data); 917 } 918 919 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 920 { 921 struct mmci_dmae_priv *dmae = host->dma_priv; 922 u32 status; 923 int i; 924 925 if (!dma_inprogress(host)) 926 return; 927 928 /* Wait up to 1ms for the DMA to complete */ 929 for (i = 0; ; i++) { 930 status = readl(host->base + MMCISTATUS); 931 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 932 break; 933 udelay(10); 934 } 935 936 /* 937 * Check to see whether we still have some data left in the FIFO - 938 * this catches DMA controllers which are unable to monitor the 939 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 940 * contiguous buffers. On TX, we'll get a FIFO underrun error. 941 */ 942 if (status & MCI_RXDATAAVLBLMASK) { 943 mmci_dma_error(host); 944 if (!data->error) 945 data->error = -EIO; 946 } else if (!data->host_cookie) { 947 mmci_dma_unmap(host, data); 948 } 949 950 /* 951 * Use of DMA with scatter-gather is impossible. 952 * Give up with DMA and switch back to PIO mode. 953 */ 954 if (status & MCI_RXDATAAVLBLMASK) { 955 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 956 mmci_dma_release(host); 957 } 958 959 host->dma_in_progress = false; 960 dmae->cur = NULL; 961 dmae->desc_current = NULL; 962 } 963 964 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 965 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 966 struct dma_chan **dma_chan, 967 struct dma_async_tx_descriptor **dma_desc) 968 { 969 struct mmci_dmae_priv *dmae = host->dma_priv; 970 struct variant_data *variant = host->variant; 971 struct dma_slave_config conf = { 972 .src_addr = host->phybase + MMCIFIFO, 973 .dst_addr = host->phybase + MMCIFIFO, 974 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 975 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 976 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 977 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 978 .device_fc = false, 979 }; 980 struct dma_chan *chan; 981 struct dma_device *device; 982 struct dma_async_tx_descriptor *desc; 983 int nr_sg; 984 unsigned long flags = DMA_CTRL_ACK; 985 986 if (data->flags & MMC_DATA_READ) { 987 conf.direction = DMA_DEV_TO_MEM; 988 chan = dmae->rx_channel; 989 } else { 990 conf.direction = DMA_MEM_TO_DEV; 991 chan = dmae->tx_channel; 992 } 993 994 /* If there's no DMA channel, fall back to PIO */ 995 if (!chan) 996 return -EINVAL; 997 998 /* If less than or equal to the fifo size, don't bother with DMA */ 999 if (data->blksz * data->blocks <= variant->fifosize) 1000 return -EINVAL; 1001 1002 /* 1003 * This is necessary to get SDIO working on the Ux500. We do not yet 1004 * know if this is a bug in: 1005 * - The Ux500 DMA controller (DMA40) 1006 * - The MMCI DMA interface on the Ux500 1007 * some power of two blocks (such as 64 bytes) are sent regularly 1008 * during SDIO traffic and those work fine so for these we enable DMA 1009 * transfers. 1010 */ 1011 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) 1012 return -EINVAL; 1013 1014 device = chan->device; 1015 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 1016 mmc_get_dma_dir(data)); 1017 if (nr_sg == 0) 1018 return -EINVAL; 1019 1020 if (host->variant->qcom_dml) 1021 flags |= DMA_PREP_INTERRUPT; 1022 1023 dmaengine_slave_config(chan, &conf); 1024 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 1025 conf.direction, flags); 1026 if (!desc) 1027 goto unmap_exit; 1028 1029 *dma_chan = chan; 1030 *dma_desc = desc; 1031 1032 return 0; 1033 1034 unmap_exit: 1035 dma_unmap_sg(device->dev, data->sg, data->sg_len, 1036 mmc_get_dma_dir(data)); 1037 return -ENOMEM; 1038 } 1039 1040 int mmci_dmae_prep_data(struct mmci_host *host, 1041 struct mmc_data *data, 1042 bool next) 1043 { 1044 struct mmci_dmae_priv *dmae = host->dma_priv; 1045 struct mmci_dmae_next *nd = &dmae->next_data; 1046 1047 if (!host->use_dma) 1048 return -EINVAL; 1049 1050 if (next) 1051 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 1052 /* Check if next job is already prepared. */ 1053 if (dmae->cur && dmae->desc_current) 1054 return 0; 1055 1056 /* No job were prepared thus do it now. */ 1057 return _mmci_dmae_prep_data(host, data, &dmae->cur, 1058 &dmae->desc_current); 1059 } 1060 1061 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 1062 { 1063 struct mmci_dmae_priv *dmae = host->dma_priv; 1064 int ret; 1065 1066 host->dma_in_progress = true; 1067 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); 1068 if (ret < 0) { 1069 host->dma_in_progress = false; 1070 return ret; 1071 } 1072 dma_async_issue_pending(dmae->cur); 1073 1074 *datactrl |= MCI_DPSM_DMAENABLE; 1075 1076 return 0; 1077 } 1078 1079 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 1080 { 1081 struct mmci_dmae_priv *dmae = host->dma_priv; 1082 struct mmci_dmae_next *next = &dmae->next_data; 1083 1084 if (!host->use_dma) 1085 return; 1086 1087 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 1088 1089 dmae->desc_current = next->desc; 1090 dmae->cur = next->chan; 1091 next->desc = NULL; 1092 next->chan = NULL; 1093 } 1094 1095 void mmci_dmae_unprep_data(struct mmci_host *host, 1096 struct mmc_data *data, int err) 1097 1098 { 1099 struct mmci_dmae_priv *dmae = host->dma_priv; 1100 1101 if (!host->use_dma) 1102 return; 1103 1104 mmci_dma_unmap(host, data); 1105 1106 if (err) { 1107 struct mmci_dmae_next *next = &dmae->next_data; 1108 struct dma_chan *chan; 1109 if (data->flags & MMC_DATA_READ) 1110 chan = dmae->rx_channel; 1111 else 1112 chan = dmae->tx_channel; 1113 dmaengine_terminate_all(chan); 1114 1115 if (dmae->desc_current == next->desc) 1116 dmae->desc_current = NULL; 1117 1118 if (dmae->cur == next->chan) { 1119 host->dma_in_progress = false; 1120 dmae->cur = NULL; 1121 } 1122 1123 next->desc = NULL; 1124 next->chan = NULL; 1125 } 1126 } 1127 1128 static struct mmci_host_ops mmci_variant_ops = { 1129 .prep_data = mmci_dmae_prep_data, 1130 .unprep_data = mmci_dmae_unprep_data, 1131 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1132 .get_next_data = mmci_dmae_get_next_data, 1133 .dma_setup = mmci_dmae_setup, 1134 .dma_release = mmci_dmae_release, 1135 .dma_start = mmci_dmae_start, 1136 .dma_finalize = mmci_dmae_finalize, 1137 .dma_error = mmci_dmae_error, 1138 }; 1139 #else 1140 static struct mmci_host_ops mmci_variant_ops = { 1141 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1142 }; 1143 #endif 1144 1145 static void mmci_variant_init(struct mmci_host *host) 1146 { 1147 host->ops = &mmci_variant_ops; 1148 } 1149 1150 static void ux500_variant_init(struct mmci_host *host) 1151 { 1152 host->ops = &mmci_variant_ops; 1153 host->ops->busy_complete = ux500_busy_complete; 1154 } 1155 1156 static void ux500v2_variant_init(struct mmci_host *host) 1157 { 1158 host->ops = &mmci_variant_ops; 1159 host->ops->busy_complete = ux500_busy_complete; 1160 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1161 } 1162 1163 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1164 { 1165 struct mmci_host *host = mmc_priv(mmc); 1166 struct mmc_data *data = mrq->data; 1167 1168 if (!data) 1169 return; 1170 1171 WARN_ON(data->host_cookie); 1172 1173 if (mmci_validate_data(host, data)) 1174 return; 1175 1176 mmci_prep_data(host, data, true); 1177 } 1178 1179 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1180 int err) 1181 { 1182 struct mmci_host *host = mmc_priv(mmc); 1183 struct mmc_data *data = mrq->data; 1184 1185 if (!data || !data->host_cookie) 1186 return; 1187 1188 mmci_unprep_data(host, data, err); 1189 } 1190 1191 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1192 { 1193 struct variant_data *variant = host->variant; 1194 unsigned int datactrl, timeout, irqmask; 1195 unsigned long long clks; 1196 void __iomem *base; 1197 1198 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1199 data->blksz, data->blocks, data->flags); 1200 1201 host->data = data; 1202 host->size = data->blksz * data->blocks; 1203 data->bytes_xfered = 0; 1204 1205 clks = (unsigned long long)data->timeout_ns * host->cclk; 1206 do_div(clks, NSEC_PER_SEC); 1207 1208 timeout = data->timeout_clks + (unsigned int)clks; 1209 1210 base = host->base; 1211 writel(timeout, base + MMCIDATATIMER); 1212 writel(host->size, base + MMCIDATALENGTH); 1213 1214 datactrl = host->ops->get_datactrl_cfg(host); 1215 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1216 1217 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1218 u32 clk; 1219 1220 datactrl |= variant->datactrl_mask_sdio; 1221 1222 /* 1223 * The ST Micro variant for SDIO small write transfers 1224 * needs to have clock H/W flow control disabled, 1225 * otherwise the transfer will not start. The threshold 1226 * depends on the rate of MCLK. 1227 */ 1228 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1229 (host->size < 8 || 1230 (host->size <= 8 && host->mclk > 50000000))) 1231 clk = host->clk_reg & ~variant->clkreg_enable; 1232 else 1233 clk = host->clk_reg | variant->clkreg_enable; 1234 1235 mmci_write_clkreg(host, clk); 1236 } 1237 1238 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1239 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1240 datactrl |= variant->datactrl_mask_ddrmode; 1241 1242 /* 1243 * Attempt to use DMA operation mode, if this 1244 * should fail, fall back to PIO mode 1245 */ 1246 if (!mmci_dma_start(host, datactrl)) 1247 return; 1248 1249 /* IRQ mode, map the SG list for CPU reading/writing */ 1250 mmci_init_sg(host, data); 1251 1252 if (data->flags & MMC_DATA_READ) { 1253 irqmask = MCI_RXFIFOHALFFULLMASK; 1254 1255 /* 1256 * If we have less than the fifo 'half-full' threshold to 1257 * transfer, trigger a PIO interrupt as soon as any data 1258 * is available. 1259 */ 1260 if (host->size < variant->fifohalfsize) 1261 irqmask |= MCI_RXDATAAVLBLMASK; 1262 } else { 1263 /* 1264 * We don't actually need to include "FIFO empty" here 1265 * since its implicit in "FIFO half empty". 1266 */ 1267 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1268 } 1269 1270 mmci_write_datactrlreg(host, datactrl); 1271 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1272 mmci_set_mask1(host, irqmask); 1273 } 1274 1275 static void 1276 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1277 { 1278 void __iomem *base = host->base; 1279 unsigned long long clks; 1280 1281 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1282 cmd->opcode, cmd->arg, cmd->flags); 1283 1284 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1285 writel(0, base + MMCICOMMAND); 1286 mmci_reg_delay(host); 1287 } 1288 1289 if (host->variant->cmdreg_stop && 1290 cmd->opcode == MMC_STOP_TRANSMISSION) 1291 c |= host->variant->cmdreg_stop; 1292 1293 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1294 if (cmd->flags & MMC_RSP_PRESENT) { 1295 if (cmd->flags & MMC_RSP_136) 1296 c |= host->variant->cmdreg_lrsp_crc; 1297 else if (cmd->flags & MMC_RSP_CRC) 1298 c |= host->variant->cmdreg_srsp_crc; 1299 else 1300 c |= host->variant->cmdreg_srsp; 1301 } 1302 1303 host->busy_status = 0; 1304 host->busy_state = MMCI_BUSY_DONE; 1305 1306 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1307 if (!cmd->busy_timeout) 1308 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1309 1310 if (cmd->busy_timeout > host->mmc->max_busy_timeout) 1311 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; 1312 else 1313 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1314 1315 do_div(clks, MSEC_PER_SEC); 1316 writel_relaxed(clks, host->base + MMCIDATATIMER); 1317 } 1318 1319 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) 1320 host->ops->pre_sig_volt_switch(host); 1321 1322 if (/*interrupt*/0) 1323 c |= MCI_CPSM_INTERRUPT; 1324 1325 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1326 c |= host->variant->data_cmd_enable; 1327 1328 host->cmd = cmd; 1329 1330 writel(cmd->arg, base + MMCIARGUMENT); 1331 writel(c, base + MMCICOMMAND); 1332 } 1333 1334 static void mmci_stop_command(struct mmci_host *host) 1335 { 1336 host->stop_abort.error = 0; 1337 mmci_start_command(host, &host->stop_abort, 0); 1338 } 1339 1340 static void 1341 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1342 unsigned int status) 1343 { 1344 unsigned int status_err; 1345 1346 /* Make sure we have data to handle */ 1347 if (!data) 1348 return; 1349 1350 /* First check for errors */ 1351 status_err = status & (host->variant->start_err | 1352 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1353 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1354 1355 if (status_err) { 1356 u32 remain, success; 1357 1358 /* Terminate the DMA transfer */ 1359 mmci_dma_error(host); 1360 1361 /* 1362 * Calculate how far we are into the transfer. Note that 1363 * the data counter gives the number of bytes transferred 1364 * on the MMC bus, not on the host side. On reads, this 1365 * can be as much as a FIFO-worth of data ahead. This 1366 * matters for FIFO overruns only. 1367 */ 1368 if (!host->variant->datacnt_useless) { 1369 remain = readl(host->base + MMCIDATACNT); 1370 success = data->blksz * data->blocks - remain; 1371 } else { 1372 success = 0; 1373 } 1374 1375 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1376 status_err, success); 1377 if (status_err & MCI_DATACRCFAIL) { 1378 /* Last block was not successful */ 1379 success -= 1; 1380 data->error = -EILSEQ; 1381 } else if (status_err & MCI_DATATIMEOUT) { 1382 data->error = -ETIMEDOUT; 1383 } else if (status_err & MCI_STARTBITERR) { 1384 data->error = -ECOMM; 1385 } else if (status_err & MCI_TXUNDERRUN) { 1386 data->error = -EIO; 1387 } else if (status_err & MCI_RXOVERRUN) { 1388 if (success > host->variant->fifosize) 1389 success -= host->variant->fifosize; 1390 else 1391 success = 0; 1392 data->error = -EIO; 1393 } 1394 data->bytes_xfered = round_down(success, data->blksz); 1395 } 1396 1397 if (status & MCI_DATABLOCKEND) 1398 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1399 1400 if (status & MCI_DATAEND || data->error) { 1401 mmci_dma_finalize(host, data); 1402 1403 mmci_stop_data(host); 1404 1405 if (!data->error) 1406 /* The error clause is handled above, success! */ 1407 data->bytes_xfered = data->blksz * data->blocks; 1408 1409 if (!data->stop) { 1410 if (host->variant->cmdreg_stop && data->error) 1411 mmci_stop_command(host); 1412 else 1413 mmci_request_end(host, data->mrq); 1414 } else if (host->mrq->sbc && !data->error) { 1415 mmci_request_end(host, data->mrq); 1416 } else { 1417 mmci_start_command(host, data->stop, 0); 1418 } 1419 } 1420 } 1421 1422 static void 1423 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1424 unsigned int status) 1425 { 1426 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1427 void __iomem *base = host->base; 1428 bool sbc, busy_resp; 1429 1430 if (!cmd) 1431 return; 1432 1433 sbc = (cmd == host->mrq->sbc); 1434 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1435 1436 /* 1437 * We need to be one of these interrupts to be considered worth 1438 * handling. Note that we tag on any latent IRQs postponed 1439 * due to waiting for busy status. 1440 */ 1441 if (host->variant->busy_timeout && busy_resp) 1442 err_msk |= MCI_DATATIMEOUT; 1443 1444 if (!((status | host->busy_status) & 1445 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1446 return; 1447 1448 /* Handle busy detection on DAT0 if the variant supports it. */ 1449 if (busy_resp && host->variant->busy_detect) 1450 if (!host->ops->busy_complete(host, status, err_msk)) 1451 return; 1452 1453 host->cmd = NULL; 1454 1455 if (status & MCI_CMDTIMEOUT) { 1456 cmd->error = -ETIMEDOUT; 1457 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1458 cmd->error = -EILSEQ; 1459 } else if (host->variant->busy_timeout && busy_resp && 1460 status & MCI_DATATIMEOUT) { 1461 cmd->error = -ETIMEDOUT; 1462 /* 1463 * This will wake up mmci_irq_thread() which will issue 1464 * a hardware reset of the MMCI block. 1465 */ 1466 host->irq_action = IRQ_WAKE_THREAD; 1467 } else { 1468 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1469 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1470 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1471 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1472 } 1473 1474 if ((!sbc && !cmd->data) || cmd->error) { 1475 if (host->data) { 1476 /* Terminate the DMA transfer */ 1477 mmci_dma_error(host); 1478 1479 mmci_stop_data(host); 1480 if (host->variant->cmdreg_stop && cmd->error) { 1481 mmci_stop_command(host); 1482 return; 1483 } 1484 } 1485 1486 if (host->irq_action != IRQ_WAKE_THREAD) 1487 mmci_request_end(host, host->mrq); 1488 1489 } else if (sbc) { 1490 mmci_start_command(host, host->mrq->cmd, 0); 1491 } else if (!host->variant->datactrl_first && 1492 !(cmd->data->flags & MMC_DATA_READ)) { 1493 mmci_start_data(host, cmd->data); 1494 } 1495 } 1496 1497 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1498 { 1499 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1500 } 1501 1502 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1503 { 1504 /* 1505 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1506 * from the fifo range should be used 1507 */ 1508 if (status & MCI_RXFIFOHALFFULL) 1509 return host->variant->fifohalfsize; 1510 else if (status & MCI_RXDATAAVLBL) 1511 return 4; 1512 1513 return 0; 1514 } 1515 1516 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1517 { 1518 void __iomem *base = host->base; 1519 char *ptr = buffer; 1520 u32 status = readl(host->base + MMCISTATUS); 1521 int host_remain = host->size; 1522 1523 do { 1524 int count = host->get_rx_fifocnt(host, status, host_remain); 1525 1526 if (count > remain) 1527 count = remain; 1528 1529 if (count <= 0) 1530 break; 1531 1532 /* 1533 * SDIO especially may want to send something that is 1534 * not divisible by 4 (as opposed to card sectors 1535 * etc). Therefore make sure to always read the last bytes 1536 * while only doing full 32-bit reads towards the FIFO. 1537 */ 1538 if (unlikely(count & 0x3)) { 1539 if (count < 4) { 1540 unsigned char buf[4]; 1541 ioread32_rep(base + MMCIFIFO, buf, 1); 1542 memcpy(ptr, buf, count); 1543 } else { 1544 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1545 count &= ~0x3; 1546 } 1547 } else { 1548 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1549 } 1550 1551 ptr += count; 1552 remain -= count; 1553 host_remain -= count; 1554 1555 if (remain == 0) 1556 break; 1557 1558 status = readl(base + MMCISTATUS); 1559 } while (status & MCI_RXDATAAVLBL); 1560 1561 return ptr - buffer; 1562 } 1563 1564 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1565 { 1566 struct variant_data *variant = host->variant; 1567 void __iomem *base = host->base; 1568 char *ptr = buffer; 1569 1570 do { 1571 unsigned int count, maxcnt; 1572 1573 maxcnt = status & MCI_TXFIFOEMPTY ? 1574 variant->fifosize : variant->fifohalfsize; 1575 count = min(remain, maxcnt); 1576 1577 /* 1578 * SDIO especially may want to send something that is 1579 * not divisible by 4 (as opposed to card sectors 1580 * etc), and the FIFO only accept full 32-bit writes. 1581 * So compensate by adding +3 on the count, a single 1582 * byte become a 32bit write, 7 bytes will be two 1583 * 32bit writes etc. 1584 */ 1585 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1586 1587 ptr += count; 1588 remain -= count; 1589 1590 if (remain == 0) 1591 break; 1592 1593 status = readl(base + MMCISTATUS); 1594 } while (status & MCI_TXFIFOHALFEMPTY); 1595 1596 return ptr - buffer; 1597 } 1598 1599 /* 1600 * PIO data transfer IRQ handler. 1601 */ 1602 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1603 { 1604 struct mmci_host *host = dev_id; 1605 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1606 struct variant_data *variant = host->variant; 1607 void __iomem *base = host->base; 1608 u32 status; 1609 1610 status = readl(base + MMCISTATUS); 1611 1612 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1613 1614 do { 1615 unsigned int remain, len; 1616 char *buffer; 1617 1618 /* 1619 * For write, we only need to test the half-empty flag 1620 * here - if the FIFO is completely empty, then by 1621 * definition it is more than half empty. 1622 * 1623 * For read, check for data available. 1624 */ 1625 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1626 break; 1627 1628 if (!sg_miter_next(sg_miter)) 1629 break; 1630 1631 buffer = sg_miter->addr; 1632 remain = sg_miter->length; 1633 1634 len = 0; 1635 if (status & MCI_RXACTIVE) 1636 len = mmci_pio_read(host, buffer, remain); 1637 if (status & MCI_TXACTIVE) 1638 len = mmci_pio_write(host, buffer, remain, status); 1639 1640 sg_miter->consumed = len; 1641 1642 host->size -= len; 1643 remain -= len; 1644 1645 if (remain) 1646 break; 1647 1648 status = readl(base + MMCISTATUS); 1649 } while (1); 1650 1651 sg_miter_stop(sg_miter); 1652 1653 /* 1654 * If we have less than the fifo 'half-full' threshold to transfer, 1655 * trigger a PIO interrupt as soon as any data is available. 1656 */ 1657 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1658 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1659 1660 /* 1661 * If we run out of data, disable the data IRQs; this 1662 * prevents a race where the FIFO becomes empty before 1663 * the chip itself has disabled the data path, and 1664 * stops us racing with our data end IRQ. 1665 */ 1666 if (host->size == 0) { 1667 mmci_set_mask1(host, 0); 1668 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1669 } 1670 1671 return IRQ_HANDLED; 1672 } 1673 1674 /* 1675 * Handle completion of command and data transfers. 1676 */ 1677 static irqreturn_t mmci_irq(int irq, void *dev_id) 1678 { 1679 struct mmci_host *host = dev_id; 1680 u32 status; 1681 1682 spin_lock(&host->lock); 1683 host->irq_action = IRQ_HANDLED; 1684 1685 do { 1686 status = readl(host->base + MMCISTATUS); 1687 if (!status) 1688 break; 1689 1690 if (host->singleirq) { 1691 if (status & host->mask1_reg) 1692 mmci_pio_irq(irq, dev_id); 1693 1694 status &= ~host->variant->irq_pio_mask; 1695 } 1696 1697 /* 1698 * Busy detection is managed by mmci_cmd_irq(), including to 1699 * clear the corresponding IRQ. 1700 */ 1701 status &= readl(host->base + MMCIMASK0); 1702 if (host->variant->busy_detect) 1703 writel(status & ~host->variant->busy_detect_mask, 1704 host->base + MMCICLEAR); 1705 else 1706 writel(status, host->base + MMCICLEAR); 1707 1708 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1709 1710 if (host->variant->reversed_irq_handling) { 1711 mmci_data_irq(host, host->data, status); 1712 mmci_cmd_irq(host, host->cmd, status); 1713 } else { 1714 mmci_cmd_irq(host, host->cmd, status); 1715 mmci_data_irq(host, host->data, status); 1716 } 1717 1718 /* 1719 * Busy detection has been handled by mmci_cmd_irq() above. 1720 * Clear the status bit to prevent polling in IRQ context. 1721 */ 1722 if (host->variant->busy_detect_flag) 1723 status &= ~host->variant->busy_detect_flag; 1724 1725 } while (status); 1726 1727 spin_unlock(&host->lock); 1728 1729 return host->irq_action; 1730 } 1731 1732 /* 1733 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. 1734 * 1735 * A reset is needed for some variants, where a datatimeout for a R1B request 1736 * causes the DPSM to stay busy (non-functional). 1737 */ 1738 static irqreturn_t mmci_irq_thread(int irq, void *dev_id) 1739 { 1740 struct mmci_host *host = dev_id; 1741 unsigned long flags; 1742 1743 if (host->rst) { 1744 reset_control_assert(host->rst); 1745 udelay(2); 1746 reset_control_deassert(host->rst); 1747 } 1748 1749 spin_lock_irqsave(&host->lock, flags); 1750 writel(host->clk_reg, host->base + MMCICLOCK); 1751 writel(host->pwr_reg, host->base + MMCIPOWER); 1752 writel(MCI_IRQENABLE | host->variant->start_err, 1753 host->base + MMCIMASK0); 1754 1755 host->irq_action = IRQ_HANDLED; 1756 mmci_request_end(host, host->mrq); 1757 spin_unlock_irqrestore(&host->lock, flags); 1758 1759 return host->irq_action; 1760 } 1761 1762 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1763 { 1764 struct mmci_host *host = mmc_priv(mmc); 1765 unsigned long flags; 1766 1767 WARN_ON(host->mrq != NULL); 1768 1769 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1770 if (mrq->cmd->error) { 1771 mmc_request_done(mmc, mrq); 1772 return; 1773 } 1774 1775 spin_lock_irqsave(&host->lock, flags); 1776 1777 host->mrq = mrq; 1778 1779 if (mrq->data) 1780 mmci_get_next_data(host, mrq->data); 1781 1782 if (mrq->data && 1783 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1784 mmci_start_data(host, mrq->data); 1785 1786 if (mrq->sbc) 1787 mmci_start_command(host, mrq->sbc, 0); 1788 else 1789 mmci_start_command(host, mrq->cmd, 0); 1790 1791 spin_unlock_irqrestore(&host->lock, flags); 1792 } 1793 1794 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1795 { 1796 struct mmci_host *host = mmc_priv(mmc); 1797 u32 max_busy_timeout = 0; 1798 1799 if (!host->variant->busy_detect) 1800 return; 1801 1802 if (host->variant->busy_timeout && mmc->actual_clock) 1803 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, 1804 MSEC_PER_SEC); 1805 1806 mmc->max_busy_timeout = max_busy_timeout; 1807 } 1808 1809 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1810 { 1811 struct mmci_host *host = mmc_priv(mmc); 1812 struct variant_data *variant = host->variant; 1813 u32 pwr = 0; 1814 unsigned long flags; 1815 int ret; 1816 1817 switch (ios->power_mode) { 1818 case MMC_POWER_OFF: 1819 if (!IS_ERR(mmc->supply.vmmc)) 1820 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1821 1822 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1823 regulator_disable(mmc->supply.vqmmc); 1824 host->vqmmc_enabled = false; 1825 } 1826 1827 break; 1828 case MMC_POWER_UP: 1829 if (!IS_ERR(mmc->supply.vmmc)) 1830 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1831 1832 /* 1833 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1834 * and instead uses MCI_PWR_ON so apply whatever value is 1835 * configured in the variant data. 1836 */ 1837 pwr |= variant->pwrreg_powerup; 1838 1839 break; 1840 case MMC_POWER_ON: 1841 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1842 ret = regulator_enable(mmc->supply.vqmmc); 1843 if (ret < 0) 1844 dev_err(mmc_dev(mmc), 1845 "failed to enable vqmmc regulator\n"); 1846 else 1847 host->vqmmc_enabled = true; 1848 } 1849 1850 pwr |= MCI_PWR_ON; 1851 break; 1852 } 1853 1854 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1855 /* 1856 * The ST Micro variant has some additional bits 1857 * indicating signal direction for the signals in 1858 * the SD/MMC bus and feedback-clock usage. 1859 */ 1860 pwr |= host->pwr_reg_add; 1861 1862 if (ios->bus_width == MMC_BUS_WIDTH_4) 1863 pwr &= ~MCI_ST_DATA74DIREN; 1864 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1865 pwr &= (~MCI_ST_DATA74DIREN & 1866 ~MCI_ST_DATA31DIREN & 1867 ~MCI_ST_DATA2DIREN); 1868 } 1869 1870 if (variant->opendrain) { 1871 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1872 pwr |= variant->opendrain; 1873 } else { 1874 /* 1875 * If the variant cannot configure the pads by its own, then we 1876 * expect the pinctrl to be able to do that for us 1877 */ 1878 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1879 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1880 else 1881 pinctrl_select_default_state(mmc_dev(mmc)); 1882 } 1883 1884 /* 1885 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1886 * gating the clock, the MCI_PWR_ON bit is cleared. 1887 */ 1888 if (!ios->clock && variant->pwrreg_clkgate) 1889 pwr &= ~MCI_PWR_ON; 1890 1891 if (host->variant->explicit_mclk_control && 1892 ios->clock != host->clock_cache) { 1893 ret = clk_set_rate(host->clk, ios->clock); 1894 if (ret < 0) 1895 dev_err(mmc_dev(host->mmc), 1896 "Error setting clock rate (%d)\n", ret); 1897 else 1898 host->mclk = clk_get_rate(host->clk); 1899 } 1900 host->clock_cache = ios->clock; 1901 1902 spin_lock_irqsave(&host->lock, flags); 1903 1904 if (host->ops && host->ops->set_clkreg) 1905 host->ops->set_clkreg(host, ios->clock); 1906 else 1907 mmci_set_clkreg(host, ios->clock); 1908 1909 mmci_set_max_busy_timeout(mmc); 1910 1911 if (host->ops && host->ops->set_pwrreg) 1912 host->ops->set_pwrreg(host, pwr); 1913 else 1914 mmci_write_pwrreg(host, pwr); 1915 1916 mmci_reg_delay(host); 1917 1918 spin_unlock_irqrestore(&host->lock, flags); 1919 } 1920 1921 static int mmci_get_cd(struct mmc_host *mmc) 1922 { 1923 struct mmci_host *host = mmc_priv(mmc); 1924 struct mmci_platform_data *plat = host->plat; 1925 unsigned int status = mmc_gpio_get_cd(mmc); 1926 1927 if (status == -ENOSYS) { 1928 if (!plat->status) 1929 return 1; /* Assume always present */ 1930 1931 status = plat->status(mmc_dev(host->mmc)); 1932 } 1933 return status; 1934 } 1935 1936 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1937 { 1938 struct mmci_host *host = mmc_priv(mmc); 1939 int ret; 1940 1941 ret = mmc_regulator_set_vqmmc(mmc, ios); 1942 1943 if (!ret && host->ops && host->ops->post_sig_volt_switch) 1944 ret = host->ops->post_sig_volt_switch(host, ios); 1945 else if (ret) 1946 ret = 0; 1947 1948 if (ret < 0) 1949 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1950 1951 return ret; 1952 } 1953 1954 static struct mmc_host_ops mmci_ops = { 1955 .request = mmci_request, 1956 .pre_req = mmci_pre_request, 1957 .post_req = mmci_post_request, 1958 .set_ios = mmci_set_ios, 1959 .get_ro = mmc_gpio_get_ro, 1960 .get_cd = mmci_get_cd, 1961 .start_signal_voltage_switch = mmci_sig_volt_switch, 1962 }; 1963 1964 static void mmci_probe_level_translator(struct mmc_host *mmc) 1965 { 1966 struct device *dev = mmc_dev(mmc); 1967 struct mmci_host *host = mmc_priv(mmc); 1968 struct gpio_desc *cmd_gpio; 1969 struct gpio_desc *ck_gpio; 1970 struct gpio_desc *ckin_gpio; 1971 int clk_hi, clk_lo; 1972 1973 /* 1974 * Assume the level translator is present if st,use-ckin is set. 1975 * This is to cater for DTs which do not implement this test. 1976 */ 1977 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1978 1979 cmd_gpio = gpiod_get(dev, "st,cmd", GPIOD_OUT_HIGH); 1980 if (IS_ERR(cmd_gpio)) 1981 goto exit_cmd; 1982 1983 ck_gpio = gpiod_get(dev, "st,ck", GPIOD_OUT_HIGH); 1984 if (IS_ERR(ck_gpio)) 1985 goto exit_ck; 1986 1987 ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); 1988 if (IS_ERR(ckin_gpio)) 1989 goto exit_ckin; 1990 1991 /* All GPIOs are valid, test whether level translator works */ 1992 1993 /* Sample CKIN */ 1994 clk_hi = !!gpiod_get_value(ckin_gpio); 1995 1996 /* Set CK low */ 1997 gpiod_set_value(ck_gpio, 0); 1998 1999 /* Sample CKIN */ 2000 clk_lo = !!gpiod_get_value(ckin_gpio); 2001 2002 /* Tristate all */ 2003 gpiod_direction_input(cmd_gpio); 2004 gpiod_direction_input(ck_gpio); 2005 2006 /* Level translator is present if CK signal is propagated to CKIN */ 2007 if (!clk_hi || clk_lo) { 2008 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; 2009 dev_warn(dev, 2010 "Level translator inoperable, CK signal not detected on CKIN, disabling.\n"); 2011 } 2012 2013 gpiod_put(ckin_gpio); 2014 2015 exit_ckin: 2016 gpiod_put(ck_gpio); 2017 exit_ck: 2018 gpiod_put(cmd_gpio); 2019 exit_cmd: 2020 pinctrl_select_default_state(dev); 2021 } 2022 2023 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 2024 { 2025 struct mmci_host *host = mmc_priv(mmc); 2026 int ret = mmc_of_parse(mmc); 2027 2028 if (ret) 2029 return ret; 2030 2031 if (of_property_read_bool(np, "st,sig-dir-dat0")) 2032 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 2033 if (of_property_read_bool(np, "st,sig-dir-dat2")) 2034 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 2035 if (of_property_read_bool(np, "st,sig-dir-dat31")) 2036 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 2037 if (of_property_read_bool(np, "st,sig-dir-dat74")) 2038 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 2039 if (of_property_read_bool(np, "st,sig-dir-cmd")) 2040 host->pwr_reg_add |= MCI_ST_CMDDIREN; 2041 if (of_property_read_bool(np, "st,sig-pin-fbclk")) 2042 host->pwr_reg_add |= MCI_ST_FBCLKEN; 2043 if (of_property_read_bool(np, "st,sig-dir")) 2044 host->pwr_reg_add |= MCI_STM32_DIRPOL; 2045 if (of_property_read_bool(np, "st,neg-edge")) 2046 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 2047 if (of_property_read_bool(np, "st,use-ckin")) 2048 mmci_probe_level_translator(mmc); 2049 2050 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) 2051 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 2052 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) 2053 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2054 2055 return 0; 2056 } 2057 2058 static int mmci_probe(struct amba_device *dev, 2059 const struct amba_id *id) 2060 { 2061 struct mmci_platform_data *plat = dev->dev.platform_data; 2062 struct device_node *np = dev->dev.of_node; 2063 struct variant_data *variant = id->data; 2064 struct mmci_host *host; 2065 struct mmc_host *mmc; 2066 int ret; 2067 2068 /* Must have platform data or Device Tree. */ 2069 if (!plat && !np) { 2070 dev_err(&dev->dev, "No plat data or DT found\n"); 2071 return -EINVAL; 2072 } 2073 2074 if (!plat) { 2075 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 2076 if (!plat) 2077 return -ENOMEM; 2078 } 2079 2080 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 2081 if (!mmc) 2082 return -ENOMEM; 2083 2084 host = mmc_priv(mmc); 2085 host->mmc = mmc; 2086 host->mmc_ops = &mmci_ops; 2087 mmc->ops = &mmci_ops; 2088 2089 ret = mmci_of_parse(np, mmc); 2090 if (ret) 2091 goto host_free; 2092 2093 /* 2094 * Some variant (STM32) doesn't have opendrain bit, nevertheless 2095 * pins can be set accordingly using pinctrl 2096 */ 2097 if (!variant->opendrain) { 2098 host->pinctrl = devm_pinctrl_get(&dev->dev); 2099 if (IS_ERR(host->pinctrl)) { 2100 dev_err(&dev->dev, "failed to get pinctrl"); 2101 ret = PTR_ERR(host->pinctrl); 2102 goto host_free; 2103 } 2104 2105 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 2106 MMCI_PINCTRL_STATE_OPENDRAIN); 2107 if (IS_ERR(host->pins_opendrain)) { 2108 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 2109 ret = PTR_ERR(host->pins_opendrain); 2110 goto host_free; 2111 } 2112 } 2113 2114 host->hw_designer = amba_manf(dev); 2115 host->hw_revision = amba_rev(dev); 2116 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 2117 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 2118 2119 host->clk = devm_clk_get(&dev->dev, NULL); 2120 if (IS_ERR(host->clk)) { 2121 ret = PTR_ERR(host->clk); 2122 goto host_free; 2123 } 2124 2125 ret = clk_prepare_enable(host->clk); 2126 if (ret) 2127 goto host_free; 2128 2129 if (variant->qcom_fifo) 2130 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 2131 else 2132 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 2133 2134 host->plat = plat; 2135 host->variant = variant; 2136 host->mclk = clk_get_rate(host->clk); 2137 /* 2138 * According to the spec, mclk is max 100 MHz, 2139 * so we try to adjust the clock down to this, 2140 * (if possible). 2141 */ 2142 if (host->mclk > variant->f_max) { 2143 ret = clk_set_rate(host->clk, variant->f_max); 2144 if (ret < 0) 2145 goto clk_disable; 2146 host->mclk = clk_get_rate(host->clk); 2147 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 2148 host->mclk); 2149 } 2150 2151 host->phybase = dev->res.start; 2152 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 2153 if (IS_ERR(host->base)) { 2154 ret = PTR_ERR(host->base); 2155 goto clk_disable; 2156 } 2157 2158 if (variant->init) 2159 variant->init(host); 2160 2161 /* 2162 * The ARM and ST versions of the block have slightly different 2163 * clock divider equations which means that the minimum divider 2164 * differs too. 2165 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 2166 */ 2167 if (variant->st_clkdiv) 2168 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 2169 else if (variant->stm32_clkdiv) 2170 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 2171 else if (variant->explicit_mclk_control) 2172 mmc->f_min = clk_round_rate(host->clk, 100000); 2173 else 2174 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 2175 /* 2176 * If no maximum operating frequency is supplied, fall back to use 2177 * the module parameter, which has a (low) default value in case it 2178 * is not specified. Either value must not exceed the clock rate into 2179 * the block, of course. 2180 */ 2181 if (mmc->f_max) 2182 mmc->f_max = variant->explicit_mclk_control ? 2183 min(variant->f_max, mmc->f_max) : 2184 min(host->mclk, mmc->f_max); 2185 else 2186 mmc->f_max = variant->explicit_mclk_control ? 2187 fmax : min(host->mclk, fmax); 2188 2189 2190 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 2191 2192 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 2193 if (IS_ERR(host->rst)) { 2194 ret = PTR_ERR(host->rst); 2195 goto clk_disable; 2196 } 2197 ret = reset_control_deassert(host->rst); 2198 if (ret) 2199 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); 2200 2201 /* Get regulators and the supported OCR mask */ 2202 ret = mmc_regulator_get_supply(mmc); 2203 if (ret) 2204 goto clk_disable; 2205 2206 if (!mmc->ocr_avail) 2207 mmc->ocr_avail = plat->ocr_mask; 2208 else if (plat->ocr_mask) 2209 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 2210 2211 /* We support these capabilities. */ 2212 mmc->caps |= MMC_CAP_CMD23; 2213 2214 /* 2215 * Enable busy detection. 2216 */ 2217 if (variant->busy_detect) { 2218 mmci_ops.card_busy = mmci_card_busy; 2219 /* 2220 * Not all variants have a flag to enable busy detection 2221 * in the DPSM, but if they do, set it here. 2222 */ 2223 if (variant->busy_dpsm_flag) 2224 mmci_write_datactrlreg(host, 2225 host->variant->busy_dpsm_flag); 2226 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2227 } 2228 2229 /* Variants with mandatory busy timeout in HW needs R1B responses. */ 2230 if (variant->busy_timeout) 2231 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 2232 2233 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2234 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2235 host->stop_abort.arg = 0; 2236 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2237 2238 /* We support these PM capabilities. */ 2239 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2240 2241 /* 2242 * We can do SGIO 2243 */ 2244 mmc->max_segs = NR_SG; 2245 2246 /* 2247 * Since only a certain number of bits are valid in the data length 2248 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2249 * single request. 2250 */ 2251 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2252 2253 /* 2254 * Set the maximum segment size. Since we aren't doing DMA 2255 * (yet) we are only limited by the data length register. 2256 */ 2257 mmc->max_seg_size = mmc->max_req_size; 2258 2259 /* 2260 * Block size can be up to 2048 bytes, but must be a power of two. 2261 */ 2262 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2263 2264 /* 2265 * Limit the number of blocks transferred so that we don't overflow 2266 * the maximum request size. 2267 */ 2268 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2269 2270 spin_lock_init(&host->lock); 2271 2272 writel(0, host->base + MMCIMASK0); 2273 2274 if (variant->mmcimask1) 2275 writel(0, host->base + MMCIMASK1); 2276 2277 writel(0xfff, host->base + MMCICLEAR); 2278 2279 /* 2280 * If: 2281 * - not using DT but using a descriptor table, or 2282 * - using a table of descriptors ALONGSIDE DT, or 2283 * look up these descriptors named "cd" and "wp" right here, fail 2284 * silently of these do not exist 2285 */ 2286 if (!np) { 2287 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 2288 if (ret == -EPROBE_DEFER) 2289 goto clk_disable; 2290 2291 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 2292 if (ret == -EPROBE_DEFER) 2293 goto clk_disable; 2294 } 2295 2296 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, 2297 mmci_irq_thread, IRQF_SHARED, 2298 DRIVER_NAME " (cmd)", host); 2299 if (ret) 2300 goto clk_disable; 2301 2302 if (!dev->irq[1]) 2303 host->singleirq = true; 2304 else { 2305 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2306 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2307 if (ret) 2308 goto clk_disable; 2309 } 2310 2311 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2312 2313 amba_set_drvdata(dev, mmc); 2314 2315 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2316 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2317 amba_rev(dev), (unsigned long long)dev->res.start, 2318 dev->irq[0], dev->irq[1]); 2319 2320 mmci_dma_setup(host); 2321 2322 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2323 pm_runtime_use_autosuspend(&dev->dev); 2324 2325 ret = mmc_add_host(mmc); 2326 if (ret) 2327 goto clk_disable; 2328 2329 pm_runtime_put(&dev->dev); 2330 return 0; 2331 2332 clk_disable: 2333 clk_disable_unprepare(host->clk); 2334 host_free: 2335 mmc_free_host(mmc); 2336 return ret; 2337 } 2338 2339 static void mmci_remove(struct amba_device *dev) 2340 { 2341 struct mmc_host *mmc = amba_get_drvdata(dev); 2342 2343 if (mmc) { 2344 struct mmci_host *host = mmc_priv(mmc); 2345 struct variant_data *variant = host->variant; 2346 2347 /* 2348 * Undo pm_runtime_put() in probe. We use the _sync 2349 * version here so that we can access the primecell. 2350 */ 2351 pm_runtime_get_sync(&dev->dev); 2352 2353 mmc_remove_host(mmc); 2354 2355 writel(0, host->base + MMCIMASK0); 2356 2357 if (variant->mmcimask1) 2358 writel(0, host->base + MMCIMASK1); 2359 2360 writel(0, host->base + MMCICOMMAND); 2361 writel(0, host->base + MMCIDATACTRL); 2362 2363 mmci_dma_release(host); 2364 clk_disable_unprepare(host->clk); 2365 mmc_free_host(mmc); 2366 } 2367 } 2368 2369 #ifdef CONFIG_PM 2370 static void mmci_save(struct mmci_host *host) 2371 { 2372 unsigned long flags; 2373 2374 spin_lock_irqsave(&host->lock, flags); 2375 2376 writel(0, host->base + MMCIMASK0); 2377 if (host->variant->pwrreg_nopower) { 2378 writel(0, host->base + MMCIDATACTRL); 2379 writel(0, host->base + MMCIPOWER); 2380 writel(0, host->base + MMCICLOCK); 2381 } 2382 mmci_reg_delay(host); 2383 2384 spin_unlock_irqrestore(&host->lock, flags); 2385 } 2386 2387 static void mmci_restore(struct mmci_host *host) 2388 { 2389 unsigned long flags; 2390 2391 spin_lock_irqsave(&host->lock, flags); 2392 2393 if (host->variant->pwrreg_nopower) { 2394 writel(host->clk_reg, host->base + MMCICLOCK); 2395 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2396 writel(host->pwr_reg, host->base + MMCIPOWER); 2397 } 2398 writel(MCI_IRQENABLE | host->variant->start_err, 2399 host->base + MMCIMASK0); 2400 mmci_reg_delay(host); 2401 2402 spin_unlock_irqrestore(&host->lock, flags); 2403 } 2404 2405 static int mmci_runtime_suspend(struct device *dev) 2406 { 2407 struct amba_device *adev = to_amba_device(dev); 2408 struct mmc_host *mmc = amba_get_drvdata(adev); 2409 2410 if (mmc) { 2411 struct mmci_host *host = mmc_priv(mmc); 2412 pinctrl_pm_select_sleep_state(dev); 2413 mmci_save(host); 2414 clk_disable_unprepare(host->clk); 2415 } 2416 2417 return 0; 2418 } 2419 2420 static int mmci_runtime_resume(struct device *dev) 2421 { 2422 struct amba_device *adev = to_amba_device(dev); 2423 struct mmc_host *mmc = amba_get_drvdata(adev); 2424 2425 if (mmc) { 2426 struct mmci_host *host = mmc_priv(mmc); 2427 clk_prepare_enable(host->clk); 2428 mmci_restore(host); 2429 pinctrl_select_default_state(dev); 2430 } 2431 2432 return 0; 2433 } 2434 #endif 2435 2436 static const struct dev_pm_ops mmci_dev_pm_ops = { 2437 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2438 pm_runtime_force_resume) 2439 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2440 }; 2441 2442 static const struct amba_id mmci_ids[] = { 2443 { 2444 .id = 0x00041180, 2445 .mask = 0xff0fffff, 2446 .data = &variant_arm, 2447 }, 2448 { 2449 .id = 0x01041180, 2450 .mask = 0xff0fffff, 2451 .data = &variant_arm_extended_fifo, 2452 }, 2453 { 2454 .id = 0x02041180, 2455 .mask = 0xff0fffff, 2456 .data = &variant_arm_extended_fifo_hwfc, 2457 }, 2458 { 2459 .id = 0x00041181, 2460 .mask = 0x000fffff, 2461 .data = &variant_arm, 2462 }, 2463 /* ST Micro variants */ 2464 { 2465 .id = 0x00180180, 2466 .mask = 0x00ffffff, 2467 .data = &variant_u300, 2468 }, 2469 { 2470 .id = 0x10180180, 2471 .mask = 0xf0ffffff, 2472 .data = &variant_nomadik, 2473 }, 2474 { 2475 .id = 0x00280180, 2476 .mask = 0x00ffffff, 2477 .data = &variant_nomadik, 2478 }, 2479 { 2480 .id = 0x00480180, 2481 .mask = 0xf0ffffff, 2482 .data = &variant_ux500, 2483 }, 2484 { 2485 .id = 0x10480180, 2486 .mask = 0xf0ffffff, 2487 .data = &variant_ux500v2, 2488 }, 2489 { 2490 .id = 0x00880180, 2491 .mask = 0x00ffffff, 2492 .data = &variant_stm32, 2493 }, 2494 { 2495 .id = 0x10153180, 2496 .mask = 0xf0ffffff, 2497 .data = &variant_stm32_sdmmc, 2498 }, 2499 { 2500 .id = 0x00253180, 2501 .mask = 0xf0ffffff, 2502 .data = &variant_stm32_sdmmcv2, 2503 }, 2504 { 2505 .id = 0x20253180, 2506 .mask = 0xf0ffffff, 2507 .data = &variant_stm32_sdmmcv2, 2508 }, 2509 /* Qualcomm variants */ 2510 { 2511 .id = 0x00051180, 2512 .mask = 0x000fffff, 2513 .data = &variant_qcom, 2514 }, 2515 { 0, 0 }, 2516 }; 2517 2518 MODULE_DEVICE_TABLE(amba, mmci_ids); 2519 2520 static struct amba_driver mmci_driver = { 2521 .drv = { 2522 .name = DRIVER_NAME, 2523 .pm = &mmci_dev_pm_ops, 2524 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2525 }, 2526 .probe = mmci_probe, 2527 .remove = mmci_remove, 2528 .id_table = mmci_ids, 2529 }; 2530 2531 module_amba_driver(mmci_driver); 2532 2533 module_param(fmax, uint, 0444); 2534 2535 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2536 MODULE_LICENSE("GPL"); 2537