1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/of.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/amba/mmci.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/types.h> 38 #include <linux/pinctrl/consumer.h> 39 40 #include <asm/div64.h> 41 #include <asm/io.h> 42 43 #include "mmci.h" 44 #include "mmci_qcom_dml.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 #ifdef CONFIG_DMA_ENGINE 49 void mmci_variant_init(struct mmci_host *host); 50 #else 51 static inline void mmci_variant_init(struct mmci_host *host) {} 52 #endif 53 54 static unsigned int fmax = 515633; 55 56 static struct variant_data variant_arm = { 57 .fifosize = 16 * 4, 58 .fifohalfsize = 8 * 4, 59 .datalength_bits = 16, 60 .pwrreg_powerup = MCI_PWR_UP, 61 .f_max = 100000000, 62 .reversed_irq_handling = true, 63 .mmcimask1 = true, 64 .start_err = MCI_STARTBITERR, 65 .opendrain = MCI_ROD, 66 .init = mmci_variant_init, 67 }; 68 69 static struct variant_data variant_arm_extended_fifo = { 70 .fifosize = 128 * 4, 71 .fifohalfsize = 64 * 4, 72 .datalength_bits = 16, 73 .pwrreg_powerup = MCI_PWR_UP, 74 .f_max = 100000000, 75 .mmcimask1 = true, 76 .start_err = MCI_STARTBITERR, 77 .opendrain = MCI_ROD, 78 .init = mmci_variant_init, 79 }; 80 81 static struct variant_data variant_arm_extended_fifo_hwfc = { 82 .fifosize = 128 * 4, 83 .fifohalfsize = 64 * 4, 84 .clkreg_enable = MCI_ARM_HWFCEN, 85 .datalength_bits = 16, 86 .pwrreg_powerup = MCI_PWR_UP, 87 .f_max = 100000000, 88 .mmcimask1 = true, 89 .start_err = MCI_STARTBITERR, 90 .opendrain = MCI_ROD, 91 .init = mmci_variant_init, 92 }; 93 94 static struct variant_data variant_u300 = { 95 .fifosize = 16 * 4, 96 .fifohalfsize = 8 * 4, 97 .clkreg_enable = MCI_ST_U300_HWFCEN, 98 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 99 .datalength_bits = 16, 100 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 101 .st_sdio = true, 102 .pwrreg_powerup = MCI_PWR_ON, 103 .f_max = 100000000, 104 .signal_direction = true, 105 .pwrreg_clkgate = true, 106 .pwrreg_nopower = true, 107 .mmcimask1 = true, 108 .start_err = MCI_STARTBITERR, 109 .opendrain = MCI_OD, 110 .init = mmci_variant_init, 111 }; 112 113 static struct variant_data variant_nomadik = { 114 .fifosize = 16 * 4, 115 .fifohalfsize = 8 * 4, 116 .clkreg = MCI_CLK_ENABLE, 117 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 118 .datalength_bits = 24, 119 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 120 .st_sdio = true, 121 .st_clkdiv = true, 122 .pwrreg_powerup = MCI_PWR_ON, 123 .f_max = 100000000, 124 .signal_direction = true, 125 .pwrreg_clkgate = true, 126 .pwrreg_nopower = true, 127 .mmcimask1 = true, 128 .start_err = MCI_STARTBITERR, 129 .opendrain = MCI_OD, 130 .init = mmci_variant_init, 131 }; 132 133 static struct variant_data variant_ux500 = { 134 .fifosize = 30 * 4, 135 .fifohalfsize = 8 * 4, 136 .clkreg = MCI_CLK_ENABLE, 137 .clkreg_enable = MCI_ST_UX500_HWFCEN, 138 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 139 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 140 .datalength_bits = 24, 141 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 142 .st_sdio = true, 143 .st_clkdiv = true, 144 .pwrreg_powerup = MCI_PWR_ON, 145 .f_max = 100000000, 146 .signal_direction = true, 147 .pwrreg_clkgate = true, 148 .busy_detect = true, 149 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 150 .busy_detect_flag = MCI_ST_CARDBUSY, 151 .busy_detect_mask = MCI_ST_BUSYENDMASK, 152 .pwrreg_nopower = true, 153 .mmcimask1 = true, 154 .start_err = MCI_STARTBITERR, 155 .opendrain = MCI_OD, 156 .init = mmci_variant_init, 157 }; 158 159 static struct variant_data variant_ux500v2 = { 160 .fifosize = 30 * 4, 161 .fifohalfsize = 8 * 4, 162 .clkreg = MCI_CLK_ENABLE, 163 .clkreg_enable = MCI_ST_UX500_HWFCEN, 164 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 165 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 166 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 167 .datalength_bits = 24, 168 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 169 .st_sdio = true, 170 .st_clkdiv = true, 171 .blksz_datactrl16 = true, 172 .pwrreg_powerup = MCI_PWR_ON, 173 .f_max = 100000000, 174 .signal_direction = true, 175 .pwrreg_clkgate = true, 176 .busy_detect = true, 177 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 178 .busy_detect_flag = MCI_ST_CARDBUSY, 179 .busy_detect_mask = MCI_ST_BUSYENDMASK, 180 .pwrreg_nopower = true, 181 .mmcimask1 = true, 182 .start_err = MCI_STARTBITERR, 183 .opendrain = MCI_OD, 184 .init = mmci_variant_init, 185 }; 186 187 static struct variant_data variant_stm32 = { 188 .fifosize = 32 * 4, 189 .fifohalfsize = 8 * 4, 190 .clkreg = MCI_CLK_ENABLE, 191 .clkreg_enable = MCI_ST_UX500_HWFCEN, 192 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 193 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 194 .datalength_bits = 24, 195 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 196 .st_sdio = true, 197 .st_clkdiv = true, 198 .pwrreg_powerup = MCI_PWR_ON, 199 .f_max = 48000000, 200 .pwrreg_clkgate = true, 201 .pwrreg_nopower = true, 202 .init = mmci_variant_init, 203 }; 204 205 static struct variant_data variant_qcom = { 206 .fifosize = 16 * 4, 207 .fifohalfsize = 8 * 4, 208 .clkreg = MCI_CLK_ENABLE, 209 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 210 MCI_QCOM_CLK_SELECT_IN_FBCLK, 211 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 212 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 213 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 214 .blksz_datactrl4 = true, 215 .datalength_bits = 24, 216 .pwrreg_powerup = MCI_PWR_UP, 217 .f_max = 208000000, 218 .explicit_mclk_control = true, 219 .qcom_fifo = true, 220 .qcom_dml = true, 221 .mmcimask1 = true, 222 .start_err = MCI_STARTBITERR, 223 .opendrain = MCI_ROD, 224 .init = qcom_variant_init, 225 }; 226 227 /* Busy detection for the ST Micro variant */ 228 static int mmci_card_busy(struct mmc_host *mmc) 229 { 230 struct mmci_host *host = mmc_priv(mmc); 231 unsigned long flags; 232 int busy = 0; 233 234 spin_lock_irqsave(&host->lock, flags); 235 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 236 busy = 1; 237 spin_unlock_irqrestore(&host->lock, flags); 238 239 return busy; 240 } 241 242 /* 243 * Validate mmc prerequisites 244 */ 245 static int mmci_validate_data(struct mmci_host *host, 246 struct mmc_data *data) 247 { 248 if (!data) 249 return 0; 250 251 if (!is_power_of_2(data->blksz)) { 252 dev_err(mmc_dev(host->mmc), 253 "unsupported block size (%d bytes)\n", data->blksz); 254 return -EINVAL; 255 } 256 257 return 0; 258 } 259 260 static void mmci_reg_delay(struct mmci_host *host) 261 { 262 /* 263 * According to the spec, at least three feedback clock cycles 264 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 265 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 266 * Worst delay time during card init is at 100 kHz => 30 us. 267 * Worst delay time when up and running is at 25 MHz => 120 ns. 268 */ 269 if (host->cclk < 25000000) 270 udelay(30); 271 else 272 ndelay(120); 273 } 274 275 /* 276 * This must be called with host->lock held 277 */ 278 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 279 { 280 if (host->clk_reg != clk) { 281 host->clk_reg = clk; 282 writel(clk, host->base + MMCICLOCK); 283 } 284 } 285 286 /* 287 * This must be called with host->lock held 288 */ 289 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 290 { 291 if (host->pwr_reg != pwr) { 292 host->pwr_reg = pwr; 293 writel(pwr, host->base + MMCIPOWER); 294 } 295 } 296 297 /* 298 * This must be called with host->lock held 299 */ 300 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 301 { 302 /* Keep busy mode in DPSM if enabled */ 303 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 304 305 if (host->datactrl_reg != datactrl) { 306 host->datactrl_reg = datactrl; 307 writel(datactrl, host->base + MMCIDATACTRL); 308 } 309 } 310 311 /* 312 * This must be called with host->lock held 313 */ 314 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 315 { 316 struct variant_data *variant = host->variant; 317 u32 clk = variant->clkreg; 318 319 /* Make sure cclk reflects the current calculated clock */ 320 host->cclk = 0; 321 322 if (desired) { 323 if (variant->explicit_mclk_control) { 324 host->cclk = host->mclk; 325 } else if (desired >= host->mclk) { 326 clk = MCI_CLK_BYPASS; 327 if (variant->st_clkdiv) 328 clk |= MCI_ST_UX500_NEG_EDGE; 329 host->cclk = host->mclk; 330 } else if (variant->st_clkdiv) { 331 /* 332 * DB8500 TRM says f = mclk / (clkdiv + 2) 333 * => clkdiv = (mclk / f) - 2 334 * Round the divider up so we don't exceed the max 335 * frequency 336 */ 337 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 338 if (clk >= 256) 339 clk = 255; 340 host->cclk = host->mclk / (clk + 2); 341 } else { 342 /* 343 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 344 * => clkdiv = mclk / (2 * f) - 1 345 */ 346 clk = host->mclk / (2 * desired) - 1; 347 if (clk >= 256) 348 clk = 255; 349 host->cclk = host->mclk / (2 * (clk + 1)); 350 } 351 352 clk |= variant->clkreg_enable; 353 clk |= MCI_CLK_ENABLE; 354 /* This hasn't proven to be worthwhile */ 355 /* clk |= MCI_CLK_PWRSAVE; */ 356 } 357 358 /* Set actual clock for debug */ 359 host->mmc->actual_clock = host->cclk; 360 361 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 362 clk |= MCI_4BIT_BUS; 363 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 364 clk |= variant->clkreg_8bit_bus_enable; 365 366 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 367 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 368 clk |= variant->clkreg_neg_edge_enable; 369 370 mmci_write_clkreg(host, clk); 371 } 372 373 void mmci_dma_release(struct mmci_host *host) 374 { 375 if (host->ops && host->ops->dma_release) 376 host->ops->dma_release(host); 377 378 host->use_dma = false; 379 } 380 381 void mmci_dma_setup(struct mmci_host *host) 382 { 383 if (!host->ops || !host->ops->dma_setup) 384 return; 385 386 if (host->ops->dma_setup(host)) 387 return; 388 389 /* initialize pre request cookie */ 390 host->next_cookie = 1; 391 392 host->use_dma = true; 393 } 394 395 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 396 { 397 int err; 398 399 if (!host->ops || !host->ops->prep_data) 400 return 0; 401 402 err = host->ops->prep_data(host, data, next); 403 404 if (next && !err) 405 data->host_cookie = ++host->next_cookie < 0 ? 406 1 : host->next_cookie; 407 408 return err; 409 } 410 411 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 412 int err) 413 { 414 if (host->ops && host->ops->unprep_data) 415 host->ops->unprep_data(host, data, err); 416 417 data->host_cookie = 0; 418 } 419 420 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 421 { 422 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 423 424 if (host->ops && host->ops->get_next_data) 425 host->ops->get_next_data(host, data); 426 } 427 428 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 429 { 430 struct mmc_data *data = host->data; 431 int ret; 432 433 if (!host->use_dma) 434 return -EINVAL; 435 436 ret = mmci_prep_data(host, data, false); 437 if (ret) 438 return ret; 439 440 if (!host->ops || !host->ops->dma_start) 441 return -EINVAL; 442 443 /* Okay, go for it. */ 444 dev_vdbg(mmc_dev(host->mmc), 445 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 446 data->sg_len, data->blksz, data->blocks, data->flags); 447 448 host->ops->dma_start(host, &datactrl); 449 450 /* Trigger the DMA transfer */ 451 mmci_write_datactrlreg(host, datactrl); 452 453 /* 454 * Let the MMCI say when the data is ended and it's time 455 * to fire next DMA request. When that happens, MMCI will 456 * call mmci_data_end() 457 */ 458 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 459 host->base + MMCIMASK0); 460 return 0; 461 } 462 463 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 464 { 465 if (!host->use_dma) 466 return; 467 468 if (host->ops && host->ops->dma_finalize) 469 host->ops->dma_finalize(host, data); 470 } 471 472 void mmci_dma_error(struct mmci_host *host) 473 { 474 if (!host->use_dma) 475 return; 476 477 if (host->ops && host->ops->dma_error) 478 host->ops->dma_error(host); 479 } 480 481 static void 482 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 483 { 484 writel(0, host->base + MMCICOMMAND); 485 486 BUG_ON(host->data); 487 488 host->mrq = NULL; 489 host->cmd = NULL; 490 491 mmc_request_done(host->mmc, mrq); 492 } 493 494 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 495 { 496 void __iomem *base = host->base; 497 struct variant_data *variant = host->variant; 498 499 if (host->singleirq) { 500 unsigned int mask0 = readl(base + MMCIMASK0); 501 502 mask0 &= ~MCI_IRQ1MASK; 503 mask0 |= mask; 504 505 writel(mask0, base + MMCIMASK0); 506 } 507 508 if (variant->mmcimask1) 509 writel(mask, base + MMCIMASK1); 510 511 host->mask1_reg = mask; 512 } 513 514 static void mmci_stop_data(struct mmci_host *host) 515 { 516 mmci_write_datactrlreg(host, 0); 517 mmci_set_mask1(host, 0); 518 host->data = NULL; 519 } 520 521 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 522 { 523 unsigned int flags = SG_MITER_ATOMIC; 524 525 if (data->flags & MMC_DATA_READ) 526 flags |= SG_MITER_TO_SG; 527 else 528 flags |= SG_MITER_FROM_SG; 529 530 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 531 } 532 533 /* 534 * All the DMA operation mode stuff goes inside this ifdef. 535 * This assumes that you have a generic DMA device interface, 536 * no custom DMA interfaces are supported. 537 */ 538 #ifdef CONFIG_DMA_ENGINE 539 struct mmci_dmae_next { 540 struct dma_async_tx_descriptor *desc; 541 struct dma_chan *chan; 542 }; 543 544 struct mmci_dmae_priv { 545 struct dma_chan *cur; 546 struct dma_chan *rx_channel; 547 struct dma_chan *tx_channel; 548 struct dma_async_tx_descriptor *desc_current; 549 struct mmci_dmae_next next_data; 550 }; 551 552 int mmci_dmae_setup(struct mmci_host *host) 553 { 554 const char *rxname, *txname; 555 struct mmci_dmae_priv *dmae; 556 557 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 558 if (!dmae) 559 return -ENOMEM; 560 561 host->dma_priv = dmae; 562 563 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 564 "rx"); 565 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 566 "tx"); 567 568 /* 569 * If only an RX channel is specified, the driver will 570 * attempt to use it bidirectionally, however if it is 571 * is specified but cannot be located, DMA will be disabled. 572 */ 573 if (dmae->rx_channel && !dmae->tx_channel) 574 dmae->tx_channel = dmae->rx_channel; 575 576 if (dmae->rx_channel) 577 rxname = dma_chan_name(dmae->rx_channel); 578 else 579 rxname = "none"; 580 581 if (dmae->tx_channel) 582 txname = dma_chan_name(dmae->tx_channel); 583 else 584 txname = "none"; 585 586 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 587 rxname, txname); 588 589 /* 590 * Limit the maximum segment size in any SG entry according to 591 * the parameters of the DMA engine device. 592 */ 593 if (dmae->tx_channel) { 594 struct device *dev = dmae->tx_channel->device->dev; 595 unsigned int max_seg_size = dma_get_max_seg_size(dev); 596 597 if (max_seg_size < host->mmc->max_seg_size) 598 host->mmc->max_seg_size = max_seg_size; 599 } 600 if (dmae->rx_channel) { 601 struct device *dev = dmae->rx_channel->device->dev; 602 unsigned int max_seg_size = dma_get_max_seg_size(dev); 603 604 if (max_seg_size < host->mmc->max_seg_size) 605 host->mmc->max_seg_size = max_seg_size; 606 } 607 608 if (!dmae->tx_channel || !dmae->rx_channel) { 609 mmci_dmae_release(host); 610 return -EINVAL; 611 } 612 613 return 0; 614 } 615 616 /* 617 * This is used in or so inline it 618 * so it can be discarded. 619 */ 620 void mmci_dmae_release(struct mmci_host *host) 621 { 622 struct mmci_dmae_priv *dmae = host->dma_priv; 623 624 if (dmae->rx_channel) 625 dma_release_channel(dmae->rx_channel); 626 if (dmae->tx_channel) 627 dma_release_channel(dmae->tx_channel); 628 dmae->rx_channel = dmae->tx_channel = NULL; 629 } 630 631 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 632 { 633 struct mmci_dmae_priv *dmae = host->dma_priv; 634 struct dma_chan *chan; 635 636 if (data->flags & MMC_DATA_READ) 637 chan = dmae->rx_channel; 638 else 639 chan = dmae->tx_channel; 640 641 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 642 mmc_get_dma_dir(data)); 643 } 644 645 void mmci_dmae_error(struct mmci_host *host) 646 { 647 struct mmci_dmae_priv *dmae = host->dma_priv; 648 649 if (!dma_inprogress(host)) 650 return; 651 652 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 653 dmaengine_terminate_all(dmae->cur); 654 host->dma_in_progress = false; 655 dmae->cur = NULL; 656 dmae->desc_current = NULL; 657 host->data->host_cookie = 0; 658 659 mmci_dma_unmap(host, host->data); 660 } 661 662 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 663 { 664 struct mmci_dmae_priv *dmae = host->dma_priv; 665 u32 status; 666 int i; 667 668 if (!dma_inprogress(host)) 669 return; 670 671 /* Wait up to 1ms for the DMA to complete */ 672 for (i = 0; ; i++) { 673 status = readl(host->base + MMCISTATUS); 674 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 675 break; 676 udelay(10); 677 } 678 679 /* 680 * Check to see whether we still have some data left in the FIFO - 681 * this catches DMA controllers which are unable to monitor the 682 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 683 * contiguous buffers. On TX, we'll get a FIFO underrun error. 684 */ 685 if (status & MCI_RXDATAAVLBLMASK) { 686 mmci_dma_error(host); 687 if (!data->error) 688 data->error = -EIO; 689 } else if (!data->host_cookie) { 690 mmci_dma_unmap(host, data); 691 } 692 693 /* 694 * Use of DMA with scatter-gather is impossible. 695 * Give up with DMA and switch back to PIO mode. 696 */ 697 if (status & MCI_RXDATAAVLBLMASK) { 698 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 699 mmci_dma_release(host); 700 } 701 702 host->dma_in_progress = false; 703 dmae->cur = NULL; 704 dmae->desc_current = NULL; 705 } 706 707 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 708 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 709 struct dma_chan **dma_chan, 710 struct dma_async_tx_descriptor **dma_desc) 711 { 712 struct mmci_dmae_priv *dmae = host->dma_priv; 713 struct variant_data *variant = host->variant; 714 struct dma_slave_config conf = { 715 .src_addr = host->phybase + MMCIFIFO, 716 .dst_addr = host->phybase + MMCIFIFO, 717 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 718 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 719 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 720 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 721 .device_fc = false, 722 }; 723 struct dma_chan *chan; 724 struct dma_device *device; 725 struct dma_async_tx_descriptor *desc; 726 int nr_sg; 727 unsigned long flags = DMA_CTRL_ACK; 728 729 if (data->flags & MMC_DATA_READ) { 730 conf.direction = DMA_DEV_TO_MEM; 731 chan = dmae->rx_channel; 732 } else { 733 conf.direction = DMA_MEM_TO_DEV; 734 chan = dmae->tx_channel; 735 } 736 737 /* If there's no DMA channel, fall back to PIO */ 738 if (!chan) 739 return -EINVAL; 740 741 /* If less than or equal to the fifo size, don't bother with DMA */ 742 if (data->blksz * data->blocks <= variant->fifosize) 743 return -EINVAL; 744 745 device = chan->device; 746 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 747 mmc_get_dma_dir(data)); 748 if (nr_sg == 0) 749 return -EINVAL; 750 751 if (host->variant->qcom_dml) 752 flags |= DMA_PREP_INTERRUPT; 753 754 dmaengine_slave_config(chan, &conf); 755 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 756 conf.direction, flags); 757 if (!desc) 758 goto unmap_exit; 759 760 *dma_chan = chan; 761 *dma_desc = desc; 762 763 return 0; 764 765 unmap_exit: 766 dma_unmap_sg(device->dev, data->sg, data->sg_len, 767 mmc_get_dma_dir(data)); 768 return -ENOMEM; 769 } 770 771 int mmci_dmae_prep_data(struct mmci_host *host, 772 struct mmc_data *data, 773 bool next) 774 { 775 struct mmci_dmae_priv *dmae = host->dma_priv; 776 struct mmci_dmae_next *nd = &dmae->next_data; 777 778 if (!host->use_dma) 779 return -EINVAL; 780 781 if (next) 782 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 783 /* Check if next job is already prepared. */ 784 if (dmae->cur && dmae->desc_current) 785 return 0; 786 787 /* No job were prepared thus do it now. */ 788 return _mmci_dmae_prep_data(host, data, &dmae->cur, 789 &dmae->desc_current); 790 } 791 792 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 793 { 794 struct mmci_dmae_priv *dmae = host->dma_priv; 795 struct mmc_data *data = host->data; 796 797 host->dma_in_progress = true; 798 dmaengine_submit(dmae->desc_current); 799 dma_async_issue_pending(dmae->cur); 800 801 if (host->variant->qcom_dml) 802 dml_start_xfer(host, data); 803 804 *datactrl |= MCI_DPSM_DMAENABLE; 805 806 return 0; 807 } 808 809 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 810 { 811 struct mmci_dmae_priv *dmae = host->dma_priv; 812 struct mmci_dmae_next *next = &dmae->next_data; 813 814 if (!host->use_dma) 815 return; 816 817 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 818 819 dmae->desc_current = next->desc; 820 dmae->cur = next->chan; 821 next->desc = NULL; 822 next->chan = NULL; 823 } 824 825 void mmci_dmae_unprep_data(struct mmci_host *host, 826 struct mmc_data *data, int err) 827 828 { 829 struct mmci_dmae_priv *dmae = host->dma_priv; 830 831 if (!host->use_dma) 832 return; 833 834 mmci_dma_unmap(host, data); 835 836 if (err) { 837 struct mmci_dmae_next *next = &dmae->next_data; 838 struct dma_chan *chan; 839 if (data->flags & MMC_DATA_READ) 840 chan = dmae->rx_channel; 841 else 842 chan = dmae->tx_channel; 843 dmaengine_terminate_all(chan); 844 845 if (dmae->desc_current == next->desc) 846 dmae->desc_current = NULL; 847 848 if (dmae->cur == next->chan) { 849 host->dma_in_progress = false; 850 dmae->cur = NULL; 851 } 852 853 next->desc = NULL; 854 next->chan = NULL; 855 } 856 } 857 858 static struct mmci_host_ops mmci_variant_ops = { 859 .prep_data = mmci_dmae_prep_data, 860 .unprep_data = mmci_dmae_unprep_data, 861 .get_next_data = mmci_dmae_get_next_data, 862 .dma_setup = mmci_dmae_setup, 863 .dma_release = mmci_dmae_release, 864 .dma_start = mmci_dmae_start, 865 .dma_finalize = mmci_dmae_finalize, 866 .dma_error = mmci_dmae_error, 867 }; 868 869 void mmci_variant_init(struct mmci_host *host) 870 { 871 host->ops = &mmci_variant_ops; 872 } 873 #endif 874 875 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 876 { 877 struct mmci_host *host = mmc_priv(mmc); 878 struct mmc_data *data = mrq->data; 879 880 if (!data) 881 return; 882 883 WARN_ON(data->host_cookie); 884 885 if (mmci_validate_data(host, data)) 886 return; 887 888 mmci_prep_data(host, data, true); 889 } 890 891 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 892 int err) 893 { 894 struct mmci_host *host = mmc_priv(mmc); 895 struct mmc_data *data = mrq->data; 896 897 if (!data || !data->host_cookie) 898 return; 899 900 mmci_unprep_data(host, data, err); 901 } 902 903 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 904 { 905 struct variant_data *variant = host->variant; 906 unsigned int datactrl, timeout, irqmask; 907 unsigned long long clks; 908 void __iomem *base; 909 int blksz_bits; 910 911 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 912 data->blksz, data->blocks, data->flags); 913 914 host->data = data; 915 host->size = data->blksz * data->blocks; 916 data->bytes_xfered = 0; 917 918 clks = (unsigned long long)data->timeout_ns * host->cclk; 919 do_div(clks, NSEC_PER_SEC); 920 921 timeout = data->timeout_clks + (unsigned int)clks; 922 923 base = host->base; 924 writel(timeout, base + MMCIDATATIMER); 925 writel(host->size, base + MMCIDATALENGTH); 926 927 blksz_bits = ffs(data->blksz) - 1; 928 BUG_ON(1 << blksz_bits != data->blksz); 929 930 if (variant->blksz_datactrl16) 931 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 932 else if (variant->blksz_datactrl4) 933 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 934 else 935 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 936 937 if (data->flags & MMC_DATA_READ) 938 datactrl |= MCI_DPSM_DIRECTION; 939 940 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 941 u32 clk; 942 943 datactrl |= variant->datactrl_mask_sdio; 944 945 /* 946 * The ST Micro variant for SDIO small write transfers 947 * needs to have clock H/W flow control disabled, 948 * otherwise the transfer will not start. The threshold 949 * depends on the rate of MCLK. 950 */ 951 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 952 (host->size < 8 || 953 (host->size <= 8 && host->mclk > 50000000))) 954 clk = host->clk_reg & ~variant->clkreg_enable; 955 else 956 clk = host->clk_reg | variant->clkreg_enable; 957 958 mmci_write_clkreg(host, clk); 959 } 960 961 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 962 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 963 datactrl |= variant->datactrl_mask_ddrmode; 964 965 /* 966 * Attempt to use DMA operation mode, if this 967 * should fail, fall back to PIO mode 968 */ 969 if (!mmci_dma_start(host, datactrl)) 970 return; 971 972 /* IRQ mode, map the SG list for CPU reading/writing */ 973 mmci_init_sg(host, data); 974 975 if (data->flags & MMC_DATA_READ) { 976 irqmask = MCI_RXFIFOHALFFULLMASK; 977 978 /* 979 * If we have less than the fifo 'half-full' threshold to 980 * transfer, trigger a PIO interrupt as soon as any data 981 * is available. 982 */ 983 if (host->size < variant->fifohalfsize) 984 irqmask |= MCI_RXDATAAVLBLMASK; 985 } else { 986 /* 987 * We don't actually need to include "FIFO empty" here 988 * since its implicit in "FIFO half empty". 989 */ 990 irqmask = MCI_TXFIFOHALFEMPTYMASK; 991 } 992 993 mmci_write_datactrlreg(host, datactrl); 994 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 995 mmci_set_mask1(host, irqmask); 996 } 997 998 static void 999 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1000 { 1001 void __iomem *base = host->base; 1002 1003 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1004 cmd->opcode, cmd->arg, cmd->flags); 1005 1006 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 1007 writel(0, base + MMCICOMMAND); 1008 mmci_reg_delay(host); 1009 } 1010 1011 c |= cmd->opcode | MCI_CPSM_ENABLE; 1012 if (cmd->flags & MMC_RSP_PRESENT) { 1013 if (cmd->flags & MMC_RSP_136) 1014 c |= MCI_CPSM_LONGRSP; 1015 c |= MCI_CPSM_RESPONSE; 1016 } 1017 if (/*interrupt*/0) 1018 c |= MCI_CPSM_INTERRUPT; 1019 1020 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1021 c |= host->variant->data_cmd_enable; 1022 1023 host->cmd = cmd; 1024 1025 writel(cmd->arg, base + MMCIARGUMENT); 1026 writel(c, base + MMCICOMMAND); 1027 } 1028 1029 static void 1030 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1031 unsigned int status) 1032 { 1033 /* Make sure we have data to handle */ 1034 if (!data) 1035 return; 1036 1037 /* First check for errors */ 1038 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1039 host->variant->start_err | 1040 MCI_TXUNDERRUN | MCI_RXOVERRUN)) { 1041 u32 remain, success; 1042 1043 /* Terminate the DMA transfer */ 1044 mmci_dma_error(host); 1045 1046 /* 1047 * Calculate how far we are into the transfer. Note that 1048 * the data counter gives the number of bytes transferred 1049 * on the MMC bus, not on the host side. On reads, this 1050 * can be as much as a FIFO-worth of data ahead. This 1051 * matters for FIFO overruns only. 1052 */ 1053 remain = readl(host->base + MMCIDATACNT); 1054 success = data->blksz * data->blocks - remain; 1055 1056 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1057 status, success); 1058 if (status & MCI_DATACRCFAIL) { 1059 /* Last block was not successful */ 1060 success -= 1; 1061 data->error = -EILSEQ; 1062 } else if (status & MCI_DATATIMEOUT) { 1063 data->error = -ETIMEDOUT; 1064 } else if (status & MCI_STARTBITERR) { 1065 data->error = -ECOMM; 1066 } else if (status & MCI_TXUNDERRUN) { 1067 data->error = -EIO; 1068 } else if (status & MCI_RXOVERRUN) { 1069 if (success > host->variant->fifosize) 1070 success -= host->variant->fifosize; 1071 else 1072 success = 0; 1073 data->error = -EIO; 1074 } 1075 data->bytes_xfered = round_down(success, data->blksz); 1076 } 1077 1078 if (status & MCI_DATABLOCKEND) 1079 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1080 1081 if (status & MCI_DATAEND || data->error) { 1082 mmci_dma_finalize(host, data); 1083 1084 mmci_stop_data(host); 1085 1086 if (!data->error) 1087 /* The error clause is handled above, success! */ 1088 data->bytes_xfered = data->blksz * data->blocks; 1089 1090 if (!data->stop || host->mrq->sbc) { 1091 mmci_request_end(host, data->mrq); 1092 } else { 1093 mmci_start_command(host, data->stop, 0); 1094 } 1095 } 1096 } 1097 1098 static void 1099 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1100 unsigned int status) 1101 { 1102 void __iomem *base = host->base; 1103 bool sbc; 1104 1105 if (!cmd) 1106 return; 1107 1108 sbc = (cmd == host->mrq->sbc); 1109 1110 /* 1111 * We need to be one of these interrupts to be considered worth 1112 * handling. Note that we tag on any latent IRQs postponed 1113 * due to waiting for busy status. 1114 */ 1115 if (!((status|host->busy_status) & 1116 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1117 return; 1118 1119 /* 1120 * ST Micro variant: handle busy detection. 1121 */ 1122 if (host->variant->busy_detect) { 1123 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1124 1125 /* We are busy with a command, return */ 1126 if (host->busy_status && 1127 (status & host->variant->busy_detect_flag)) 1128 return; 1129 1130 /* 1131 * We were not busy, but we now got a busy response on 1132 * something that was not an error, and we double-check 1133 * that the special busy status bit is still set before 1134 * proceeding. 1135 */ 1136 if (!host->busy_status && busy_resp && 1137 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1138 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1139 1140 /* Clear the busy start IRQ */ 1141 writel(host->variant->busy_detect_mask, 1142 host->base + MMCICLEAR); 1143 1144 /* Unmask the busy end IRQ */ 1145 writel(readl(base + MMCIMASK0) | 1146 host->variant->busy_detect_mask, 1147 base + MMCIMASK0); 1148 /* 1149 * Now cache the last response status code (until 1150 * the busy bit goes low), and return. 1151 */ 1152 host->busy_status = 1153 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1154 return; 1155 } 1156 1157 /* 1158 * At this point we are not busy with a command, we have 1159 * not received a new busy request, clear and mask the busy 1160 * end IRQ and fall through to process the IRQ. 1161 */ 1162 if (host->busy_status) { 1163 1164 writel(host->variant->busy_detect_mask, 1165 host->base + MMCICLEAR); 1166 1167 writel(readl(base + MMCIMASK0) & 1168 ~host->variant->busy_detect_mask, 1169 base + MMCIMASK0); 1170 host->busy_status = 0; 1171 } 1172 } 1173 1174 host->cmd = NULL; 1175 1176 if (status & MCI_CMDTIMEOUT) { 1177 cmd->error = -ETIMEDOUT; 1178 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1179 cmd->error = -EILSEQ; 1180 } else { 1181 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1182 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1183 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1184 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1185 } 1186 1187 if ((!sbc && !cmd->data) || cmd->error) { 1188 if (host->data) { 1189 /* Terminate the DMA transfer */ 1190 mmci_dma_error(host); 1191 1192 mmci_stop_data(host); 1193 } 1194 mmci_request_end(host, host->mrq); 1195 } else if (sbc) { 1196 mmci_start_command(host, host->mrq->cmd, 0); 1197 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 1198 mmci_start_data(host, cmd->data); 1199 } 1200 } 1201 1202 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1203 { 1204 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1205 } 1206 1207 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1208 { 1209 /* 1210 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1211 * from the fifo range should be used 1212 */ 1213 if (status & MCI_RXFIFOHALFFULL) 1214 return host->variant->fifohalfsize; 1215 else if (status & MCI_RXDATAAVLBL) 1216 return 4; 1217 1218 return 0; 1219 } 1220 1221 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1222 { 1223 void __iomem *base = host->base; 1224 char *ptr = buffer; 1225 u32 status = readl(host->base + MMCISTATUS); 1226 int host_remain = host->size; 1227 1228 do { 1229 int count = host->get_rx_fifocnt(host, status, host_remain); 1230 1231 if (count > remain) 1232 count = remain; 1233 1234 if (count <= 0) 1235 break; 1236 1237 /* 1238 * SDIO especially may want to send something that is 1239 * not divisible by 4 (as opposed to card sectors 1240 * etc). Therefore make sure to always read the last bytes 1241 * while only doing full 32-bit reads towards the FIFO. 1242 */ 1243 if (unlikely(count & 0x3)) { 1244 if (count < 4) { 1245 unsigned char buf[4]; 1246 ioread32_rep(base + MMCIFIFO, buf, 1); 1247 memcpy(ptr, buf, count); 1248 } else { 1249 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1250 count &= ~0x3; 1251 } 1252 } else { 1253 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1254 } 1255 1256 ptr += count; 1257 remain -= count; 1258 host_remain -= count; 1259 1260 if (remain == 0) 1261 break; 1262 1263 status = readl(base + MMCISTATUS); 1264 } while (status & MCI_RXDATAAVLBL); 1265 1266 return ptr - buffer; 1267 } 1268 1269 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1270 { 1271 struct variant_data *variant = host->variant; 1272 void __iomem *base = host->base; 1273 char *ptr = buffer; 1274 1275 do { 1276 unsigned int count, maxcnt; 1277 1278 maxcnt = status & MCI_TXFIFOEMPTY ? 1279 variant->fifosize : variant->fifohalfsize; 1280 count = min(remain, maxcnt); 1281 1282 /* 1283 * SDIO especially may want to send something that is 1284 * not divisible by 4 (as opposed to card sectors 1285 * etc), and the FIFO only accept full 32-bit writes. 1286 * So compensate by adding +3 on the count, a single 1287 * byte become a 32bit write, 7 bytes will be two 1288 * 32bit writes etc. 1289 */ 1290 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1291 1292 ptr += count; 1293 remain -= count; 1294 1295 if (remain == 0) 1296 break; 1297 1298 status = readl(base + MMCISTATUS); 1299 } while (status & MCI_TXFIFOHALFEMPTY); 1300 1301 return ptr - buffer; 1302 } 1303 1304 /* 1305 * PIO data transfer IRQ handler. 1306 */ 1307 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1308 { 1309 struct mmci_host *host = dev_id; 1310 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1311 struct variant_data *variant = host->variant; 1312 void __iomem *base = host->base; 1313 u32 status; 1314 1315 status = readl(base + MMCISTATUS); 1316 1317 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1318 1319 do { 1320 unsigned int remain, len; 1321 char *buffer; 1322 1323 /* 1324 * For write, we only need to test the half-empty flag 1325 * here - if the FIFO is completely empty, then by 1326 * definition it is more than half empty. 1327 * 1328 * For read, check for data available. 1329 */ 1330 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1331 break; 1332 1333 if (!sg_miter_next(sg_miter)) 1334 break; 1335 1336 buffer = sg_miter->addr; 1337 remain = sg_miter->length; 1338 1339 len = 0; 1340 if (status & MCI_RXACTIVE) 1341 len = mmci_pio_read(host, buffer, remain); 1342 if (status & MCI_TXACTIVE) 1343 len = mmci_pio_write(host, buffer, remain, status); 1344 1345 sg_miter->consumed = len; 1346 1347 host->size -= len; 1348 remain -= len; 1349 1350 if (remain) 1351 break; 1352 1353 status = readl(base + MMCISTATUS); 1354 } while (1); 1355 1356 sg_miter_stop(sg_miter); 1357 1358 /* 1359 * If we have less than the fifo 'half-full' threshold to transfer, 1360 * trigger a PIO interrupt as soon as any data is available. 1361 */ 1362 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1363 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1364 1365 /* 1366 * If we run out of data, disable the data IRQs; this 1367 * prevents a race where the FIFO becomes empty before 1368 * the chip itself has disabled the data path, and 1369 * stops us racing with our data end IRQ. 1370 */ 1371 if (host->size == 0) { 1372 mmci_set_mask1(host, 0); 1373 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1374 } 1375 1376 return IRQ_HANDLED; 1377 } 1378 1379 /* 1380 * Handle completion of command and data transfers. 1381 */ 1382 static irqreturn_t mmci_irq(int irq, void *dev_id) 1383 { 1384 struct mmci_host *host = dev_id; 1385 u32 status; 1386 int ret = 0; 1387 1388 spin_lock(&host->lock); 1389 1390 do { 1391 status = readl(host->base + MMCISTATUS); 1392 1393 if (host->singleirq) { 1394 if (status & host->mask1_reg) 1395 mmci_pio_irq(irq, dev_id); 1396 1397 status &= ~MCI_IRQ1MASK; 1398 } 1399 1400 /* 1401 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1402 * enabled) in mmci_cmd_irq() function where ST Micro busy 1403 * detection variant is handled. Considering the HW seems to be 1404 * triggering the IRQ on both edges while monitoring DAT0 for 1405 * busy completion and that same status bit is used to monitor 1406 * start and end of busy detection, special care must be taken 1407 * to make sure that both start and end interrupts are always 1408 * cleared one after the other. 1409 */ 1410 status &= readl(host->base + MMCIMASK0); 1411 if (host->variant->busy_detect) 1412 writel(status & ~host->variant->busy_detect_mask, 1413 host->base + MMCICLEAR); 1414 else 1415 writel(status, host->base + MMCICLEAR); 1416 1417 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1418 1419 if (host->variant->reversed_irq_handling) { 1420 mmci_data_irq(host, host->data, status); 1421 mmci_cmd_irq(host, host->cmd, status); 1422 } else { 1423 mmci_cmd_irq(host, host->cmd, status); 1424 mmci_data_irq(host, host->data, status); 1425 } 1426 1427 /* 1428 * Don't poll for busy completion in irq context. 1429 */ 1430 if (host->variant->busy_detect && host->busy_status) 1431 status &= ~host->variant->busy_detect_flag; 1432 1433 ret = 1; 1434 } while (status); 1435 1436 spin_unlock(&host->lock); 1437 1438 return IRQ_RETVAL(ret); 1439 } 1440 1441 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1442 { 1443 struct mmci_host *host = mmc_priv(mmc); 1444 unsigned long flags; 1445 1446 WARN_ON(host->mrq != NULL); 1447 1448 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1449 if (mrq->cmd->error) { 1450 mmc_request_done(mmc, mrq); 1451 return; 1452 } 1453 1454 spin_lock_irqsave(&host->lock, flags); 1455 1456 host->mrq = mrq; 1457 1458 if (mrq->data) 1459 mmci_get_next_data(host, mrq->data); 1460 1461 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1462 mmci_start_data(host, mrq->data); 1463 1464 if (mrq->sbc) 1465 mmci_start_command(host, mrq->sbc, 0); 1466 else 1467 mmci_start_command(host, mrq->cmd, 0); 1468 1469 spin_unlock_irqrestore(&host->lock, flags); 1470 } 1471 1472 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1473 { 1474 struct mmci_host *host = mmc_priv(mmc); 1475 struct variant_data *variant = host->variant; 1476 u32 pwr = 0; 1477 unsigned long flags; 1478 int ret; 1479 1480 if (host->plat->ios_handler && 1481 host->plat->ios_handler(mmc_dev(mmc), ios)) 1482 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1483 1484 switch (ios->power_mode) { 1485 case MMC_POWER_OFF: 1486 if (!IS_ERR(mmc->supply.vmmc)) 1487 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1488 1489 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1490 regulator_disable(mmc->supply.vqmmc); 1491 host->vqmmc_enabled = false; 1492 } 1493 1494 break; 1495 case MMC_POWER_UP: 1496 if (!IS_ERR(mmc->supply.vmmc)) 1497 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1498 1499 /* 1500 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1501 * and instead uses MCI_PWR_ON so apply whatever value is 1502 * configured in the variant data. 1503 */ 1504 pwr |= variant->pwrreg_powerup; 1505 1506 break; 1507 case MMC_POWER_ON: 1508 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1509 ret = regulator_enable(mmc->supply.vqmmc); 1510 if (ret < 0) 1511 dev_err(mmc_dev(mmc), 1512 "failed to enable vqmmc regulator\n"); 1513 else 1514 host->vqmmc_enabled = true; 1515 } 1516 1517 pwr |= MCI_PWR_ON; 1518 break; 1519 } 1520 1521 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1522 /* 1523 * The ST Micro variant has some additional bits 1524 * indicating signal direction for the signals in 1525 * the SD/MMC bus and feedback-clock usage. 1526 */ 1527 pwr |= host->pwr_reg_add; 1528 1529 if (ios->bus_width == MMC_BUS_WIDTH_4) 1530 pwr &= ~MCI_ST_DATA74DIREN; 1531 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1532 pwr &= (~MCI_ST_DATA74DIREN & 1533 ~MCI_ST_DATA31DIREN & 1534 ~MCI_ST_DATA2DIREN); 1535 } 1536 1537 if (variant->opendrain) { 1538 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1539 pwr |= variant->opendrain; 1540 } else { 1541 /* 1542 * If the variant cannot configure the pads by its own, then we 1543 * expect the pinctrl to be able to do that for us 1544 */ 1545 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1546 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1547 else 1548 pinctrl_select_state(host->pinctrl, host->pins_default); 1549 } 1550 1551 /* 1552 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1553 * gating the clock, the MCI_PWR_ON bit is cleared. 1554 */ 1555 if (!ios->clock && variant->pwrreg_clkgate) 1556 pwr &= ~MCI_PWR_ON; 1557 1558 if (host->variant->explicit_mclk_control && 1559 ios->clock != host->clock_cache) { 1560 ret = clk_set_rate(host->clk, ios->clock); 1561 if (ret < 0) 1562 dev_err(mmc_dev(host->mmc), 1563 "Error setting clock rate (%d)\n", ret); 1564 else 1565 host->mclk = clk_get_rate(host->clk); 1566 } 1567 host->clock_cache = ios->clock; 1568 1569 spin_lock_irqsave(&host->lock, flags); 1570 1571 mmci_set_clkreg(host, ios->clock); 1572 mmci_write_pwrreg(host, pwr); 1573 mmci_reg_delay(host); 1574 1575 spin_unlock_irqrestore(&host->lock, flags); 1576 } 1577 1578 static int mmci_get_cd(struct mmc_host *mmc) 1579 { 1580 struct mmci_host *host = mmc_priv(mmc); 1581 struct mmci_platform_data *plat = host->plat; 1582 unsigned int status = mmc_gpio_get_cd(mmc); 1583 1584 if (status == -ENOSYS) { 1585 if (!plat->status) 1586 return 1; /* Assume always present */ 1587 1588 status = plat->status(mmc_dev(host->mmc)); 1589 } 1590 return status; 1591 } 1592 1593 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1594 { 1595 int ret = 0; 1596 1597 if (!IS_ERR(mmc->supply.vqmmc)) { 1598 1599 switch (ios->signal_voltage) { 1600 case MMC_SIGNAL_VOLTAGE_330: 1601 ret = regulator_set_voltage(mmc->supply.vqmmc, 1602 2700000, 3600000); 1603 break; 1604 case MMC_SIGNAL_VOLTAGE_180: 1605 ret = regulator_set_voltage(mmc->supply.vqmmc, 1606 1700000, 1950000); 1607 break; 1608 case MMC_SIGNAL_VOLTAGE_120: 1609 ret = regulator_set_voltage(mmc->supply.vqmmc, 1610 1100000, 1300000); 1611 break; 1612 } 1613 1614 if (ret) 1615 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1616 } 1617 1618 return ret; 1619 } 1620 1621 static struct mmc_host_ops mmci_ops = { 1622 .request = mmci_request, 1623 .pre_req = mmci_pre_request, 1624 .post_req = mmci_post_request, 1625 .set_ios = mmci_set_ios, 1626 .get_ro = mmc_gpio_get_ro, 1627 .get_cd = mmci_get_cd, 1628 .start_signal_voltage_switch = mmci_sig_volt_switch, 1629 }; 1630 1631 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1632 { 1633 struct mmci_host *host = mmc_priv(mmc); 1634 int ret = mmc_of_parse(mmc); 1635 1636 if (ret) 1637 return ret; 1638 1639 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1640 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1641 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1642 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1643 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1644 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1645 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1646 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1647 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1648 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1649 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1650 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1651 1652 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1653 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1654 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1655 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1656 1657 return 0; 1658 } 1659 1660 static int mmci_probe(struct amba_device *dev, 1661 const struct amba_id *id) 1662 { 1663 struct mmci_platform_data *plat = dev->dev.platform_data; 1664 struct device_node *np = dev->dev.of_node; 1665 struct variant_data *variant = id->data; 1666 struct mmci_host *host; 1667 struct mmc_host *mmc; 1668 int ret; 1669 1670 /* Must have platform data or Device Tree. */ 1671 if (!plat && !np) { 1672 dev_err(&dev->dev, "No plat data or DT found\n"); 1673 return -EINVAL; 1674 } 1675 1676 if (!plat) { 1677 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1678 if (!plat) 1679 return -ENOMEM; 1680 } 1681 1682 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1683 if (!mmc) 1684 return -ENOMEM; 1685 1686 ret = mmci_of_parse(np, mmc); 1687 if (ret) 1688 goto host_free; 1689 1690 host = mmc_priv(mmc); 1691 host->mmc = mmc; 1692 1693 /* 1694 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1695 * pins can be set accordingly using pinctrl 1696 */ 1697 if (!variant->opendrain) { 1698 host->pinctrl = devm_pinctrl_get(&dev->dev); 1699 if (IS_ERR(host->pinctrl)) { 1700 dev_err(&dev->dev, "failed to get pinctrl"); 1701 ret = PTR_ERR(host->pinctrl); 1702 goto host_free; 1703 } 1704 1705 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1706 PINCTRL_STATE_DEFAULT); 1707 if (IS_ERR(host->pins_default)) { 1708 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1709 ret = PTR_ERR(host->pins_default); 1710 goto host_free; 1711 } 1712 1713 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1714 MMCI_PINCTRL_STATE_OPENDRAIN); 1715 if (IS_ERR(host->pins_opendrain)) { 1716 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1717 ret = PTR_ERR(host->pins_opendrain); 1718 goto host_free; 1719 } 1720 } 1721 1722 host->hw_designer = amba_manf(dev); 1723 host->hw_revision = amba_rev(dev); 1724 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1725 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1726 1727 host->clk = devm_clk_get(&dev->dev, NULL); 1728 if (IS_ERR(host->clk)) { 1729 ret = PTR_ERR(host->clk); 1730 goto host_free; 1731 } 1732 1733 ret = clk_prepare_enable(host->clk); 1734 if (ret) 1735 goto host_free; 1736 1737 if (variant->qcom_fifo) 1738 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1739 else 1740 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1741 1742 host->plat = plat; 1743 host->variant = variant; 1744 host->mclk = clk_get_rate(host->clk); 1745 /* 1746 * According to the spec, mclk is max 100 MHz, 1747 * so we try to adjust the clock down to this, 1748 * (if possible). 1749 */ 1750 if (host->mclk > variant->f_max) { 1751 ret = clk_set_rate(host->clk, variant->f_max); 1752 if (ret < 0) 1753 goto clk_disable; 1754 host->mclk = clk_get_rate(host->clk); 1755 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1756 host->mclk); 1757 } 1758 1759 host->phybase = dev->res.start; 1760 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1761 if (IS_ERR(host->base)) { 1762 ret = PTR_ERR(host->base); 1763 goto clk_disable; 1764 } 1765 1766 if (variant->init) 1767 variant->init(host); 1768 1769 /* 1770 * The ARM and ST versions of the block have slightly different 1771 * clock divider equations which means that the minimum divider 1772 * differs too. 1773 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1774 */ 1775 if (variant->st_clkdiv) 1776 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1777 else if (variant->explicit_mclk_control) 1778 mmc->f_min = clk_round_rate(host->clk, 100000); 1779 else 1780 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1781 /* 1782 * If no maximum operating frequency is supplied, fall back to use 1783 * the module parameter, which has a (low) default value in case it 1784 * is not specified. Either value must not exceed the clock rate into 1785 * the block, of course. 1786 */ 1787 if (mmc->f_max) 1788 mmc->f_max = variant->explicit_mclk_control ? 1789 min(variant->f_max, mmc->f_max) : 1790 min(host->mclk, mmc->f_max); 1791 else 1792 mmc->f_max = variant->explicit_mclk_control ? 1793 fmax : min(host->mclk, fmax); 1794 1795 1796 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1797 1798 /* Get regulators and the supported OCR mask */ 1799 ret = mmc_regulator_get_supply(mmc); 1800 if (ret) 1801 goto clk_disable; 1802 1803 if (!mmc->ocr_avail) 1804 mmc->ocr_avail = plat->ocr_mask; 1805 else if (plat->ocr_mask) 1806 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1807 1808 /* We support these capabilities. */ 1809 mmc->caps |= MMC_CAP_CMD23; 1810 1811 /* 1812 * Enable busy detection. 1813 */ 1814 if (variant->busy_detect) { 1815 mmci_ops.card_busy = mmci_card_busy; 1816 /* 1817 * Not all variants have a flag to enable busy detection 1818 * in the DPSM, but if they do, set it here. 1819 */ 1820 if (variant->busy_dpsm_flag) 1821 mmci_write_datactrlreg(host, 1822 host->variant->busy_dpsm_flag); 1823 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1824 mmc->max_busy_timeout = 0; 1825 } 1826 1827 mmc->ops = &mmci_ops; 1828 1829 /* We support these PM capabilities. */ 1830 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1831 1832 /* 1833 * We can do SGIO 1834 */ 1835 mmc->max_segs = NR_SG; 1836 1837 /* 1838 * Since only a certain number of bits are valid in the data length 1839 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1840 * single request. 1841 */ 1842 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1843 1844 /* 1845 * Set the maximum segment size. Since we aren't doing DMA 1846 * (yet) we are only limited by the data length register. 1847 */ 1848 mmc->max_seg_size = mmc->max_req_size; 1849 1850 /* 1851 * Block size can be up to 2048 bytes, but must be a power of two. 1852 */ 1853 mmc->max_blk_size = 1 << 11; 1854 1855 /* 1856 * Limit the number of blocks transferred so that we don't overflow 1857 * the maximum request size. 1858 */ 1859 mmc->max_blk_count = mmc->max_req_size >> 11; 1860 1861 spin_lock_init(&host->lock); 1862 1863 writel(0, host->base + MMCIMASK0); 1864 1865 if (variant->mmcimask1) 1866 writel(0, host->base + MMCIMASK1); 1867 1868 writel(0xfff, host->base + MMCICLEAR); 1869 1870 /* 1871 * If: 1872 * - not using DT but using a descriptor table, or 1873 * - using a table of descriptors ALONGSIDE DT, or 1874 * look up these descriptors named "cd" and "wp" right here, fail 1875 * silently of these do not exist 1876 */ 1877 if (!np) { 1878 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1879 if (ret == -EPROBE_DEFER) 1880 goto clk_disable; 1881 1882 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1883 if (ret == -EPROBE_DEFER) 1884 goto clk_disable; 1885 } 1886 1887 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1888 DRIVER_NAME " (cmd)", host); 1889 if (ret) 1890 goto clk_disable; 1891 1892 if (!dev->irq[1]) 1893 host->singleirq = true; 1894 else { 1895 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1896 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1897 if (ret) 1898 goto clk_disable; 1899 } 1900 1901 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1902 1903 amba_set_drvdata(dev, mmc); 1904 1905 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1906 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1907 amba_rev(dev), (unsigned long long)dev->res.start, 1908 dev->irq[0], dev->irq[1]); 1909 1910 mmci_dma_setup(host); 1911 1912 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1913 pm_runtime_use_autosuspend(&dev->dev); 1914 1915 mmc_add_host(mmc); 1916 1917 pm_runtime_put(&dev->dev); 1918 return 0; 1919 1920 clk_disable: 1921 clk_disable_unprepare(host->clk); 1922 host_free: 1923 mmc_free_host(mmc); 1924 return ret; 1925 } 1926 1927 static int mmci_remove(struct amba_device *dev) 1928 { 1929 struct mmc_host *mmc = amba_get_drvdata(dev); 1930 1931 if (mmc) { 1932 struct mmci_host *host = mmc_priv(mmc); 1933 struct variant_data *variant = host->variant; 1934 1935 /* 1936 * Undo pm_runtime_put() in probe. We use the _sync 1937 * version here so that we can access the primecell. 1938 */ 1939 pm_runtime_get_sync(&dev->dev); 1940 1941 mmc_remove_host(mmc); 1942 1943 writel(0, host->base + MMCIMASK0); 1944 1945 if (variant->mmcimask1) 1946 writel(0, host->base + MMCIMASK1); 1947 1948 writel(0, host->base + MMCICOMMAND); 1949 writel(0, host->base + MMCIDATACTRL); 1950 1951 mmci_dma_release(host); 1952 clk_disable_unprepare(host->clk); 1953 mmc_free_host(mmc); 1954 } 1955 1956 return 0; 1957 } 1958 1959 #ifdef CONFIG_PM 1960 static void mmci_save(struct mmci_host *host) 1961 { 1962 unsigned long flags; 1963 1964 spin_lock_irqsave(&host->lock, flags); 1965 1966 writel(0, host->base + MMCIMASK0); 1967 if (host->variant->pwrreg_nopower) { 1968 writel(0, host->base + MMCIDATACTRL); 1969 writel(0, host->base + MMCIPOWER); 1970 writel(0, host->base + MMCICLOCK); 1971 } 1972 mmci_reg_delay(host); 1973 1974 spin_unlock_irqrestore(&host->lock, flags); 1975 } 1976 1977 static void mmci_restore(struct mmci_host *host) 1978 { 1979 unsigned long flags; 1980 1981 spin_lock_irqsave(&host->lock, flags); 1982 1983 if (host->variant->pwrreg_nopower) { 1984 writel(host->clk_reg, host->base + MMCICLOCK); 1985 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1986 writel(host->pwr_reg, host->base + MMCIPOWER); 1987 } 1988 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1989 mmci_reg_delay(host); 1990 1991 spin_unlock_irqrestore(&host->lock, flags); 1992 } 1993 1994 static int mmci_runtime_suspend(struct device *dev) 1995 { 1996 struct amba_device *adev = to_amba_device(dev); 1997 struct mmc_host *mmc = amba_get_drvdata(adev); 1998 1999 if (mmc) { 2000 struct mmci_host *host = mmc_priv(mmc); 2001 pinctrl_pm_select_sleep_state(dev); 2002 mmci_save(host); 2003 clk_disable_unprepare(host->clk); 2004 } 2005 2006 return 0; 2007 } 2008 2009 static int mmci_runtime_resume(struct device *dev) 2010 { 2011 struct amba_device *adev = to_amba_device(dev); 2012 struct mmc_host *mmc = amba_get_drvdata(adev); 2013 2014 if (mmc) { 2015 struct mmci_host *host = mmc_priv(mmc); 2016 clk_prepare_enable(host->clk); 2017 mmci_restore(host); 2018 pinctrl_pm_select_default_state(dev); 2019 } 2020 2021 return 0; 2022 } 2023 #endif 2024 2025 static const struct dev_pm_ops mmci_dev_pm_ops = { 2026 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2027 pm_runtime_force_resume) 2028 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2029 }; 2030 2031 static const struct amba_id mmci_ids[] = { 2032 { 2033 .id = 0x00041180, 2034 .mask = 0xff0fffff, 2035 .data = &variant_arm, 2036 }, 2037 { 2038 .id = 0x01041180, 2039 .mask = 0xff0fffff, 2040 .data = &variant_arm_extended_fifo, 2041 }, 2042 { 2043 .id = 0x02041180, 2044 .mask = 0xff0fffff, 2045 .data = &variant_arm_extended_fifo_hwfc, 2046 }, 2047 { 2048 .id = 0x00041181, 2049 .mask = 0x000fffff, 2050 .data = &variant_arm, 2051 }, 2052 /* ST Micro variants */ 2053 { 2054 .id = 0x00180180, 2055 .mask = 0x00ffffff, 2056 .data = &variant_u300, 2057 }, 2058 { 2059 .id = 0x10180180, 2060 .mask = 0xf0ffffff, 2061 .data = &variant_nomadik, 2062 }, 2063 { 2064 .id = 0x00280180, 2065 .mask = 0x00ffffff, 2066 .data = &variant_nomadik, 2067 }, 2068 { 2069 .id = 0x00480180, 2070 .mask = 0xf0ffffff, 2071 .data = &variant_ux500, 2072 }, 2073 { 2074 .id = 0x10480180, 2075 .mask = 0xf0ffffff, 2076 .data = &variant_ux500v2, 2077 }, 2078 { 2079 .id = 0x00880180, 2080 .mask = 0x00ffffff, 2081 .data = &variant_stm32, 2082 }, 2083 /* Qualcomm variants */ 2084 { 2085 .id = 0x00051180, 2086 .mask = 0x000fffff, 2087 .data = &variant_qcom, 2088 }, 2089 { 0, 0 }, 2090 }; 2091 2092 MODULE_DEVICE_TABLE(amba, mmci_ids); 2093 2094 static struct amba_driver mmci_driver = { 2095 .drv = { 2096 .name = DRIVER_NAME, 2097 .pm = &mmci_dev_pm_ops, 2098 }, 2099 .probe = mmci_probe, 2100 .remove = mmci_remove, 2101 .id_table = mmci_ids, 2102 }; 2103 2104 module_amba_driver(mmci_driver); 2105 2106 module_param(fmax, uint, 0444); 2107 2108 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2109 MODULE_LICENSE("GPL"); 2110