1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson AB. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/highmem.h> 21 #include <linux/log2.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/card.h> 24 #include <linux/amba/bus.h> 25 #include <linux/clk.h> 26 #include <linux/scatterlist.h> 27 #include <linux/gpio.h> 28 #include <linux/amba/mmci.h> 29 #include <linux/regulator/consumer.h> 30 31 #include <asm/div64.h> 32 #include <asm/io.h> 33 #include <asm/sizes.h> 34 35 #include "mmci.h" 36 37 #define DRIVER_NAME "mmci-pl18x" 38 39 static unsigned int fmax = 515633; 40 41 /** 42 * struct variant_data - MMCI variant-specific quirks 43 * @clkreg: default value for MCICLOCK register 44 * @clkreg_enable: enable value for MMCICLOCK register 45 * @datalength_bits: number of bits in the MMCIDATALENGTH register 46 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 47 * is asserted (likewise for RX) 48 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 49 * is asserted (likewise for RX) 50 * @sdio: variant supports SDIO 51 * @st_clkdiv: true if using a ST-specific clock divider algorithm 52 */ 53 struct variant_data { 54 unsigned int clkreg; 55 unsigned int clkreg_enable; 56 unsigned int datalength_bits; 57 unsigned int fifosize; 58 unsigned int fifohalfsize; 59 bool sdio; 60 bool st_clkdiv; 61 }; 62 63 static struct variant_data variant_arm = { 64 .fifosize = 16 * 4, 65 .fifohalfsize = 8 * 4, 66 .datalength_bits = 16, 67 }; 68 69 static struct variant_data variant_u300 = { 70 .fifosize = 16 * 4, 71 .fifohalfsize = 8 * 4, 72 .clkreg_enable = 1 << 13, /* HWFCEN */ 73 .datalength_bits = 16, 74 .sdio = true, 75 }; 76 77 static struct variant_data variant_ux500 = { 78 .fifosize = 30 * 4, 79 .fifohalfsize = 8 * 4, 80 .clkreg = MCI_CLK_ENABLE, 81 .clkreg_enable = 1 << 14, /* HWFCEN */ 82 .datalength_bits = 24, 83 .sdio = true, 84 .st_clkdiv = true, 85 }; 86 87 /* 88 * This must be called with host->lock held 89 */ 90 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 91 { 92 struct variant_data *variant = host->variant; 93 u32 clk = variant->clkreg; 94 95 if (desired) { 96 if (desired >= host->mclk) { 97 clk = MCI_CLK_BYPASS; 98 host->cclk = host->mclk; 99 } else if (variant->st_clkdiv) { 100 /* 101 * DB8500 TRM says f = mclk / (clkdiv + 2) 102 * => clkdiv = (mclk / f) - 2 103 * Round the divider up so we don't exceed the max 104 * frequency 105 */ 106 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 107 if (clk >= 256) 108 clk = 255; 109 host->cclk = host->mclk / (clk + 2); 110 } else { 111 /* 112 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 113 * => clkdiv = mclk / (2 * f) - 1 114 */ 115 clk = host->mclk / (2 * desired) - 1; 116 if (clk >= 256) 117 clk = 255; 118 host->cclk = host->mclk / (2 * (clk + 1)); 119 } 120 121 clk |= variant->clkreg_enable; 122 clk |= MCI_CLK_ENABLE; 123 /* This hasn't proven to be worthwhile */ 124 /* clk |= MCI_CLK_PWRSAVE; */ 125 } 126 127 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 128 clk |= MCI_4BIT_BUS; 129 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 130 clk |= MCI_ST_8BIT_BUS; 131 132 writel(clk, host->base + MMCICLOCK); 133 } 134 135 static void 136 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 137 { 138 writel(0, host->base + MMCICOMMAND); 139 140 BUG_ON(host->data); 141 142 host->mrq = NULL; 143 host->cmd = NULL; 144 145 if (mrq->data) 146 mrq->data->bytes_xfered = host->data_xfered; 147 148 /* 149 * Need to drop the host lock here; mmc_request_done may call 150 * back into the driver... 151 */ 152 spin_unlock(&host->lock); 153 mmc_request_done(host->mmc, mrq); 154 spin_lock(&host->lock); 155 } 156 157 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 158 { 159 void __iomem *base = host->base; 160 161 if (host->singleirq) { 162 unsigned int mask0 = readl(base + MMCIMASK0); 163 164 mask0 &= ~MCI_IRQ1MASK; 165 mask0 |= mask; 166 167 writel(mask0, base + MMCIMASK0); 168 } 169 170 writel(mask, base + MMCIMASK1); 171 } 172 173 static void mmci_stop_data(struct mmci_host *host) 174 { 175 writel(0, host->base + MMCIDATACTRL); 176 mmci_set_mask1(host, 0); 177 host->data = NULL; 178 } 179 180 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 181 { 182 unsigned int flags = SG_MITER_ATOMIC; 183 184 if (data->flags & MMC_DATA_READ) 185 flags |= SG_MITER_TO_SG; 186 else 187 flags |= SG_MITER_FROM_SG; 188 189 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 190 } 191 192 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 193 { 194 struct variant_data *variant = host->variant; 195 unsigned int datactrl, timeout, irqmask; 196 unsigned long long clks; 197 void __iomem *base; 198 int blksz_bits; 199 200 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 201 data->blksz, data->blocks, data->flags); 202 203 host->data = data; 204 host->size = data->blksz * data->blocks; 205 host->data_xfered = 0; 206 207 mmci_init_sg(host, data); 208 209 clks = (unsigned long long)data->timeout_ns * host->cclk; 210 do_div(clks, 1000000000UL); 211 212 timeout = data->timeout_clks + (unsigned int)clks; 213 214 base = host->base; 215 writel(timeout, base + MMCIDATATIMER); 216 writel(host->size, base + MMCIDATALENGTH); 217 218 blksz_bits = ffs(data->blksz) - 1; 219 BUG_ON(1 << blksz_bits != data->blksz); 220 221 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 222 if (data->flags & MMC_DATA_READ) { 223 datactrl |= MCI_DPSM_DIRECTION; 224 irqmask = MCI_RXFIFOHALFFULLMASK; 225 226 /* 227 * If we have less than a FIFOSIZE of bytes to transfer, 228 * trigger a PIO interrupt as soon as any data is available. 229 */ 230 if (host->size < variant->fifosize) 231 irqmask |= MCI_RXDATAAVLBLMASK; 232 } else { 233 /* 234 * We don't actually need to include "FIFO empty" here 235 * since its implicit in "FIFO half empty". 236 */ 237 irqmask = MCI_TXFIFOHALFEMPTYMASK; 238 } 239 240 /* The ST Micro variants has a special bit to enable SDIO */ 241 if (variant->sdio && host->mmc->card) 242 if (mmc_card_sdio(host->mmc->card)) 243 datactrl |= MCI_ST_DPSM_SDIOEN; 244 245 writel(datactrl, base + MMCIDATACTRL); 246 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 247 mmci_set_mask1(host, irqmask); 248 } 249 250 static void 251 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 252 { 253 void __iomem *base = host->base; 254 255 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 256 cmd->opcode, cmd->arg, cmd->flags); 257 258 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 259 writel(0, base + MMCICOMMAND); 260 udelay(1); 261 } 262 263 c |= cmd->opcode | MCI_CPSM_ENABLE; 264 if (cmd->flags & MMC_RSP_PRESENT) { 265 if (cmd->flags & MMC_RSP_136) 266 c |= MCI_CPSM_LONGRSP; 267 c |= MCI_CPSM_RESPONSE; 268 } 269 if (/*interrupt*/0) 270 c |= MCI_CPSM_INTERRUPT; 271 272 host->cmd = cmd; 273 274 writel(cmd->arg, base + MMCIARGUMENT); 275 writel(c, base + MMCICOMMAND); 276 } 277 278 static void 279 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 280 unsigned int status) 281 { 282 /* First check for errors */ 283 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 284 u32 remain, success; 285 286 /* 287 * Calculate how far we are into the transfer. Note that 288 * the data counter gives the number of bytes transferred 289 * on the MMC bus, not on the host side. On reads, this 290 * can be as much as a FIFO-worth of data ahead. This 291 * matters for FIFO overruns only. 292 */ 293 remain = readl(host->base + MMCIDATACNT); 294 success = data->blksz * data->blocks - remain; 295 296 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 297 status, success); 298 if (status & MCI_DATACRCFAIL) { 299 /* Last block was not successful */ 300 success -= 1; 301 data->error = -EILSEQ; 302 } else if (status & MCI_DATATIMEOUT) { 303 data->error = -ETIMEDOUT; 304 } else if (status & MCI_TXUNDERRUN) { 305 data->error = -EIO; 306 } else if (status & MCI_RXOVERRUN) { 307 if (success > host->variant->fifosize) 308 success -= host->variant->fifosize; 309 else 310 success = 0; 311 data->error = -EIO; 312 } 313 host->data_xfered = round_down(success, data->blksz); 314 315 /* 316 * We hit an error condition. Ensure that any data 317 * partially written to a page is properly coherent. 318 */ 319 if (data->flags & MMC_DATA_READ) { 320 struct sg_mapping_iter *sg_miter = &host->sg_miter; 321 unsigned long flags; 322 323 local_irq_save(flags); 324 if (sg_miter_next(sg_miter)) { 325 flush_dcache_page(sg_miter->page); 326 sg_miter_stop(sg_miter); 327 } 328 local_irq_restore(flags); 329 } 330 } 331 332 if (status & MCI_DATABLOCKEND) 333 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 334 335 if (status & MCI_DATAEND || data->error) { 336 mmci_stop_data(host); 337 338 if (!data->error) 339 /* The error clause is handled above, success! */ 340 host->data_xfered += data->blksz * data->blocks; 341 342 if (!data->stop) { 343 mmci_request_end(host, data->mrq); 344 } else { 345 mmci_start_command(host, data->stop, 0); 346 } 347 } 348 } 349 350 static void 351 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 352 unsigned int status) 353 { 354 void __iomem *base = host->base; 355 356 host->cmd = NULL; 357 358 if (status & MCI_CMDTIMEOUT) { 359 cmd->error = -ETIMEDOUT; 360 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 361 cmd->error = -EILSEQ; 362 } else { 363 cmd->resp[0] = readl(base + MMCIRESPONSE0); 364 cmd->resp[1] = readl(base + MMCIRESPONSE1); 365 cmd->resp[2] = readl(base + MMCIRESPONSE2); 366 cmd->resp[3] = readl(base + MMCIRESPONSE3); 367 } 368 369 if (!cmd->data || cmd->error) { 370 if (host->data) 371 mmci_stop_data(host); 372 mmci_request_end(host, cmd->mrq); 373 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 374 mmci_start_data(host, cmd->data); 375 } 376 } 377 378 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 379 { 380 void __iomem *base = host->base; 381 char *ptr = buffer; 382 u32 status; 383 int host_remain = host->size; 384 385 do { 386 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 387 388 if (count > remain) 389 count = remain; 390 391 if (count <= 0) 392 break; 393 394 readsl(base + MMCIFIFO, ptr, count >> 2); 395 396 ptr += count; 397 remain -= count; 398 host_remain -= count; 399 400 if (remain == 0) 401 break; 402 403 status = readl(base + MMCISTATUS); 404 } while (status & MCI_RXDATAAVLBL); 405 406 return ptr - buffer; 407 } 408 409 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 410 { 411 struct variant_data *variant = host->variant; 412 void __iomem *base = host->base; 413 char *ptr = buffer; 414 415 do { 416 unsigned int count, maxcnt; 417 418 maxcnt = status & MCI_TXFIFOEMPTY ? 419 variant->fifosize : variant->fifohalfsize; 420 count = min(remain, maxcnt); 421 422 /* 423 * The ST Micro variant for SDIO transfer sizes 424 * less then 8 bytes should have clock H/W flow 425 * control disabled. 426 */ 427 if (variant->sdio && 428 mmc_card_sdio(host->mmc->card)) { 429 if (count < 8) 430 writel(readl(host->base + MMCICLOCK) & 431 ~variant->clkreg_enable, 432 host->base + MMCICLOCK); 433 else 434 writel(readl(host->base + MMCICLOCK) | 435 variant->clkreg_enable, 436 host->base + MMCICLOCK); 437 } 438 439 /* 440 * SDIO especially may want to send something that is 441 * not divisible by 4 (as opposed to card sectors 442 * etc), and the FIFO only accept full 32-bit writes. 443 * So compensate by adding +3 on the count, a single 444 * byte become a 32bit write, 7 bytes will be two 445 * 32bit writes etc. 446 */ 447 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 448 449 ptr += count; 450 remain -= count; 451 452 if (remain == 0) 453 break; 454 455 status = readl(base + MMCISTATUS); 456 } while (status & MCI_TXFIFOHALFEMPTY); 457 458 return ptr - buffer; 459 } 460 461 /* 462 * PIO data transfer IRQ handler. 463 */ 464 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 465 { 466 struct mmci_host *host = dev_id; 467 struct sg_mapping_iter *sg_miter = &host->sg_miter; 468 struct variant_data *variant = host->variant; 469 void __iomem *base = host->base; 470 unsigned long flags; 471 u32 status; 472 473 status = readl(base + MMCISTATUS); 474 475 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 476 477 local_irq_save(flags); 478 479 do { 480 unsigned int remain, len; 481 char *buffer; 482 483 /* 484 * For write, we only need to test the half-empty flag 485 * here - if the FIFO is completely empty, then by 486 * definition it is more than half empty. 487 * 488 * For read, check for data available. 489 */ 490 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 491 break; 492 493 if (!sg_miter_next(sg_miter)) 494 break; 495 496 buffer = sg_miter->addr; 497 remain = sg_miter->length; 498 499 len = 0; 500 if (status & MCI_RXACTIVE) 501 len = mmci_pio_read(host, buffer, remain); 502 if (status & MCI_TXACTIVE) 503 len = mmci_pio_write(host, buffer, remain, status); 504 505 sg_miter->consumed = len; 506 507 host->size -= len; 508 remain -= len; 509 510 if (remain) 511 break; 512 513 if (status & MCI_RXACTIVE) 514 flush_dcache_page(sg_miter->page); 515 516 status = readl(base + MMCISTATUS); 517 } while (1); 518 519 sg_miter_stop(sg_miter); 520 521 local_irq_restore(flags); 522 523 /* 524 * If we're nearing the end of the read, switch to 525 * "any data available" mode. 526 */ 527 if (status & MCI_RXACTIVE && host->size < variant->fifosize) 528 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 529 530 /* 531 * If we run out of data, disable the data IRQs; this 532 * prevents a race where the FIFO becomes empty before 533 * the chip itself has disabled the data path, and 534 * stops us racing with our data end IRQ. 535 */ 536 if (host->size == 0) { 537 mmci_set_mask1(host, 0); 538 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 539 } 540 541 return IRQ_HANDLED; 542 } 543 544 /* 545 * Handle completion of command and data transfers. 546 */ 547 static irqreturn_t mmci_irq(int irq, void *dev_id) 548 { 549 struct mmci_host *host = dev_id; 550 u32 status; 551 int ret = 0; 552 553 spin_lock(&host->lock); 554 555 do { 556 struct mmc_command *cmd; 557 struct mmc_data *data; 558 559 status = readl(host->base + MMCISTATUS); 560 561 if (host->singleirq) { 562 if (status & readl(host->base + MMCIMASK1)) 563 mmci_pio_irq(irq, dev_id); 564 565 status &= ~MCI_IRQ1MASK; 566 } 567 568 status &= readl(host->base + MMCIMASK0); 569 writel(status, host->base + MMCICLEAR); 570 571 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 572 573 data = host->data; 574 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 575 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 576 mmci_data_irq(host, data, status); 577 578 cmd = host->cmd; 579 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 580 mmci_cmd_irq(host, cmd, status); 581 582 ret = 1; 583 } while (status); 584 585 spin_unlock(&host->lock); 586 587 return IRQ_RETVAL(ret); 588 } 589 590 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 591 { 592 struct mmci_host *host = mmc_priv(mmc); 593 unsigned long flags; 594 595 WARN_ON(host->mrq != NULL); 596 597 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 598 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 599 mrq->data->blksz); 600 mrq->cmd->error = -EINVAL; 601 mmc_request_done(mmc, mrq); 602 return; 603 } 604 605 spin_lock_irqsave(&host->lock, flags); 606 607 host->mrq = mrq; 608 609 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 610 mmci_start_data(host, mrq->data); 611 612 mmci_start_command(host, mrq->cmd, 0); 613 614 spin_unlock_irqrestore(&host->lock, flags); 615 } 616 617 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 618 { 619 struct mmci_host *host = mmc_priv(mmc); 620 u32 pwr = 0; 621 unsigned long flags; 622 int ret; 623 624 switch (ios->power_mode) { 625 case MMC_POWER_OFF: 626 if (host->vcc) 627 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 628 break; 629 case MMC_POWER_UP: 630 if (host->vcc) { 631 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 632 if (ret) { 633 dev_err(mmc_dev(mmc), "unable to set OCR\n"); 634 /* 635 * The .set_ios() function in the mmc_host_ops 636 * struct return void, and failing to set the 637 * power should be rare so we print an error 638 * and return here. 639 */ 640 return; 641 } 642 } 643 if (host->plat->vdd_handler) 644 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, 645 ios->power_mode); 646 /* The ST version does not have this, fall through to POWER_ON */ 647 if (host->hw_designer != AMBA_VENDOR_ST) { 648 pwr |= MCI_PWR_UP; 649 break; 650 } 651 case MMC_POWER_ON: 652 pwr |= MCI_PWR_ON; 653 break; 654 } 655 656 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 657 if (host->hw_designer != AMBA_VENDOR_ST) 658 pwr |= MCI_ROD; 659 else { 660 /* 661 * The ST Micro variant use the ROD bit for something 662 * else and only has OD (Open Drain). 663 */ 664 pwr |= MCI_OD; 665 } 666 } 667 668 spin_lock_irqsave(&host->lock, flags); 669 670 mmci_set_clkreg(host, ios->clock); 671 672 if (host->pwr != pwr) { 673 host->pwr = pwr; 674 writel(pwr, host->base + MMCIPOWER); 675 } 676 677 spin_unlock_irqrestore(&host->lock, flags); 678 } 679 680 static int mmci_get_ro(struct mmc_host *mmc) 681 { 682 struct mmci_host *host = mmc_priv(mmc); 683 684 if (host->gpio_wp == -ENOSYS) 685 return -ENOSYS; 686 687 return gpio_get_value_cansleep(host->gpio_wp); 688 } 689 690 static int mmci_get_cd(struct mmc_host *mmc) 691 { 692 struct mmci_host *host = mmc_priv(mmc); 693 struct mmci_platform_data *plat = host->plat; 694 unsigned int status; 695 696 if (host->gpio_cd == -ENOSYS) { 697 if (!plat->status) 698 return 1; /* Assume always present */ 699 700 status = plat->status(mmc_dev(host->mmc)); 701 } else 702 status = !!gpio_get_value_cansleep(host->gpio_cd) 703 ^ plat->cd_invert; 704 705 /* 706 * Use positive logic throughout - status is zero for no card, 707 * non-zero for card inserted. 708 */ 709 return status; 710 } 711 712 static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 713 { 714 struct mmci_host *host = dev_id; 715 716 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 717 718 return IRQ_HANDLED; 719 } 720 721 static const struct mmc_host_ops mmci_ops = { 722 .request = mmci_request, 723 .set_ios = mmci_set_ios, 724 .get_ro = mmci_get_ro, 725 .get_cd = mmci_get_cd, 726 }; 727 728 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) 729 { 730 struct mmci_platform_data *plat = dev->dev.platform_data; 731 struct variant_data *variant = id->data; 732 struct mmci_host *host; 733 struct mmc_host *mmc; 734 int ret; 735 736 /* must have platform data */ 737 if (!plat) { 738 ret = -EINVAL; 739 goto out; 740 } 741 742 ret = amba_request_regions(dev, DRIVER_NAME); 743 if (ret) 744 goto out; 745 746 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 747 if (!mmc) { 748 ret = -ENOMEM; 749 goto rel_regions; 750 } 751 752 host = mmc_priv(mmc); 753 host->mmc = mmc; 754 755 host->gpio_wp = -ENOSYS; 756 host->gpio_cd = -ENOSYS; 757 host->gpio_cd_irq = -1; 758 759 host->hw_designer = amba_manf(dev); 760 host->hw_revision = amba_rev(dev); 761 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 762 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 763 764 host->clk = clk_get(&dev->dev, NULL); 765 if (IS_ERR(host->clk)) { 766 ret = PTR_ERR(host->clk); 767 host->clk = NULL; 768 goto host_free; 769 } 770 771 ret = clk_enable(host->clk); 772 if (ret) 773 goto clk_free; 774 775 host->plat = plat; 776 host->variant = variant; 777 host->mclk = clk_get_rate(host->clk); 778 /* 779 * According to the spec, mclk is max 100 MHz, 780 * so we try to adjust the clock down to this, 781 * (if possible). 782 */ 783 if (host->mclk > 100000000) { 784 ret = clk_set_rate(host->clk, 100000000); 785 if (ret < 0) 786 goto clk_disable; 787 host->mclk = clk_get_rate(host->clk); 788 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 789 host->mclk); 790 } 791 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 792 if (!host->base) { 793 ret = -ENOMEM; 794 goto clk_disable; 795 } 796 797 mmc->ops = &mmci_ops; 798 mmc->f_min = (host->mclk + 511) / 512; 799 /* 800 * If the platform data supplies a maximum operating 801 * frequency, this takes precedence. Else, we fall back 802 * to using the module parameter, which has a (low) 803 * default value in case it is not specified. Either 804 * value must not exceed the clock rate into the block, 805 * of course. 806 */ 807 if (plat->f_max) 808 mmc->f_max = min(host->mclk, plat->f_max); 809 else 810 mmc->f_max = min(host->mclk, fmax); 811 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 812 813 #ifdef CONFIG_REGULATOR 814 /* If we're using the regulator framework, try to fetch a regulator */ 815 host->vcc = regulator_get(&dev->dev, "vmmc"); 816 if (IS_ERR(host->vcc)) 817 host->vcc = NULL; 818 else { 819 int mask = mmc_regulator_get_ocrmask(host->vcc); 820 821 if (mask < 0) 822 dev_err(&dev->dev, "error getting OCR mask (%d)\n", 823 mask); 824 else { 825 host->mmc->ocr_avail = (u32) mask; 826 if (plat->ocr_mask) 827 dev_warn(&dev->dev, 828 "Provided ocr_mask/setpower will not be used " 829 "(using regulator instead)\n"); 830 } 831 } 832 #endif 833 /* Fall back to platform data if no regulator is found */ 834 if (host->vcc == NULL) 835 mmc->ocr_avail = plat->ocr_mask; 836 mmc->caps = plat->capabilities; 837 838 /* 839 * We can do SGIO 840 */ 841 mmc->max_segs = NR_SG; 842 843 /* 844 * Since only a certain number of bits are valid in the data length 845 * register, we must ensure that we don't exceed 2^num-1 bytes in a 846 * single request. 847 */ 848 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 849 850 /* 851 * Set the maximum segment size. Since we aren't doing DMA 852 * (yet) we are only limited by the data length register. 853 */ 854 mmc->max_seg_size = mmc->max_req_size; 855 856 /* 857 * Block size can be up to 2048 bytes, but must be a power of two. 858 */ 859 mmc->max_blk_size = 2048; 860 861 /* 862 * No limit on the number of blocks transferred. 863 */ 864 mmc->max_blk_count = mmc->max_req_size; 865 866 spin_lock_init(&host->lock); 867 868 writel(0, host->base + MMCIMASK0); 869 writel(0, host->base + MMCIMASK1); 870 writel(0xfff, host->base + MMCICLEAR); 871 872 if (gpio_is_valid(plat->gpio_cd)) { 873 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 874 if (ret == 0) 875 ret = gpio_direction_input(plat->gpio_cd); 876 if (ret == 0) 877 host->gpio_cd = plat->gpio_cd; 878 else if (ret != -ENOSYS) 879 goto err_gpio_cd; 880 881 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 882 mmci_cd_irq, 0, 883 DRIVER_NAME " (cd)", host); 884 if (ret >= 0) 885 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 886 } 887 if (gpio_is_valid(plat->gpio_wp)) { 888 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 889 if (ret == 0) 890 ret = gpio_direction_input(plat->gpio_wp); 891 if (ret == 0) 892 host->gpio_wp = plat->gpio_wp; 893 else if (ret != -ENOSYS) 894 goto err_gpio_wp; 895 } 896 897 if ((host->plat->status || host->gpio_cd != -ENOSYS) 898 && host->gpio_cd_irq < 0) 899 mmc->caps |= MMC_CAP_NEEDS_POLL; 900 901 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 902 if (ret) 903 goto unmap; 904 905 if (dev->irq[1] == NO_IRQ) 906 host->singleirq = true; 907 else { 908 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 909 DRIVER_NAME " (pio)", host); 910 if (ret) 911 goto irq0_free; 912 } 913 914 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 915 916 amba_set_drvdata(dev, mmc); 917 918 dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n", 919 mmc_hostname(mmc), amba_part(dev), amba_rev(dev), 920 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 921 922 mmc_add_host(mmc); 923 924 return 0; 925 926 irq0_free: 927 free_irq(dev->irq[0], host); 928 unmap: 929 if (host->gpio_wp != -ENOSYS) 930 gpio_free(host->gpio_wp); 931 err_gpio_wp: 932 if (host->gpio_cd_irq >= 0) 933 free_irq(host->gpio_cd_irq, host); 934 if (host->gpio_cd != -ENOSYS) 935 gpio_free(host->gpio_cd); 936 err_gpio_cd: 937 iounmap(host->base); 938 clk_disable: 939 clk_disable(host->clk); 940 clk_free: 941 clk_put(host->clk); 942 host_free: 943 mmc_free_host(mmc); 944 rel_regions: 945 amba_release_regions(dev); 946 out: 947 return ret; 948 } 949 950 static int __devexit mmci_remove(struct amba_device *dev) 951 { 952 struct mmc_host *mmc = amba_get_drvdata(dev); 953 954 amba_set_drvdata(dev, NULL); 955 956 if (mmc) { 957 struct mmci_host *host = mmc_priv(mmc); 958 959 mmc_remove_host(mmc); 960 961 writel(0, host->base + MMCIMASK0); 962 writel(0, host->base + MMCIMASK1); 963 964 writel(0, host->base + MMCICOMMAND); 965 writel(0, host->base + MMCIDATACTRL); 966 967 free_irq(dev->irq[0], host); 968 if (!host->singleirq) 969 free_irq(dev->irq[1], host); 970 971 if (host->gpio_wp != -ENOSYS) 972 gpio_free(host->gpio_wp); 973 if (host->gpio_cd_irq >= 0) 974 free_irq(host->gpio_cd_irq, host); 975 if (host->gpio_cd != -ENOSYS) 976 gpio_free(host->gpio_cd); 977 978 iounmap(host->base); 979 clk_disable(host->clk); 980 clk_put(host->clk); 981 982 if (host->vcc) 983 mmc_regulator_set_ocr(mmc, host->vcc, 0); 984 regulator_put(host->vcc); 985 986 mmc_free_host(mmc); 987 988 amba_release_regions(dev); 989 } 990 991 return 0; 992 } 993 994 #ifdef CONFIG_PM 995 static int mmci_suspend(struct amba_device *dev, pm_message_t state) 996 { 997 struct mmc_host *mmc = amba_get_drvdata(dev); 998 int ret = 0; 999 1000 if (mmc) { 1001 struct mmci_host *host = mmc_priv(mmc); 1002 1003 ret = mmc_suspend_host(mmc); 1004 if (ret == 0) 1005 writel(0, host->base + MMCIMASK0); 1006 } 1007 1008 return ret; 1009 } 1010 1011 static int mmci_resume(struct amba_device *dev) 1012 { 1013 struct mmc_host *mmc = amba_get_drvdata(dev); 1014 int ret = 0; 1015 1016 if (mmc) { 1017 struct mmci_host *host = mmc_priv(mmc); 1018 1019 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1020 1021 ret = mmc_resume_host(mmc); 1022 } 1023 1024 return ret; 1025 } 1026 #else 1027 #define mmci_suspend NULL 1028 #define mmci_resume NULL 1029 #endif 1030 1031 static struct amba_id mmci_ids[] = { 1032 { 1033 .id = 0x00041180, 1034 .mask = 0x000fffff, 1035 .data = &variant_arm, 1036 }, 1037 { 1038 .id = 0x00041181, 1039 .mask = 0x000fffff, 1040 .data = &variant_arm, 1041 }, 1042 /* ST Micro variants */ 1043 { 1044 .id = 0x00180180, 1045 .mask = 0x00ffffff, 1046 .data = &variant_u300, 1047 }, 1048 { 1049 .id = 0x00280180, 1050 .mask = 0x00ffffff, 1051 .data = &variant_u300, 1052 }, 1053 { 1054 .id = 0x00480180, 1055 .mask = 0x00ffffff, 1056 .data = &variant_ux500, 1057 }, 1058 { 0, 0 }, 1059 }; 1060 1061 static struct amba_driver mmci_driver = { 1062 .drv = { 1063 .name = DRIVER_NAME, 1064 }, 1065 .probe = mmci_probe, 1066 .remove = __devexit_p(mmci_remove), 1067 .suspend = mmci_suspend, 1068 .resume = mmci_resume, 1069 .id_table = mmci_ids, 1070 }; 1071 1072 static int __init mmci_init(void) 1073 { 1074 return amba_driver_register(&mmci_driver); 1075 } 1076 1077 static void __exit mmci_exit(void) 1078 { 1079 amba_driver_unregister(&mmci_driver); 1080 } 1081 1082 module_init(mmci_init); 1083 module_exit(mmci_exit); 1084 module_param(fmax, uint, 0444); 1085 1086 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1087 MODULE_LICENSE("GPL"); 1088