1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/mmc/pm.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/amba/bus.h> 30 #include <linux/clk.h> 31 #include <linux/scatterlist.h> 32 #include <linux/of.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/amba/mmci.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/types.h> 39 #include <linux/pinctrl/consumer.h> 40 #include <linux/reset.h> 41 42 #include <asm/div64.h> 43 #include <asm/io.h> 44 45 #include "mmci.h" 46 #include "mmci_qcom_dml.h" 47 48 #define DRIVER_NAME "mmci-pl18x" 49 50 #ifdef CONFIG_DMA_ENGINE 51 void mmci_variant_init(struct mmci_host *host); 52 #else 53 static inline void mmci_variant_init(struct mmci_host *host) {} 54 #endif 55 56 #ifdef CONFIG_MMC_STM32_SDMMC 57 void sdmmc_variant_init(struct mmci_host *host); 58 #else 59 static inline void sdmmc_variant_init(struct mmci_host *host) {} 60 #endif 61 62 static unsigned int fmax = 515633; 63 64 static struct variant_data variant_arm = { 65 .fifosize = 16 * 4, 66 .fifohalfsize = 8 * 4, 67 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 68 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 69 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 70 .cmdreg_srsp = MCI_CPSM_RESPONSE, 71 .datalength_bits = 16, 72 .datactrl_blocksz = 11, 73 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 74 .pwrreg_powerup = MCI_PWR_UP, 75 .f_max = 100000000, 76 .reversed_irq_handling = true, 77 .mmcimask1 = true, 78 .irq_pio_mask = MCI_IRQ_PIO_MASK, 79 .start_err = MCI_STARTBITERR, 80 .opendrain = MCI_ROD, 81 .init = mmci_variant_init, 82 }; 83 84 static struct variant_data variant_arm_extended_fifo = { 85 .fifosize = 128 * 4, 86 .fifohalfsize = 64 * 4, 87 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 88 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 89 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 90 .cmdreg_srsp = MCI_CPSM_RESPONSE, 91 .datalength_bits = 16, 92 .datactrl_blocksz = 11, 93 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 94 .pwrreg_powerup = MCI_PWR_UP, 95 .f_max = 100000000, 96 .mmcimask1 = true, 97 .irq_pio_mask = MCI_IRQ_PIO_MASK, 98 .start_err = MCI_STARTBITERR, 99 .opendrain = MCI_ROD, 100 .init = mmci_variant_init, 101 }; 102 103 static struct variant_data variant_arm_extended_fifo_hwfc = { 104 .fifosize = 128 * 4, 105 .fifohalfsize = 64 * 4, 106 .clkreg_enable = MCI_ARM_HWFCEN, 107 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 108 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 109 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 110 .cmdreg_srsp = MCI_CPSM_RESPONSE, 111 .datalength_bits = 16, 112 .datactrl_blocksz = 11, 113 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 114 .pwrreg_powerup = MCI_PWR_UP, 115 .f_max = 100000000, 116 .mmcimask1 = true, 117 .irq_pio_mask = MCI_IRQ_PIO_MASK, 118 .start_err = MCI_STARTBITERR, 119 .opendrain = MCI_ROD, 120 .init = mmci_variant_init, 121 }; 122 123 static struct variant_data variant_u300 = { 124 .fifosize = 16 * 4, 125 .fifohalfsize = 8 * 4, 126 .clkreg_enable = MCI_ST_U300_HWFCEN, 127 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 128 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 129 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 130 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 131 .cmdreg_srsp = MCI_CPSM_RESPONSE, 132 .datalength_bits = 16, 133 .datactrl_blocksz = 11, 134 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 135 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 136 .st_sdio = true, 137 .pwrreg_powerup = MCI_PWR_ON, 138 .f_max = 100000000, 139 .signal_direction = true, 140 .pwrreg_clkgate = true, 141 .pwrreg_nopower = true, 142 .mmcimask1 = true, 143 .irq_pio_mask = MCI_IRQ_PIO_MASK, 144 .start_err = MCI_STARTBITERR, 145 .opendrain = MCI_OD, 146 .init = mmci_variant_init, 147 }; 148 149 static struct variant_data variant_nomadik = { 150 .fifosize = 16 * 4, 151 .fifohalfsize = 8 * 4, 152 .clkreg = MCI_CLK_ENABLE, 153 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 154 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 155 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 156 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 157 .cmdreg_srsp = MCI_CPSM_RESPONSE, 158 .datalength_bits = 24, 159 .datactrl_blocksz = 11, 160 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 161 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 162 .st_sdio = true, 163 .st_clkdiv = true, 164 .pwrreg_powerup = MCI_PWR_ON, 165 .f_max = 100000000, 166 .signal_direction = true, 167 .pwrreg_clkgate = true, 168 .pwrreg_nopower = true, 169 .mmcimask1 = true, 170 .irq_pio_mask = MCI_IRQ_PIO_MASK, 171 .start_err = MCI_STARTBITERR, 172 .opendrain = MCI_OD, 173 .init = mmci_variant_init, 174 }; 175 176 static struct variant_data variant_ux500 = { 177 .fifosize = 30 * 4, 178 .fifohalfsize = 8 * 4, 179 .clkreg = MCI_CLK_ENABLE, 180 .clkreg_enable = MCI_ST_UX500_HWFCEN, 181 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 182 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 183 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 184 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 185 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 186 .cmdreg_srsp = MCI_CPSM_RESPONSE, 187 .datalength_bits = 24, 188 .datactrl_blocksz = 11, 189 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 190 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 191 .st_sdio = true, 192 .st_clkdiv = true, 193 .pwrreg_powerup = MCI_PWR_ON, 194 .f_max = 100000000, 195 .signal_direction = true, 196 .pwrreg_clkgate = true, 197 .busy_detect = true, 198 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 199 .busy_detect_flag = MCI_ST_CARDBUSY, 200 .busy_detect_mask = MCI_ST_BUSYENDMASK, 201 .pwrreg_nopower = true, 202 .mmcimask1 = true, 203 .irq_pio_mask = MCI_IRQ_PIO_MASK, 204 .start_err = MCI_STARTBITERR, 205 .opendrain = MCI_OD, 206 .init = mmci_variant_init, 207 }; 208 209 static struct variant_data variant_ux500v2 = { 210 .fifosize = 30 * 4, 211 .fifohalfsize = 8 * 4, 212 .clkreg = MCI_CLK_ENABLE, 213 .clkreg_enable = MCI_ST_UX500_HWFCEN, 214 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 215 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 216 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 217 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 218 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 219 .cmdreg_srsp = MCI_CPSM_RESPONSE, 220 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 221 .datalength_bits = 24, 222 .datactrl_blocksz = 11, 223 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 224 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 225 .st_sdio = true, 226 .st_clkdiv = true, 227 .blksz_datactrl16 = true, 228 .pwrreg_powerup = MCI_PWR_ON, 229 .f_max = 100000000, 230 .signal_direction = true, 231 .pwrreg_clkgate = true, 232 .busy_detect = true, 233 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 234 .busy_detect_flag = MCI_ST_CARDBUSY, 235 .busy_detect_mask = MCI_ST_BUSYENDMASK, 236 .pwrreg_nopower = true, 237 .mmcimask1 = true, 238 .irq_pio_mask = MCI_IRQ_PIO_MASK, 239 .start_err = MCI_STARTBITERR, 240 .opendrain = MCI_OD, 241 .init = mmci_variant_init, 242 }; 243 244 static struct variant_data variant_stm32 = { 245 .fifosize = 32 * 4, 246 .fifohalfsize = 8 * 4, 247 .clkreg = MCI_CLK_ENABLE, 248 .clkreg_enable = MCI_ST_UX500_HWFCEN, 249 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 250 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 251 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 252 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 253 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 254 .cmdreg_srsp = MCI_CPSM_RESPONSE, 255 .irq_pio_mask = MCI_IRQ_PIO_MASK, 256 .datalength_bits = 24, 257 .datactrl_blocksz = 11, 258 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 259 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 260 .st_sdio = true, 261 .st_clkdiv = true, 262 .pwrreg_powerup = MCI_PWR_ON, 263 .f_max = 48000000, 264 .pwrreg_clkgate = true, 265 .pwrreg_nopower = true, 266 .init = mmci_variant_init, 267 }; 268 269 static struct variant_data variant_stm32_sdmmc = { 270 .fifosize = 16 * 4, 271 .fifohalfsize = 8 * 4, 272 .f_max = 208000000, 273 .stm32_clkdiv = true, 274 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 275 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 276 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 277 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 278 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 279 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 280 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 281 .datactrl_first = true, 282 .datacnt_useless = true, 283 .datalength_bits = 25, 284 .datactrl_blocksz = 14, 285 .stm32_idmabsize_mask = GENMASK(12, 5), 286 .init = sdmmc_variant_init, 287 }; 288 289 static struct variant_data variant_qcom = { 290 .fifosize = 16 * 4, 291 .fifohalfsize = 8 * 4, 292 .clkreg = MCI_CLK_ENABLE, 293 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 294 MCI_QCOM_CLK_SELECT_IN_FBCLK, 295 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 296 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 297 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 298 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 299 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 300 .cmdreg_srsp = MCI_CPSM_RESPONSE, 301 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 302 .blksz_datactrl4 = true, 303 .datalength_bits = 24, 304 .datactrl_blocksz = 11, 305 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 306 .pwrreg_powerup = MCI_PWR_UP, 307 .f_max = 208000000, 308 .explicit_mclk_control = true, 309 .qcom_fifo = true, 310 .qcom_dml = true, 311 .mmcimask1 = true, 312 .irq_pio_mask = MCI_IRQ_PIO_MASK, 313 .start_err = MCI_STARTBITERR, 314 .opendrain = MCI_ROD, 315 .init = qcom_variant_init, 316 }; 317 318 /* Busy detection for the ST Micro variant */ 319 static int mmci_card_busy(struct mmc_host *mmc) 320 { 321 struct mmci_host *host = mmc_priv(mmc); 322 unsigned long flags; 323 int busy = 0; 324 325 spin_lock_irqsave(&host->lock, flags); 326 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 327 busy = 1; 328 spin_unlock_irqrestore(&host->lock, flags); 329 330 return busy; 331 } 332 333 static void mmci_reg_delay(struct mmci_host *host) 334 { 335 /* 336 * According to the spec, at least three feedback clock cycles 337 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 338 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 339 * Worst delay time during card init is at 100 kHz => 30 us. 340 * Worst delay time when up and running is at 25 MHz => 120 ns. 341 */ 342 if (host->cclk < 25000000) 343 udelay(30); 344 else 345 ndelay(120); 346 } 347 348 /* 349 * This must be called with host->lock held 350 */ 351 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 352 { 353 if (host->clk_reg != clk) { 354 host->clk_reg = clk; 355 writel(clk, host->base + MMCICLOCK); 356 } 357 } 358 359 /* 360 * This must be called with host->lock held 361 */ 362 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 363 { 364 if (host->pwr_reg != pwr) { 365 host->pwr_reg = pwr; 366 writel(pwr, host->base + MMCIPOWER); 367 } 368 } 369 370 /* 371 * This must be called with host->lock held 372 */ 373 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 374 { 375 /* Keep busy mode in DPSM if enabled */ 376 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 377 378 if (host->datactrl_reg != datactrl) { 379 host->datactrl_reg = datactrl; 380 writel(datactrl, host->base + MMCIDATACTRL); 381 } 382 } 383 384 /* 385 * This must be called with host->lock held 386 */ 387 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 388 { 389 struct variant_data *variant = host->variant; 390 u32 clk = variant->clkreg; 391 392 /* Make sure cclk reflects the current calculated clock */ 393 host->cclk = 0; 394 395 if (desired) { 396 if (variant->explicit_mclk_control) { 397 host->cclk = host->mclk; 398 } else if (desired >= host->mclk) { 399 clk = MCI_CLK_BYPASS; 400 if (variant->st_clkdiv) 401 clk |= MCI_ST_UX500_NEG_EDGE; 402 host->cclk = host->mclk; 403 } else if (variant->st_clkdiv) { 404 /* 405 * DB8500 TRM says f = mclk / (clkdiv + 2) 406 * => clkdiv = (mclk / f) - 2 407 * Round the divider up so we don't exceed the max 408 * frequency 409 */ 410 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 411 if (clk >= 256) 412 clk = 255; 413 host->cclk = host->mclk / (clk + 2); 414 } else { 415 /* 416 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 417 * => clkdiv = mclk / (2 * f) - 1 418 */ 419 clk = host->mclk / (2 * desired) - 1; 420 if (clk >= 256) 421 clk = 255; 422 host->cclk = host->mclk / (2 * (clk + 1)); 423 } 424 425 clk |= variant->clkreg_enable; 426 clk |= MCI_CLK_ENABLE; 427 /* This hasn't proven to be worthwhile */ 428 /* clk |= MCI_CLK_PWRSAVE; */ 429 } 430 431 /* Set actual clock for debug */ 432 host->mmc->actual_clock = host->cclk; 433 434 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 435 clk |= MCI_4BIT_BUS; 436 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 437 clk |= variant->clkreg_8bit_bus_enable; 438 439 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 440 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 441 clk |= variant->clkreg_neg_edge_enable; 442 443 mmci_write_clkreg(host, clk); 444 } 445 446 void mmci_dma_release(struct mmci_host *host) 447 { 448 if (host->ops && host->ops->dma_release) 449 host->ops->dma_release(host); 450 451 host->use_dma = false; 452 } 453 454 void mmci_dma_setup(struct mmci_host *host) 455 { 456 if (!host->ops || !host->ops->dma_setup) 457 return; 458 459 if (host->ops->dma_setup(host)) 460 return; 461 462 /* initialize pre request cookie */ 463 host->next_cookie = 1; 464 465 host->use_dma = true; 466 } 467 468 /* 469 * Validate mmc prerequisites 470 */ 471 static int mmci_validate_data(struct mmci_host *host, 472 struct mmc_data *data) 473 { 474 if (!data) 475 return 0; 476 477 if (!is_power_of_2(data->blksz)) { 478 dev_err(mmc_dev(host->mmc), 479 "unsupported block size (%d bytes)\n", data->blksz); 480 return -EINVAL; 481 } 482 483 if (host->ops && host->ops->validate_data) 484 return host->ops->validate_data(host, data); 485 486 return 0; 487 } 488 489 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 490 { 491 int err; 492 493 if (!host->ops || !host->ops->prep_data) 494 return 0; 495 496 err = host->ops->prep_data(host, data, next); 497 498 if (next && !err) 499 data->host_cookie = ++host->next_cookie < 0 ? 500 1 : host->next_cookie; 501 502 return err; 503 } 504 505 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 506 int err) 507 { 508 if (host->ops && host->ops->unprep_data) 509 host->ops->unprep_data(host, data, err); 510 511 data->host_cookie = 0; 512 } 513 514 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 515 { 516 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 517 518 if (host->ops && host->ops->get_next_data) 519 host->ops->get_next_data(host, data); 520 } 521 522 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 523 { 524 struct mmc_data *data = host->data; 525 int ret; 526 527 if (!host->use_dma) 528 return -EINVAL; 529 530 ret = mmci_prep_data(host, data, false); 531 if (ret) 532 return ret; 533 534 if (!host->ops || !host->ops->dma_start) 535 return -EINVAL; 536 537 /* Okay, go for it. */ 538 dev_vdbg(mmc_dev(host->mmc), 539 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 540 data->sg_len, data->blksz, data->blocks, data->flags); 541 542 host->ops->dma_start(host, &datactrl); 543 544 /* Trigger the DMA transfer */ 545 mmci_write_datactrlreg(host, datactrl); 546 547 /* 548 * Let the MMCI say when the data is ended and it's time 549 * to fire next DMA request. When that happens, MMCI will 550 * call mmci_data_end() 551 */ 552 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 553 host->base + MMCIMASK0); 554 return 0; 555 } 556 557 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 558 { 559 if (!host->use_dma) 560 return; 561 562 if (host->ops && host->ops->dma_finalize) 563 host->ops->dma_finalize(host, data); 564 } 565 566 void mmci_dma_error(struct mmci_host *host) 567 { 568 if (!host->use_dma) 569 return; 570 571 if (host->ops && host->ops->dma_error) 572 host->ops->dma_error(host); 573 } 574 575 static void 576 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 577 { 578 writel(0, host->base + MMCICOMMAND); 579 580 BUG_ON(host->data); 581 582 host->mrq = NULL; 583 host->cmd = NULL; 584 585 mmc_request_done(host->mmc, mrq); 586 } 587 588 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 589 { 590 void __iomem *base = host->base; 591 struct variant_data *variant = host->variant; 592 593 if (host->singleirq) { 594 unsigned int mask0 = readl(base + MMCIMASK0); 595 596 mask0 &= ~variant->irq_pio_mask; 597 mask0 |= mask; 598 599 writel(mask0, base + MMCIMASK0); 600 } 601 602 if (variant->mmcimask1) 603 writel(mask, base + MMCIMASK1); 604 605 host->mask1_reg = mask; 606 } 607 608 static void mmci_stop_data(struct mmci_host *host) 609 { 610 mmci_write_datactrlreg(host, 0); 611 mmci_set_mask1(host, 0); 612 host->data = NULL; 613 } 614 615 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 616 { 617 unsigned int flags = SG_MITER_ATOMIC; 618 619 if (data->flags & MMC_DATA_READ) 620 flags |= SG_MITER_TO_SG; 621 else 622 flags |= SG_MITER_FROM_SG; 623 624 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 625 } 626 627 /* 628 * All the DMA operation mode stuff goes inside this ifdef. 629 * This assumes that you have a generic DMA device interface, 630 * no custom DMA interfaces are supported. 631 */ 632 #ifdef CONFIG_DMA_ENGINE 633 struct mmci_dmae_next { 634 struct dma_async_tx_descriptor *desc; 635 struct dma_chan *chan; 636 }; 637 638 struct mmci_dmae_priv { 639 struct dma_chan *cur; 640 struct dma_chan *rx_channel; 641 struct dma_chan *tx_channel; 642 struct dma_async_tx_descriptor *desc_current; 643 struct mmci_dmae_next next_data; 644 }; 645 646 int mmci_dmae_setup(struct mmci_host *host) 647 { 648 const char *rxname, *txname; 649 struct mmci_dmae_priv *dmae; 650 651 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 652 if (!dmae) 653 return -ENOMEM; 654 655 host->dma_priv = dmae; 656 657 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 658 "rx"); 659 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 660 "tx"); 661 662 /* 663 * If only an RX channel is specified, the driver will 664 * attempt to use it bidirectionally, however if it is 665 * is specified but cannot be located, DMA will be disabled. 666 */ 667 if (dmae->rx_channel && !dmae->tx_channel) 668 dmae->tx_channel = dmae->rx_channel; 669 670 if (dmae->rx_channel) 671 rxname = dma_chan_name(dmae->rx_channel); 672 else 673 rxname = "none"; 674 675 if (dmae->tx_channel) 676 txname = dma_chan_name(dmae->tx_channel); 677 else 678 txname = "none"; 679 680 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 681 rxname, txname); 682 683 /* 684 * Limit the maximum segment size in any SG entry according to 685 * the parameters of the DMA engine device. 686 */ 687 if (dmae->tx_channel) { 688 struct device *dev = dmae->tx_channel->device->dev; 689 unsigned int max_seg_size = dma_get_max_seg_size(dev); 690 691 if (max_seg_size < host->mmc->max_seg_size) 692 host->mmc->max_seg_size = max_seg_size; 693 } 694 if (dmae->rx_channel) { 695 struct device *dev = dmae->rx_channel->device->dev; 696 unsigned int max_seg_size = dma_get_max_seg_size(dev); 697 698 if (max_seg_size < host->mmc->max_seg_size) 699 host->mmc->max_seg_size = max_seg_size; 700 } 701 702 if (!dmae->tx_channel || !dmae->rx_channel) { 703 mmci_dmae_release(host); 704 return -EINVAL; 705 } 706 707 return 0; 708 } 709 710 /* 711 * This is used in or so inline it 712 * so it can be discarded. 713 */ 714 void mmci_dmae_release(struct mmci_host *host) 715 { 716 struct mmci_dmae_priv *dmae = host->dma_priv; 717 718 if (dmae->rx_channel) 719 dma_release_channel(dmae->rx_channel); 720 if (dmae->tx_channel) 721 dma_release_channel(dmae->tx_channel); 722 dmae->rx_channel = dmae->tx_channel = NULL; 723 } 724 725 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 726 { 727 struct mmci_dmae_priv *dmae = host->dma_priv; 728 struct dma_chan *chan; 729 730 if (data->flags & MMC_DATA_READ) 731 chan = dmae->rx_channel; 732 else 733 chan = dmae->tx_channel; 734 735 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 736 mmc_get_dma_dir(data)); 737 } 738 739 void mmci_dmae_error(struct mmci_host *host) 740 { 741 struct mmci_dmae_priv *dmae = host->dma_priv; 742 743 if (!dma_inprogress(host)) 744 return; 745 746 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 747 dmaengine_terminate_all(dmae->cur); 748 host->dma_in_progress = false; 749 dmae->cur = NULL; 750 dmae->desc_current = NULL; 751 host->data->host_cookie = 0; 752 753 mmci_dma_unmap(host, host->data); 754 } 755 756 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 757 { 758 struct mmci_dmae_priv *dmae = host->dma_priv; 759 u32 status; 760 int i; 761 762 if (!dma_inprogress(host)) 763 return; 764 765 /* Wait up to 1ms for the DMA to complete */ 766 for (i = 0; ; i++) { 767 status = readl(host->base + MMCISTATUS); 768 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 769 break; 770 udelay(10); 771 } 772 773 /* 774 * Check to see whether we still have some data left in the FIFO - 775 * this catches DMA controllers which are unable to monitor the 776 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 777 * contiguous buffers. On TX, we'll get a FIFO underrun error. 778 */ 779 if (status & MCI_RXDATAAVLBLMASK) { 780 mmci_dma_error(host); 781 if (!data->error) 782 data->error = -EIO; 783 } else if (!data->host_cookie) { 784 mmci_dma_unmap(host, data); 785 } 786 787 /* 788 * Use of DMA with scatter-gather is impossible. 789 * Give up with DMA and switch back to PIO mode. 790 */ 791 if (status & MCI_RXDATAAVLBLMASK) { 792 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 793 mmci_dma_release(host); 794 } 795 796 host->dma_in_progress = false; 797 dmae->cur = NULL; 798 dmae->desc_current = NULL; 799 } 800 801 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 802 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 803 struct dma_chan **dma_chan, 804 struct dma_async_tx_descriptor **dma_desc) 805 { 806 struct mmci_dmae_priv *dmae = host->dma_priv; 807 struct variant_data *variant = host->variant; 808 struct dma_slave_config conf = { 809 .src_addr = host->phybase + MMCIFIFO, 810 .dst_addr = host->phybase + MMCIFIFO, 811 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 812 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 813 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 814 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 815 .device_fc = false, 816 }; 817 struct dma_chan *chan; 818 struct dma_device *device; 819 struct dma_async_tx_descriptor *desc; 820 int nr_sg; 821 unsigned long flags = DMA_CTRL_ACK; 822 823 if (data->flags & MMC_DATA_READ) { 824 conf.direction = DMA_DEV_TO_MEM; 825 chan = dmae->rx_channel; 826 } else { 827 conf.direction = DMA_MEM_TO_DEV; 828 chan = dmae->tx_channel; 829 } 830 831 /* If there's no DMA channel, fall back to PIO */ 832 if (!chan) 833 return -EINVAL; 834 835 /* If less than or equal to the fifo size, don't bother with DMA */ 836 if (data->blksz * data->blocks <= variant->fifosize) 837 return -EINVAL; 838 839 device = chan->device; 840 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 841 mmc_get_dma_dir(data)); 842 if (nr_sg == 0) 843 return -EINVAL; 844 845 if (host->variant->qcom_dml) 846 flags |= DMA_PREP_INTERRUPT; 847 848 dmaengine_slave_config(chan, &conf); 849 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 850 conf.direction, flags); 851 if (!desc) 852 goto unmap_exit; 853 854 *dma_chan = chan; 855 *dma_desc = desc; 856 857 return 0; 858 859 unmap_exit: 860 dma_unmap_sg(device->dev, data->sg, data->sg_len, 861 mmc_get_dma_dir(data)); 862 return -ENOMEM; 863 } 864 865 int mmci_dmae_prep_data(struct mmci_host *host, 866 struct mmc_data *data, 867 bool next) 868 { 869 struct mmci_dmae_priv *dmae = host->dma_priv; 870 struct mmci_dmae_next *nd = &dmae->next_data; 871 872 if (!host->use_dma) 873 return -EINVAL; 874 875 if (next) 876 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 877 /* Check if next job is already prepared. */ 878 if (dmae->cur && dmae->desc_current) 879 return 0; 880 881 /* No job were prepared thus do it now. */ 882 return _mmci_dmae_prep_data(host, data, &dmae->cur, 883 &dmae->desc_current); 884 } 885 886 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 887 { 888 struct mmci_dmae_priv *dmae = host->dma_priv; 889 struct mmc_data *data = host->data; 890 891 host->dma_in_progress = true; 892 dmaengine_submit(dmae->desc_current); 893 dma_async_issue_pending(dmae->cur); 894 895 if (host->variant->qcom_dml) 896 dml_start_xfer(host, data); 897 898 *datactrl |= MCI_DPSM_DMAENABLE; 899 900 return 0; 901 } 902 903 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 904 { 905 struct mmci_dmae_priv *dmae = host->dma_priv; 906 struct mmci_dmae_next *next = &dmae->next_data; 907 908 if (!host->use_dma) 909 return; 910 911 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 912 913 dmae->desc_current = next->desc; 914 dmae->cur = next->chan; 915 next->desc = NULL; 916 next->chan = NULL; 917 } 918 919 void mmci_dmae_unprep_data(struct mmci_host *host, 920 struct mmc_data *data, int err) 921 922 { 923 struct mmci_dmae_priv *dmae = host->dma_priv; 924 925 if (!host->use_dma) 926 return; 927 928 mmci_dma_unmap(host, data); 929 930 if (err) { 931 struct mmci_dmae_next *next = &dmae->next_data; 932 struct dma_chan *chan; 933 if (data->flags & MMC_DATA_READ) 934 chan = dmae->rx_channel; 935 else 936 chan = dmae->tx_channel; 937 dmaengine_terminate_all(chan); 938 939 if (dmae->desc_current == next->desc) 940 dmae->desc_current = NULL; 941 942 if (dmae->cur == next->chan) { 943 host->dma_in_progress = false; 944 dmae->cur = NULL; 945 } 946 947 next->desc = NULL; 948 next->chan = NULL; 949 } 950 } 951 952 static struct mmci_host_ops mmci_variant_ops = { 953 .prep_data = mmci_dmae_prep_data, 954 .unprep_data = mmci_dmae_unprep_data, 955 .get_next_data = mmci_dmae_get_next_data, 956 .dma_setup = mmci_dmae_setup, 957 .dma_release = mmci_dmae_release, 958 .dma_start = mmci_dmae_start, 959 .dma_finalize = mmci_dmae_finalize, 960 .dma_error = mmci_dmae_error, 961 }; 962 963 void mmci_variant_init(struct mmci_host *host) 964 { 965 host->ops = &mmci_variant_ops; 966 } 967 #endif 968 969 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 970 { 971 struct mmci_host *host = mmc_priv(mmc); 972 struct mmc_data *data = mrq->data; 973 974 if (!data) 975 return; 976 977 WARN_ON(data->host_cookie); 978 979 if (mmci_validate_data(host, data)) 980 return; 981 982 mmci_prep_data(host, data, true); 983 } 984 985 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 986 int err) 987 { 988 struct mmci_host *host = mmc_priv(mmc); 989 struct mmc_data *data = mrq->data; 990 991 if (!data || !data->host_cookie) 992 return; 993 994 mmci_unprep_data(host, data, err); 995 } 996 997 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 998 { 999 struct variant_data *variant = host->variant; 1000 unsigned int datactrl, timeout, irqmask; 1001 unsigned long long clks; 1002 void __iomem *base; 1003 int blksz_bits; 1004 1005 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1006 data->blksz, data->blocks, data->flags); 1007 1008 host->data = data; 1009 host->size = data->blksz * data->blocks; 1010 data->bytes_xfered = 0; 1011 1012 clks = (unsigned long long)data->timeout_ns * host->cclk; 1013 do_div(clks, NSEC_PER_SEC); 1014 1015 timeout = data->timeout_clks + (unsigned int)clks; 1016 1017 base = host->base; 1018 writel(timeout, base + MMCIDATATIMER); 1019 writel(host->size, base + MMCIDATALENGTH); 1020 1021 blksz_bits = ffs(data->blksz) - 1; 1022 BUG_ON(1 << blksz_bits != data->blksz); 1023 1024 if (variant->blksz_datactrl16) 1025 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16); 1026 else if (variant->blksz_datactrl4) 1027 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4); 1028 else 1029 datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; 1030 1031 if (data->flags & MMC_DATA_READ) 1032 datactrl |= MCI_DPSM_DIRECTION; 1033 1034 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1035 u32 clk; 1036 1037 datactrl |= variant->datactrl_mask_sdio; 1038 1039 /* 1040 * The ST Micro variant for SDIO small write transfers 1041 * needs to have clock H/W flow control disabled, 1042 * otherwise the transfer will not start. The threshold 1043 * depends on the rate of MCLK. 1044 */ 1045 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1046 (host->size < 8 || 1047 (host->size <= 8 && host->mclk > 50000000))) 1048 clk = host->clk_reg & ~variant->clkreg_enable; 1049 else 1050 clk = host->clk_reg | variant->clkreg_enable; 1051 1052 mmci_write_clkreg(host, clk); 1053 } 1054 1055 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1056 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1057 datactrl |= variant->datactrl_mask_ddrmode; 1058 1059 /* 1060 * Attempt to use DMA operation mode, if this 1061 * should fail, fall back to PIO mode 1062 */ 1063 if (!mmci_dma_start(host, datactrl)) 1064 return; 1065 1066 /* IRQ mode, map the SG list for CPU reading/writing */ 1067 mmci_init_sg(host, data); 1068 1069 if (data->flags & MMC_DATA_READ) { 1070 irqmask = MCI_RXFIFOHALFFULLMASK; 1071 1072 /* 1073 * If we have less than the fifo 'half-full' threshold to 1074 * transfer, trigger a PIO interrupt as soon as any data 1075 * is available. 1076 */ 1077 if (host->size < variant->fifohalfsize) 1078 irqmask |= MCI_RXDATAAVLBLMASK; 1079 } else { 1080 /* 1081 * We don't actually need to include "FIFO empty" here 1082 * since its implicit in "FIFO half empty". 1083 */ 1084 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1085 } 1086 1087 mmci_write_datactrlreg(host, datactrl); 1088 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1089 mmci_set_mask1(host, irqmask); 1090 } 1091 1092 static void 1093 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1094 { 1095 void __iomem *base = host->base; 1096 1097 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1098 cmd->opcode, cmd->arg, cmd->flags); 1099 1100 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1101 writel(0, base + MMCICOMMAND); 1102 mmci_reg_delay(host); 1103 } 1104 1105 if (host->variant->cmdreg_stop && 1106 cmd->opcode == MMC_STOP_TRANSMISSION) 1107 c |= host->variant->cmdreg_stop; 1108 1109 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1110 if (cmd->flags & MMC_RSP_PRESENT) { 1111 if (cmd->flags & MMC_RSP_136) 1112 c |= host->variant->cmdreg_lrsp_crc; 1113 else if (cmd->flags & MMC_RSP_CRC) 1114 c |= host->variant->cmdreg_srsp_crc; 1115 else 1116 c |= host->variant->cmdreg_srsp; 1117 } 1118 if (/*interrupt*/0) 1119 c |= MCI_CPSM_INTERRUPT; 1120 1121 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1122 c |= host->variant->data_cmd_enable; 1123 1124 host->cmd = cmd; 1125 1126 writel(cmd->arg, base + MMCIARGUMENT); 1127 writel(c, base + MMCICOMMAND); 1128 } 1129 1130 static void 1131 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1132 unsigned int status) 1133 { 1134 unsigned int status_err; 1135 1136 /* Make sure we have data to handle */ 1137 if (!data) 1138 return; 1139 1140 /* First check for errors */ 1141 status_err = status & (host->variant->start_err | 1142 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1143 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1144 1145 if (status_err) { 1146 u32 remain, success; 1147 1148 /* Terminate the DMA transfer */ 1149 mmci_dma_error(host); 1150 1151 /* 1152 * Calculate how far we are into the transfer. Note that 1153 * the data counter gives the number of bytes transferred 1154 * on the MMC bus, not on the host side. On reads, this 1155 * can be as much as a FIFO-worth of data ahead. This 1156 * matters for FIFO overruns only. 1157 */ 1158 if (!host->variant->datacnt_useless) { 1159 remain = readl(host->base + MMCIDATACNT); 1160 success = data->blksz * data->blocks - remain; 1161 } else { 1162 success = 0; 1163 } 1164 1165 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1166 status_err, success); 1167 if (status_err & MCI_DATACRCFAIL) { 1168 /* Last block was not successful */ 1169 success -= 1; 1170 data->error = -EILSEQ; 1171 } else if (status_err & MCI_DATATIMEOUT) { 1172 data->error = -ETIMEDOUT; 1173 } else if (status_err & MCI_STARTBITERR) { 1174 data->error = -ECOMM; 1175 } else if (status_err & MCI_TXUNDERRUN) { 1176 data->error = -EIO; 1177 } else if (status_err & MCI_RXOVERRUN) { 1178 if (success > host->variant->fifosize) 1179 success -= host->variant->fifosize; 1180 else 1181 success = 0; 1182 data->error = -EIO; 1183 } 1184 data->bytes_xfered = round_down(success, data->blksz); 1185 } 1186 1187 if (status & MCI_DATABLOCKEND) 1188 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1189 1190 if (status & MCI_DATAEND || data->error) { 1191 mmci_dma_finalize(host, data); 1192 1193 mmci_stop_data(host); 1194 1195 if (!data->error) 1196 /* The error clause is handled above, success! */ 1197 data->bytes_xfered = data->blksz * data->blocks; 1198 1199 if (!data->stop || (host->mrq->sbc && !data->error)) 1200 mmci_request_end(host, data->mrq); 1201 else 1202 mmci_start_command(host, data->stop, 0); 1203 } 1204 } 1205 1206 static void 1207 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1208 unsigned int status) 1209 { 1210 void __iomem *base = host->base; 1211 bool sbc; 1212 1213 if (!cmd) 1214 return; 1215 1216 sbc = (cmd == host->mrq->sbc); 1217 1218 /* 1219 * We need to be one of these interrupts to be considered worth 1220 * handling. Note that we tag on any latent IRQs postponed 1221 * due to waiting for busy status. 1222 */ 1223 if (!((status|host->busy_status) & 1224 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1225 return; 1226 1227 /* 1228 * ST Micro variant: handle busy detection. 1229 */ 1230 if (host->variant->busy_detect) { 1231 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1232 1233 /* We are busy with a command, return */ 1234 if (host->busy_status && 1235 (status & host->variant->busy_detect_flag)) 1236 return; 1237 1238 /* 1239 * We were not busy, but we now got a busy response on 1240 * something that was not an error, and we double-check 1241 * that the special busy status bit is still set before 1242 * proceeding. 1243 */ 1244 if (!host->busy_status && busy_resp && 1245 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1246 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1247 1248 /* Clear the busy start IRQ */ 1249 writel(host->variant->busy_detect_mask, 1250 host->base + MMCICLEAR); 1251 1252 /* Unmask the busy end IRQ */ 1253 writel(readl(base + MMCIMASK0) | 1254 host->variant->busy_detect_mask, 1255 base + MMCIMASK0); 1256 /* 1257 * Now cache the last response status code (until 1258 * the busy bit goes low), and return. 1259 */ 1260 host->busy_status = 1261 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1262 return; 1263 } 1264 1265 /* 1266 * At this point we are not busy with a command, we have 1267 * not received a new busy request, clear and mask the busy 1268 * end IRQ and fall through to process the IRQ. 1269 */ 1270 if (host->busy_status) { 1271 1272 writel(host->variant->busy_detect_mask, 1273 host->base + MMCICLEAR); 1274 1275 writel(readl(base + MMCIMASK0) & 1276 ~host->variant->busy_detect_mask, 1277 base + MMCIMASK0); 1278 host->busy_status = 0; 1279 } 1280 } 1281 1282 host->cmd = NULL; 1283 1284 if (status & MCI_CMDTIMEOUT) { 1285 cmd->error = -ETIMEDOUT; 1286 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1287 cmd->error = -EILSEQ; 1288 } else { 1289 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1290 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1291 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1292 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1293 } 1294 1295 if ((!sbc && !cmd->data) || cmd->error) { 1296 if (host->data) { 1297 /* Terminate the DMA transfer */ 1298 mmci_dma_error(host); 1299 1300 mmci_stop_data(host); 1301 } 1302 mmci_request_end(host, host->mrq); 1303 } else if (sbc) { 1304 mmci_start_command(host, host->mrq->cmd, 0); 1305 } else if (!host->variant->datactrl_first && 1306 !(cmd->data->flags & MMC_DATA_READ)) { 1307 mmci_start_data(host, cmd->data); 1308 } 1309 } 1310 1311 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1312 { 1313 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1314 } 1315 1316 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1317 { 1318 /* 1319 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1320 * from the fifo range should be used 1321 */ 1322 if (status & MCI_RXFIFOHALFFULL) 1323 return host->variant->fifohalfsize; 1324 else if (status & MCI_RXDATAAVLBL) 1325 return 4; 1326 1327 return 0; 1328 } 1329 1330 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1331 { 1332 void __iomem *base = host->base; 1333 char *ptr = buffer; 1334 u32 status = readl(host->base + MMCISTATUS); 1335 int host_remain = host->size; 1336 1337 do { 1338 int count = host->get_rx_fifocnt(host, status, host_remain); 1339 1340 if (count > remain) 1341 count = remain; 1342 1343 if (count <= 0) 1344 break; 1345 1346 /* 1347 * SDIO especially may want to send something that is 1348 * not divisible by 4 (as opposed to card sectors 1349 * etc). Therefore make sure to always read the last bytes 1350 * while only doing full 32-bit reads towards the FIFO. 1351 */ 1352 if (unlikely(count & 0x3)) { 1353 if (count < 4) { 1354 unsigned char buf[4]; 1355 ioread32_rep(base + MMCIFIFO, buf, 1); 1356 memcpy(ptr, buf, count); 1357 } else { 1358 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1359 count &= ~0x3; 1360 } 1361 } else { 1362 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1363 } 1364 1365 ptr += count; 1366 remain -= count; 1367 host_remain -= count; 1368 1369 if (remain == 0) 1370 break; 1371 1372 status = readl(base + MMCISTATUS); 1373 } while (status & MCI_RXDATAAVLBL); 1374 1375 return ptr - buffer; 1376 } 1377 1378 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1379 { 1380 struct variant_data *variant = host->variant; 1381 void __iomem *base = host->base; 1382 char *ptr = buffer; 1383 1384 do { 1385 unsigned int count, maxcnt; 1386 1387 maxcnt = status & MCI_TXFIFOEMPTY ? 1388 variant->fifosize : variant->fifohalfsize; 1389 count = min(remain, maxcnt); 1390 1391 /* 1392 * SDIO especially may want to send something that is 1393 * not divisible by 4 (as opposed to card sectors 1394 * etc), and the FIFO only accept full 32-bit writes. 1395 * So compensate by adding +3 on the count, a single 1396 * byte become a 32bit write, 7 bytes will be two 1397 * 32bit writes etc. 1398 */ 1399 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1400 1401 ptr += count; 1402 remain -= count; 1403 1404 if (remain == 0) 1405 break; 1406 1407 status = readl(base + MMCISTATUS); 1408 } while (status & MCI_TXFIFOHALFEMPTY); 1409 1410 return ptr - buffer; 1411 } 1412 1413 /* 1414 * PIO data transfer IRQ handler. 1415 */ 1416 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1417 { 1418 struct mmci_host *host = dev_id; 1419 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1420 struct variant_data *variant = host->variant; 1421 void __iomem *base = host->base; 1422 u32 status; 1423 1424 status = readl(base + MMCISTATUS); 1425 1426 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1427 1428 do { 1429 unsigned int remain, len; 1430 char *buffer; 1431 1432 /* 1433 * For write, we only need to test the half-empty flag 1434 * here - if the FIFO is completely empty, then by 1435 * definition it is more than half empty. 1436 * 1437 * For read, check for data available. 1438 */ 1439 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1440 break; 1441 1442 if (!sg_miter_next(sg_miter)) 1443 break; 1444 1445 buffer = sg_miter->addr; 1446 remain = sg_miter->length; 1447 1448 len = 0; 1449 if (status & MCI_RXACTIVE) 1450 len = mmci_pio_read(host, buffer, remain); 1451 if (status & MCI_TXACTIVE) 1452 len = mmci_pio_write(host, buffer, remain, status); 1453 1454 sg_miter->consumed = len; 1455 1456 host->size -= len; 1457 remain -= len; 1458 1459 if (remain) 1460 break; 1461 1462 status = readl(base + MMCISTATUS); 1463 } while (1); 1464 1465 sg_miter_stop(sg_miter); 1466 1467 /* 1468 * If we have less than the fifo 'half-full' threshold to transfer, 1469 * trigger a PIO interrupt as soon as any data is available. 1470 */ 1471 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1472 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1473 1474 /* 1475 * If we run out of data, disable the data IRQs; this 1476 * prevents a race where the FIFO becomes empty before 1477 * the chip itself has disabled the data path, and 1478 * stops us racing with our data end IRQ. 1479 */ 1480 if (host->size == 0) { 1481 mmci_set_mask1(host, 0); 1482 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1483 } 1484 1485 return IRQ_HANDLED; 1486 } 1487 1488 /* 1489 * Handle completion of command and data transfers. 1490 */ 1491 static irqreturn_t mmci_irq(int irq, void *dev_id) 1492 { 1493 struct mmci_host *host = dev_id; 1494 u32 status; 1495 int ret = 0; 1496 1497 spin_lock(&host->lock); 1498 1499 do { 1500 status = readl(host->base + MMCISTATUS); 1501 1502 if (host->singleirq) { 1503 if (status & host->mask1_reg) 1504 mmci_pio_irq(irq, dev_id); 1505 1506 status &= ~host->variant->irq_pio_mask; 1507 } 1508 1509 /* 1510 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1511 * enabled) in mmci_cmd_irq() function where ST Micro busy 1512 * detection variant is handled. Considering the HW seems to be 1513 * triggering the IRQ on both edges while monitoring DAT0 for 1514 * busy completion and that same status bit is used to monitor 1515 * start and end of busy detection, special care must be taken 1516 * to make sure that both start and end interrupts are always 1517 * cleared one after the other. 1518 */ 1519 status &= readl(host->base + MMCIMASK0); 1520 if (host->variant->busy_detect) 1521 writel(status & ~host->variant->busy_detect_mask, 1522 host->base + MMCICLEAR); 1523 else 1524 writel(status, host->base + MMCICLEAR); 1525 1526 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1527 1528 if (host->variant->reversed_irq_handling) { 1529 mmci_data_irq(host, host->data, status); 1530 mmci_cmd_irq(host, host->cmd, status); 1531 } else { 1532 mmci_cmd_irq(host, host->cmd, status); 1533 mmci_data_irq(host, host->data, status); 1534 } 1535 1536 /* 1537 * Don't poll for busy completion in irq context. 1538 */ 1539 if (host->variant->busy_detect && host->busy_status) 1540 status &= ~host->variant->busy_detect_flag; 1541 1542 ret = 1; 1543 } while (status); 1544 1545 spin_unlock(&host->lock); 1546 1547 return IRQ_RETVAL(ret); 1548 } 1549 1550 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1551 { 1552 struct mmci_host *host = mmc_priv(mmc); 1553 unsigned long flags; 1554 1555 WARN_ON(host->mrq != NULL); 1556 1557 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1558 if (mrq->cmd->error) { 1559 mmc_request_done(mmc, mrq); 1560 return; 1561 } 1562 1563 spin_lock_irqsave(&host->lock, flags); 1564 1565 host->mrq = mrq; 1566 1567 if (mrq->data) 1568 mmci_get_next_data(host, mrq->data); 1569 1570 if (mrq->data && 1571 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1572 mmci_start_data(host, mrq->data); 1573 1574 if (mrq->sbc) 1575 mmci_start_command(host, mrq->sbc, 0); 1576 else 1577 mmci_start_command(host, mrq->cmd, 0); 1578 1579 spin_unlock_irqrestore(&host->lock, flags); 1580 } 1581 1582 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1583 { 1584 struct mmci_host *host = mmc_priv(mmc); 1585 struct variant_data *variant = host->variant; 1586 u32 pwr = 0; 1587 unsigned long flags; 1588 int ret; 1589 1590 if (host->plat->ios_handler && 1591 host->plat->ios_handler(mmc_dev(mmc), ios)) 1592 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1593 1594 switch (ios->power_mode) { 1595 case MMC_POWER_OFF: 1596 if (!IS_ERR(mmc->supply.vmmc)) 1597 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1598 1599 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1600 regulator_disable(mmc->supply.vqmmc); 1601 host->vqmmc_enabled = false; 1602 } 1603 1604 break; 1605 case MMC_POWER_UP: 1606 if (!IS_ERR(mmc->supply.vmmc)) 1607 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1608 1609 /* 1610 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1611 * and instead uses MCI_PWR_ON so apply whatever value is 1612 * configured in the variant data. 1613 */ 1614 pwr |= variant->pwrreg_powerup; 1615 1616 break; 1617 case MMC_POWER_ON: 1618 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1619 ret = regulator_enable(mmc->supply.vqmmc); 1620 if (ret < 0) 1621 dev_err(mmc_dev(mmc), 1622 "failed to enable vqmmc regulator\n"); 1623 else 1624 host->vqmmc_enabled = true; 1625 } 1626 1627 pwr |= MCI_PWR_ON; 1628 break; 1629 } 1630 1631 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1632 /* 1633 * The ST Micro variant has some additional bits 1634 * indicating signal direction for the signals in 1635 * the SD/MMC bus and feedback-clock usage. 1636 */ 1637 pwr |= host->pwr_reg_add; 1638 1639 if (ios->bus_width == MMC_BUS_WIDTH_4) 1640 pwr &= ~MCI_ST_DATA74DIREN; 1641 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1642 pwr &= (~MCI_ST_DATA74DIREN & 1643 ~MCI_ST_DATA31DIREN & 1644 ~MCI_ST_DATA2DIREN); 1645 } 1646 1647 if (variant->opendrain) { 1648 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1649 pwr |= variant->opendrain; 1650 } else { 1651 /* 1652 * If the variant cannot configure the pads by its own, then we 1653 * expect the pinctrl to be able to do that for us 1654 */ 1655 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1656 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1657 else 1658 pinctrl_select_state(host->pinctrl, host->pins_default); 1659 } 1660 1661 /* 1662 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1663 * gating the clock, the MCI_PWR_ON bit is cleared. 1664 */ 1665 if (!ios->clock && variant->pwrreg_clkgate) 1666 pwr &= ~MCI_PWR_ON; 1667 1668 if (host->variant->explicit_mclk_control && 1669 ios->clock != host->clock_cache) { 1670 ret = clk_set_rate(host->clk, ios->clock); 1671 if (ret < 0) 1672 dev_err(mmc_dev(host->mmc), 1673 "Error setting clock rate (%d)\n", ret); 1674 else 1675 host->mclk = clk_get_rate(host->clk); 1676 } 1677 host->clock_cache = ios->clock; 1678 1679 spin_lock_irqsave(&host->lock, flags); 1680 1681 if (host->ops && host->ops->set_clkreg) 1682 host->ops->set_clkreg(host, ios->clock); 1683 else 1684 mmci_set_clkreg(host, ios->clock); 1685 1686 if (host->ops && host->ops->set_pwrreg) 1687 host->ops->set_pwrreg(host, pwr); 1688 else 1689 mmci_write_pwrreg(host, pwr); 1690 1691 mmci_reg_delay(host); 1692 1693 spin_unlock_irqrestore(&host->lock, flags); 1694 } 1695 1696 static int mmci_get_cd(struct mmc_host *mmc) 1697 { 1698 struct mmci_host *host = mmc_priv(mmc); 1699 struct mmci_platform_data *plat = host->plat; 1700 unsigned int status = mmc_gpio_get_cd(mmc); 1701 1702 if (status == -ENOSYS) { 1703 if (!plat->status) 1704 return 1; /* Assume always present */ 1705 1706 status = plat->status(mmc_dev(host->mmc)); 1707 } 1708 return status; 1709 } 1710 1711 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1712 { 1713 int ret = 0; 1714 1715 if (!IS_ERR(mmc->supply.vqmmc)) { 1716 1717 switch (ios->signal_voltage) { 1718 case MMC_SIGNAL_VOLTAGE_330: 1719 ret = regulator_set_voltage(mmc->supply.vqmmc, 1720 2700000, 3600000); 1721 break; 1722 case MMC_SIGNAL_VOLTAGE_180: 1723 ret = regulator_set_voltage(mmc->supply.vqmmc, 1724 1700000, 1950000); 1725 break; 1726 case MMC_SIGNAL_VOLTAGE_120: 1727 ret = regulator_set_voltage(mmc->supply.vqmmc, 1728 1100000, 1300000); 1729 break; 1730 } 1731 1732 if (ret) 1733 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1734 } 1735 1736 return ret; 1737 } 1738 1739 static struct mmc_host_ops mmci_ops = { 1740 .request = mmci_request, 1741 .pre_req = mmci_pre_request, 1742 .post_req = mmci_post_request, 1743 .set_ios = mmci_set_ios, 1744 .get_ro = mmc_gpio_get_ro, 1745 .get_cd = mmci_get_cd, 1746 .start_signal_voltage_switch = mmci_sig_volt_switch, 1747 }; 1748 1749 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1750 { 1751 struct mmci_host *host = mmc_priv(mmc); 1752 int ret = mmc_of_parse(mmc); 1753 1754 if (ret) 1755 return ret; 1756 1757 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1758 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1759 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1760 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1761 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1762 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1763 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1764 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1765 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1766 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1767 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1768 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1769 if (of_get_property(np, "st,sig-dir", NULL)) 1770 host->pwr_reg_add |= MCI_STM32_DIRPOL; 1771 if (of_get_property(np, "st,neg-edge", NULL)) 1772 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 1773 if (of_get_property(np, "st,use-ckin", NULL)) 1774 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1775 1776 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1777 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1778 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1779 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1780 1781 return 0; 1782 } 1783 1784 static int mmci_probe(struct amba_device *dev, 1785 const struct amba_id *id) 1786 { 1787 struct mmci_platform_data *plat = dev->dev.platform_data; 1788 struct device_node *np = dev->dev.of_node; 1789 struct variant_data *variant = id->data; 1790 struct mmci_host *host; 1791 struct mmc_host *mmc; 1792 int ret; 1793 1794 /* Must have platform data or Device Tree. */ 1795 if (!plat && !np) { 1796 dev_err(&dev->dev, "No plat data or DT found\n"); 1797 return -EINVAL; 1798 } 1799 1800 if (!plat) { 1801 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1802 if (!plat) 1803 return -ENOMEM; 1804 } 1805 1806 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1807 if (!mmc) 1808 return -ENOMEM; 1809 1810 ret = mmci_of_parse(np, mmc); 1811 if (ret) 1812 goto host_free; 1813 1814 host = mmc_priv(mmc); 1815 host->mmc = mmc; 1816 1817 /* 1818 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1819 * pins can be set accordingly using pinctrl 1820 */ 1821 if (!variant->opendrain) { 1822 host->pinctrl = devm_pinctrl_get(&dev->dev); 1823 if (IS_ERR(host->pinctrl)) { 1824 dev_err(&dev->dev, "failed to get pinctrl"); 1825 ret = PTR_ERR(host->pinctrl); 1826 goto host_free; 1827 } 1828 1829 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1830 PINCTRL_STATE_DEFAULT); 1831 if (IS_ERR(host->pins_default)) { 1832 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1833 ret = PTR_ERR(host->pins_default); 1834 goto host_free; 1835 } 1836 1837 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1838 MMCI_PINCTRL_STATE_OPENDRAIN); 1839 if (IS_ERR(host->pins_opendrain)) { 1840 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1841 ret = PTR_ERR(host->pins_opendrain); 1842 goto host_free; 1843 } 1844 } 1845 1846 host->hw_designer = amba_manf(dev); 1847 host->hw_revision = amba_rev(dev); 1848 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1849 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1850 1851 host->clk = devm_clk_get(&dev->dev, NULL); 1852 if (IS_ERR(host->clk)) { 1853 ret = PTR_ERR(host->clk); 1854 goto host_free; 1855 } 1856 1857 ret = clk_prepare_enable(host->clk); 1858 if (ret) 1859 goto host_free; 1860 1861 if (variant->qcom_fifo) 1862 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1863 else 1864 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1865 1866 host->plat = plat; 1867 host->variant = variant; 1868 host->mclk = clk_get_rate(host->clk); 1869 /* 1870 * According to the spec, mclk is max 100 MHz, 1871 * so we try to adjust the clock down to this, 1872 * (if possible). 1873 */ 1874 if (host->mclk > variant->f_max) { 1875 ret = clk_set_rate(host->clk, variant->f_max); 1876 if (ret < 0) 1877 goto clk_disable; 1878 host->mclk = clk_get_rate(host->clk); 1879 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1880 host->mclk); 1881 } 1882 1883 host->phybase = dev->res.start; 1884 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1885 if (IS_ERR(host->base)) { 1886 ret = PTR_ERR(host->base); 1887 goto clk_disable; 1888 } 1889 1890 if (variant->init) 1891 variant->init(host); 1892 1893 /* 1894 * The ARM and ST versions of the block have slightly different 1895 * clock divider equations which means that the minimum divider 1896 * differs too. 1897 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1898 */ 1899 if (variant->st_clkdiv) 1900 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1901 else if (variant->stm32_clkdiv) 1902 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 1903 else if (variant->explicit_mclk_control) 1904 mmc->f_min = clk_round_rate(host->clk, 100000); 1905 else 1906 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1907 /* 1908 * If no maximum operating frequency is supplied, fall back to use 1909 * the module parameter, which has a (low) default value in case it 1910 * is not specified. Either value must not exceed the clock rate into 1911 * the block, of course. 1912 */ 1913 if (mmc->f_max) 1914 mmc->f_max = variant->explicit_mclk_control ? 1915 min(variant->f_max, mmc->f_max) : 1916 min(host->mclk, mmc->f_max); 1917 else 1918 mmc->f_max = variant->explicit_mclk_control ? 1919 fmax : min(host->mclk, fmax); 1920 1921 1922 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1923 1924 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 1925 if (IS_ERR(host->rst)) { 1926 ret = PTR_ERR(host->rst); 1927 goto clk_disable; 1928 } 1929 1930 /* Get regulators and the supported OCR mask */ 1931 ret = mmc_regulator_get_supply(mmc); 1932 if (ret) 1933 goto clk_disable; 1934 1935 if (!mmc->ocr_avail) 1936 mmc->ocr_avail = plat->ocr_mask; 1937 else if (plat->ocr_mask) 1938 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1939 1940 /* We support these capabilities. */ 1941 mmc->caps |= MMC_CAP_CMD23; 1942 1943 /* 1944 * Enable busy detection. 1945 */ 1946 if (variant->busy_detect) { 1947 mmci_ops.card_busy = mmci_card_busy; 1948 /* 1949 * Not all variants have a flag to enable busy detection 1950 * in the DPSM, but if they do, set it here. 1951 */ 1952 if (variant->busy_dpsm_flag) 1953 mmci_write_datactrlreg(host, 1954 host->variant->busy_dpsm_flag); 1955 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1956 mmc->max_busy_timeout = 0; 1957 } 1958 1959 mmc->ops = &mmci_ops; 1960 1961 /* We support these PM capabilities. */ 1962 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1963 1964 /* 1965 * We can do SGIO 1966 */ 1967 mmc->max_segs = NR_SG; 1968 1969 /* 1970 * Since only a certain number of bits are valid in the data length 1971 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1972 * single request. 1973 */ 1974 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1975 1976 /* 1977 * Set the maximum segment size. Since we aren't doing DMA 1978 * (yet) we are only limited by the data length register. 1979 */ 1980 mmc->max_seg_size = mmc->max_req_size; 1981 1982 /* 1983 * Block size can be up to 2048 bytes, but must be a power of two. 1984 */ 1985 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 1986 1987 /* 1988 * Limit the number of blocks transferred so that we don't overflow 1989 * the maximum request size. 1990 */ 1991 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 1992 1993 spin_lock_init(&host->lock); 1994 1995 writel(0, host->base + MMCIMASK0); 1996 1997 if (variant->mmcimask1) 1998 writel(0, host->base + MMCIMASK1); 1999 2000 writel(0xfff, host->base + MMCICLEAR); 2001 2002 /* 2003 * If: 2004 * - not using DT but using a descriptor table, or 2005 * - using a table of descriptors ALONGSIDE DT, or 2006 * look up these descriptors named "cd" and "wp" right here, fail 2007 * silently of these do not exist 2008 */ 2009 if (!np) { 2010 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 2011 if (ret == -EPROBE_DEFER) 2012 goto clk_disable; 2013 2014 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 2015 if (ret == -EPROBE_DEFER) 2016 goto clk_disable; 2017 } 2018 2019 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 2020 DRIVER_NAME " (cmd)", host); 2021 if (ret) 2022 goto clk_disable; 2023 2024 if (!dev->irq[1]) 2025 host->singleirq = true; 2026 else { 2027 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2028 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2029 if (ret) 2030 goto clk_disable; 2031 } 2032 2033 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2034 2035 amba_set_drvdata(dev, mmc); 2036 2037 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2038 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2039 amba_rev(dev), (unsigned long long)dev->res.start, 2040 dev->irq[0], dev->irq[1]); 2041 2042 mmci_dma_setup(host); 2043 2044 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2045 pm_runtime_use_autosuspend(&dev->dev); 2046 2047 mmc_add_host(mmc); 2048 2049 pm_runtime_put(&dev->dev); 2050 return 0; 2051 2052 clk_disable: 2053 clk_disable_unprepare(host->clk); 2054 host_free: 2055 mmc_free_host(mmc); 2056 return ret; 2057 } 2058 2059 static int mmci_remove(struct amba_device *dev) 2060 { 2061 struct mmc_host *mmc = amba_get_drvdata(dev); 2062 2063 if (mmc) { 2064 struct mmci_host *host = mmc_priv(mmc); 2065 struct variant_data *variant = host->variant; 2066 2067 /* 2068 * Undo pm_runtime_put() in probe. We use the _sync 2069 * version here so that we can access the primecell. 2070 */ 2071 pm_runtime_get_sync(&dev->dev); 2072 2073 mmc_remove_host(mmc); 2074 2075 writel(0, host->base + MMCIMASK0); 2076 2077 if (variant->mmcimask1) 2078 writel(0, host->base + MMCIMASK1); 2079 2080 writel(0, host->base + MMCICOMMAND); 2081 writel(0, host->base + MMCIDATACTRL); 2082 2083 mmci_dma_release(host); 2084 clk_disable_unprepare(host->clk); 2085 mmc_free_host(mmc); 2086 } 2087 2088 return 0; 2089 } 2090 2091 #ifdef CONFIG_PM 2092 static void mmci_save(struct mmci_host *host) 2093 { 2094 unsigned long flags; 2095 2096 spin_lock_irqsave(&host->lock, flags); 2097 2098 writel(0, host->base + MMCIMASK0); 2099 if (host->variant->pwrreg_nopower) { 2100 writel(0, host->base + MMCIDATACTRL); 2101 writel(0, host->base + MMCIPOWER); 2102 writel(0, host->base + MMCICLOCK); 2103 } 2104 mmci_reg_delay(host); 2105 2106 spin_unlock_irqrestore(&host->lock, flags); 2107 } 2108 2109 static void mmci_restore(struct mmci_host *host) 2110 { 2111 unsigned long flags; 2112 2113 spin_lock_irqsave(&host->lock, flags); 2114 2115 if (host->variant->pwrreg_nopower) { 2116 writel(host->clk_reg, host->base + MMCICLOCK); 2117 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2118 writel(host->pwr_reg, host->base + MMCIPOWER); 2119 } 2120 writel(MCI_IRQENABLE | host->variant->start_err, 2121 host->base + MMCIMASK0); 2122 mmci_reg_delay(host); 2123 2124 spin_unlock_irqrestore(&host->lock, flags); 2125 } 2126 2127 static int mmci_runtime_suspend(struct device *dev) 2128 { 2129 struct amba_device *adev = to_amba_device(dev); 2130 struct mmc_host *mmc = amba_get_drvdata(adev); 2131 2132 if (mmc) { 2133 struct mmci_host *host = mmc_priv(mmc); 2134 pinctrl_pm_select_sleep_state(dev); 2135 mmci_save(host); 2136 clk_disable_unprepare(host->clk); 2137 } 2138 2139 return 0; 2140 } 2141 2142 static int mmci_runtime_resume(struct device *dev) 2143 { 2144 struct amba_device *adev = to_amba_device(dev); 2145 struct mmc_host *mmc = amba_get_drvdata(adev); 2146 2147 if (mmc) { 2148 struct mmci_host *host = mmc_priv(mmc); 2149 clk_prepare_enable(host->clk); 2150 mmci_restore(host); 2151 pinctrl_pm_select_default_state(dev); 2152 } 2153 2154 return 0; 2155 } 2156 #endif 2157 2158 static const struct dev_pm_ops mmci_dev_pm_ops = { 2159 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2160 pm_runtime_force_resume) 2161 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2162 }; 2163 2164 static const struct amba_id mmci_ids[] = { 2165 { 2166 .id = 0x00041180, 2167 .mask = 0xff0fffff, 2168 .data = &variant_arm, 2169 }, 2170 { 2171 .id = 0x01041180, 2172 .mask = 0xff0fffff, 2173 .data = &variant_arm_extended_fifo, 2174 }, 2175 { 2176 .id = 0x02041180, 2177 .mask = 0xff0fffff, 2178 .data = &variant_arm_extended_fifo_hwfc, 2179 }, 2180 { 2181 .id = 0x00041181, 2182 .mask = 0x000fffff, 2183 .data = &variant_arm, 2184 }, 2185 /* ST Micro variants */ 2186 { 2187 .id = 0x00180180, 2188 .mask = 0x00ffffff, 2189 .data = &variant_u300, 2190 }, 2191 { 2192 .id = 0x10180180, 2193 .mask = 0xf0ffffff, 2194 .data = &variant_nomadik, 2195 }, 2196 { 2197 .id = 0x00280180, 2198 .mask = 0x00ffffff, 2199 .data = &variant_nomadik, 2200 }, 2201 { 2202 .id = 0x00480180, 2203 .mask = 0xf0ffffff, 2204 .data = &variant_ux500, 2205 }, 2206 { 2207 .id = 0x10480180, 2208 .mask = 0xf0ffffff, 2209 .data = &variant_ux500v2, 2210 }, 2211 { 2212 .id = 0x00880180, 2213 .mask = 0x00ffffff, 2214 .data = &variant_stm32, 2215 }, 2216 { 2217 .id = 0x10153180, 2218 .mask = 0xf0ffffff, 2219 .data = &variant_stm32_sdmmc, 2220 }, 2221 /* Qualcomm variants */ 2222 { 2223 .id = 0x00051180, 2224 .mask = 0x000fffff, 2225 .data = &variant_qcom, 2226 }, 2227 { 0, 0 }, 2228 }; 2229 2230 MODULE_DEVICE_TABLE(amba, mmci_ids); 2231 2232 static struct amba_driver mmci_driver = { 2233 .drv = { 2234 .name = DRIVER_NAME, 2235 .pm = &mmci_dev_pm_ops, 2236 }, 2237 .probe = mmci_probe, 2238 .remove = mmci_remove, 2239 .id_table = mmci_ids, 2240 }; 2241 2242 module_amba_driver(mmci_driver); 2243 2244 module_param(fmax, uint, 0444); 2245 2246 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2247 MODULE_LICENSE("GPL"); 2248