1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/slot-gpio.h> 26 #include <linux/amba/bus.h> 27 #include <linux/clk.h> 28 #include <linux/scatterlist.h> 29 #include <linux/of.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/dmaengine.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/amba/mmci.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/types.h> 36 #include <linux/pinctrl/consumer.h> 37 #include <linux/reset.h> 38 39 #include <asm/div64.h> 40 #include <asm/io.h> 41 42 #include "mmci.h" 43 44 #define DRIVER_NAME "mmci-pl18x" 45 46 static void mmci_variant_init(struct mmci_host *host); 47 static void ux500v2_variant_init(struct mmci_host *host); 48 49 static unsigned int fmax = 515633; 50 51 static struct variant_data variant_arm = { 52 .fifosize = 16 * 4, 53 .fifohalfsize = 8 * 4, 54 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 55 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 56 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 57 .cmdreg_srsp = MCI_CPSM_RESPONSE, 58 .datalength_bits = 16, 59 .datactrl_blocksz = 11, 60 .pwrreg_powerup = MCI_PWR_UP, 61 .f_max = 100000000, 62 .reversed_irq_handling = true, 63 .mmcimask1 = true, 64 .irq_pio_mask = MCI_IRQ_PIO_MASK, 65 .start_err = MCI_STARTBITERR, 66 .opendrain = MCI_ROD, 67 .init = mmci_variant_init, 68 }; 69 70 static struct variant_data variant_arm_extended_fifo = { 71 .fifosize = 128 * 4, 72 .fifohalfsize = 64 * 4, 73 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 74 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 75 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 76 .cmdreg_srsp = MCI_CPSM_RESPONSE, 77 .datalength_bits = 16, 78 .datactrl_blocksz = 11, 79 .pwrreg_powerup = MCI_PWR_UP, 80 .f_max = 100000000, 81 .mmcimask1 = true, 82 .irq_pio_mask = MCI_IRQ_PIO_MASK, 83 .start_err = MCI_STARTBITERR, 84 .opendrain = MCI_ROD, 85 .init = mmci_variant_init, 86 }; 87 88 static struct variant_data variant_arm_extended_fifo_hwfc = { 89 .fifosize = 128 * 4, 90 .fifohalfsize = 64 * 4, 91 .clkreg_enable = MCI_ARM_HWFCEN, 92 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 93 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 94 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 95 .cmdreg_srsp = MCI_CPSM_RESPONSE, 96 .datalength_bits = 16, 97 .datactrl_blocksz = 11, 98 .pwrreg_powerup = MCI_PWR_UP, 99 .f_max = 100000000, 100 .mmcimask1 = true, 101 .irq_pio_mask = MCI_IRQ_PIO_MASK, 102 .start_err = MCI_STARTBITERR, 103 .opendrain = MCI_ROD, 104 .init = mmci_variant_init, 105 }; 106 107 static struct variant_data variant_u300 = { 108 .fifosize = 16 * 4, 109 .fifohalfsize = 8 * 4, 110 .clkreg_enable = MCI_ST_U300_HWFCEN, 111 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 112 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 113 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 114 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 115 .cmdreg_srsp = MCI_CPSM_RESPONSE, 116 .datalength_bits = 16, 117 .datactrl_blocksz = 11, 118 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 119 .st_sdio = true, 120 .pwrreg_powerup = MCI_PWR_ON, 121 .f_max = 100000000, 122 .signal_direction = true, 123 .pwrreg_clkgate = true, 124 .pwrreg_nopower = true, 125 .mmcimask1 = true, 126 .irq_pio_mask = MCI_IRQ_PIO_MASK, 127 .start_err = MCI_STARTBITERR, 128 .opendrain = MCI_OD, 129 .init = mmci_variant_init, 130 }; 131 132 static struct variant_data variant_nomadik = { 133 .fifosize = 16 * 4, 134 .fifohalfsize = 8 * 4, 135 .clkreg = MCI_CLK_ENABLE, 136 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 137 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 138 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 139 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 140 .cmdreg_srsp = MCI_CPSM_RESPONSE, 141 .datalength_bits = 24, 142 .datactrl_blocksz = 11, 143 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 144 .st_sdio = true, 145 .st_clkdiv = true, 146 .pwrreg_powerup = MCI_PWR_ON, 147 .f_max = 100000000, 148 .signal_direction = true, 149 .pwrreg_clkgate = true, 150 .pwrreg_nopower = true, 151 .mmcimask1 = true, 152 .irq_pio_mask = MCI_IRQ_PIO_MASK, 153 .start_err = MCI_STARTBITERR, 154 .opendrain = MCI_OD, 155 .init = mmci_variant_init, 156 }; 157 158 static struct variant_data variant_ux500 = { 159 .fifosize = 30 * 4, 160 .fifohalfsize = 8 * 4, 161 .clkreg = MCI_CLK_ENABLE, 162 .clkreg_enable = MCI_ST_UX500_HWFCEN, 163 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 164 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 165 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 166 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 167 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 168 .cmdreg_srsp = MCI_CPSM_RESPONSE, 169 .datalength_bits = 24, 170 .datactrl_blocksz = 11, 171 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 172 .st_sdio = true, 173 .st_clkdiv = true, 174 .pwrreg_powerup = MCI_PWR_ON, 175 .f_max = 100000000, 176 .signal_direction = true, 177 .pwrreg_clkgate = true, 178 .busy_detect = true, 179 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 180 .busy_detect_flag = MCI_ST_CARDBUSY, 181 .busy_detect_mask = MCI_ST_BUSYENDMASK, 182 .pwrreg_nopower = true, 183 .mmcimask1 = true, 184 .irq_pio_mask = MCI_IRQ_PIO_MASK, 185 .start_err = MCI_STARTBITERR, 186 .opendrain = MCI_OD, 187 .init = mmci_variant_init, 188 }; 189 190 static struct variant_data variant_ux500v2 = { 191 .fifosize = 30 * 4, 192 .fifohalfsize = 8 * 4, 193 .clkreg = MCI_CLK_ENABLE, 194 .clkreg_enable = MCI_ST_UX500_HWFCEN, 195 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 196 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 197 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 198 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 199 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 200 .cmdreg_srsp = MCI_CPSM_RESPONSE, 201 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 202 .datalength_bits = 24, 203 .datactrl_blocksz = 11, 204 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 205 .st_sdio = true, 206 .st_clkdiv = true, 207 .pwrreg_powerup = MCI_PWR_ON, 208 .f_max = 100000000, 209 .signal_direction = true, 210 .pwrreg_clkgate = true, 211 .busy_detect = true, 212 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 213 .busy_detect_flag = MCI_ST_CARDBUSY, 214 .busy_detect_mask = MCI_ST_BUSYENDMASK, 215 .pwrreg_nopower = true, 216 .mmcimask1 = true, 217 .irq_pio_mask = MCI_IRQ_PIO_MASK, 218 .start_err = MCI_STARTBITERR, 219 .opendrain = MCI_OD, 220 .init = ux500v2_variant_init, 221 }; 222 223 static struct variant_data variant_stm32 = { 224 .fifosize = 32 * 4, 225 .fifohalfsize = 8 * 4, 226 .clkreg = MCI_CLK_ENABLE, 227 .clkreg_enable = MCI_ST_UX500_HWFCEN, 228 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 229 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 230 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 231 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 232 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 233 .cmdreg_srsp = MCI_CPSM_RESPONSE, 234 .irq_pio_mask = MCI_IRQ_PIO_MASK, 235 .datalength_bits = 24, 236 .datactrl_blocksz = 11, 237 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 238 .st_sdio = true, 239 .st_clkdiv = true, 240 .pwrreg_powerup = MCI_PWR_ON, 241 .f_max = 48000000, 242 .pwrreg_clkgate = true, 243 .pwrreg_nopower = true, 244 .init = mmci_variant_init, 245 }; 246 247 static struct variant_data variant_stm32_sdmmc = { 248 .fifosize = 16 * 4, 249 .fifohalfsize = 8 * 4, 250 .f_max = 208000000, 251 .stm32_clkdiv = true, 252 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 253 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 254 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 255 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 256 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 257 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 258 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 259 .datactrl_first = true, 260 .datacnt_useless = true, 261 .datalength_bits = 25, 262 .datactrl_blocksz = 14, 263 .stm32_idmabsize_mask = GENMASK(12, 5), 264 .init = sdmmc_variant_init, 265 }; 266 267 static struct variant_data variant_qcom = { 268 .fifosize = 16 * 4, 269 .fifohalfsize = 8 * 4, 270 .clkreg = MCI_CLK_ENABLE, 271 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 272 MCI_QCOM_CLK_SELECT_IN_FBCLK, 273 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 274 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 275 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 276 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 277 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 278 .cmdreg_srsp = MCI_CPSM_RESPONSE, 279 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 280 .datalength_bits = 24, 281 .datactrl_blocksz = 11, 282 .pwrreg_powerup = MCI_PWR_UP, 283 .f_max = 208000000, 284 .explicit_mclk_control = true, 285 .qcom_fifo = true, 286 .qcom_dml = true, 287 .mmcimask1 = true, 288 .irq_pio_mask = MCI_IRQ_PIO_MASK, 289 .start_err = MCI_STARTBITERR, 290 .opendrain = MCI_ROD, 291 .init = qcom_variant_init, 292 }; 293 294 /* Busy detection for the ST Micro variant */ 295 static int mmci_card_busy(struct mmc_host *mmc) 296 { 297 struct mmci_host *host = mmc_priv(mmc); 298 unsigned long flags; 299 int busy = 0; 300 301 spin_lock_irqsave(&host->lock, flags); 302 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 303 busy = 1; 304 spin_unlock_irqrestore(&host->lock, flags); 305 306 return busy; 307 } 308 309 static void mmci_reg_delay(struct mmci_host *host) 310 { 311 /* 312 * According to the spec, at least three feedback clock cycles 313 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 314 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 315 * Worst delay time during card init is at 100 kHz => 30 us. 316 * Worst delay time when up and running is at 25 MHz => 120 ns. 317 */ 318 if (host->cclk < 25000000) 319 udelay(30); 320 else 321 ndelay(120); 322 } 323 324 /* 325 * This must be called with host->lock held 326 */ 327 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 328 { 329 if (host->clk_reg != clk) { 330 host->clk_reg = clk; 331 writel(clk, host->base + MMCICLOCK); 332 } 333 } 334 335 /* 336 * This must be called with host->lock held 337 */ 338 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 339 { 340 if (host->pwr_reg != pwr) { 341 host->pwr_reg = pwr; 342 writel(pwr, host->base + MMCIPOWER); 343 } 344 } 345 346 /* 347 * This must be called with host->lock held 348 */ 349 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 350 { 351 /* Keep busy mode in DPSM if enabled */ 352 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 353 354 if (host->datactrl_reg != datactrl) { 355 host->datactrl_reg = datactrl; 356 writel(datactrl, host->base + MMCIDATACTRL); 357 } 358 } 359 360 /* 361 * This must be called with host->lock held 362 */ 363 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 364 { 365 struct variant_data *variant = host->variant; 366 u32 clk = variant->clkreg; 367 368 /* Make sure cclk reflects the current calculated clock */ 369 host->cclk = 0; 370 371 if (desired) { 372 if (variant->explicit_mclk_control) { 373 host->cclk = host->mclk; 374 } else if (desired >= host->mclk) { 375 clk = MCI_CLK_BYPASS; 376 if (variant->st_clkdiv) 377 clk |= MCI_ST_UX500_NEG_EDGE; 378 host->cclk = host->mclk; 379 } else if (variant->st_clkdiv) { 380 /* 381 * DB8500 TRM says f = mclk / (clkdiv + 2) 382 * => clkdiv = (mclk / f) - 2 383 * Round the divider up so we don't exceed the max 384 * frequency 385 */ 386 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 387 if (clk >= 256) 388 clk = 255; 389 host->cclk = host->mclk / (clk + 2); 390 } else { 391 /* 392 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 393 * => clkdiv = mclk / (2 * f) - 1 394 */ 395 clk = host->mclk / (2 * desired) - 1; 396 if (clk >= 256) 397 clk = 255; 398 host->cclk = host->mclk / (2 * (clk + 1)); 399 } 400 401 clk |= variant->clkreg_enable; 402 clk |= MCI_CLK_ENABLE; 403 /* This hasn't proven to be worthwhile */ 404 /* clk |= MCI_CLK_PWRSAVE; */ 405 } 406 407 /* Set actual clock for debug */ 408 host->mmc->actual_clock = host->cclk; 409 410 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 411 clk |= MCI_4BIT_BUS; 412 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 413 clk |= variant->clkreg_8bit_bus_enable; 414 415 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 416 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 417 clk |= variant->clkreg_neg_edge_enable; 418 419 mmci_write_clkreg(host, clk); 420 } 421 422 void mmci_dma_release(struct mmci_host *host) 423 { 424 if (host->ops && host->ops->dma_release) 425 host->ops->dma_release(host); 426 427 host->use_dma = false; 428 } 429 430 void mmci_dma_setup(struct mmci_host *host) 431 { 432 if (!host->ops || !host->ops->dma_setup) 433 return; 434 435 if (host->ops->dma_setup(host)) 436 return; 437 438 /* initialize pre request cookie */ 439 host->next_cookie = 1; 440 441 host->use_dma = true; 442 } 443 444 /* 445 * Validate mmc prerequisites 446 */ 447 static int mmci_validate_data(struct mmci_host *host, 448 struct mmc_data *data) 449 { 450 if (!data) 451 return 0; 452 453 if (!is_power_of_2(data->blksz)) { 454 dev_err(mmc_dev(host->mmc), 455 "unsupported block size (%d bytes)\n", data->blksz); 456 return -EINVAL; 457 } 458 459 if (host->ops && host->ops->validate_data) 460 return host->ops->validate_data(host, data); 461 462 return 0; 463 } 464 465 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 466 { 467 int err; 468 469 if (!host->ops || !host->ops->prep_data) 470 return 0; 471 472 err = host->ops->prep_data(host, data, next); 473 474 if (next && !err) 475 data->host_cookie = ++host->next_cookie < 0 ? 476 1 : host->next_cookie; 477 478 return err; 479 } 480 481 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 482 int err) 483 { 484 if (host->ops && host->ops->unprep_data) 485 host->ops->unprep_data(host, data, err); 486 487 data->host_cookie = 0; 488 } 489 490 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 491 { 492 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 493 494 if (host->ops && host->ops->get_next_data) 495 host->ops->get_next_data(host, data); 496 } 497 498 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 499 { 500 struct mmc_data *data = host->data; 501 int ret; 502 503 if (!host->use_dma) 504 return -EINVAL; 505 506 ret = mmci_prep_data(host, data, false); 507 if (ret) 508 return ret; 509 510 if (!host->ops || !host->ops->dma_start) 511 return -EINVAL; 512 513 /* Okay, go for it. */ 514 dev_vdbg(mmc_dev(host->mmc), 515 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 516 data->sg_len, data->blksz, data->blocks, data->flags); 517 518 host->ops->dma_start(host, &datactrl); 519 520 /* Trigger the DMA transfer */ 521 mmci_write_datactrlreg(host, datactrl); 522 523 /* 524 * Let the MMCI say when the data is ended and it's time 525 * to fire next DMA request. When that happens, MMCI will 526 * call mmci_data_end() 527 */ 528 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 529 host->base + MMCIMASK0); 530 return 0; 531 } 532 533 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 534 { 535 if (!host->use_dma) 536 return; 537 538 if (host->ops && host->ops->dma_finalize) 539 host->ops->dma_finalize(host, data); 540 } 541 542 void mmci_dma_error(struct mmci_host *host) 543 { 544 if (!host->use_dma) 545 return; 546 547 if (host->ops && host->ops->dma_error) 548 host->ops->dma_error(host); 549 } 550 551 static void 552 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 553 { 554 writel(0, host->base + MMCICOMMAND); 555 556 BUG_ON(host->data); 557 558 host->mrq = NULL; 559 host->cmd = NULL; 560 561 mmc_request_done(host->mmc, mrq); 562 } 563 564 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 565 { 566 void __iomem *base = host->base; 567 struct variant_data *variant = host->variant; 568 569 if (host->singleirq) { 570 unsigned int mask0 = readl(base + MMCIMASK0); 571 572 mask0 &= ~variant->irq_pio_mask; 573 mask0 |= mask; 574 575 writel(mask0, base + MMCIMASK0); 576 } 577 578 if (variant->mmcimask1) 579 writel(mask, base + MMCIMASK1); 580 581 host->mask1_reg = mask; 582 } 583 584 static void mmci_stop_data(struct mmci_host *host) 585 { 586 mmci_write_datactrlreg(host, 0); 587 mmci_set_mask1(host, 0); 588 host->data = NULL; 589 } 590 591 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 592 { 593 unsigned int flags = SG_MITER_ATOMIC; 594 595 if (data->flags & MMC_DATA_READ) 596 flags |= SG_MITER_TO_SG; 597 else 598 flags |= SG_MITER_FROM_SG; 599 600 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 601 } 602 603 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 604 { 605 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 606 } 607 608 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 609 { 610 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 611 } 612 613 /* 614 * All the DMA operation mode stuff goes inside this ifdef. 615 * This assumes that you have a generic DMA device interface, 616 * no custom DMA interfaces are supported. 617 */ 618 #ifdef CONFIG_DMA_ENGINE 619 struct mmci_dmae_next { 620 struct dma_async_tx_descriptor *desc; 621 struct dma_chan *chan; 622 }; 623 624 struct mmci_dmae_priv { 625 struct dma_chan *cur; 626 struct dma_chan *rx_channel; 627 struct dma_chan *tx_channel; 628 struct dma_async_tx_descriptor *desc_current; 629 struct mmci_dmae_next next_data; 630 }; 631 632 int mmci_dmae_setup(struct mmci_host *host) 633 { 634 const char *rxname, *txname; 635 struct mmci_dmae_priv *dmae; 636 637 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 638 if (!dmae) 639 return -ENOMEM; 640 641 host->dma_priv = dmae; 642 643 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 644 "rx"); 645 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 646 "tx"); 647 648 /* 649 * If only an RX channel is specified, the driver will 650 * attempt to use it bidirectionally, however if it is 651 * is specified but cannot be located, DMA will be disabled. 652 */ 653 if (dmae->rx_channel && !dmae->tx_channel) 654 dmae->tx_channel = dmae->rx_channel; 655 656 if (dmae->rx_channel) 657 rxname = dma_chan_name(dmae->rx_channel); 658 else 659 rxname = "none"; 660 661 if (dmae->tx_channel) 662 txname = dma_chan_name(dmae->tx_channel); 663 else 664 txname = "none"; 665 666 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 667 rxname, txname); 668 669 /* 670 * Limit the maximum segment size in any SG entry according to 671 * the parameters of the DMA engine device. 672 */ 673 if (dmae->tx_channel) { 674 struct device *dev = dmae->tx_channel->device->dev; 675 unsigned int max_seg_size = dma_get_max_seg_size(dev); 676 677 if (max_seg_size < host->mmc->max_seg_size) 678 host->mmc->max_seg_size = max_seg_size; 679 } 680 if (dmae->rx_channel) { 681 struct device *dev = dmae->rx_channel->device->dev; 682 unsigned int max_seg_size = dma_get_max_seg_size(dev); 683 684 if (max_seg_size < host->mmc->max_seg_size) 685 host->mmc->max_seg_size = max_seg_size; 686 } 687 688 if (!dmae->tx_channel || !dmae->rx_channel) { 689 mmci_dmae_release(host); 690 return -EINVAL; 691 } 692 693 return 0; 694 } 695 696 /* 697 * This is used in or so inline it 698 * so it can be discarded. 699 */ 700 void mmci_dmae_release(struct mmci_host *host) 701 { 702 struct mmci_dmae_priv *dmae = host->dma_priv; 703 704 if (dmae->rx_channel) 705 dma_release_channel(dmae->rx_channel); 706 if (dmae->tx_channel) 707 dma_release_channel(dmae->tx_channel); 708 dmae->rx_channel = dmae->tx_channel = NULL; 709 } 710 711 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 712 { 713 struct mmci_dmae_priv *dmae = host->dma_priv; 714 struct dma_chan *chan; 715 716 if (data->flags & MMC_DATA_READ) 717 chan = dmae->rx_channel; 718 else 719 chan = dmae->tx_channel; 720 721 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 722 mmc_get_dma_dir(data)); 723 } 724 725 void mmci_dmae_error(struct mmci_host *host) 726 { 727 struct mmci_dmae_priv *dmae = host->dma_priv; 728 729 if (!dma_inprogress(host)) 730 return; 731 732 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 733 dmaengine_terminate_all(dmae->cur); 734 host->dma_in_progress = false; 735 dmae->cur = NULL; 736 dmae->desc_current = NULL; 737 host->data->host_cookie = 0; 738 739 mmci_dma_unmap(host, host->data); 740 } 741 742 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 743 { 744 struct mmci_dmae_priv *dmae = host->dma_priv; 745 u32 status; 746 int i; 747 748 if (!dma_inprogress(host)) 749 return; 750 751 /* Wait up to 1ms for the DMA to complete */ 752 for (i = 0; ; i++) { 753 status = readl(host->base + MMCISTATUS); 754 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 755 break; 756 udelay(10); 757 } 758 759 /* 760 * Check to see whether we still have some data left in the FIFO - 761 * this catches DMA controllers which are unable to monitor the 762 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 763 * contiguous buffers. On TX, we'll get a FIFO underrun error. 764 */ 765 if (status & MCI_RXDATAAVLBLMASK) { 766 mmci_dma_error(host); 767 if (!data->error) 768 data->error = -EIO; 769 } else if (!data->host_cookie) { 770 mmci_dma_unmap(host, data); 771 } 772 773 /* 774 * Use of DMA with scatter-gather is impossible. 775 * Give up with DMA and switch back to PIO mode. 776 */ 777 if (status & MCI_RXDATAAVLBLMASK) { 778 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 779 mmci_dma_release(host); 780 } 781 782 host->dma_in_progress = false; 783 dmae->cur = NULL; 784 dmae->desc_current = NULL; 785 } 786 787 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 788 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 789 struct dma_chan **dma_chan, 790 struct dma_async_tx_descriptor **dma_desc) 791 { 792 struct mmci_dmae_priv *dmae = host->dma_priv; 793 struct variant_data *variant = host->variant; 794 struct dma_slave_config conf = { 795 .src_addr = host->phybase + MMCIFIFO, 796 .dst_addr = host->phybase + MMCIFIFO, 797 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 798 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 799 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 800 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 801 .device_fc = false, 802 }; 803 struct dma_chan *chan; 804 struct dma_device *device; 805 struct dma_async_tx_descriptor *desc; 806 int nr_sg; 807 unsigned long flags = DMA_CTRL_ACK; 808 809 if (data->flags & MMC_DATA_READ) { 810 conf.direction = DMA_DEV_TO_MEM; 811 chan = dmae->rx_channel; 812 } else { 813 conf.direction = DMA_MEM_TO_DEV; 814 chan = dmae->tx_channel; 815 } 816 817 /* If there's no DMA channel, fall back to PIO */ 818 if (!chan) 819 return -EINVAL; 820 821 /* If less than or equal to the fifo size, don't bother with DMA */ 822 if (data->blksz * data->blocks <= variant->fifosize) 823 return -EINVAL; 824 825 device = chan->device; 826 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 827 mmc_get_dma_dir(data)); 828 if (nr_sg == 0) 829 return -EINVAL; 830 831 if (host->variant->qcom_dml) 832 flags |= DMA_PREP_INTERRUPT; 833 834 dmaengine_slave_config(chan, &conf); 835 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 836 conf.direction, flags); 837 if (!desc) 838 goto unmap_exit; 839 840 *dma_chan = chan; 841 *dma_desc = desc; 842 843 return 0; 844 845 unmap_exit: 846 dma_unmap_sg(device->dev, data->sg, data->sg_len, 847 mmc_get_dma_dir(data)); 848 return -ENOMEM; 849 } 850 851 int mmci_dmae_prep_data(struct mmci_host *host, 852 struct mmc_data *data, 853 bool next) 854 { 855 struct mmci_dmae_priv *dmae = host->dma_priv; 856 struct mmci_dmae_next *nd = &dmae->next_data; 857 858 if (!host->use_dma) 859 return -EINVAL; 860 861 if (next) 862 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 863 /* Check if next job is already prepared. */ 864 if (dmae->cur && dmae->desc_current) 865 return 0; 866 867 /* No job were prepared thus do it now. */ 868 return _mmci_dmae_prep_data(host, data, &dmae->cur, 869 &dmae->desc_current); 870 } 871 872 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 873 { 874 struct mmci_dmae_priv *dmae = host->dma_priv; 875 876 host->dma_in_progress = true; 877 dmaengine_submit(dmae->desc_current); 878 dma_async_issue_pending(dmae->cur); 879 880 *datactrl |= MCI_DPSM_DMAENABLE; 881 882 return 0; 883 } 884 885 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 886 { 887 struct mmci_dmae_priv *dmae = host->dma_priv; 888 struct mmci_dmae_next *next = &dmae->next_data; 889 890 if (!host->use_dma) 891 return; 892 893 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 894 895 dmae->desc_current = next->desc; 896 dmae->cur = next->chan; 897 next->desc = NULL; 898 next->chan = NULL; 899 } 900 901 void mmci_dmae_unprep_data(struct mmci_host *host, 902 struct mmc_data *data, int err) 903 904 { 905 struct mmci_dmae_priv *dmae = host->dma_priv; 906 907 if (!host->use_dma) 908 return; 909 910 mmci_dma_unmap(host, data); 911 912 if (err) { 913 struct mmci_dmae_next *next = &dmae->next_data; 914 struct dma_chan *chan; 915 if (data->flags & MMC_DATA_READ) 916 chan = dmae->rx_channel; 917 else 918 chan = dmae->tx_channel; 919 dmaengine_terminate_all(chan); 920 921 if (dmae->desc_current == next->desc) 922 dmae->desc_current = NULL; 923 924 if (dmae->cur == next->chan) { 925 host->dma_in_progress = false; 926 dmae->cur = NULL; 927 } 928 929 next->desc = NULL; 930 next->chan = NULL; 931 } 932 } 933 934 static struct mmci_host_ops mmci_variant_ops = { 935 .prep_data = mmci_dmae_prep_data, 936 .unprep_data = mmci_dmae_unprep_data, 937 .get_datactrl_cfg = mmci_get_dctrl_cfg, 938 .get_next_data = mmci_dmae_get_next_data, 939 .dma_setup = mmci_dmae_setup, 940 .dma_release = mmci_dmae_release, 941 .dma_start = mmci_dmae_start, 942 .dma_finalize = mmci_dmae_finalize, 943 .dma_error = mmci_dmae_error, 944 }; 945 #else 946 static struct mmci_host_ops mmci_variant_ops = { 947 .get_datactrl_cfg = mmci_get_dctrl_cfg, 948 }; 949 #endif 950 951 void mmci_variant_init(struct mmci_host *host) 952 { 953 host->ops = &mmci_variant_ops; 954 } 955 956 void ux500v2_variant_init(struct mmci_host *host) 957 { 958 host->ops = &mmci_variant_ops; 959 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 960 } 961 962 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 963 { 964 struct mmci_host *host = mmc_priv(mmc); 965 struct mmc_data *data = mrq->data; 966 967 if (!data) 968 return; 969 970 WARN_ON(data->host_cookie); 971 972 if (mmci_validate_data(host, data)) 973 return; 974 975 mmci_prep_data(host, data, true); 976 } 977 978 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 979 int err) 980 { 981 struct mmci_host *host = mmc_priv(mmc); 982 struct mmc_data *data = mrq->data; 983 984 if (!data || !data->host_cookie) 985 return; 986 987 mmci_unprep_data(host, data, err); 988 } 989 990 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 991 { 992 struct variant_data *variant = host->variant; 993 unsigned int datactrl, timeout, irqmask; 994 unsigned long long clks; 995 void __iomem *base; 996 997 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 998 data->blksz, data->blocks, data->flags); 999 1000 host->data = data; 1001 host->size = data->blksz * data->blocks; 1002 data->bytes_xfered = 0; 1003 1004 clks = (unsigned long long)data->timeout_ns * host->cclk; 1005 do_div(clks, NSEC_PER_SEC); 1006 1007 timeout = data->timeout_clks + (unsigned int)clks; 1008 1009 base = host->base; 1010 writel(timeout, base + MMCIDATATIMER); 1011 writel(host->size, base + MMCIDATALENGTH); 1012 1013 datactrl = host->ops->get_datactrl_cfg(host); 1014 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1015 1016 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1017 u32 clk; 1018 1019 datactrl |= variant->datactrl_mask_sdio; 1020 1021 /* 1022 * The ST Micro variant for SDIO small write transfers 1023 * needs to have clock H/W flow control disabled, 1024 * otherwise the transfer will not start. The threshold 1025 * depends on the rate of MCLK. 1026 */ 1027 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1028 (host->size < 8 || 1029 (host->size <= 8 && host->mclk > 50000000))) 1030 clk = host->clk_reg & ~variant->clkreg_enable; 1031 else 1032 clk = host->clk_reg | variant->clkreg_enable; 1033 1034 mmci_write_clkreg(host, clk); 1035 } 1036 1037 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1038 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1039 datactrl |= variant->datactrl_mask_ddrmode; 1040 1041 /* 1042 * Attempt to use DMA operation mode, if this 1043 * should fail, fall back to PIO mode 1044 */ 1045 if (!mmci_dma_start(host, datactrl)) 1046 return; 1047 1048 /* IRQ mode, map the SG list for CPU reading/writing */ 1049 mmci_init_sg(host, data); 1050 1051 if (data->flags & MMC_DATA_READ) { 1052 irqmask = MCI_RXFIFOHALFFULLMASK; 1053 1054 /* 1055 * If we have less than the fifo 'half-full' threshold to 1056 * transfer, trigger a PIO interrupt as soon as any data 1057 * is available. 1058 */ 1059 if (host->size < variant->fifohalfsize) 1060 irqmask |= MCI_RXDATAAVLBLMASK; 1061 } else { 1062 /* 1063 * We don't actually need to include "FIFO empty" here 1064 * since its implicit in "FIFO half empty". 1065 */ 1066 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1067 } 1068 1069 mmci_write_datactrlreg(host, datactrl); 1070 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1071 mmci_set_mask1(host, irqmask); 1072 } 1073 1074 static void 1075 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1076 { 1077 void __iomem *base = host->base; 1078 1079 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1080 cmd->opcode, cmd->arg, cmd->flags); 1081 1082 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1083 writel(0, base + MMCICOMMAND); 1084 mmci_reg_delay(host); 1085 } 1086 1087 if (host->variant->cmdreg_stop && 1088 cmd->opcode == MMC_STOP_TRANSMISSION) 1089 c |= host->variant->cmdreg_stop; 1090 1091 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1092 if (cmd->flags & MMC_RSP_PRESENT) { 1093 if (cmd->flags & MMC_RSP_136) 1094 c |= host->variant->cmdreg_lrsp_crc; 1095 else if (cmd->flags & MMC_RSP_CRC) 1096 c |= host->variant->cmdreg_srsp_crc; 1097 else 1098 c |= host->variant->cmdreg_srsp; 1099 } 1100 if (/*interrupt*/0) 1101 c |= MCI_CPSM_INTERRUPT; 1102 1103 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1104 c |= host->variant->data_cmd_enable; 1105 1106 host->cmd = cmd; 1107 1108 writel(cmd->arg, base + MMCIARGUMENT); 1109 writel(c, base + MMCICOMMAND); 1110 } 1111 1112 static void mmci_stop_command(struct mmci_host *host) 1113 { 1114 host->stop_abort.error = 0; 1115 mmci_start_command(host, &host->stop_abort, 0); 1116 } 1117 1118 static void 1119 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1120 unsigned int status) 1121 { 1122 unsigned int status_err; 1123 1124 /* Make sure we have data to handle */ 1125 if (!data) 1126 return; 1127 1128 /* First check for errors */ 1129 status_err = status & (host->variant->start_err | 1130 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1131 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1132 1133 if (status_err) { 1134 u32 remain, success; 1135 1136 /* Terminate the DMA transfer */ 1137 mmci_dma_error(host); 1138 1139 /* 1140 * Calculate how far we are into the transfer. Note that 1141 * the data counter gives the number of bytes transferred 1142 * on the MMC bus, not on the host side. On reads, this 1143 * can be as much as a FIFO-worth of data ahead. This 1144 * matters for FIFO overruns only. 1145 */ 1146 if (!host->variant->datacnt_useless) { 1147 remain = readl(host->base + MMCIDATACNT); 1148 success = data->blksz * data->blocks - remain; 1149 } else { 1150 success = 0; 1151 } 1152 1153 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1154 status_err, success); 1155 if (status_err & MCI_DATACRCFAIL) { 1156 /* Last block was not successful */ 1157 success -= 1; 1158 data->error = -EILSEQ; 1159 } else if (status_err & MCI_DATATIMEOUT) { 1160 data->error = -ETIMEDOUT; 1161 } else if (status_err & MCI_STARTBITERR) { 1162 data->error = -ECOMM; 1163 } else if (status_err & MCI_TXUNDERRUN) { 1164 data->error = -EIO; 1165 } else if (status_err & MCI_RXOVERRUN) { 1166 if (success > host->variant->fifosize) 1167 success -= host->variant->fifosize; 1168 else 1169 success = 0; 1170 data->error = -EIO; 1171 } 1172 data->bytes_xfered = round_down(success, data->blksz); 1173 } 1174 1175 if (status & MCI_DATABLOCKEND) 1176 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1177 1178 if (status & MCI_DATAEND || data->error) { 1179 mmci_dma_finalize(host, data); 1180 1181 mmci_stop_data(host); 1182 1183 if (!data->error) 1184 /* The error clause is handled above, success! */ 1185 data->bytes_xfered = data->blksz * data->blocks; 1186 1187 if (!data->stop) { 1188 if (host->variant->cmdreg_stop && data->error) 1189 mmci_stop_command(host); 1190 else 1191 mmci_request_end(host, data->mrq); 1192 } else if (host->mrq->sbc && !data->error) { 1193 mmci_request_end(host, data->mrq); 1194 } else { 1195 mmci_start_command(host, data->stop, 0); 1196 } 1197 } 1198 } 1199 1200 static void 1201 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1202 unsigned int status) 1203 { 1204 void __iomem *base = host->base; 1205 bool sbc, busy_resp; 1206 1207 if (!cmd) 1208 return; 1209 1210 sbc = (cmd == host->mrq->sbc); 1211 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1212 1213 /* 1214 * We need to be one of these interrupts to be considered worth 1215 * handling. Note that we tag on any latent IRQs postponed 1216 * due to waiting for busy status. 1217 */ 1218 if (!((status|host->busy_status) & 1219 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1220 return; 1221 1222 /* 1223 * ST Micro variant: handle busy detection. 1224 */ 1225 if (busy_resp && host->variant->busy_detect) { 1226 1227 /* We are busy with a command, return */ 1228 if (host->busy_status && 1229 (status & host->variant->busy_detect_flag)) 1230 return; 1231 1232 /* 1233 * We were not busy, but we now got a busy response on 1234 * something that was not an error, and we double-check 1235 * that the special busy status bit is still set before 1236 * proceeding. 1237 */ 1238 if (!host->busy_status && 1239 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1240 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1241 1242 /* Clear the busy start IRQ */ 1243 writel(host->variant->busy_detect_mask, 1244 host->base + MMCICLEAR); 1245 1246 /* Unmask the busy end IRQ */ 1247 writel(readl(base + MMCIMASK0) | 1248 host->variant->busy_detect_mask, 1249 base + MMCIMASK0); 1250 /* 1251 * Now cache the last response status code (until 1252 * the busy bit goes low), and return. 1253 */ 1254 host->busy_status = 1255 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1256 return; 1257 } 1258 1259 /* 1260 * At this point we are not busy with a command, we have 1261 * not received a new busy request, clear and mask the busy 1262 * end IRQ and fall through to process the IRQ. 1263 */ 1264 if (host->busy_status) { 1265 1266 writel(host->variant->busy_detect_mask, 1267 host->base + MMCICLEAR); 1268 1269 writel(readl(base + MMCIMASK0) & 1270 ~host->variant->busy_detect_mask, 1271 base + MMCIMASK0); 1272 host->busy_status = 0; 1273 } 1274 } 1275 1276 host->cmd = NULL; 1277 1278 if (status & MCI_CMDTIMEOUT) { 1279 cmd->error = -ETIMEDOUT; 1280 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1281 cmd->error = -EILSEQ; 1282 } else { 1283 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1284 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1285 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1286 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1287 } 1288 1289 if ((!sbc && !cmd->data) || cmd->error) { 1290 if (host->data) { 1291 /* Terminate the DMA transfer */ 1292 mmci_dma_error(host); 1293 1294 mmci_stop_data(host); 1295 if (host->variant->cmdreg_stop && cmd->error) { 1296 mmci_stop_command(host); 1297 return; 1298 } 1299 } 1300 mmci_request_end(host, host->mrq); 1301 } else if (sbc) { 1302 mmci_start_command(host, host->mrq->cmd, 0); 1303 } else if (!host->variant->datactrl_first && 1304 !(cmd->data->flags & MMC_DATA_READ)) { 1305 mmci_start_data(host, cmd->data); 1306 } 1307 } 1308 1309 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1310 { 1311 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1312 } 1313 1314 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1315 { 1316 /* 1317 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1318 * from the fifo range should be used 1319 */ 1320 if (status & MCI_RXFIFOHALFFULL) 1321 return host->variant->fifohalfsize; 1322 else if (status & MCI_RXDATAAVLBL) 1323 return 4; 1324 1325 return 0; 1326 } 1327 1328 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1329 { 1330 void __iomem *base = host->base; 1331 char *ptr = buffer; 1332 u32 status = readl(host->base + MMCISTATUS); 1333 int host_remain = host->size; 1334 1335 do { 1336 int count = host->get_rx_fifocnt(host, status, host_remain); 1337 1338 if (count > remain) 1339 count = remain; 1340 1341 if (count <= 0) 1342 break; 1343 1344 /* 1345 * SDIO especially may want to send something that is 1346 * not divisible by 4 (as opposed to card sectors 1347 * etc). Therefore make sure to always read the last bytes 1348 * while only doing full 32-bit reads towards the FIFO. 1349 */ 1350 if (unlikely(count & 0x3)) { 1351 if (count < 4) { 1352 unsigned char buf[4]; 1353 ioread32_rep(base + MMCIFIFO, buf, 1); 1354 memcpy(ptr, buf, count); 1355 } else { 1356 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1357 count &= ~0x3; 1358 } 1359 } else { 1360 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1361 } 1362 1363 ptr += count; 1364 remain -= count; 1365 host_remain -= count; 1366 1367 if (remain == 0) 1368 break; 1369 1370 status = readl(base + MMCISTATUS); 1371 } while (status & MCI_RXDATAAVLBL); 1372 1373 return ptr - buffer; 1374 } 1375 1376 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1377 { 1378 struct variant_data *variant = host->variant; 1379 void __iomem *base = host->base; 1380 char *ptr = buffer; 1381 1382 do { 1383 unsigned int count, maxcnt; 1384 1385 maxcnt = status & MCI_TXFIFOEMPTY ? 1386 variant->fifosize : variant->fifohalfsize; 1387 count = min(remain, maxcnt); 1388 1389 /* 1390 * SDIO especially may want to send something that is 1391 * not divisible by 4 (as opposed to card sectors 1392 * etc), and the FIFO only accept full 32-bit writes. 1393 * So compensate by adding +3 on the count, a single 1394 * byte become a 32bit write, 7 bytes will be two 1395 * 32bit writes etc. 1396 */ 1397 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1398 1399 ptr += count; 1400 remain -= count; 1401 1402 if (remain == 0) 1403 break; 1404 1405 status = readl(base + MMCISTATUS); 1406 } while (status & MCI_TXFIFOHALFEMPTY); 1407 1408 return ptr - buffer; 1409 } 1410 1411 /* 1412 * PIO data transfer IRQ handler. 1413 */ 1414 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1415 { 1416 struct mmci_host *host = dev_id; 1417 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1418 struct variant_data *variant = host->variant; 1419 void __iomem *base = host->base; 1420 u32 status; 1421 1422 status = readl(base + MMCISTATUS); 1423 1424 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1425 1426 do { 1427 unsigned int remain, len; 1428 char *buffer; 1429 1430 /* 1431 * For write, we only need to test the half-empty flag 1432 * here - if the FIFO is completely empty, then by 1433 * definition it is more than half empty. 1434 * 1435 * For read, check for data available. 1436 */ 1437 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1438 break; 1439 1440 if (!sg_miter_next(sg_miter)) 1441 break; 1442 1443 buffer = sg_miter->addr; 1444 remain = sg_miter->length; 1445 1446 len = 0; 1447 if (status & MCI_RXACTIVE) 1448 len = mmci_pio_read(host, buffer, remain); 1449 if (status & MCI_TXACTIVE) 1450 len = mmci_pio_write(host, buffer, remain, status); 1451 1452 sg_miter->consumed = len; 1453 1454 host->size -= len; 1455 remain -= len; 1456 1457 if (remain) 1458 break; 1459 1460 status = readl(base + MMCISTATUS); 1461 } while (1); 1462 1463 sg_miter_stop(sg_miter); 1464 1465 /* 1466 * If we have less than the fifo 'half-full' threshold to transfer, 1467 * trigger a PIO interrupt as soon as any data is available. 1468 */ 1469 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1470 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1471 1472 /* 1473 * If we run out of data, disable the data IRQs; this 1474 * prevents a race where the FIFO becomes empty before 1475 * the chip itself has disabled the data path, and 1476 * stops us racing with our data end IRQ. 1477 */ 1478 if (host->size == 0) { 1479 mmci_set_mask1(host, 0); 1480 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1481 } 1482 1483 return IRQ_HANDLED; 1484 } 1485 1486 /* 1487 * Handle completion of command and data transfers. 1488 */ 1489 static irqreturn_t mmci_irq(int irq, void *dev_id) 1490 { 1491 struct mmci_host *host = dev_id; 1492 u32 status; 1493 int ret = 0; 1494 1495 spin_lock(&host->lock); 1496 1497 do { 1498 status = readl(host->base + MMCISTATUS); 1499 1500 if (host->singleirq) { 1501 if (status & host->mask1_reg) 1502 mmci_pio_irq(irq, dev_id); 1503 1504 status &= ~host->variant->irq_pio_mask; 1505 } 1506 1507 /* 1508 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1509 * enabled) in mmci_cmd_irq() function where ST Micro busy 1510 * detection variant is handled. Considering the HW seems to be 1511 * triggering the IRQ on both edges while monitoring DAT0 for 1512 * busy completion and that same status bit is used to monitor 1513 * start and end of busy detection, special care must be taken 1514 * to make sure that both start and end interrupts are always 1515 * cleared one after the other. 1516 */ 1517 status &= readl(host->base + MMCIMASK0); 1518 if (host->variant->busy_detect) 1519 writel(status & ~host->variant->busy_detect_mask, 1520 host->base + MMCICLEAR); 1521 else 1522 writel(status, host->base + MMCICLEAR); 1523 1524 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1525 1526 if (host->variant->reversed_irq_handling) { 1527 mmci_data_irq(host, host->data, status); 1528 mmci_cmd_irq(host, host->cmd, status); 1529 } else { 1530 mmci_cmd_irq(host, host->cmd, status); 1531 mmci_data_irq(host, host->data, status); 1532 } 1533 1534 /* 1535 * Busy detection has been handled by mmci_cmd_irq() above. 1536 * Clear the status bit to prevent polling in IRQ context. 1537 */ 1538 if (host->variant->busy_detect_flag) 1539 status &= ~host->variant->busy_detect_flag; 1540 1541 ret = 1; 1542 } while (status); 1543 1544 spin_unlock(&host->lock); 1545 1546 return IRQ_RETVAL(ret); 1547 } 1548 1549 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1550 { 1551 struct mmci_host *host = mmc_priv(mmc); 1552 unsigned long flags; 1553 1554 WARN_ON(host->mrq != NULL); 1555 1556 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1557 if (mrq->cmd->error) { 1558 mmc_request_done(mmc, mrq); 1559 return; 1560 } 1561 1562 spin_lock_irqsave(&host->lock, flags); 1563 1564 host->mrq = mrq; 1565 1566 if (mrq->data) 1567 mmci_get_next_data(host, mrq->data); 1568 1569 if (mrq->data && 1570 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1571 mmci_start_data(host, mrq->data); 1572 1573 if (mrq->sbc) 1574 mmci_start_command(host, mrq->sbc, 0); 1575 else 1576 mmci_start_command(host, mrq->cmd, 0); 1577 1578 spin_unlock_irqrestore(&host->lock, flags); 1579 } 1580 1581 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1582 { 1583 struct mmci_host *host = mmc_priv(mmc); 1584 struct variant_data *variant = host->variant; 1585 u32 pwr = 0; 1586 unsigned long flags; 1587 int ret; 1588 1589 if (host->plat->ios_handler && 1590 host->plat->ios_handler(mmc_dev(mmc), ios)) 1591 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1592 1593 switch (ios->power_mode) { 1594 case MMC_POWER_OFF: 1595 if (!IS_ERR(mmc->supply.vmmc)) 1596 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1597 1598 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1599 regulator_disable(mmc->supply.vqmmc); 1600 host->vqmmc_enabled = false; 1601 } 1602 1603 break; 1604 case MMC_POWER_UP: 1605 if (!IS_ERR(mmc->supply.vmmc)) 1606 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1607 1608 /* 1609 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1610 * and instead uses MCI_PWR_ON so apply whatever value is 1611 * configured in the variant data. 1612 */ 1613 pwr |= variant->pwrreg_powerup; 1614 1615 break; 1616 case MMC_POWER_ON: 1617 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1618 ret = regulator_enable(mmc->supply.vqmmc); 1619 if (ret < 0) 1620 dev_err(mmc_dev(mmc), 1621 "failed to enable vqmmc regulator\n"); 1622 else 1623 host->vqmmc_enabled = true; 1624 } 1625 1626 pwr |= MCI_PWR_ON; 1627 break; 1628 } 1629 1630 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1631 /* 1632 * The ST Micro variant has some additional bits 1633 * indicating signal direction for the signals in 1634 * the SD/MMC bus and feedback-clock usage. 1635 */ 1636 pwr |= host->pwr_reg_add; 1637 1638 if (ios->bus_width == MMC_BUS_WIDTH_4) 1639 pwr &= ~MCI_ST_DATA74DIREN; 1640 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1641 pwr &= (~MCI_ST_DATA74DIREN & 1642 ~MCI_ST_DATA31DIREN & 1643 ~MCI_ST_DATA2DIREN); 1644 } 1645 1646 if (variant->opendrain) { 1647 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1648 pwr |= variant->opendrain; 1649 } else { 1650 /* 1651 * If the variant cannot configure the pads by its own, then we 1652 * expect the pinctrl to be able to do that for us 1653 */ 1654 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1655 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1656 else 1657 pinctrl_select_state(host->pinctrl, host->pins_default); 1658 } 1659 1660 /* 1661 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1662 * gating the clock, the MCI_PWR_ON bit is cleared. 1663 */ 1664 if (!ios->clock && variant->pwrreg_clkgate) 1665 pwr &= ~MCI_PWR_ON; 1666 1667 if (host->variant->explicit_mclk_control && 1668 ios->clock != host->clock_cache) { 1669 ret = clk_set_rate(host->clk, ios->clock); 1670 if (ret < 0) 1671 dev_err(mmc_dev(host->mmc), 1672 "Error setting clock rate (%d)\n", ret); 1673 else 1674 host->mclk = clk_get_rate(host->clk); 1675 } 1676 host->clock_cache = ios->clock; 1677 1678 spin_lock_irqsave(&host->lock, flags); 1679 1680 if (host->ops && host->ops->set_clkreg) 1681 host->ops->set_clkreg(host, ios->clock); 1682 else 1683 mmci_set_clkreg(host, ios->clock); 1684 1685 if (host->ops && host->ops->set_pwrreg) 1686 host->ops->set_pwrreg(host, pwr); 1687 else 1688 mmci_write_pwrreg(host, pwr); 1689 1690 mmci_reg_delay(host); 1691 1692 spin_unlock_irqrestore(&host->lock, flags); 1693 } 1694 1695 static int mmci_get_cd(struct mmc_host *mmc) 1696 { 1697 struct mmci_host *host = mmc_priv(mmc); 1698 struct mmci_platform_data *plat = host->plat; 1699 unsigned int status = mmc_gpio_get_cd(mmc); 1700 1701 if (status == -ENOSYS) { 1702 if (!plat->status) 1703 return 1; /* Assume always present */ 1704 1705 status = plat->status(mmc_dev(host->mmc)); 1706 } 1707 return status; 1708 } 1709 1710 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1711 { 1712 int ret = 0; 1713 1714 if (!IS_ERR(mmc->supply.vqmmc)) { 1715 1716 switch (ios->signal_voltage) { 1717 case MMC_SIGNAL_VOLTAGE_330: 1718 ret = regulator_set_voltage(mmc->supply.vqmmc, 1719 2700000, 3600000); 1720 break; 1721 case MMC_SIGNAL_VOLTAGE_180: 1722 ret = regulator_set_voltage(mmc->supply.vqmmc, 1723 1700000, 1950000); 1724 break; 1725 case MMC_SIGNAL_VOLTAGE_120: 1726 ret = regulator_set_voltage(mmc->supply.vqmmc, 1727 1100000, 1300000); 1728 break; 1729 } 1730 1731 if (ret) 1732 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1733 } 1734 1735 return ret; 1736 } 1737 1738 static struct mmc_host_ops mmci_ops = { 1739 .request = mmci_request, 1740 .pre_req = mmci_pre_request, 1741 .post_req = mmci_post_request, 1742 .set_ios = mmci_set_ios, 1743 .get_ro = mmc_gpio_get_ro, 1744 .get_cd = mmci_get_cd, 1745 .start_signal_voltage_switch = mmci_sig_volt_switch, 1746 }; 1747 1748 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1749 { 1750 struct mmci_host *host = mmc_priv(mmc); 1751 int ret = mmc_of_parse(mmc); 1752 1753 if (ret) 1754 return ret; 1755 1756 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1757 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1758 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1759 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1760 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1761 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1762 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1763 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1764 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1765 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1766 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1767 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1768 if (of_get_property(np, "st,sig-dir", NULL)) 1769 host->pwr_reg_add |= MCI_STM32_DIRPOL; 1770 if (of_get_property(np, "st,neg-edge", NULL)) 1771 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 1772 if (of_get_property(np, "st,use-ckin", NULL)) 1773 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1774 1775 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1776 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1777 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1778 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1779 1780 return 0; 1781 } 1782 1783 static int mmci_probe(struct amba_device *dev, 1784 const struct amba_id *id) 1785 { 1786 struct mmci_platform_data *plat = dev->dev.platform_data; 1787 struct device_node *np = dev->dev.of_node; 1788 struct variant_data *variant = id->data; 1789 struct mmci_host *host; 1790 struct mmc_host *mmc; 1791 int ret; 1792 1793 /* Must have platform data or Device Tree. */ 1794 if (!plat && !np) { 1795 dev_err(&dev->dev, "No plat data or DT found\n"); 1796 return -EINVAL; 1797 } 1798 1799 if (!plat) { 1800 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1801 if (!plat) 1802 return -ENOMEM; 1803 } 1804 1805 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1806 if (!mmc) 1807 return -ENOMEM; 1808 1809 ret = mmci_of_parse(np, mmc); 1810 if (ret) 1811 goto host_free; 1812 1813 host = mmc_priv(mmc); 1814 host->mmc = mmc; 1815 1816 /* 1817 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1818 * pins can be set accordingly using pinctrl 1819 */ 1820 if (!variant->opendrain) { 1821 host->pinctrl = devm_pinctrl_get(&dev->dev); 1822 if (IS_ERR(host->pinctrl)) { 1823 dev_err(&dev->dev, "failed to get pinctrl"); 1824 ret = PTR_ERR(host->pinctrl); 1825 goto host_free; 1826 } 1827 1828 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1829 PINCTRL_STATE_DEFAULT); 1830 if (IS_ERR(host->pins_default)) { 1831 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1832 ret = PTR_ERR(host->pins_default); 1833 goto host_free; 1834 } 1835 1836 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1837 MMCI_PINCTRL_STATE_OPENDRAIN); 1838 if (IS_ERR(host->pins_opendrain)) { 1839 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1840 ret = PTR_ERR(host->pins_opendrain); 1841 goto host_free; 1842 } 1843 } 1844 1845 host->hw_designer = amba_manf(dev); 1846 host->hw_revision = amba_rev(dev); 1847 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1848 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1849 1850 host->clk = devm_clk_get(&dev->dev, NULL); 1851 if (IS_ERR(host->clk)) { 1852 ret = PTR_ERR(host->clk); 1853 goto host_free; 1854 } 1855 1856 ret = clk_prepare_enable(host->clk); 1857 if (ret) 1858 goto host_free; 1859 1860 if (variant->qcom_fifo) 1861 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1862 else 1863 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1864 1865 host->plat = plat; 1866 host->variant = variant; 1867 host->mclk = clk_get_rate(host->clk); 1868 /* 1869 * According to the spec, mclk is max 100 MHz, 1870 * so we try to adjust the clock down to this, 1871 * (if possible). 1872 */ 1873 if (host->mclk > variant->f_max) { 1874 ret = clk_set_rate(host->clk, variant->f_max); 1875 if (ret < 0) 1876 goto clk_disable; 1877 host->mclk = clk_get_rate(host->clk); 1878 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1879 host->mclk); 1880 } 1881 1882 host->phybase = dev->res.start; 1883 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1884 if (IS_ERR(host->base)) { 1885 ret = PTR_ERR(host->base); 1886 goto clk_disable; 1887 } 1888 1889 if (variant->init) 1890 variant->init(host); 1891 1892 /* 1893 * The ARM and ST versions of the block have slightly different 1894 * clock divider equations which means that the minimum divider 1895 * differs too. 1896 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1897 */ 1898 if (variant->st_clkdiv) 1899 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1900 else if (variant->stm32_clkdiv) 1901 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 1902 else if (variant->explicit_mclk_control) 1903 mmc->f_min = clk_round_rate(host->clk, 100000); 1904 else 1905 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1906 /* 1907 * If no maximum operating frequency is supplied, fall back to use 1908 * the module parameter, which has a (low) default value in case it 1909 * is not specified. Either value must not exceed the clock rate into 1910 * the block, of course. 1911 */ 1912 if (mmc->f_max) 1913 mmc->f_max = variant->explicit_mclk_control ? 1914 min(variant->f_max, mmc->f_max) : 1915 min(host->mclk, mmc->f_max); 1916 else 1917 mmc->f_max = variant->explicit_mclk_control ? 1918 fmax : min(host->mclk, fmax); 1919 1920 1921 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1922 1923 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 1924 if (IS_ERR(host->rst)) { 1925 ret = PTR_ERR(host->rst); 1926 goto clk_disable; 1927 } 1928 1929 /* Get regulators and the supported OCR mask */ 1930 ret = mmc_regulator_get_supply(mmc); 1931 if (ret) 1932 goto clk_disable; 1933 1934 if (!mmc->ocr_avail) 1935 mmc->ocr_avail = plat->ocr_mask; 1936 else if (plat->ocr_mask) 1937 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1938 1939 /* We support these capabilities. */ 1940 mmc->caps |= MMC_CAP_CMD23; 1941 1942 /* 1943 * Enable busy detection. 1944 */ 1945 if (variant->busy_detect) { 1946 mmci_ops.card_busy = mmci_card_busy; 1947 /* 1948 * Not all variants have a flag to enable busy detection 1949 * in the DPSM, but if they do, set it here. 1950 */ 1951 if (variant->busy_dpsm_flag) 1952 mmci_write_datactrlreg(host, 1953 host->variant->busy_dpsm_flag); 1954 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1955 mmc->max_busy_timeout = 0; 1956 } 1957 1958 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 1959 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 1960 host->stop_abort.arg = 0; 1961 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 1962 1963 mmc->ops = &mmci_ops; 1964 1965 /* We support these PM capabilities. */ 1966 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1967 1968 /* 1969 * We can do SGIO 1970 */ 1971 mmc->max_segs = NR_SG; 1972 1973 /* 1974 * Since only a certain number of bits are valid in the data length 1975 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1976 * single request. 1977 */ 1978 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1979 1980 /* 1981 * Set the maximum segment size. Since we aren't doing DMA 1982 * (yet) we are only limited by the data length register. 1983 */ 1984 mmc->max_seg_size = mmc->max_req_size; 1985 1986 /* 1987 * Block size can be up to 2048 bytes, but must be a power of two. 1988 */ 1989 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 1990 1991 /* 1992 * Limit the number of blocks transferred so that we don't overflow 1993 * the maximum request size. 1994 */ 1995 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 1996 1997 spin_lock_init(&host->lock); 1998 1999 writel(0, host->base + MMCIMASK0); 2000 2001 if (variant->mmcimask1) 2002 writel(0, host->base + MMCIMASK1); 2003 2004 writel(0xfff, host->base + MMCICLEAR); 2005 2006 /* 2007 * If: 2008 * - not using DT but using a descriptor table, or 2009 * - using a table of descriptors ALONGSIDE DT, or 2010 * look up these descriptors named "cd" and "wp" right here, fail 2011 * silently of these do not exist 2012 */ 2013 if (!np) { 2014 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 2015 if (ret == -EPROBE_DEFER) 2016 goto clk_disable; 2017 2018 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL); 2019 if (ret == -EPROBE_DEFER) 2020 goto clk_disable; 2021 } 2022 2023 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 2024 DRIVER_NAME " (cmd)", host); 2025 if (ret) 2026 goto clk_disable; 2027 2028 if (!dev->irq[1]) 2029 host->singleirq = true; 2030 else { 2031 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2032 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2033 if (ret) 2034 goto clk_disable; 2035 } 2036 2037 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2038 2039 amba_set_drvdata(dev, mmc); 2040 2041 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2042 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2043 amba_rev(dev), (unsigned long long)dev->res.start, 2044 dev->irq[0], dev->irq[1]); 2045 2046 mmci_dma_setup(host); 2047 2048 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2049 pm_runtime_use_autosuspend(&dev->dev); 2050 2051 mmc_add_host(mmc); 2052 2053 pm_runtime_put(&dev->dev); 2054 return 0; 2055 2056 clk_disable: 2057 clk_disable_unprepare(host->clk); 2058 host_free: 2059 mmc_free_host(mmc); 2060 return ret; 2061 } 2062 2063 static int mmci_remove(struct amba_device *dev) 2064 { 2065 struct mmc_host *mmc = amba_get_drvdata(dev); 2066 2067 if (mmc) { 2068 struct mmci_host *host = mmc_priv(mmc); 2069 struct variant_data *variant = host->variant; 2070 2071 /* 2072 * Undo pm_runtime_put() in probe. We use the _sync 2073 * version here so that we can access the primecell. 2074 */ 2075 pm_runtime_get_sync(&dev->dev); 2076 2077 mmc_remove_host(mmc); 2078 2079 writel(0, host->base + MMCIMASK0); 2080 2081 if (variant->mmcimask1) 2082 writel(0, host->base + MMCIMASK1); 2083 2084 writel(0, host->base + MMCICOMMAND); 2085 writel(0, host->base + MMCIDATACTRL); 2086 2087 mmci_dma_release(host); 2088 clk_disable_unprepare(host->clk); 2089 mmc_free_host(mmc); 2090 } 2091 2092 return 0; 2093 } 2094 2095 #ifdef CONFIG_PM 2096 static void mmci_save(struct mmci_host *host) 2097 { 2098 unsigned long flags; 2099 2100 spin_lock_irqsave(&host->lock, flags); 2101 2102 writel(0, host->base + MMCIMASK0); 2103 if (host->variant->pwrreg_nopower) { 2104 writel(0, host->base + MMCIDATACTRL); 2105 writel(0, host->base + MMCIPOWER); 2106 writel(0, host->base + MMCICLOCK); 2107 } 2108 mmci_reg_delay(host); 2109 2110 spin_unlock_irqrestore(&host->lock, flags); 2111 } 2112 2113 static void mmci_restore(struct mmci_host *host) 2114 { 2115 unsigned long flags; 2116 2117 spin_lock_irqsave(&host->lock, flags); 2118 2119 if (host->variant->pwrreg_nopower) { 2120 writel(host->clk_reg, host->base + MMCICLOCK); 2121 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2122 writel(host->pwr_reg, host->base + MMCIPOWER); 2123 } 2124 writel(MCI_IRQENABLE | host->variant->start_err, 2125 host->base + MMCIMASK0); 2126 mmci_reg_delay(host); 2127 2128 spin_unlock_irqrestore(&host->lock, flags); 2129 } 2130 2131 static int mmci_runtime_suspend(struct device *dev) 2132 { 2133 struct amba_device *adev = to_amba_device(dev); 2134 struct mmc_host *mmc = amba_get_drvdata(adev); 2135 2136 if (mmc) { 2137 struct mmci_host *host = mmc_priv(mmc); 2138 pinctrl_pm_select_sleep_state(dev); 2139 mmci_save(host); 2140 clk_disable_unprepare(host->clk); 2141 } 2142 2143 return 0; 2144 } 2145 2146 static int mmci_runtime_resume(struct device *dev) 2147 { 2148 struct amba_device *adev = to_amba_device(dev); 2149 struct mmc_host *mmc = amba_get_drvdata(adev); 2150 2151 if (mmc) { 2152 struct mmci_host *host = mmc_priv(mmc); 2153 clk_prepare_enable(host->clk); 2154 mmci_restore(host); 2155 pinctrl_pm_select_default_state(dev); 2156 } 2157 2158 return 0; 2159 } 2160 #endif 2161 2162 static const struct dev_pm_ops mmci_dev_pm_ops = { 2163 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2164 pm_runtime_force_resume) 2165 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2166 }; 2167 2168 static const struct amba_id mmci_ids[] = { 2169 { 2170 .id = 0x00041180, 2171 .mask = 0xff0fffff, 2172 .data = &variant_arm, 2173 }, 2174 { 2175 .id = 0x01041180, 2176 .mask = 0xff0fffff, 2177 .data = &variant_arm_extended_fifo, 2178 }, 2179 { 2180 .id = 0x02041180, 2181 .mask = 0xff0fffff, 2182 .data = &variant_arm_extended_fifo_hwfc, 2183 }, 2184 { 2185 .id = 0x00041181, 2186 .mask = 0x000fffff, 2187 .data = &variant_arm, 2188 }, 2189 /* ST Micro variants */ 2190 { 2191 .id = 0x00180180, 2192 .mask = 0x00ffffff, 2193 .data = &variant_u300, 2194 }, 2195 { 2196 .id = 0x10180180, 2197 .mask = 0xf0ffffff, 2198 .data = &variant_nomadik, 2199 }, 2200 { 2201 .id = 0x00280180, 2202 .mask = 0x00ffffff, 2203 .data = &variant_nomadik, 2204 }, 2205 { 2206 .id = 0x00480180, 2207 .mask = 0xf0ffffff, 2208 .data = &variant_ux500, 2209 }, 2210 { 2211 .id = 0x10480180, 2212 .mask = 0xf0ffffff, 2213 .data = &variant_ux500v2, 2214 }, 2215 { 2216 .id = 0x00880180, 2217 .mask = 0x00ffffff, 2218 .data = &variant_stm32, 2219 }, 2220 { 2221 .id = 0x10153180, 2222 .mask = 0xf0ffffff, 2223 .data = &variant_stm32_sdmmc, 2224 }, 2225 /* Qualcomm variants */ 2226 { 2227 .id = 0x00051180, 2228 .mask = 0x000fffff, 2229 .data = &variant_qcom, 2230 }, 2231 { 0, 0 }, 2232 }; 2233 2234 MODULE_DEVICE_TABLE(amba, mmci_ids); 2235 2236 static struct amba_driver mmci_driver = { 2237 .drv = { 2238 .name = DRIVER_NAME, 2239 .pm = &mmci_dev_pm_ops, 2240 }, 2241 .probe = mmci_probe, 2242 .remove = mmci_remove, 2243 .id_table = mmci_ids, 2244 }; 2245 2246 module_amba_driver(mmci_driver); 2247 2248 module_param(fmax, uint, 0444); 2249 2250 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2251 MODULE_LICENSE("GPL"); 2252