1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/of.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/amba/mmci.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/types.h> 38 #include <linux/pinctrl/consumer.h> 39 40 #include <asm/div64.h> 41 #include <asm/io.h> 42 43 #include "mmci.h" 44 #include "mmci_qcom_dml.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 #ifdef CONFIG_DMA_ENGINE 49 void mmci_variant_init(struct mmci_host *host); 50 #else 51 static inline void mmci_variant_init(struct mmci_host *host) {} 52 #endif 53 54 static unsigned int fmax = 515633; 55 56 static struct variant_data variant_arm = { 57 .fifosize = 16 * 4, 58 .fifohalfsize = 8 * 4, 59 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 60 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 61 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 62 .cmdreg_srsp = MCI_CPSM_RESPONSE, 63 .datalength_bits = 16, 64 .datactrl_blocksz = 11, 65 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 66 .pwrreg_powerup = MCI_PWR_UP, 67 .f_max = 100000000, 68 .reversed_irq_handling = true, 69 .mmcimask1 = true, 70 .irq_pio_mask = MCI_IRQ_PIO_MASK, 71 .start_err = MCI_STARTBITERR, 72 .opendrain = MCI_ROD, 73 .init = mmci_variant_init, 74 }; 75 76 static struct variant_data variant_arm_extended_fifo = { 77 .fifosize = 128 * 4, 78 .fifohalfsize = 64 * 4, 79 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 80 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 81 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 82 .cmdreg_srsp = MCI_CPSM_RESPONSE, 83 .datalength_bits = 16, 84 .datactrl_blocksz = 11, 85 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 86 .pwrreg_powerup = MCI_PWR_UP, 87 .f_max = 100000000, 88 .mmcimask1 = true, 89 .irq_pio_mask = MCI_IRQ_PIO_MASK, 90 .start_err = MCI_STARTBITERR, 91 .opendrain = MCI_ROD, 92 .init = mmci_variant_init, 93 }; 94 95 static struct variant_data variant_arm_extended_fifo_hwfc = { 96 .fifosize = 128 * 4, 97 .fifohalfsize = 64 * 4, 98 .clkreg_enable = MCI_ARM_HWFCEN, 99 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 100 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 101 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 102 .cmdreg_srsp = MCI_CPSM_RESPONSE, 103 .datalength_bits = 16, 104 .datactrl_blocksz = 11, 105 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 106 .pwrreg_powerup = MCI_PWR_UP, 107 .f_max = 100000000, 108 .mmcimask1 = true, 109 .irq_pio_mask = MCI_IRQ_PIO_MASK, 110 .start_err = MCI_STARTBITERR, 111 .opendrain = MCI_ROD, 112 .init = mmci_variant_init, 113 }; 114 115 static struct variant_data variant_u300 = { 116 .fifosize = 16 * 4, 117 .fifohalfsize = 8 * 4, 118 .clkreg_enable = MCI_ST_U300_HWFCEN, 119 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 120 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 121 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 122 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 123 .cmdreg_srsp = MCI_CPSM_RESPONSE, 124 .datalength_bits = 16, 125 .datactrl_blocksz = 11, 126 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 127 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 128 .st_sdio = true, 129 .pwrreg_powerup = MCI_PWR_ON, 130 .f_max = 100000000, 131 .signal_direction = true, 132 .pwrreg_clkgate = true, 133 .pwrreg_nopower = true, 134 .mmcimask1 = true, 135 .irq_pio_mask = MCI_IRQ_PIO_MASK, 136 .start_err = MCI_STARTBITERR, 137 .opendrain = MCI_OD, 138 .init = mmci_variant_init, 139 }; 140 141 static struct variant_data variant_nomadik = { 142 .fifosize = 16 * 4, 143 .fifohalfsize = 8 * 4, 144 .clkreg = MCI_CLK_ENABLE, 145 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 146 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 147 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 148 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 149 .cmdreg_srsp = MCI_CPSM_RESPONSE, 150 .datalength_bits = 24, 151 .datactrl_blocksz = 11, 152 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 153 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 154 .st_sdio = true, 155 .st_clkdiv = true, 156 .pwrreg_powerup = MCI_PWR_ON, 157 .f_max = 100000000, 158 .signal_direction = true, 159 .pwrreg_clkgate = true, 160 .pwrreg_nopower = true, 161 .mmcimask1 = true, 162 .irq_pio_mask = MCI_IRQ_PIO_MASK, 163 .start_err = MCI_STARTBITERR, 164 .opendrain = MCI_OD, 165 .init = mmci_variant_init, 166 }; 167 168 static struct variant_data variant_ux500 = { 169 .fifosize = 30 * 4, 170 .fifohalfsize = 8 * 4, 171 .clkreg = MCI_CLK_ENABLE, 172 .clkreg_enable = MCI_ST_UX500_HWFCEN, 173 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 174 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 175 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 176 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 177 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 178 .cmdreg_srsp = MCI_CPSM_RESPONSE, 179 .datalength_bits = 24, 180 .datactrl_blocksz = 11, 181 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 182 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 183 .st_sdio = true, 184 .st_clkdiv = true, 185 .pwrreg_powerup = MCI_PWR_ON, 186 .f_max = 100000000, 187 .signal_direction = true, 188 .pwrreg_clkgate = true, 189 .busy_detect = true, 190 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 191 .busy_detect_flag = MCI_ST_CARDBUSY, 192 .busy_detect_mask = MCI_ST_BUSYENDMASK, 193 .pwrreg_nopower = true, 194 .mmcimask1 = true, 195 .irq_pio_mask = MCI_IRQ_PIO_MASK, 196 .start_err = MCI_STARTBITERR, 197 .opendrain = MCI_OD, 198 .init = mmci_variant_init, 199 }; 200 201 static struct variant_data variant_ux500v2 = { 202 .fifosize = 30 * 4, 203 .fifohalfsize = 8 * 4, 204 .clkreg = MCI_CLK_ENABLE, 205 .clkreg_enable = MCI_ST_UX500_HWFCEN, 206 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 207 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 208 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 209 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 210 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 211 .cmdreg_srsp = MCI_CPSM_RESPONSE, 212 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 213 .datalength_bits = 24, 214 .datactrl_blocksz = 11, 215 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 216 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 217 .st_sdio = true, 218 .st_clkdiv = true, 219 .blksz_datactrl16 = true, 220 .pwrreg_powerup = MCI_PWR_ON, 221 .f_max = 100000000, 222 .signal_direction = true, 223 .pwrreg_clkgate = true, 224 .busy_detect = true, 225 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 226 .busy_detect_flag = MCI_ST_CARDBUSY, 227 .busy_detect_mask = MCI_ST_BUSYENDMASK, 228 .pwrreg_nopower = true, 229 .mmcimask1 = true, 230 .irq_pio_mask = MCI_IRQ_PIO_MASK, 231 .start_err = MCI_STARTBITERR, 232 .opendrain = MCI_OD, 233 .init = mmci_variant_init, 234 }; 235 236 static struct variant_data variant_stm32 = { 237 .fifosize = 32 * 4, 238 .fifohalfsize = 8 * 4, 239 .clkreg = MCI_CLK_ENABLE, 240 .clkreg_enable = MCI_ST_UX500_HWFCEN, 241 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 242 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 243 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 244 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 245 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 246 .cmdreg_srsp = MCI_CPSM_RESPONSE, 247 .irq_pio_mask = MCI_IRQ_PIO_MASK, 248 .datalength_bits = 24, 249 .datactrl_blocksz = 11, 250 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 251 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 252 .st_sdio = true, 253 .st_clkdiv = true, 254 .pwrreg_powerup = MCI_PWR_ON, 255 .f_max = 48000000, 256 .pwrreg_clkgate = true, 257 .pwrreg_nopower = true, 258 .init = mmci_variant_init, 259 }; 260 261 static struct variant_data variant_qcom = { 262 .fifosize = 16 * 4, 263 .fifohalfsize = 8 * 4, 264 .clkreg = MCI_CLK_ENABLE, 265 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 266 MCI_QCOM_CLK_SELECT_IN_FBCLK, 267 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 268 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 269 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 270 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 271 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 272 .cmdreg_srsp = MCI_CPSM_RESPONSE, 273 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 274 .blksz_datactrl4 = true, 275 .datalength_bits = 24, 276 .datactrl_blocksz = 11, 277 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 278 .pwrreg_powerup = MCI_PWR_UP, 279 .f_max = 208000000, 280 .explicit_mclk_control = true, 281 .qcom_fifo = true, 282 .qcom_dml = true, 283 .mmcimask1 = true, 284 .irq_pio_mask = MCI_IRQ_PIO_MASK, 285 .start_err = MCI_STARTBITERR, 286 .opendrain = MCI_ROD, 287 .init = qcom_variant_init, 288 }; 289 290 /* Busy detection for the ST Micro variant */ 291 static int mmci_card_busy(struct mmc_host *mmc) 292 { 293 struct mmci_host *host = mmc_priv(mmc); 294 unsigned long flags; 295 int busy = 0; 296 297 spin_lock_irqsave(&host->lock, flags); 298 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 299 busy = 1; 300 spin_unlock_irqrestore(&host->lock, flags); 301 302 return busy; 303 } 304 305 static void mmci_reg_delay(struct mmci_host *host) 306 { 307 /* 308 * According to the spec, at least three feedback clock cycles 309 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 310 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 311 * Worst delay time during card init is at 100 kHz => 30 us. 312 * Worst delay time when up and running is at 25 MHz => 120 ns. 313 */ 314 if (host->cclk < 25000000) 315 udelay(30); 316 else 317 ndelay(120); 318 } 319 320 /* 321 * This must be called with host->lock held 322 */ 323 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 324 { 325 if (host->clk_reg != clk) { 326 host->clk_reg = clk; 327 writel(clk, host->base + MMCICLOCK); 328 } 329 } 330 331 /* 332 * This must be called with host->lock held 333 */ 334 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 335 { 336 if (host->pwr_reg != pwr) { 337 host->pwr_reg = pwr; 338 writel(pwr, host->base + MMCIPOWER); 339 } 340 } 341 342 /* 343 * This must be called with host->lock held 344 */ 345 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 346 { 347 /* Keep busy mode in DPSM if enabled */ 348 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 349 350 if (host->datactrl_reg != datactrl) { 351 host->datactrl_reg = datactrl; 352 writel(datactrl, host->base + MMCIDATACTRL); 353 } 354 } 355 356 /* 357 * This must be called with host->lock held 358 */ 359 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 360 { 361 struct variant_data *variant = host->variant; 362 u32 clk = variant->clkreg; 363 364 /* Make sure cclk reflects the current calculated clock */ 365 host->cclk = 0; 366 367 if (desired) { 368 if (variant->explicit_mclk_control) { 369 host->cclk = host->mclk; 370 } else if (desired >= host->mclk) { 371 clk = MCI_CLK_BYPASS; 372 if (variant->st_clkdiv) 373 clk |= MCI_ST_UX500_NEG_EDGE; 374 host->cclk = host->mclk; 375 } else if (variant->st_clkdiv) { 376 /* 377 * DB8500 TRM says f = mclk / (clkdiv + 2) 378 * => clkdiv = (mclk / f) - 2 379 * Round the divider up so we don't exceed the max 380 * frequency 381 */ 382 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 383 if (clk >= 256) 384 clk = 255; 385 host->cclk = host->mclk / (clk + 2); 386 } else { 387 /* 388 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 389 * => clkdiv = mclk / (2 * f) - 1 390 */ 391 clk = host->mclk / (2 * desired) - 1; 392 if (clk >= 256) 393 clk = 255; 394 host->cclk = host->mclk / (2 * (clk + 1)); 395 } 396 397 clk |= variant->clkreg_enable; 398 clk |= MCI_CLK_ENABLE; 399 /* This hasn't proven to be worthwhile */ 400 /* clk |= MCI_CLK_PWRSAVE; */ 401 } 402 403 /* Set actual clock for debug */ 404 host->mmc->actual_clock = host->cclk; 405 406 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 407 clk |= MCI_4BIT_BUS; 408 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 409 clk |= variant->clkreg_8bit_bus_enable; 410 411 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 412 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 413 clk |= variant->clkreg_neg_edge_enable; 414 415 mmci_write_clkreg(host, clk); 416 } 417 418 void mmci_dma_release(struct mmci_host *host) 419 { 420 if (host->ops && host->ops->dma_release) 421 host->ops->dma_release(host); 422 423 host->use_dma = false; 424 } 425 426 void mmci_dma_setup(struct mmci_host *host) 427 { 428 if (!host->ops || !host->ops->dma_setup) 429 return; 430 431 if (host->ops->dma_setup(host)) 432 return; 433 434 /* initialize pre request cookie */ 435 host->next_cookie = 1; 436 437 host->use_dma = true; 438 } 439 440 /* 441 * Validate mmc prerequisites 442 */ 443 static int mmci_validate_data(struct mmci_host *host, 444 struct mmc_data *data) 445 { 446 if (!data) 447 return 0; 448 449 if (!is_power_of_2(data->blksz)) { 450 dev_err(mmc_dev(host->mmc), 451 "unsupported block size (%d bytes)\n", data->blksz); 452 return -EINVAL; 453 } 454 455 if (host->ops && host->ops->validate_data) 456 return host->ops->validate_data(host, data); 457 458 return 0; 459 } 460 461 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 462 { 463 int err; 464 465 if (!host->ops || !host->ops->prep_data) 466 return 0; 467 468 err = host->ops->prep_data(host, data, next); 469 470 if (next && !err) 471 data->host_cookie = ++host->next_cookie < 0 ? 472 1 : host->next_cookie; 473 474 return err; 475 } 476 477 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 478 int err) 479 { 480 if (host->ops && host->ops->unprep_data) 481 host->ops->unprep_data(host, data, err); 482 483 data->host_cookie = 0; 484 } 485 486 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 487 { 488 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 489 490 if (host->ops && host->ops->get_next_data) 491 host->ops->get_next_data(host, data); 492 } 493 494 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 495 { 496 struct mmc_data *data = host->data; 497 int ret; 498 499 if (!host->use_dma) 500 return -EINVAL; 501 502 ret = mmci_prep_data(host, data, false); 503 if (ret) 504 return ret; 505 506 if (!host->ops || !host->ops->dma_start) 507 return -EINVAL; 508 509 /* Okay, go for it. */ 510 dev_vdbg(mmc_dev(host->mmc), 511 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 512 data->sg_len, data->blksz, data->blocks, data->flags); 513 514 host->ops->dma_start(host, &datactrl); 515 516 /* Trigger the DMA transfer */ 517 mmci_write_datactrlreg(host, datactrl); 518 519 /* 520 * Let the MMCI say when the data is ended and it's time 521 * to fire next DMA request. When that happens, MMCI will 522 * call mmci_data_end() 523 */ 524 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 525 host->base + MMCIMASK0); 526 return 0; 527 } 528 529 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 530 { 531 if (!host->use_dma) 532 return; 533 534 if (host->ops && host->ops->dma_finalize) 535 host->ops->dma_finalize(host, data); 536 } 537 538 void mmci_dma_error(struct mmci_host *host) 539 { 540 if (!host->use_dma) 541 return; 542 543 if (host->ops && host->ops->dma_error) 544 host->ops->dma_error(host); 545 } 546 547 static void 548 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 549 { 550 writel(0, host->base + MMCICOMMAND); 551 552 BUG_ON(host->data); 553 554 host->mrq = NULL; 555 host->cmd = NULL; 556 557 mmc_request_done(host->mmc, mrq); 558 } 559 560 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 561 { 562 void __iomem *base = host->base; 563 struct variant_data *variant = host->variant; 564 565 if (host->singleirq) { 566 unsigned int mask0 = readl(base + MMCIMASK0); 567 568 mask0 &= ~variant->irq_pio_mask; 569 mask0 |= mask; 570 571 writel(mask0, base + MMCIMASK0); 572 } 573 574 if (variant->mmcimask1) 575 writel(mask, base + MMCIMASK1); 576 577 host->mask1_reg = mask; 578 } 579 580 static void mmci_stop_data(struct mmci_host *host) 581 { 582 mmci_write_datactrlreg(host, 0); 583 mmci_set_mask1(host, 0); 584 host->data = NULL; 585 } 586 587 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 588 { 589 unsigned int flags = SG_MITER_ATOMIC; 590 591 if (data->flags & MMC_DATA_READ) 592 flags |= SG_MITER_TO_SG; 593 else 594 flags |= SG_MITER_FROM_SG; 595 596 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 597 } 598 599 /* 600 * All the DMA operation mode stuff goes inside this ifdef. 601 * This assumes that you have a generic DMA device interface, 602 * no custom DMA interfaces are supported. 603 */ 604 #ifdef CONFIG_DMA_ENGINE 605 struct mmci_dmae_next { 606 struct dma_async_tx_descriptor *desc; 607 struct dma_chan *chan; 608 }; 609 610 struct mmci_dmae_priv { 611 struct dma_chan *cur; 612 struct dma_chan *rx_channel; 613 struct dma_chan *tx_channel; 614 struct dma_async_tx_descriptor *desc_current; 615 struct mmci_dmae_next next_data; 616 }; 617 618 int mmci_dmae_setup(struct mmci_host *host) 619 { 620 const char *rxname, *txname; 621 struct mmci_dmae_priv *dmae; 622 623 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 624 if (!dmae) 625 return -ENOMEM; 626 627 host->dma_priv = dmae; 628 629 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 630 "rx"); 631 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 632 "tx"); 633 634 /* 635 * If only an RX channel is specified, the driver will 636 * attempt to use it bidirectionally, however if it is 637 * is specified but cannot be located, DMA will be disabled. 638 */ 639 if (dmae->rx_channel && !dmae->tx_channel) 640 dmae->tx_channel = dmae->rx_channel; 641 642 if (dmae->rx_channel) 643 rxname = dma_chan_name(dmae->rx_channel); 644 else 645 rxname = "none"; 646 647 if (dmae->tx_channel) 648 txname = dma_chan_name(dmae->tx_channel); 649 else 650 txname = "none"; 651 652 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 653 rxname, txname); 654 655 /* 656 * Limit the maximum segment size in any SG entry according to 657 * the parameters of the DMA engine device. 658 */ 659 if (dmae->tx_channel) { 660 struct device *dev = dmae->tx_channel->device->dev; 661 unsigned int max_seg_size = dma_get_max_seg_size(dev); 662 663 if (max_seg_size < host->mmc->max_seg_size) 664 host->mmc->max_seg_size = max_seg_size; 665 } 666 if (dmae->rx_channel) { 667 struct device *dev = dmae->rx_channel->device->dev; 668 unsigned int max_seg_size = dma_get_max_seg_size(dev); 669 670 if (max_seg_size < host->mmc->max_seg_size) 671 host->mmc->max_seg_size = max_seg_size; 672 } 673 674 if (!dmae->tx_channel || !dmae->rx_channel) { 675 mmci_dmae_release(host); 676 return -EINVAL; 677 } 678 679 return 0; 680 } 681 682 /* 683 * This is used in or so inline it 684 * so it can be discarded. 685 */ 686 void mmci_dmae_release(struct mmci_host *host) 687 { 688 struct mmci_dmae_priv *dmae = host->dma_priv; 689 690 if (dmae->rx_channel) 691 dma_release_channel(dmae->rx_channel); 692 if (dmae->tx_channel) 693 dma_release_channel(dmae->tx_channel); 694 dmae->rx_channel = dmae->tx_channel = NULL; 695 } 696 697 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 698 { 699 struct mmci_dmae_priv *dmae = host->dma_priv; 700 struct dma_chan *chan; 701 702 if (data->flags & MMC_DATA_READ) 703 chan = dmae->rx_channel; 704 else 705 chan = dmae->tx_channel; 706 707 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 708 mmc_get_dma_dir(data)); 709 } 710 711 void mmci_dmae_error(struct mmci_host *host) 712 { 713 struct mmci_dmae_priv *dmae = host->dma_priv; 714 715 if (!dma_inprogress(host)) 716 return; 717 718 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 719 dmaengine_terminate_all(dmae->cur); 720 host->dma_in_progress = false; 721 dmae->cur = NULL; 722 dmae->desc_current = NULL; 723 host->data->host_cookie = 0; 724 725 mmci_dma_unmap(host, host->data); 726 } 727 728 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 729 { 730 struct mmci_dmae_priv *dmae = host->dma_priv; 731 u32 status; 732 int i; 733 734 if (!dma_inprogress(host)) 735 return; 736 737 /* Wait up to 1ms for the DMA to complete */ 738 for (i = 0; ; i++) { 739 status = readl(host->base + MMCISTATUS); 740 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 741 break; 742 udelay(10); 743 } 744 745 /* 746 * Check to see whether we still have some data left in the FIFO - 747 * this catches DMA controllers which are unable to monitor the 748 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 749 * contiguous buffers. On TX, we'll get a FIFO underrun error. 750 */ 751 if (status & MCI_RXDATAAVLBLMASK) { 752 mmci_dma_error(host); 753 if (!data->error) 754 data->error = -EIO; 755 } else if (!data->host_cookie) { 756 mmci_dma_unmap(host, data); 757 } 758 759 /* 760 * Use of DMA with scatter-gather is impossible. 761 * Give up with DMA and switch back to PIO mode. 762 */ 763 if (status & MCI_RXDATAAVLBLMASK) { 764 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 765 mmci_dma_release(host); 766 } 767 768 host->dma_in_progress = false; 769 dmae->cur = NULL; 770 dmae->desc_current = NULL; 771 } 772 773 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 774 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 775 struct dma_chan **dma_chan, 776 struct dma_async_tx_descriptor **dma_desc) 777 { 778 struct mmci_dmae_priv *dmae = host->dma_priv; 779 struct variant_data *variant = host->variant; 780 struct dma_slave_config conf = { 781 .src_addr = host->phybase + MMCIFIFO, 782 .dst_addr = host->phybase + MMCIFIFO, 783 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 784 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 785 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 786 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 787 .device_fc = false, 788 }; 789 struct dma_chan *chan; 790 struct dma_device *device; 791 struct dma_async_tx_descriptor *desc; 792 int nr_sg; 793 unsigned long flags = DMA_CTRL_ACK; 794 795 if (data->flags & MMC_DATA_READ) { 796 conf.direction = DMA_DEV_TO_MEM; 797 chan = dmae->rx_channel; 798 } else { 799 conf.direction = DMA_MEM_TO_DEV; 800 chan = dmae->tx_channel; 801 } 802 803 /* If there's no DMA channel, fall back to PIO */ 804 if (!chan) 805 return -EINVAL; 806 807 /* If less than or equal to the fifo size, don't bother with DMA */ 808 if (data->blksz * data->blocks <= variant->fifosize) 809 return -EINVAL; 810 811 device = chan->device; 812 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 813 mmc_get_dma_dir(data)); 814 if (nr_sg == 0) 815 return -EINVAL; 816 817 if (host->variant->qcom_dml) 818 flags |= DMA_PREP_INTERRUPT; 819 820 dmaengine_slave_config(chan, &conf); 821 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 822 conf.direction, flags); 823 if (!desc) 824 goto unmap_exit; 825 826 *dma_chan = chan; 827 *dma_desc = desc; 828 829 return 0; 830 831 unmap_exit: 832 dma_unmap_sg(device->dev, data->sg, data->sg_len, 833 mmc_get_dma_dir(data)); 834 return -ENOMEM; 835 } 836 837 int mmci_dmae_prep_data(struct mmci_host *host, 838 struct mmc_data *data, 839 bool next) 840 { 841 struct mmci_dmae_priv *dmae = host->dma_priv; 842 struct mmci_dmae_next *nd = &dmae->next_data; 843 844 if (!host->use_dma) 845 return -EINVAL; 846 847 if (next) 848 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 849 /* Check if next job is already prepared. */ 850 if (dmae->cur && dmae->desc_current) 851 return 0; 852 853 /* No job were prepared thus do it now. */ 854 return _mmci_dmae_prep_data(host, data, &dmae->cur, 855 &dmae->desc_current); 856 } 857 858 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 859 { 860 struct mmci_dmae_priv *dmae = host->dma_priv; 861 struct mmc_data *data = host->data; 862 863 host->dma_in_progress = true; 864 dmaengine_submit(dmae->desc_current); 865 dma_async_issue_pending(dmae->cur); 866 867 if (host->variant->qcom_dml) 868 dml_start_xfer(host, data); 869 870 *datactrl |= MCI_DPSM_DMAENABLE; 871 872 return 0; 873 } 874 875 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 876 { 877 struct mmci_dmae_priv *dmae = host->dma_priv; 878 struct mmci_dmae_next *next = &dmae->next_data; 879 880 if (!host->use_dma) 881 return; 882 883 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 884 885 dmae->desc_current = next->desc; 886 dmae->cur = next->chan; 887 next->desc = NULL; 888 next->chan = NULL; 889 } 890 891 void mmci_dmae_unprep_data(struct mmci_host *host, 892 struct mmc_data *data, int err) 893 894 { 895 struct mmci_dmae_priv *dmae = host->dma_priv; 896 897 if (!host->use_dma) 898 return; 899 900 mmci_dma_unmap(host, data); 901 902 if (err) { 903 struct mmci_dmae_next *next = &dmae->next_data; 904 struct dma_chan *chan; 905 if (data->flags & MMC_DATA_READ) 906 chan = dmae->rx_channel; 907 else 908 chan = dmae->tx_channel; 909 dmaengine_terminate_all(chan); 910 911 if (dmae->desc_current == next->desc) 912 dmae->desc_current = NULL; 913 914 if (dmae->cur == next->chan) { 915 host->dma_in_progress = false; 916 dmae->cur = NULL; 917 } 918 919 next->desc = NULL; 920 next->chan = NULL; 921 } 922 } 923 924 static struct mmci_host_ops mmci_variant_ops = { 925 .prep_data = mmci_dmae_prep_data, 926 .unprep_data = mmci_dmae_unprep_data, 927 .get_next_data = mmci_dmae_get_next_data, 928 .dma_setup = mmci_dmae_setup, 929 .dma_release = mmci_dmae_release, 930 .dma_start = mmci_dmae_start, 931 .dma_finalize = mmci_dmae_finalize, 932 .dma_error = mmci_dmae_error, 933 }; 934 935 void mmci_variant_init(struct mmci_host *host) 936 { 937 host->ops = &mmci_variant_ops; 938 } 939 #endif 940 941 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 942 { 943 struct mmci_host *host = mmc_priv(mmc); 944 struct mmc_data *data = mrq->data; 945 946 if (!data) 947 return; 948 949 WARN_ON(data->host_cookie); 950 951 if (mmci_validate_data(host, data)) 952 return; 953 954 mmci_prep_data(host, data, true); 955 } 956 957 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 958 int err) 959 { 960 struct mmci_host *host = mmc_priv(mmc); 961 struct mmc_data *data = mrq->data; 962 963 if (!data || !data->host_cookie) 964 return; 965 966 mmci_unprep_data(host, data, err); 967 } 968 969 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 970 { 971 struct variant_data *variant = host->variant; 972 unsigned int datactrl, timeout, irqmask; 973 unsigned long long clks; 974 void __iomem *base; 975 int blksz_bits; 976 977 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 978 data->blksz, data->blocks, data->flags); 979 980 host->data = data; 981 host->size = data->blksz * data->blocks; 982 data->bytes_xfered = 0; 983 984 clks = (unsigned long long)data->timeout_ns * host->cclk; 985 do_div(clks, NSEC_PER_SEC); 986 987 timeout = data->timeout_clks + (unsigned int)clks; 988 989 base = host->base; 990 writel(timeout, base + MMCIDATATIMER); 991 writel(host->size, base + MMCIDATALENGTH); 992 993 blksz_bits = ffs(data->blksz) - 1; 994 BUG_ON(1 << blksz_bits != data->blksz); 995 996 if (variant->blksz_datactrl16) 997 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16); 998 else if (variant->blksz_datactrl4) 999 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4); 1000 else 1001 datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; 1002 1003 if (data->flags & MMC_DATA_READ) 1004 datactrl |= MCI_DPSM_DIRECTION; 1005 1006 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1007 u32 clk; 1008 1009 datactrl |= variant->datactrl_mask_sdio; 1010 1011 /* 1012 * The ST Micro variant for SDIO small write transfers 1013 * needs to have clock H/W flow control disabled, 1014 * otherwise the transfer will not start. The threshold 1015 * depends on the rate of MCLK. 1016 */ 1017 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1018 (host->size < 8 || 1019 (host->size <= 8 && host->mclk > 50000000))) 1020 clk = host->clk_reg & ~variant->clkreg_enable; 1021 else 1022 clk = host->clk_reg | variant->clkreg_enable; 1023 1024 mmci_write_clkreg(host, clk); 1025 } 1026 1027 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1028 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1029 datactrl |= variant->datactrl_mask_ddrmode; 1030 1031 /* 1032 * Attempt to use DMA operation mode, if this 1033 * should fail, fall back to PIO mode 1034 */ 1035 if (!mmci_dma_start(host, datactrl)) 1036 return; 1037 1038 /* IRQ mode, map the SG list for CPU reading/writing */ 1039 mmci_init_sg(host, data); 1040 1041 if (data->flags & MMC_DATA_READ) { 1042 irqmask = MCI_RXFIFOHALFFULLMASK; 1043 1044 /* 1045 * If we have less than the fifo 'half-full' threshold to 1046 * transfer, trigger a PIO interrupt as soon as any data 1047 * is available. 1048 */ 1049 if (host->size < variant->fifohalfsize) 1050 irqmask |= MCI_RXDATAAVLBLMASK; 1051 } else { 1052 /* 1053 * We don't actually need to include "FIFO empty" here 1054 * since its implicit in "FIFO half empty". 1055 */ 1056 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1057 } 1058 1059 mmci_write_datactrlreg(host, datactrl); 1060 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1061 mmci_set_mask1(host, irqmask); 1062 } 1063 1064 static void 1065 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1066 { 1067 void __iomem *base = host->base; 1068 1069 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1070 cmd->opcode, cmd->arg, cmd->flags); 1071 1072 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1073 writel(0, base + MMCICOMMAND); 1074 mmci_reg_delay(host); 1075 } 1076 1077 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1078 if (cmd->flags & MMC_RSP_PRESENT) { 1079 if (cmd->flags & MMC_RSP_136) 1080 c |= host->variant->cmdreg_lrsp_crc; 1081 else if (cmd->flags & MMC_RSP_CRC) 1082 c |= host->variant->cmdreg_srsp_crc; 1083 else 1084 c |= host->variant->cmdreg_srsp; 1085 } 1086 if (/*interrupt*/0) 1087 c |= MCI_CPSM_INTERRUPT; 1088 1089 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1090 c |= host->variant->data_cmd_enable; 1091 1092 host->cmd = cmd; 1093 1094 writel(cmd->arg, base + MMCIARGUMENT); 1095 writel(c, base + MMCICOMMAND); 1096 } 1097 1098 static void 1099 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1100 unsigned int status) 1101 { 1102 unsigned int status_err; 1103 1104 /* Make sure we have data to handle */ 1105 if (!data) 1106 return; 1107 1108 /* First check for errors */ 1109 status_err = status & (host->variant->start_err | 1110 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1111 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1112 1113 if (status_err) { 1114 u32 remain, success; 1115 1116 /* Terminate the DMA transfer */ 1117 mmci_dma_error(host); 1118 1119 /* 1120 * Calculate how far we are into the transfer. Note that 1121 * the data counter gives the number of bytes transferred 1122 * on the MMC bus, not on the host side. On reads, this 1123 * can be as much as a FIFO-worth of data ahead. This 1124 * matters for FIFO overruns only. 1125 */ 1126 if (!host->variant->datacnt_useless) { 1127 remain = readl(host->base + MMCIDATACNT); 1128 success = data->blksz * data->blocks - remain; 1129 } else { 1130 success = 0; 1131 } 1132 1133 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1134 status_err, success); 1135 if (status_err & MCI_DATACRCFAIL) { 1136 /* Last block was not successful */ 1137 success -= 1; 1138 data->error = -EILSEQ; 1139 } else if (status_err & MCI_DATATIMEOUT) { 1140 data->error = -ETIMEDOUT; 1141 } else if (status_err & MCI_STARTBITERR) { 1142 data->error = -ECOMM; 1143 } else if (status_err & MCI_TXUNDERRUN) { 1144 data->error = -EIO; 1145 } else if (status_err & MCI_RXOVERRUN) { 1146 if (success > host->variant->fifosize) 1147 success -= host->variant->fifosize; 1148 else 1149 success = 0; 1150 data->error = -EIO; 1151 } 1152 data->bytes_xfered = round_down(success, data->blksz); 1153 } 1154 1155 if (status & MCI_DATABLOCKEND) 1156 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1157 1158 if (status & MCI_DATAEND || data->error) { 1159 mmci_dma_finalize(host, data); 1160 1161 mmci_stop_data(host); 1162 1163 if (!data->error) 1164 /* The error clause is handled above, success! */ 1165 data->bytes_xfered = data->blksz * data->blocks; 1166 1167 if (!data->stop || host->mrq->sbc) { 1168 mmci_request_end(host, data->mrq); 1169 } else { 1170 mmci_start_command(host, data->stop, 0); 1171 } 1172 } 1173 } 1174 1175 static void 1176 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1177 unsigned int status) 1178 { 1179 void __iomem *base = host->base; 1180 bool sbc; 1181 1182 if (!cmd) 1183 return; 1184 1185 sbc = (cmd == host->mrq->sbc); 1186 1187 /* 1188 * We need to be one of these interrupts to be considered worth 1189 * handling. Note that we tag on any latent IRQs postponed 1190 * due to waiting for busy status. 1191 */ 1192 if (!((status|host->busy_status) & 1193 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1194 return; 1195 1196 /* 1197 * ST Micro variant: handle busy detection. 1198 */ 1199 if (host->variant->busy_detect) { 1200 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1201 1202 /* We are busy with a command, return */ 1203 if (host->busy_status && 1204 (status & host->variant->busy_detect_flag)) 1205 return; 1206 1207 /* 1208 * We were not busy, but we now got a busy response on 1209 * something that was not an error, and we double-check 1210 * that the special busy status bit is still set before 1211 * proceeding. 1212 */ 1213 if (!host->busy_status && busy_resp && 1214 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1215 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1216 1217 /* Clear the busy start IRQ */ 1218 writel(host->variant->busy_detect_mask, 1219 host->base + MMCICLEAR); 1220 1221 /* Unmask the busy end IRQ */ 1222 writel(readl(base + MMCIMASK0) | 1223 host->variant->busy_detect_mask, 1224 base + MMCIMASK0); 1225 /* 1226 * Now cache the last response status code (until 1227 * the busy bit goes low), and return. 1228 */ 1229 host->busy_status = 1230 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1231 return; 1232 } 1233 1234 /* 1235 * At this point we are not busy with a command, we have 1236 * not received a new busy request, clear and mask the busy 1237 * end IRQ and fall through to process the IRQ. 1238 */ 1239 if (host->busy_status) { 1240 1241 writel(host->variant->busy_detect_mask, 1242 host->base + MMCICLEAR); 1243 1244 writel(readl(base + MMCIMASK0) & 1245 ~host->variant->busy_detect_mask, 1246 base + MMCIMASK0); 1247 host->busy_status = 0; 1248 } 1249 } 1250 1251 host->cmd = NULL; 1252 1253 if (status & MCI_CMDTIMEOUT) { 1254 cmd->error = -ETIMEDOUT; 1255 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1256 cmd->error = -EILSEQ; 1257 } else { 1258 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1259 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1260 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1261 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1262 } 1263 1264 if ((!sbc && !cmd->data) || cmd->error) { 1265 if (host->data) { 1266 /* Terminate the DMA transfer */ 1267 mmci_dma_error(host); 1268 1269 mmci_stop_data(host); 1270 } 1271 mmci_request_end(host, host->mrq); 1272 } else if (sbc) { 1273 mmci_start_command(host, host->mrq->cmd, 0); 1274 } else if (!host->variant->datactrl_first && 1275 !(cmd->data->flags & MMC_DATA_READ)) { 1276 mmci_start_data(host, cmd->data); 1277 } 1278 } 1279 1280 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1281 { 1282 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1283 } 1284 1285 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1286 { 1287 /* 1288 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1289 * from the fifo range should be used 1290 */ 1291 if (status & MCI_RXFIFOHALFFULL) 1292 return host->variant->fifohalfsize; 1293 else if (status & MCI_RXDATAAVLBL) 1294 return 4; 1295 1296 return 0; 1297 } 1298 1299 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1300 { 1301 void __iomem *base = host->base; 1302 char *ptr = buffer; 1303 u32 status = readl(host->base + MMCISTATUS); 1304 int host_remain = host->size; 1305 1306 do { 1307 int count = host->get_rx_fifocnt(host, status, host_remain); 1308 1309 if (count > remain) 1310 count = remain; 1311 1312 if (count <= 0) 1313 break; 1314 1315 /* 1316 * SDIO especially may want to send something that is 1317 * not divisible by 4 (as opposed to card sectors 1318 * etc). Therefore make sure to always read the last bytes 1319 * while only doing full 32-bit reads towards the FIFO. 1320 */ 1321 if (unlikely(count & 0x3)) { 1322 if (count < 4) { 1323 unsigned char buf[4]; 1324 ioread32_rep(base + MMCIFIFO, buf, 1); 1325 memcpy(ptr, buf, count); 1326 } else { 1327 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1328 count &= ~0x3; 1329 } 1330 } else { 1331 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1332 } 1333 1334 ptr += count; 1335 remain -= count; 1336 host_remain -= count; 1337 1338 if (remain == 0) 1339 break; 1340 1341 status = readl(base + MMCISTATUS); 1342 } while (status & MCI_RXDATAAVLBL); 1343 1344 return ptr - buffer; 1345 } 1346 1347 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1348 { 1349 struct variant_data *variant = host->variant; 1350 void __iomem *base = host->base; 1351 char *ptr = buffer; 1352 1353 do { 1354 unsigned int count, maxcnt; 1355 1356 maxcnt = status & MCI_TXFIFOEMPTY ? 1357 variant->fifosize : variant->fifohalfsize; 1358 count = min(remain, maxcnt); 1359 1360 /* 1361 * SDIO especially may want to send something that is 1362 * not divisible by 4 (as opposed to card sectors 1363 * etc), and the FIFO only accept full 32-bit writes. 1364 * So compensate by adding +3 on the count, a single 1365 * byte become a 32bit write, 7 bytes will be two 1366 * 32bit writes etc. 1367 */ 1368 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1369 1370 ptr += count; 1371 remain -= count; 1372 1373 if (remain == 0) 1374 break; 1375 1376 status = readl(base + MMCISTATUS); 1377 } while (status & MCI_TXFIFOHALFEMPTY); 1378 1379 return ptr - buffer; 1380 } 1381 1382 /* 1383 * PIO data transfer IRQ handler. 1384 */ 1385 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1386 { 1387 struct mmci_host *host = dev_id; 1388 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1389 struct variant_data *variant = host->variant; 1390 void __iomem *base = host->base; 1391 u32 status; 1392 1393 status = readl(base + MMCISTATUS); 1394 1395 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1396 1397 do { 1398 unsigned int remain, len; 1399 char *buffer; 1400 1401 /* 1402 * For write, we only need to test the half-empty flag 1403 * here - if the FIFO is completely empty, then by 1404 * definition it is more than half empty. 1405 * 1406 * For read, check for data available. 1407 */ 1408 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1409 break; 1410 1411 if (!sg_miter_next(sg_miter)) 1412 break; 1413 1414 buffer = sg_miter->addr; 1415 remain = sg_miter->length; 1416 1417 len = 0; 1418 if (status & MCI_RXACTIVE) 1419 len = mmci_pio_read(host, buffer, remain); 1420 if (status & MCI_TXACTIVE) 1421 len = mmci_pio_write(host, buffer, remain, status); 1422 1423 sg_miter->consumed = len; 1424 1425 host->size -= len; 1426 remain -= len; 1427 1428 if (remain) 1429 break; 1430 1431 status = readl(base + MMCISTATUS); 1432 } while (1); 1433 1434 sg_miter_stop(sg_miter); 1435 1436 /* 1437 * If we have less than the fifo 'half-full' threshold to transfer, 1438 * trigger a PIO interrupt as soon as any data is available. 1439 */ 1440 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1441 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1442 1443 /* 1444 * If we run out of data, disable the data IRQs; this 1445 * prevents a race where the FIFO becomes empty before 1446 * the chip itself has disabled the data path, and 1447 * stops us racing with our data end IRQ. 1448 */ 1449 if (host->size == 0) { 1450 mmci_set_mask1(host, 0); 1451 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1452 } 1453 1454 return IRQ_HANDLED; 1455 } 1456 1457 /* 1458 * Handle completion of command and data transfers. 1459 */ 1460 static irqreturn_t mmci_irq(int irq, void *dev_id) 1461 { 1462 struct mmci_host *host = dev_id; 1463 u32 status; 1464 int ret = 0; 1465 1466 spin_lock(&host->lock); 1467 1468 do { 1469 status = readl(host->base + MMCISTATUS); 1470 1471 if (host->singleirq) { 1472 if (status & host->mask1_reg) 1473 mmci_pio_irq(irq, dev_id); 1474 1475 status &= ~host->variant->irq_pio_mask; 1476 } 1477 1478 /* 1479 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1480 * enabled) in mmci_cmd_irq() function where ST Micro busy 1481 * detection variant is handled. Considering the HW seems to be 1482 * triggering the IRQ on both edges while monitoring DAT0 for 1483 * busy completion and that same status bit is used to monitor 1484 * start and end of busy detection, special care must be taken 1485 * to make sure that both start and end interrupts are always 1486 * cleared one after the other. 1487 */ 1488 status &= readl(host->base + MMCIMASK0); 1489 if (host->variant->busy_detect) 1490 writel(status & ~host->variant->busy_detect_mask, 1491 host->base + MMCICLEAR); 1492 else 1493 writel(status, host->base + MMCICLEAR); 1494 1495 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1496 1497 if (host->variant->reversed_irq_handling) { 1498 mmci_data_irq(host, host->data, status); 1499 mmci_cmd_irq(host, host->cmd, status); 1500 } else { 1501 mmci_cmd_irq(host, host->cmd, status); 1502 mmci_data_irq(host, host->data, status); 1503 } 1504 1505 /* 1506 * Don't poll for busy completion in irq context. 1507 */ 1508 if (host->variant->busy_detect && host->busy_status) 1509 status &= ~host->variant->busy_detect_flag; 1510 1511 ret = 1; 1512 } while (status); 1513 1514 spin_unlock(&host->lock); 1515 1516 return IRQ_RETVAL(ret); 1517 } 1518 1519 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1520 { 1521 struct mmci_host *host = mmc_priv(mmc); 1522 unsigned long flags; 1523 1524 WARN_ON(host->mrq != NULL); 1525 1526 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1527 if (mrq->cmd->error) { 1528 mmc_request_done(mmc, mrq); 1529 return; 1530 } 1531 1532 spin_lock_irqsave(&host->lock, flags); 1533 1534 host->mrq = mrq; 1535 1536 if (mrq->data) 1537 mmci_get_next_data(host, mrq->data); 1538 1539 if (mrq->data && 1540 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1541 mmci_start_data(host, mrq->data); 1542 1543 if (mrq->sbc) 1544 mmci_start_command(host, mrq->sbc, 0); 1545 else 1546 mmci_start_command(host, mrq->cmd, 0); 1547 1548 spin_unlock_irqrestore(&host->lock, flags); 1549 } 1550 1551 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1552 { 1553 struct mmci_host *host = mmc_priv(mmc); 1554 struct variant_data *variant = host->variant; 1555 u32 pwr = 0; 1556 unsigned long flags; 1557 int ret; 1558 1559 if (host->plat->ios_handler && 1560 host->plat->ios_handler(mmc_dev(mmc), ios)) 1561 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1562 1563 switch (ios->power_mode) { 1564 case MMC_POWER_OFF: 1565 if (!IS_ERR(mmc->supply.vmmc)) 1566 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1567 1568 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1569 regulator_disable(mmc->supply.vqmmc); 1570 host->vqmmc_enabled = false; 1571 } 1572 1573 break; 1574 case MMC_POWER_UP: 1575 if (!IS_ERR(mmc->supply.vmmc)) 1576 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1577 1578 /* 1579 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1580 * and instead uses MCI_PWR_ON so apply whatever value is 1581 * configured in the variant data. 1582 */ 1583 pwr |= variant->pwrreg_powerup; 1584 1585 break; 1586 case MMC_POWER_ON: 1587 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1588 ret = regulator_enable(mmc->supply.vqmmc); 1589 if (ret < 0) 1590 dev_err(mmc_dev(mmc), 1591 "failed to enable vqmmc regulator\n"); 1592 else 1593 host->vqmmc_enabled = true; 1594 } 1595 1596 pwr |= MCI_PWR_ON; 1597 break; 1598 } 1599 1600 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1601 /* 1602 * The ST Micro variant has some additional bits 1603 * indicating signal direction for the signals in 1604 * the SD/MMC bus and feedback-clock usage. 1605 */ 1606 pwr |= host->pwr_reg_add; 1607 1608 if (ios->bus_width == MMC_BUS_WIDTH_4) 1609 pwr &= ~MCI_ST_DATA74DIREN; 1610 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1611 pwr &= (~MCI_ST_DATA74DIREN & 1612 ~MCI_ST_DATA31DIREN & 1613 ~MCI_ST_DATA2DIREN); 1614 } 1615 1616 if (variant->opendrain) { 1617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1618 pwr |= variant->opendrain; 1619 } else { 1620 /* 1621 * If the variant cannot configure the pads by its own, then we 1622 * expect the pinctrl to be able to do that for us 1623 */ 1624 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1625 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1626 else 1627 pinctrl_select_state(host->pinctrl, host->pins_default); 1628 } 1629 1630 /* 1631 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1632 * gating the clock, the MCI_PWR_ON bit is cleared. 1633 */ 1634 if (!ios->clock && variant->pwrreg_clkgate) 1635 pwr &= ~MCI_PWR_ON; 1636 1637 if (host->variant->explicit_mclk_control && 1638 ios->clock != host->clock_cache) { 1639 ret = clk_set_rate(host->clk, ios->clock); 1640 if (ret < 0) 1641 dev_err(mmc_dev(host->mmc), 1642 "Error setting clock rate (%d)\n", ret); 1643 else 1644 host->mclk = clk_get_rate(host->clk); 1645 } 1646 host->clock_cache = ios->clock; 1647 1648 spin_lock_irqsave(&host->lock, flags); 1649 1650 if (host->ops && host->ops->set_clkreg) 1651 host->ops->set_clkreg(host, ios->clock); 1652 else 1653 mmci_set_clkreg(host, ios->clock); 1654 1655 if (host->ops && host->ops->set_pwrreg) 1656 host->ops->set_pwrreg(host, pwr); 1657 else 1658 mmci_write_pwrreg(host, pwr); 1659 1660 mmci_reg_delay(host); 1661 1662 spin_unlock_irqrestore(&host->lock, flags); 1663 } 1664 1665 static int mmci_get_cd(struct mmc_host *mmc) 1666 { 1667 struct mmci_host *host = mmc_priv(mmc); 1668 struct mmci_platform_data *plat = host->plat; 1669 unsigned int status = mmc_gpio_get_cd(mmc); 1670 1671 if (status == -ENOSYS) { 1672 if (!plat->status) 1673 return 1; /* Assume always present */ 1674 1675 status = plat->status(mmc_dev(host->mmc)); 1676 } 1677 return status; 1678 } 1679 1680 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1681 { 1682 int ret = 0; 1683 1684 if (!IS_ERR(mmc->supply.vqmmc)) { 1685 1686 switch (ios->signal_voltage) { 1687 case MMC_SIGNAL_VOLTAGE_330: 1688 ret = regulator_set_voltage(mmc->supply.vqmmc, 1689 2700000, 3600000); 1690 break; 1691 case MMC_SIGNAL_VOLTAGE_180: 1692 ret = regulator_set_voltage(mmc->supply.vqmmc, 1693 1700000, 1950000); 1694 break; 1695 case MMC_SIGNAL_VOLTAGE_120: 1696 ret = regulator_set_voltage(mmc->supply.vqmmc, 1697 1100000, 1300000); 1698 break; 1699 } 1700 1701 if (ret) 1702 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1703 } 1704 1705 return ret; 1706 } 1707 1708 static struct mmc_host_ops mmci_ops = { 1709 .request = mmci_request, 1710 .pre_req = mmci_pre_request, 1711 .post_req = mmci_post_request, 1712 .set_ios = mmci_set_ios, 1713 .get_ro = mmc_gpio_get_ro, 1714 .get_cd = mmci_get_cd, 1715 .start_signal_voltage_switch = mmci_sig_volt_switch, 1716 }; 1717 1718 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1719 { 1720 struct mmci_host *host = mmc_priv(mmc); 1721 int ret = mmc_of_parse(mmc); 1722 1723 if (ret) 1724 return ret; 1725 1726 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1727 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1728 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1729 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1730 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1731 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1732 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1733 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1734 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1735 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1736 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1737 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1738 1739 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1740 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1741 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1742 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1743 1744 return 0; 1745 } 1746 1747 static int mmci_probe(struct amba_device *dev, 1748 const struct amba_id *id) 1749 { 1750 struct mmci_platform_data *plat = dev->dev.platform_data; 1751 struct device_node *np = dev->dev.of_node; 1752 struct variant_data *variant = id->data; 1753 struct mmci_host *host; 1754 struct mmc_host *mmc; 1755 int ret; 1756 1757 /* Must have platform data or Device Tree. */ 1758 if (!plat && !np) { 1759 dev_err(&dev->dev, "No plat data or DT found\n"); 1760 return -EINVAL; 1761 } 1762 1763 if (!plat) { 1764 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1765 if (!plat) 1766 return -ENOMEM; 1767 } 1768 1769 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1770 if (!mmc) 1771 return -ENOMEM; 1772 1773 ret = mmci_of_parse(np, mmc); 1774 if (ret) 1775 goto host_free; 1776 1777 host = mmc_priv(mmc); 1778 host->mmc = mmc; 1779 1780 /* 1781 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1782 * pins can be set accordingly using pinctrl 1783 */ 1784 if (!variant->opendrain) { 1785 host->pinctrl = devm_pinctrl_get(&dev->dev); 1786 if (IS_ERR(host->pinctrl)) { 1787 dev_err(&dev->dev, "failed to get pinctrl"); 1788 ret = PTR_ERR(host->pinctrl); 1789 goto host_free; 1790 } 1791 1792 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1793 PINCTRL_STATE_DEFAULT); 1794 if (IS_ERR(host->pins_default)) { 1795 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1796 ret = PTR_ERR(host->pins_default); 1797 goto host_free; 1798 } 1799 1800 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1801 MMCI_PINCTRL_STATE_OPENDRAIN); 1802 if (IS_ERR(host->pins_opendrain)) { 1803 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1804 ret = PTR_ERR(host->pins_opendrain); 1805 goto host_free; 1806 } 1807 } 1808 1809 host->hw_designer = amba_manf(dev); 1810 host->hw_revision = amba_rev(dev); 1811 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1812 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1813 1814 host->clk = devm_clk_get(&dev->dev, NULL); 1815 if (IS_ERR(host->clk)) { 1816 ret = PTR_ERR(host->clk); 1817 goto host_free; 1818 } 1819 1820 ret = clk_prepare_enable(host->clk); 1821 if (ret) 1822 goto host_free; 1823 1824 if (variant->qcom_fifo) 1825 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1826 else 1827 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1828 1829 host->plat = plat; 1830 host->variant = variant; 1831 host->mclk = clk_get_rate(host->clk); 1832 /* 1833 * According to the spec, mclk is max 100 MHz, 1834 * so we try to adjust the clock down to this, 1835 * (if possible). 1836 */ 1837 if (host->mclk > variant->f_max) { 1838 ret = clk_set_rate(host->clk, variant->f_max); 1839 if (ret < 0) 1840 goto clk_disable; 1841 host->mclk = clk_get_rate(host->clk); 1842 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1843 host->mclk); 1844 } 1845 1846 host->phybase = dev->res.start; 1847 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1848 if (IS_ERR(host->base)) { 1849 ret = PTR_ERR(host->base); 1850 goto clk_disable; 1851 } 1852 1853 if (variant->init) 1854 variant->init(host); 1855 1856 /* 1857 * The ARM and ST versions of the block have slightly different 1858 * clock divider equations which means that the minimum divider 1859 * differs too. 1860 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1861 */ 1862 if (variant->st_clkdiv) 1863 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1864 else if (variant->explicit_mclk_control) 1865 mmc->f_min = clk_round_rate(host->clk, 100000); 1866 else 1867 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1868 /* 1869 * If no maximum operating frequency is supplied, fall back to use 1870 * the module parameter, which has a (low) default value in case it 1871 * is not specified. Either value must not exceed the clock rate into 1872 * the block, of course. 1873 */ 1874 if (mmc->f_max) 1875 mmc->f_max = variant->explicit_mclk_control ? 1876 min(variant->f_max, mmc->f_max) : 1877 min(host->mclk, mmc->f_max); 1878 else 1879 mmc->f_max = variant->explicit_mclk_control ? 1880 fmax : min(host->mclk, fmax); 1881 1882 1883 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1884 1885 /* Get regulators and the supported OCR mask */ 1886 ret = mmc_regulator_get_supply(mmc); 1887 if (ret) 1888 goto clk_disable; 1889 1890 if (!mmc->ocr_avail) 1891 mmc->ocr_avail = plat->ocr_mask; 1892 else if (plat->ocr_mask) 1893 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1894 1895 /* We support these capabilities. */ 1896 mmc->caps |= MMC_CAP_CMD23; 1897 1898 /* 1899 * Enable busy detection. 1900 */ 1901 if (variant->busy_detect) { 1902 mmci_ops.card_busy = mmci_card_busy; 1903 /* 1904 * Not all variants have a flag to enable busy detection 1905 * in the DPSM, but if they do, set it here. 1906 */ 1907 if (variant->busy_dpsm_flag) 1908 mmci_write_datactrlreg(host, 1909 host->variant->busy_dpsm_flag); 1910 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1911 mmc->max_busy_timeout = 0; 1912 } 1913 1914 mmc->ops = &mmci_ops; 1915 1916 /* We support these PM capabilities. */ 1917 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1918 1919 /* 1920 * We can do SGIO 1921 */ 1922 mmc->max_segs = NR_SG; 1923 1924 /* 1925 * Since only a certain number of bits are valid in the data length 1926 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1927 * single request. 1928 */ 1929 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1930 1931 /* 1932 * Set the maximum segment size. Since we aren't doing DMA 1933 * (yet) we are only limited by the data length register. 1934 */ 1935 mmc->max_seg_size = mmc->max_req_size; 1936 1937 /* 1938 * Block size can be up to 2048 bytes, but must be a power of two. 1939 */ 1940 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 1941 1942 /* 1943 * Limit the number of blocks transferred so that we don't overflow 1944 * the maximum request size. 1945 */ 1946 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 1947 1948 spin_lock_init(&host->lock); 1949 1950 writel(0, host->base + MMCIMASK0); 1951 1952 if (variant->mmcimask1) 1953 writel(0, host->base + MMCIMASK1); 1954 1955 writel(0xfff, host->base + MMCICLEAR); 1956 1957 /* 1958 * If: 1959 * - not using DT but using a descriptor table, or 1960 * - using a table of descriptors ALONGSIDE DT, or 1961 * look up these descriptors named "cd" and "wp" right here, fail 1962 * silently of these do not exist 1963 */ 1964 if (!np) { 1965 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1966 if (ret == -EPROBE_DEFER) 1967 goto clk_disable; 1968 1969 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1970 if (ret == -EPROBE_DEFER) 1971 goto clk_disable; 1972 } 1973 1974 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1975 DRIVER_NAME " (cmd)", host); 1976 if (ret) 1977 goto clk_disable; 1978 1979 if (!dev->irq[1]) 1980 host->singleirq = true; 1981 else { 1982 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1983 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1984 if (ret) 1985 goto clk_disable; 1986 } 1987 1988 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 1989 1990 amba_set_drvdata(dev, mmc); 1991 1992 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1993 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1994 amba_rev(dev), (unsigned long long)dev->res.start, 1995 dev->irq[0], dev->irq[1]); 1996 1997 mmci_dma_setup(host); 1998 1999 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2000 pm_runtime_use_autosuspend(&dev->dev); 2001 2002 mmc_add_host(mmc); 2003 2004 pm_runtime_put(&dev->dev); 2005 return 0; 2006 2007 clk_disable: 2008 clk_disable_unprepare(host->clk); 2009 host_free: 2010 mmc_free_host(mmc); 2011 return ret; 2012 } 2013 2014 static int mmci_remove(struct amba_device *dev) 2015 { 2016 struct mmc_host *mmc = amba_get_drvdata(dev); 2017 2018 if (mmc) { 2019 struct mmci_host *host = mmc_priv(mmc); 2020 struct variant_data *variant = host->variant; 2021 2022 /* 2023 * Undo pm_runtime_put() in probe. We use the _sync 2024 * version here so that we can access the primecell. 2025 */ 2026 pm_runtime_get_sync(&dev->dev); 2027 2028 mmc_remove_host(mmc); 2029 2030 writel(0, host->base + MMCIMASK0); 2031 2032 if (variant->mmcimask1) 2033 writel(0, host->base + MMCIMASK1); 2034 2035 writel(0, host->base + MMCICOMMAND); 2036 writel(0, host->base + MMCIDATACTRL); 2037 2038 mmci_dma_release(host); 2039 clk_disable_unprepare(host->clk); 2040 mmc_free_host(mmc); 2041 } 2042 2043 return 0; 2044 } 2045 2046 #ifdef CONFIG_PM 2047 static void mmci_save(struct mmci_host *host) 2048 { 2049 unsigned long flags; 2050 2051 spin_lock_irqsave(&host->lock, flags); 2052 2053 writel(0, host->base + MMCIMASK0); 2054 if (host->variant->pwrreg_nopower) { 2055 writel(0, host->base + MMCIDATACTRL); 2056 writel(0, host->base + MMCIPOWER); 2057 writel(0, host->base + MMCICLOCK); 2058 } 2059 mmci_reg_delay(host); 2060 2061 spin_unlock_irqrestore(&host->lock, flags); 2062 } 2063 2064 static void mmci_restore(struct mmci_host *host) 2065 { 2066 unsigned long flags; 2067 2068 spin_lock_irqsave(&host->lock, flags); 2069 2070 if (host->variant->pwrreg_nopower) { 2071 writel(host->clk_reg, host->base + MMCICLOCK); 2072 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2073 writel(host->pwr_reg, host->base + MMCIPOWER); 2074 } 2075 writel(MCI_IRQENABLE | host->variant->start_err, 2076 host->base + MMCIMASK0); 2077 mmci_reg_delay(host); 2078 2079 spin_unlock_irqrestore(&host->lock, flags); 2080 } 2081 2082 static int mmci_runtime_suspend(struct device *dev) 2083 { 2084 struct amba_device *adev = to_amba_device(dev); 2085 struct mmc_host *mmc = amba_get_drvdata(adev); 2086 2087 if (mmc) { 2088 struct mmci_host *host = mmc_priv(mmc); 2089 pinctrl_pm_select_sleep_state(dev); 2090 mmci_save(host); 2091 clk_disable_unprepare(host->clk); 2092 } 2093 2094 return 0; 2095 } 2096 2097 static int mmci_runtime_resume(struct device *dev) 2098 { 2099 struct amba_device *adev = to_amba_device(dev); 2100 struct mmc_host *mmc = amba_get_drvdata(adev); 2101 2102 if (mmc) { 2103 struct mmci_host *host = mmc_priv(mmc); 2104 clk_prepare_enable(host->clk); 2105 mmci_restore(host); 2106 pinctrl_pm_select_default_state(dev); 2107 } 2108 2109 return 0; 2110 } 2111 #endif 2112 2113 static const struct dev_pm_ops mmci_dev_pm_ops = { 2114 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2115 pm_runtime_force_resume) 2116 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2117 }; 2118 2119 static const struct amba_id mmci_ids[] = { 2120 { 2121 .id = 0x00041180, 2122 .mask = 0xff0fffff, 2123 .data = &variant_arm, 2124 }, 2125 { 2126 .id = 0x01041180, 2127 .mask = 0xff0fffff, 2128 .data = &variant_arm_extended_fifo, 2129 }, 2130 { 2131 .id = 0x02041180, 2132 .mask = 0xff0fffff, 2133 .data = &variant_arm_extended_fifo_hwfc, 2134 }, 2135 { 2136 .id = 0x00041181, 2137 .mask = 0x000fffff, 2138 .data = &variant_arm, 2139 }, 2140 /* ST Micro variants */ 2141 { 2142 .id = 0x00180180, 2143 .mask = 0x00ffffff, 2144 .data = &variant_u300, 2145 }, 2146 { 2147 .id = 0x10180180, 2148 .mask = 0xf0ffffff, 2149 .data = &variant_nomadik, 2150 }, 2151 { 2152 .id = 0x00280180, 2153 .mask = 0x00ffffff, 2154 .data = &variant_nomadik, 2155 }, 2156 { 2157 .id = 0x00480180, 2158 .mask = 0xf0ffffff, 2159 .data = &variant_ux500, 2160 }, 2161 { 2162 .id = 0x10480180, 2163 .mask = 0xf0ffffff, 2164 .data = &variant_ux500v2, 2165 }, 2166 { 2167 .id = 0x00880180, 2168 .mask = 0x00ffffff, 2169 .data = &variant_stm32, 2170 }, 2171 /* Qualcomm variants */ 2172 { 2173 .id = 0x00051180, 2174 .mask = 0x000fffff, 2175 .data = &variant_qcom, 2176 }, 2177 { 0, 0 }, 2178 }; 2179 2180 MODULE_DEVICE_TABLE(amba, mmci_ids); 2181 2182 static struct amba_driver mmci_driver = { 2183 .drv = { 2184 .name = DRIVER_NAME, 2185 .pm = &mmci_dev_pm_ops, 2186 }, 2187 .probe = mmci_probe, 2188 .remove = mmci_remove, 2189 .id_table = mmci_ids, 2190 }; 2191 2192 module_amba_driver(mmci_driver); 2193 2194 module_param(fmax, uint, 0444); 2195 2196 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2197 MODULE_LICENSE("GPL"); 2198