1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/mmc/pm.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/amba/bus.h> 30 #include <linux/clk.h> 31 #include <linux/scatterlist.h> 32 #include <linux/of.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/amba/mmci.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/types.h> 39 #include <linux/pinctrl/consumer.h> 40 #include <linux/reset.h> 41 42 #include <asm/div64.h> 43 #include <asm/io.h> 44 45 #include "mmci.h" 46 47 #define DRIVER_NAME "mmci-pl18x" 48 49 static void mmci_variant_init(struct mmci_host *host); 50 static void ux500v2_variant_init(struct mmci_host *host); 51 52 static unsigned int fmax = 515633; 53 54 static struct variant_data variant_arm = { 55 .fifosize = 16 * 4, 56 .fifohalfsize = 8 * 4, 57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 60 .cmdreg_srsp = MCI_CPSM_RESPONSE, 61 .datalength_bits = 16, 62 .datactrl_blocksz = 11, 63 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 64 .pwrreg_powerup = MCI_PWR_UP, 65 .f_max = 100000000, 66 .reversed_irq_handling = true, 67 .mmcimask1 = true, 68 .irq_pio_mask = MCI_IRQ_PIO_MASK, 69 .start_err = MCI_STARTBITERR, 70 .opendrain = MCI_ROD, 71 .init = mmci_variant_init, 72 }; 73 74 static struct variant_data variant_arm_extended_fifo = { 75 .fifosize = 128 * 4, 76 .fifohalfsize = 64 * 4, 77 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 78 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 79 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 80 .cmdreg_srsp = MCI_CPSM_RESPONSE, 81 .datalength_bits = 16, 82 .datactrl_blocksz = 11, 83 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 84 .pwrreg_powerup = MCI_PWR_UP, 85 .f_max = 100000000, 86 .mmcimask1 = true, 87 .irq_pio_mask = MCI_IRQ_PIO_MASK, 88 .start_err = MCI_STARTBITERR, 89 .opendrain = MCI_ROD, 90 .init = mmci_variant_init, 91 }; 92 93 static struct variant_data variant_arm_extended_fifo_hwfc = { 94 .fifosize = 128 * 4, 95 .fifohalfsize = 64 * 4, 96 .clkreg_enable = MCI_ARM_HWFCEN, 97 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 98 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 99 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 100 .cmdreg_srsp = MCI_CPSM_RESPONSE, 101 .datalength_bits = 16, 102 .datactrl_blocksz = 11, 103 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 104 .pwrreg_powerup = MCI_PWR_UP, 105 .f_max = 100000000, 106 .mmcimask1 = true, 107 .irq_pio_mask = MCI_IRQ_PIO_MASK, 108 .start_err = MCI_STARTBITERR, 109 .opendrain = MCI_ROD, 110 .init = mmci_variant_init, 111 }; 112 113 static struct variant_data variant_u300 = { 114 .fifosize = 16 * 4, 115 .fifohalfsize = 8 * 4, 116 .clkreg_enable = MCI_ST_U300_HWFCEN, 117 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 118 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 119 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 120 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 121 .cmdreg_srsp = MCI_CPSM_RESPONSE, 122 .datalength_bits = 16, 123 .datactrl_blocksz = 11, 124 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 125 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 126 .st_sdio = true, 127 .pwrreg_powerup = MCI_PWR_ON, 128 .f_max = 100000000, 129 .signal_direction = true, 130 .pwrreg_clkgate = true, 131 .pwrreg_nopower = true, 132 .mmcimask1 = true, 133 .irq_pio_mask = MCI_IRQ_PIO_MASK, 134 .start_err = MCI_STARTBITERR, 135 .opendrain = MCI_OD, 136 .init = mmci_variant_init, 137 }; 138 139 static struct variant_data variant_nomadik = { 140 .fifosize = 16 * 4, 141 .fifohalfsize = 8 * 4, 142 .clkreg = MCI_CLK_ENABLE, 143 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 144 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 145 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 146 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 147 .cmdreg_srsp = MCI_CPSM_RESPONSE, 148 .datalength_bits = 24, 149 .datactrl_blocksz = 11, 150 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 151 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 152 .st_sdio = true, 153 .st_clkdiv = true, 154 .pwrreg_powerup = MCI_PWR_ON, 155 .f_max = 100000000, 156 .signal_direction = true, 157 .pwrreg_clkgate = true, 158 .pwrreg_nopower = true, 159 .mmcimask1 = true, 160 .irq_pio_mask = MCI_IRQ_PIO_MASK, 161 .start_err = MCI_STARTBITERR, 162 .opendrain = MCI_OD, 163 .init = mmci_variant_init, 164 }; 165 166 static struct variant_data variant_ux500 = { 167 .fifosize = 30 * 4, 168 .fifohalfsize = 8 * 4, 169 .clkreg = MCI_CLK_ENABLE, 170 .clkreg_enable = MCI_ST_UX500_HWFCEN, 171 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 172 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 173 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 174 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 175 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 176 .cmdreg_srsp = MCI_CPSM_RESPONSE, 177 .datalength_bits = 24, 178 .datactrl_blocksz = 11, 179 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 180 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 181 .st_sdio = true, 182 .st_clkdiv = true, 183 .pwrreg_powerup = MCI_PWR_ON, 184 .f_max = 100000000, 185 .signal_direction = true, 186 .pwrreg_clkgate = true, 187 .busy_detect = true, 188 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 189 .busy_detect_flag = MCI_ST_CARDBUSY, 190 .busy_detect_mask = MCI_ST_BUSYENDMASK, 191 .pwrreg_nopower = true, 192 .mmcimask1 = true, 193 .irq_pio_mask = MCI_IRQ_PIO_MASK, 194 .start_err = MCI_STARTBITERR, 195 .opendrain = MCI_OD, 196 .init = mmci_variant_init, 197 }; 198 199 static struct variant_data variant_ux500v2 = { 200 .fifosize = 30 * 4, 201 .fifohalfsize = 8 * 4, 202 .clkreg = MCI_CLK_ENABLE, 203 .clkreg_enable = MCI_ST_UX500_HWFCEN, 204 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 205 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 206 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 207 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 208 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 209 .cmdreg_srsp = MCI_CPSM_RESPONSE, 210 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 211 .datalength_bits = 24, 212 .datactrl_blocksz = 11, 213 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 214 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 215 .st_sdio = true, 216 .st_clkdiv = true, 217 .blksz_datactrl16 = true, 218 .pwrreg_powerup = MCI_PWR_ON, 219 .f_max = 100000000, 220 .signal_direction = true, 221 .pwrreg_clkgate = true, 222 .busy_detect = true, 223 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 224 .busy_detect_flag = MCI_ST_CARDBUSY, 225 .busy_detect_mask = MCI_ST_BUSYENDMASK, 226 .pwrreg_nopower = true, 227 .mmcimask1 = true, 228 .irq_pio_mask = MCI_IRQ_PIO_MASK, 229 .start_err = MCI_STARTBITERR, 230 .opendrain = MCI_OD, 231 .init = ux500v2_variant_init, 232 }; 233 234 static struct variant_data variant_stm32 = { 235 .fifosize = 32 * 4, 236 .fifohalfsize = 8 * 4, 237 .clkreg = MCI_CLK_ENABLE, 238 .clkreg_enable = MCI_ST_UX500_HWFCEN, 239 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 240 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 241 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 242 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 243 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 244 .cmdreg_srsp = MCI_CPSM_RESPONSE, 245 .irq_pio_mask = MCI_IRQ_PIO_MASK, 246 .datalength_bits = 24, 247 .datactrl_blocksz = 11, 248 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 249 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 250 .st_sdio = true, 251 .st_clkdiv = true, 252 .pwrreg_powerup = MCI_PWR_ON, 253 .f_max = 48000000, 254 .pwrreg_clkgate = true, 255 .pwrreg_nopower = true, 256 .init = mmci_variant_init, 257 }; 258 259 static struct variant_data variant_stm32_sdmmc = { 260 .fifosize = 16 * 4, 261 .fifohalfsize = 8 * 4, 262 .f_max = 208000000, 263 .stm32_clkdiv = true, 264 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 265 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 266 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 267 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 268 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 269 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 270 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 271 .datactrl_first = true, 272 .datacnt_useless = true, 273 .datalength_bits = 25, 274 .datactrl_blocksz = 14, 275 .stm32_idmabsize_mask = GENMASK(12, 5), 276 .init = sdmmc_variant_init, 277 }; 278 279 static struct variant_data variant_qcom = { 280 .fifosize = 16 * 4, 281 .fifohalfsize = 8 * 4, 282 .clkreg = MCI_CLK_ENABLE, 283 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 284 MCI_QCOM_CLK_SELECT_IN_FBCLK, 285 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 286 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 287 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 288 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 289 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 290 .cmdreg_srsp = MCI_CPSM_RESPONSE, 291 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 292 .blksz_datactrl4 = true, 293 .datalength_bits = 24, 294 .datactrl_blocksz = 11, 295 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 296 .pwrreg_powerup = MCI_PWR_UP, 297 .f_max = 208000000, 298 .explicit_mclk_control = true, 299 .qcom_fifo = true, 300 .qcom_dml = true, 301 .mmcimask1 = true, 302 .irq_pio_mask = MCI_IRQ_PIO_MASK, 303 .start_err = MCI_STARTBITERR, 304 .opendrain = MCI_ROD, 305 .init = qcom_variant_init, 306 }; 307 308 /* Busy detection for the ST Micro variant */ 309 static int mmci_card_busy(struct mmc_host *mmc) 310 { 311 struct mmci_host *host = mmc_priv(mmc); 312 unsigned long flags; 313 int busy = 0; 314 315 spin_lock_irqsave(&host->lock, flags); 316 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 317 busy = 1; 318 spin_unlock_irqrestore(&host->lock, flags); 319 320 return busy; 321 } 322 323 static void mmci_reg_delay(struct mmci_host *host) 324 { 325 /* 326 * According to the spec, at least three feedback clock cycles 327 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 328 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 329 * Worst delay time during card init is at 100 kHz => 30 us. 330 * Worst delay time when up and running is at 25 MHz => 120 ns. 331 */ 332 if (host->cclk < 25000000) 333 udelay(30); 334 else 335 ndelay(120); 336 } 337 338 /* 339 * This must be called with host->lock held 340 */ 341 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 342 { 343 if (host->clk_reg != clk) { 344 host->clk_reg = clk; 345 writel(clk, host->base + MMCICLOCK); 346 } 347 } 348 349 /* 350 * This must be called with host->lock held 351 */ 352 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 353 { 354 if (host->pwr_reg != pwr) { 355 host->pwr_reg = pwr; 356 writel(pwr, host->base + MMCIPOWER); 357 } 358 } 359 360 /* 361 * This must be called with host->lock held 362 */ 363 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 364 { 365 /* Keep busy mode in DPSM if enabled */ 366 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 367 368 if (host->datactrl_reg != datactrl) { 369 host->datactrl_reg = datactrl; 370 writel(datactrl, host->base + MMCIDATACTRL); 371 } 372 } 373 374 /* 375 * This must be called with host->lock held 376 */ 377 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 378 { 379 struct variant_data *variant = host->variant; 380 u32 clk = variant->clkreg; 381 382 /* Make sure cclk reflects the current calculated clock */ 383 host->cclk = 0; 384 385 if (desired) { 386 if (variant->explicit_mclk_control) { 387 host->cclk = host->mclk; 388 } else if (desired >= host->mclk) { 389 clk = MCI_CLK_BYPASS; 390 if (variant->st_clkdiv) 391 clk |= MCI_ST_UX500_NEG_EDGE; 392 host->cclk = host->mclk; 393 } else if (variant->st_clkdiv) { 394 /* 395 * DB8500 TRM says f = mclk / (clkdiv + 2) 396 * => clkdiv = (mclk / f) - 2 397 * Round the divider up so we don't exceed the max 398 * frequency 399 */ 400 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 401 if (clk >= 256) 402 clk = 255; 403 host->cclk = host->mclk / (clk + 2); 404 } else { 405 /* 406 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 407 * => clkdiv = mclk / (2 * f) - 1 408 */ 409 clk = host->mclk / (2 * desired) - 1; 410 if (clk >= 256) 411 clk = 255; 412 host->cclk = host->mclk / (2 * (clk + 1)); 413 } 414 415 clk |= variant->clkreg_enable; 416 clk |= MCI_CLK_ENABLE; 417 /* This hasn't proven to be worthwhile */ 418 /* clk |= MCI_CLK_PWRSAVE; */ 419 } 420 421 /* Set actual clock for debug */ 422 host->mmc->actual_clock = host->cclk; 423 424 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 425 clk |= MCI_4BIT_BUS; 426 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 427 clk |= variant->clkreg_8bit_bus_enable; 428 429 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 430 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 431 clk |= variant->clkreg_neg_edge_enable; 432 433 mmci_write_clkreg(host, clk); 434 } 435 436 void mmci_dma_release(struct mmci_host *host) 437 { 438 if (host->ops && host->ops->dma_release) 439 host->ops->dma_release(host); 440 441 host->use_dma = false; 442 } 443 444 void mmci_dma_setup(struct mmci_host *host) 445 { 446 if (!host->ops || !host->ops->dma_setup) 447 return; 448 449 if (host->ops->dma_setup(host)) 450 return; 451 452 /* initialize pre request cookie */ 453 host->next_cookie = 1; 454 455 host->use_dma = true; 456 } 457 458 /* 459 * Validate mmc prerequisites 460 */ 461 static int mmci_validate_data(struct mmci_host *host, 462 struct mmc_data *data) 463 { 464 if (!data) 465 return 0; 466 467 if (!is_power_of_2(data->blksz)) { 468 dev_err(mmc_dev(host->mmc), 469 "unsupported block size (%d bytes)\n", data->blksz); 470 return -EINVAL; 471 } 472 473 if (host->ops && host->ops->validate_data) 474 return host->ops->validate_data(host, data); 475 476 return 0; 477 } 478 479 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 480 { 481 int err; 482 483 if (!host->ops || !host->ops->prep_data) 484 return 0; 485 486 err = host->ops->prep_data(host, data, next); 487 488 if (next && !err) 489 data->host_cookie = ++host->next_cookie < 0 ? 490 1 : host->next_cookie; 491 492 return err; 493 } 494 495 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 496 int err) 497 { 498 if (host->ops && host->ops->unprep_data) 499 host->ops->unprep_data(host, data, err); 500 501 data->host_cookie = 0; 502 } 503 504 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 505 { 506 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 507 508 if (host->ops && host->ops->get_next_data) 509 host->ops->get_next_data(host, data); 510 } 511 512 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 513 { 514 struct mmc_data *data = host->data; 515 int ret; 516 517 if (!host->use_dma) 518 return -EINVAL; 519 520 ret = mmci_prep_data(host, data, false); 521 if (ret) 522 return ret; 523 524 if (!host->ops || !host->ops->dma_start) 525 return -EINVAL; 526 527 /* Okay, go for it. */ 528 dev_vdbg(mmc_dev(host->mmc), 529 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 530 data->sg_len, data->blksz, data->blocks, data->flags); 531 532 host->ops->dma_start(host, &datactrl); 533 534 /* Trigger the DMA transfer */ 535 mmci_write_datactrlreg(host, datactrl); 536 537 /* 538 * Let the MMCI say when the data is ended and it's time 539 * to fire next DMA request. When that happens, MMCI will 540 * call mmci_data_end() 541 */ 542 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 543 host->base + MMCIMASK0); 544 return 0; 545 } 546 547 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 548 { 549 if (!host->use_dma) 550 return; 551 552 if (host->ops && host->ops->dma_finalize) 553 host->ops->dma_finalize(host, data); 554 } 555 556 void mmci_dma_error(struct mmci_host *host) 557 { 558 if (!host->use_dma) 559 return; 560 561 if (host->ops && host->ops->dma_error) 562 host->ops->dma_error(host); 563 } 564 565 static void 566 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 567 { 568 writel(0, host->base + MMCICOMMAND); 569 570 BUG_ON(host->data); 571 572 host->mrq = NULL; 573 host->cmd = NULL; 574 575 mmc_request_done(host->mmc, mrq); 576 } 577 578 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 579 { 580 void __iomem *base = host->base; 581 struct variant_data *variant = host->variant; 582 583 if (host->singleirq) { 584 unsigned int mask0 = readl(base + MMCIMASK0); 585 586 mask0 &= ~variant->irq_pio_mask; 587 mask0 |= mask; 588 589 writel(mask0, base + MMCIMASK0); 590 } 591 592 if (variant->mmcimask1) 593 writel(mask, base + MMCIMASK1); 594 595 host->mask1_reg = mask; 596 } 597 598 static void mmci_stop_data(struct mmci_host *host) 599 { 600 mmci_write_datactrlreg(host, 0); 601 mmci_set_mask1(host, 0); 602 host->data = NULL; 603 } 604 605 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 606 { 607 unsigned int flags = SG_MITER_ATOMIC; 608 609 if (data->flags & MMC_DATA_READ) 610 flags |= SG_MITER_TO_SG; 611 else 612 flags |= SG_MITER_FROM_SG; 613 614 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 615 } 616 617 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 618 { 619 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 620 } 621 622 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 623 { 624 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 625 } 626 627 /* 628 * All the DMA operation mode stuff goes inside this ifdef. 629 * This assumes that you have a generic DMA device interface, 630 * no custom DMA interfaces are supported. 631 */ 632 #ifdef CONFIG_DMA_ENGINE 633 struct mmci_dmae_next { 634 struct dma_async_tx_descriptor *desc; 635 struct dma_chan *chan; 636 }; 637 638 struct mmci_dmae_priv { 639 struct dma_chan *cur; 640 struct dma_chan *rx_channel; 641 struct dma_chan *tx_channel; 642 struct dma_async_tx_descriptor *desc_current; 643 struct mmci_dmae_next next_data; 644 }; 645 646 int mmci_dmae_setup(struct mmci_host *host) 647 { 648 const char *rxname, *txname; 649 struct mmci_dmae_priv *dmae; 650 651 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 652 if (!dmae) 653 return -ENOMEM; 654 655 host->dma_priv = dmae; 656 657 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 658 "rx"); 659 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 660 "tx"); 661 662 /* 663 * If only an RX channel is specified, the driver will 664 * attempt to use it bidirectionally, however if it is 665 * is specified but cannot be located, DMA will be disabled. 666 */ 667 if (dmae->rx_channel && !dmae->tx_channel) 668 dmae->tx_channel = dmae->rx_channel; 669 670 if (dmae->rx_channel) 671 rxname = dma_chan_name(dmae->rx_channel); 672 else 673 rxname = "none"; 674 675 if (dmae->tx_channel) 676 txname = dma_chan_name(dmae->tx_channel); 677 else 678 txname = "none"; 679 680 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 681 rxname, txname); 682 683 /* 684 * Limit the maximum segment size in any SG entry according to 685 * the parameters of the DMA engine device. 686 */ 687 if (dmae->tx_channel) { 688 struct device *dev = dmae->tx_channel->device->dev; 689 unsigned int max_seg_size = dma_get_max_seg_size(dev); 690 691 if (max_seg_size < host->mmc->max_seg_size) 692 host->mmc->max_seg_size = max_seg_size; 693 } 694 if (dmae->rx_channel) { 695 struct device *dev = dmae->rx_channel->device->dev; 696 unsigned int max_seg_size = dma_get_max_seg_size(dev); 697 698 if (max_seg_size < host->mmc->max_seg_size) 699 host->mmc->max_seg_size = max_seg_size; 700 } 701 702 if (!dmae->tx_channel || !dmae->rx_channel) { 703 mmci_dmae_release(host); 704 return -EINVAL; 705 } 706 707 return 0; 708 } 709 710 /* 711 * This is used in or so inline it 712 * so it can be discarded. 713 */ 714 void mmci_dmae_release(struct mmci_host *host) 715 { 716 struct mmci_dmae_priv *dmae = host->dma_priv; 717 718 if (dmae->rx_channel) 719 dma_release_channel(dmae->rx_channel); 720 if (dmae->tx_channel) 721 dma_release_channel(dmae->tx_channel); 722 dmae->rx_channel = dmae->tx_channel = NULL; 723 } 724 725 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 726 { 727 struct mmci_dmae_priv *dmae = host->dma_priv; 728 struct dma_chan *chan; 729 730 if (data->flags & MMC_DATA_READ) 731 chan = dmae->rx_channel; 732 else 733 chan = dmae->tx_channel; 734 735 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 736 mmc_get_dma_dir(data)); 737 } 738 739 void mmci_dmae_error(struct mmci_host *host) 740 { 741 struct mmci_dmae_priv *dmae = host->dma_priv; 742 743 if (!dma_inprogress(host)) 744 return; 745 746 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 747 dmaengine_terminate_all(dmae->cur); 748 host->dma_in_progress = false; 749 dmae->cur = NULL; 750 dmae->desc_current = NULL; 751 host->data->host_cookie = 0; 752 753 mmci_dma_unmap(host, host->data); 754 } 755 756 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 757 { 758 struct mmci_dmae_priv *dmae = host->dma_priv; 759 u32 status; 760 int i; 761 762 if (!dma_inprogress(host)) 763 return; 764 765 /* Wait up to 1ms for the DMA to complete */ 766 for (i = 0; ; i++) { 767 status = readl(host->base + MMCISTATUS); 768 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 769 break; 770 udelay(10); 771 } 772 773 /* 774 * Check to see whether we still have some data left in the FIFO - 775 * this catches DMA controllers which are unable to monitor the 776 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 777 * contiguous buffers. On TX, we'll get a FIFO underrun error. 778 */ 779 if (status & MCI_RXDATAAVLBLMASK) { 780 mmci_dma_error(host); 781 if (!data->error) 782 data->error = -EIO; 783 } else if (!data->host_cookie) { 784 mmci_dma_unmap(host, data); 785 } 786 787 /* 788 * Use of DMA with scatter-gather is impossible. 789 * Give up with DMA and switch back to PIO mode. 790 */ 791 if (status & MCI_RXDATAAVLBLMASK) { 792 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 793 mmci_dma_release(host); 794 } 795 796 host->dma_in_progress = false; 797 dmae->cur = NULL; 798 dmae->desc_current = NULL; 799 } 800 801 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 802 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 803 struct dma_chan **dma_chan, 804 struct dma_async_tx_descriptor **dma_desc) 805 { 806 struct mmci_dmae_priv *dmae = host->dma_priv; 807 struct variant_data *variant = host->variant; 808 struct dma_slave_config conf = { 809 .src_addr = host->phybase + MMCIFIFO, 810 .dst_addr = host->phybase + MMCIFIFO, 811 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 812 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 813 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 814 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 815 .device_fc = false, 816 }; 817 struct dma_chan *chan; 818 struct dma_device *device; 819 struct dma_async_tx_descriptor *desc; 820 int nr_sg; 821 unsigned long flags = DMA_CTRL_ACK; 822 823 if (data->flags & MMC_DATA_READ) { 824 conf.direction = DMA_DEV_TO_MEM; 825 chan = dmae->rx_channel; 826 } else { 827 conf.direction = DMA_MEM_TO_DEV; 828 chan = dmae->tx_channel; 829 } 830 831 /* If there's no DMA channel, fall back to PIO */ 832 if (!chan) 833 return -EINVAL; 834 835 /* If less than or equal to the fifo size, don't bother with DMA */ 836 if (data->blksz * data->blocks <= variant->fifosize) 837 return -EINVAL; 838 839 device = chan->device; 840 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 841 mmc_get_dma_dir(data)); 842 if (nr_sg == 0) 843 return -EINVAL; 844 845 if (host->variant->qcom_dml) 846 flags |= DMA_PREP_INTERRUPT; 847 848 dmaengine_slave_config(chan, &conf); 849 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 850 conf.direction, flags); 851 if (!desc) 852 goto unmap_exit; 853 854 *dma_chan = chan; 855 *dma_desc = desc; 856 857 return 0; 858 859 unmap_exit: 860 dma_unmap_sg(device->dev, data->sg, data->sg_len, 861 mmc_get_dma_dir(data)); 862 return -ENOMEM; 863 } 864 865 int mmci_dmae_prep_data(struct mmci_host *host, 866 struct mmc_data *data, 867 bool next) 868 { 869 struct mmci_dmae_priv *dmae = host->dma_priv; 870 struct mmci_dmae_next *nd = &dmae->next_data; 871 872 if (!host->use_dma) 873 return -EINVAL; 874 875 if (next) 876 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 877 /* Check if next job is already prepared. */ 878 if (dmae->cur && dmae->desc_current) 879 return 0; 880 881 /* No job were prepared thus do it now. */ 882 return _mmci_dmae_prep_data(host, data, &dmae->cur, 883 &dmae->desc_current); 884 } 885 886 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 887 { 888 struct mmci_dmae_priv *dmae = host->dma_priv; 889 890 host->dma_in_progress = true; 891 dmaengine_submit(dmae->desc_current); 892 dma_async_issue_pending(dmae->cur); 893 894 *datactrl |= MCI_DPSM_DMAENABLE; 895 896 return 0; 897 } 898 899 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 900 { 901 struct mmci_dmae_priv *dmae = host->dma_priv; 902 struct mmci_dmae_next *next = &dmae->next_data; 903 904 if (!host->use_dma) 905 return; 906 907 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 908 909 dmae->desc_current = next->desc; 910 dmae->cur = next->chan; 911 next->desc = NULL; 912 next->chan = NULL; 913 } 914 915 void mmci_dmae_unprep_data(struct mmci_host *host, 916 struct mmc_data *data, int err) 917 918 { 919 struct mmci_dmae_priv *dmae = host->dma_priv; 920 921 if (!host->use_dma) 922 return; 923 924 mmci_dma_unmap(host, data); 925 926 if (err) { 927 struct mmci_dmae_next *next = &dmae->next_data; 928 struct dma_chan *chan; 929 if (data->flags & MMC_DATA_READ) 930 chan = dmae->rx_channel; 931 else 932 chan = dmae->tx_channel; 933 dmaengine_terminate_all(chan); 934 935 if (dmae->desc_current == next->desc) 936 dmae->desc_current = NULL; 937 938 if (dmae->cur == next->chan) { 939 host->dma_in_progress = false; 940 dmae->cur = NULL; 941 } 942 943 next->desc = NULL; 944 next->chan = NULL; 945 } 946 } 947 948 static struct mmci_host_ops mmci_variant_ops = { 949 .prep_data = mmci_dmae_prep_data, 950 .unprep_data = mmci_dmae_unprep_data, 951 .get_datactrl_cfg = mmci_get_dctrl_cfg, 952 .get_next_data = mmci_dmae_get_next_data, 953 .dma_setup = mmci_dmae_setup, 954 .dma_release = mmci_dmae_release, 955 .dma_start = mmci_dmae_start, 956 .dma_finalize = mmci_dmae_finalize, 957 .dma_error = mmci_dmae_error, 958 }; 959 #else 960 static struct mmci_host_ops mmci_variant_ops = { 961 .get_datactrl_cfg = mmci_get_dctrl_cfg, 962 }; 963 #endif 964 965 void mmci_variant_init(struct mmci_host *host) 966 { 967 host->ops = &mmci_variant_ops; 968 } 969 970 void ux500v2_variant_init(struct mmci_host *host) 971 { 972 host->ops = &mmci_variant_ops; 973 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 974 } 975 976 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 977 { 978 struct mmci_host *host = mmc_priv(mmc); 979 struct mmc_data *data = mrq->data; 980 981 if (!data) 982 return; 983 984 WARN_ON(data->host_cookie); 985 986 if (mmci_validate_data(host, data)) 987 return; 988 989 mmci_prep_data(host, data, true); 990 } 991 992 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 993 int err) 994 { 995 struct mmci_host *host = mmc_priv(mmc); 996 struct mmc_data *data = mrq->data; 997 998 if (!data || !data->host_cookie) 999 return; 1000 1001 mmci_unprep_data(host, data, err); 1002 } 1003 1004 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1005 { 1006 struct variant_data *variant = host->variant; 1007 unsigned int datactrl, timeout, irqmask; 1008 unsigned long long clks; 1009 void __iomem *base; 1010 int blksz_bits; 1011 1012 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1013 data->blksz, data->blocks, data->flags); 1014 1015 host->data = data; 1016 host->size = data->blksz * data->blocks; 1017 data->bytes_xfered = 0; 1018 1019 clks = (unsigned long long)data->timeout_ns * host->cclk; 1020 do_div(clks, NSEC_PER_SEC); 1021 1022 timeout = data->timeout_clks + (unsigned int)clks; 1023 1024 base = host->base; 1025 writel(timeout, base + MMCIDATATIMER); 1026 writel(host->size, base + MMCIDATALENGTH); 1027 1028 blksz_bits = ffs(data->blksz) - 1; 1029 BUG_ON(1 << blksz_bits != data->blksz); 1030 1031 if (variant->blksz_datactrl16) 1032 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16); 1033 else if (variant->blksz_datactrl4) 1034 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4); 1035 else 1036 datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; 1037 1038 if (data->flags & MMC_DATA_READ) 1039 datactrl |= MCI_DPSM_DIRECTION; 1040 1041 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1042 u32 clk; 1043 1044 datactrl |= variant->datactrl_mask_sdio; 1045 1046 /* 1047 * The ST Micro variant for SDIO small write transfers 1048 * needs to have clock H/W flow control disabled, 1049 * otherwise the transfer will not start. The threshold 1050 * depends on the rate of MCLK. 1051 */ 1052 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1053 (host->size < 8 || 1054 (host->size <= 8 && host->mclk > 50000000))) 1055 clk = host->clk_reg & ~variant->clkreg_enable; 1056 else 1057 clk = host->clk_reg | variant->clkreg_enable; 1058 1059 mmci_write_clkreg(host, clk); 1060 } 1061 1062 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1063 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1064 datactrl |= variant->datactrl_mask_ddrmode; 1065 1066 /* 1067 * Attempt to use DMA operation mode, if this 1068 * should fail, fall back to PIO mode 1069 */ 1070 if (!mmci_dma_start(host, datactrl)) 1071 return; 1072 1073 /* IRQ mode, map the SG list for CPU reading/writing */ 1074 mmci_init_sg(host, data); 1075 1076 if (data->flags & MMC_DATA_READ) { 1077 irqmask = MCI_RXFIFOHALFFULLMASK; 1078 1079 /* 1080 * If we have less than the fifo 'half-full' threshold to 1081 * transfer, trigger a PIO interrupt as soon as any data 1082 * is available. 1083 */ 1084 if (host->size < variant->fifohalfsize) 1085 irqmask |= MCI_RXDATAAVLBLMASK; 1086 } else { 1087 /* 1088 * We don't actually need to include "FIFO empty" here 1089 * since its implicit in "FIFO half empty". 1090 */ 1091 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1092 } 1093 1094 mmci_write_datactrlreg(host, datactrl); 1095 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1096 mmci_set_mask1(host, irqmask); 1097 } 1098 1099 static void 1100 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1101 { 1102 void __iomem *base = host->base; 1103 1104 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1105 cmd->opcode, cmd->arg, cmd->flags); 1106 1107 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1108 writel(0, base + MMCICOMMAND); 1109 mmci_reg_delay(host); 1110 } 1111 1112 if (host->variant->cmdreg_stop && 1113 cmd->opcode == MMC_STOP_TRANSMISSION) 1114 c |= host->variant->cmdreg_stop; 1115 1116 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1117 if (cmd->flags & MMC_RSP_PRESENT) { 1118 if (cmd->flags & MMC_RSP_136) 1119 c |= host->variant->cmdreg_lrsp_crc; 1120 else if (cmd->flags & MMC_RSP_CRC) 1121 c |= host->variant->cmdreg_srsp_crc; 1122 else 1123 c |= host->variant->cmdreg_srsp; 1124 } 1125 if (/*interrupt*/0) 1126 c |= MCI_CPSM_INTERRUPT; 1127 1128 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1129 c |= host->variant->data_cmd_enable; 1130 1131 host->cmd = cmd; 1132 1133 writel(cmd->arg, base + MMCIARGUMENT); 1134 writel(c, base + MMCICOMMAND); 1135 } 1136 1137 static void mmci_stop_command(struct mmci_host *host) 1138 { 1139 host->stop_abort.error = 0; 1140 mmci_start_command(host, &host->stop_abort, 0); 1141 } 1142 1143 static void 1144 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1145 unsigned int status) 1146 { 1147 unsigned int status_err; 1148 1149 /* Make sure we have data to handle */ 1150 if (!data) 1151 return; 1152 1153 /* First check for errors */ 1154 status_err = status & (host->variant->start_err | 1155 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1156 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1157 1158 if (status_err) { 1159 u32 remain, success; 1160 1161 /* Terminate the DMA transfer */ 1162 mmci_dma_error(host); 1163 1164 /* 1165 * Calculate how far we are into the transfer. Note that 1166 * the data counter gives the number of bytes transferred 1167 * on the MMC bus, not on the host side. On reads, this 1168 * can be as much as a FIFO-worth of data ahead. This 1169 * matters for FIFO overruns only. 1170 */ 1171 if (!host->variant->datacnt_useless) { 1172 remain = readl(host->base + MMCIDATACNT); 1173 success = data->blksz * data->blocks - remain; 1174 } else { 1175 success = 0; 1176 } 1177 1178 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1179 status_err, success); 1180 if (status_err & MCI_DATACRCFAIL) { 1181 /* Last block was not successful */ 1182 success -= 1; 1183 data->error = -EILSEQ; 1184 } else if (status_err & MCI_DATATIMEOUT) { 1185 data->error = -ETIMEDOUT; 1186 } else if (status_err & MCI_STARTBITERR) { 1187 data->error = -ECOMM; 1188 } else if (status_err & MCI_TXUNDERRUN) { 1189 data->error = -EIO; 1190 } else if (status_err & MCI_RXOVERRUN) { 1191 if (success > host->variant->fifosize) 1192 success -= host->variant->fifosize; 1193 else 1194 success = 0; 1195 data->error = -EIO; 1196 } 1197 data->bytes_xfered = round_down(success, data->blksz); 1198 } 1199 1200 if (status & MCI_DATABLOCKEND) 1201 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1202 1203 if (status & MCI_DATAEND || data->error) { 1204 mmci_dma_finalize(host, data); 1205 1206 mmci_stop_data(host); 1207 1208 if (!data->error) 1209 /* The error clause is handled above, success! */ 1210 data->bytes_xfered = data->blksz * data->blocks; 1211 1212 if (!data->stop) { 1213 if (host->variant->cmdreg_stop && data->error) 1214 mmci_stop_command(host); 1215 else 1216 mmci_request_end(host, data->mrq); 1217 } else if (host->mrq->sbc && !data->error) { 1218 mmci_request_end(host, data->mrq); 1219 } else { 1220 mmci_start_command(host, data->stop, 0); 1221 } 1222 } 1223 } 1224 1225 static void 1226 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1227 unsigned int status) 1228 { 1229 void __iomem *base = host->base; 1230 bool sbc; 1231 1232 if (!cmd) 1233 return; 1234 1235 sbc = (cmd == host->mrq->sbc); 1236 1237 /* 1238 * We need to be one of these interrupts to be considered worth 1239 * handling. Note that we tag on any latent IRQs postponed 1240 * due to waiting for busy status. 1241 */ 1242 if (!((status|host->busy_status) & 1243 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1244 return; 1245 1246 /* 1247 * ST Micro variant: handle busy detection. 1248 */ 1249 if (host->variant->busy_detect) { 1250 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1251 1252 /* We are busy with a command, return */ 1253 if (host->busy_status && 1254 (status & host->variant->busy_detect_flag)) 1255 return; 1256 1257 /* 1258 * We were not busy, but we now got a busy response on 1259 * something that was not an error, and we double-check 1260 * that the special busy status bit is still set before 1261 * proceeding. 1262 */ 1263 if (!host->busy_status && busy_resp && 1264 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1265 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1266 1267 /* Clear the busy start IRQ */ 1268 writel(host->variant->busy_detect_mask, 1269 host->base + MMCICLEAR); 1270 1271 /* Unmask the busy end IRQ */ 1272 writel(readl(base + MMCIMASK0) | 1273 host->variant->busy_detect_mask, 1274 base + MMCIMASK0); 1275 /* 1276 * Now cache the last response status code (until 1277 * the busy bit goes low), and return. 1278 */ 1279 host->busy_status = 1280 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1281 return; 1282 } 1283 1284 /* 1285 * At this point we are not busy with a command, we have 1286 * not received a new busy request, clear and mask the busy 1287 * end IRQ and fall through to process the IRQ. 1288 */ 1289 if (host->busy_status) { 1290 1291 writel(host->variant->busy_detect_mask, 1292 host->base + MMCICLEAR); 1293 1294 writel(readl(base + MMCIMASK0) & 1295 ~host->variant->busy_detect_mask, 1296 base + MMCIMASK0); 1297 host->busy_status = 0; 1298 } 1299 } 1300 1301 host->cmd = NULL; 1302 1303 if (status & MCI_CMDTIMEOUT) { 1304 cmd->error = -ETIMEDOUT; 1305 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1306 cmd->error = -EILSEQ; 1307 } else { 1308 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1309 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1310 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1311 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1312 } 1313 1314 if ((!sbc && !cmd->data) || cmd->error) { 1315 if (host->data) { 1316 /* Terminate the DMA transfer */ 1317 mmci_dma_error(host); 1318 1319 mmci_stop_data(host); 1320 if (host->variant->cmdreg_stop && cmd->error) { 1321 mmci_stop_command(host); 1322 return; 1323 } 1324 } 1325 mmci_request_end(host, host->mrq); 1326 } else if (sbc) { 1327 mmci_start_command(host, host->mrq->cmd, 0); 1328 } else if (!host->variant->datactrl_first && 1329 !(cmd->data->flags & MMC_DATA_READ)) { 1330 mmci_start_data(host, cmd->data); 1331 } 1332 } 1333 1334 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1335 { 1336 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1337 } 1338 1339 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1340 { 1341 /* 1342 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1343 * from the fifo range should be used 1344 */ 1345 if (status & MCI_RXFIFOHALFFULL) 1346 return host->variant->fifohalfsize; 1347 else if (status & MCI_RXDATAAVLBL) 1348 return 4; 1349 1350 return 0; 1351 } 1352 1353 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1354 { 1355 void __iomem *base = host->base; 1356 char *ptr = buffer; 1357 u32 status = readl(host->base + MMCISTATUS); 1358 int host_remain = host->size; 1359 1360 do { 1361 int count = host->get_rx_fifocnt(host, status, host_remain); 1362 1363 if (count > remain) 1364 count = remain; 1365 1366 if (count <= 0) 1367 break; 1368 1369 /* 1370 * SDIO especially may want to send something that is 1371 * not divisible by 4 (as opposed to card sectors 1372 * etc). Therefore make sure to always read the last bytes 1373 * while only doing full 32-bit reads towards the FIFO. 1374 */ 1375 if (unlikely(count & 0x3)) { 1376 if (count < 4) { 1377 unsigned char buf[4]; 1378 ioread32_rep(base + MMCIFIFO, buf, 1); 1379 memcpy(ptr, buf, count); 1380 } else { 1381 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1382 count &= ~0x3; 1383 } 1384 } else { 1385 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1386 } 1387 1388 ptr += count; 1389 remain -= count; 1390 host_remain -= count; 1391 1392 if (remain == 0) 1393 break; 1394 1395 status = readl(base + MMCISTATUS); 1396 } while (status & MCI_RXDATAAVLBL); 1397 1398 return ptr - buffer; 1399 } 1400 1401 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1402 { 1403 struct variant_data *variant = host->variant; 1404 void __iomem *base = host->base; 1405 char *ptr = buffer; 1406 1407 do { 1408 unsigned int count, maxcnt; 1409 1410 maxcnt = status & MCI_TXFIFOEMPTY ? 1411 variant->fifosize : variant->fifohalfsize; 1412 count = min(remain, maxcnt); 1413 1414 /* 1415 * SDIO especially may want to send something that is 1416 * not divisible by 4 (as opposed to card sectors 1417 * etc), and the FIFO only accept full 32-bit writes. 1418 * So compensate by adding +3 on the count, a single 1419 * byte become a 32bit write, 7 bytes will be two 1420 * 32bit writes etc. 1421 */ 1422 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1423 1424 ptr += count; 1425 remain -= count; 1426 1427 if (remain == 0) 1428 break; 1429 1430 status = readl(base + MMCISTATUS); 1431 } while (status & MCI_TXFIFOHALFEMPTY); 1432 1433 return ptr - buffer; 1434 } 1435 1436 /* 1437 * PIO data transfer IRQ handler. 1438 */ 1439 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1440 { 1441 struct mmci_host *host = dev_id; 1442 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1443 struct variant_data *variant = host->variant; 1444 void __iomem *base = host->base; 1445 u32 status; 1446 1447 status = readl(base + MMCISTATUS); 1448 1449 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1450 1451 do { 1452 unsigned int remain, len; 1453 char *buffer; 1454 1455 /* 1456 * For write, we only need to test the half-empty flag 1457 * here - if the FIFO is completely empty, then by 1458 * definition it is more than half empty. 1459 * 1460 * For read, check for data available. 1461 */ 1462 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1463 break; 1464 1465 if (!sg_miter_next(sg_miter)) 1466 break; 1467 1468 buffer = sg_miter->addr; 1469 remain = sg_miter->length; 1470 1471 len = 0; 1472 if (status & MCI_RXACTIVE) 1473 len = mmci_pio_read(host, buffer, remain); 1474 if (status & MCI_TXACTIVE) 1475 len = mmci_pio_write(host, buffer, remain, status); 1476 1477 sg_miter->consumed = len; 1478 1479 host->size -= len; 1480 remain -= len; 1481 1482 if (remain) 1483 break; 1484 1485 status = readl(base + MMCISTATUS); 1486 } while (1); 1487 1488 sg_miter_stop(sg_miter); 1489 1490 /* 1491 * If we have less than the fifo 'half-full' threshold to transfer, 1492 * trigger a PIO interrupt as soon as any data is available. 1493 */ 1494 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1495 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1496 1497 /* 1498 * If we run out of data, disable the data IRQs; this 1499 * prevents a race where the FIFO becomes empty before 1500 * the chip itself has disabled the data path, and 1501 * stops us racing with our data end IRQ. 1502 */ 1503 if (host->size == 0) { 1504 mmci_set_mask1(host, 0); 1505 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1506 } 1507 1508 return IRQ_HANDLED; 1509 } 1510 1511 /* 1512 * Handle completion of command and data transfers. 1513 */ 1514 static irqreturn_t mmci_irq(int irq, void *dev_id) 1515 { 1516 struct mmci_host *host = dev_id; 1517 u32 status; 1518 int ret = 0; 1519 1520 spin_lock(&host->lock); 1521 1522 do { 1523 status = readl(host->base + MMCISTATUS); 1524 1525 if (host->singleirq) { 1526 if (status & host->mask1_reg) 1527 mmci_pio_irq(irq, dev_id); 1528 1529 status &= ~host->variant->irq_pio_mask; 1530 } 1531 1532 /* 1533 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1534 * enabled) in mmci_cmd_irq() function where ST Micro busy 1535 * detection variant is handled. Considering the HW seems to be 1536 * triggering the IRQ on both edges while monitoring DAT0 for 1537 * busy completion and that same status bit is used to monitor 1538 * start and end of busy detection, special care must be taken 1539 * to make sure that both start and end interrupts are always 1540 * cleared one after the other. 1541 */ 1542 status &= readl(host->base + MMCIMASK0); 1543 if (host->variant->busy_detect) 1544 writel(status & ~host->variant->busy_detect_mask, 1545 host->base + MMCICLEAR); 1546 else 1547 writel(status, host->base + MMCICLEAR); 1548 1549 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1550 1551 if (host->variant->reversed_irq_handling) { 1552 mmci_data_irq(host, host->data, status); 1553 mmci_cmd_irq(host, host->cmd, status); 1554 } else { 1555 mmci_cmd_irq(host, host->cmd, status); 1556 mmci_data_irq(host, host->data, status); 1557 } 1558 1559 /* 1560 * Don't poll for busy completion in irq context. 1561 */ 1562 if (host->variant->busy_detect && host->busy_status) 1563 status &= ~host->variant->busy_detect_flag; 1564 1565 ret = 1; 1566 } while (status); 1567 1568 spin_unlock(&host->lock); 1569 1570 return IRQ_RETVAL(ret); 1571 } 1572 1573 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1574 { 1575 struct mmci_host *host = mmc_priv(mmc); 1576 unsigned long flags; 1577 1578 WARN_ON(host->mrq != NULL); 1579 1580 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1581 if (mrq->cmd->error) { 1582 mmc_request_done(mmc, mrq); 1583 return; 1584 } 1585 1586 spin_lock_irqsave(&host->lock, flags); 1587 1588 host->mrq = mrq; 1589 1590 if (mrq->data) 1591 mmci_get_next_data(host, mrq->data); 1592 1593 if (mrq->data && 1594 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1595 mmci_start_data(host, mrq->data); 1596 1597 if (mrq->sbc) 1598 mmci_start_command(host, mrq->sbc, 0); 1599 else 1600 mmci_start_command(host, mrq->cmd, 0); 1601 1602 spin_unlock_irqrestore(&host->lock, flags); 1603 } 1604 1605 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1606 { 1607 struct mmci_host *host = mmc_priv(mmc); 1608 struct variant_data *variant = host->variant; 1609 u32 pwr = 0; 1610 unsigned long flags; 1611 int ret; 1612 1613 if (host->plat->ios_handler && 1614 host->plat->ios_handler(mmc_dev(mmc), ios)) 1615 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1616 1617 switch (ios->power_mode) { 1618 case MMC_POWER_OFF: 1619 if (!IS_ERR(mmc->supply.vmmc)) 1620 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1621 1622 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1623 regulator_disable(mmc->supply.vqmmc); 1624 host->vqmmc_enabled = false; 1625 } 1626 1627 break; 1628 case MMC_POWER_UP: 1629 if (!IS_ERR(mmc->supply.vmmc)) 1630 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1631 1632 /* 1633 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1634 * and instead uses MCI_PWR_ON so apply whatever value is 1635 * configured in the variant data. 1636 */ 1637 pwr |= variant->pwrreg_powerup; 1638 1639 break; 1640 case MMC_POWER_ON: 1641 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1642 ret = regulator_enable(mmc->supply.vqmmc); 1643 if (ret < 0) 1644 dev_err(mmc_dev(mmc), 1645 "failed to enable vqmmc regulator\n"); 1646 else 1647 host->vqmmc_enabled = true; 1648 } 1649 1650 pwr |= MCI_PWR_ON; 1651 break; 1652 } 1653 1654 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1655 /* 1656 * The ST Micro variant has some additional bits 1657 * indicating signal direction for the signals in 1658 * the SD/MMC bus and feedback-clock usage. 1659 */ 1660 pwr |= host->pwr_reg_add; 1661 1662 if (ios->bus_width == MMC_BUS_WIDTH_4) 1663 pwr &= ~MCI_ST_DATA74DIREN; 1664 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1665 pwr &= (~MCI_ST_DATA74DIREN & 1666 ~MCI_ST_DATA31DIREN & 1667 ~MCI_ST_DATA2DIREN); 1668 } 1669 1670 if (variant->opendrain) { 1671 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1672 pwr |= variant->opendrain; 1673 } else { 1674 /* 1675 * If the variant cannot configure the pads by its own, then we 1676 * expect the pinctrl to be able to do that for us 1677 */ 1678 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1679 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1680 else 1681 pinctrl_select_state(host->pinctrl, host->pins_default); 1682 } 1683 1684 /* 1685 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1686 * gating the clock, the MCI_PWR_ON bit is cleared. 1687 */ 1688 if (!ios->clock && variant->pwrreg_clkgate) 1689 pwr &= ~MCI_PWR_ON; 1690 1691 if (host->variant->explicit_mclk_control && 1692 ios->clock != host->clock_cache) { 1693 ret = clk_set_rate(host->clk, ios->clock); 1694 if (ret < 0) 1695 dev_err(mmc_dev(host->mmc), 1696 "Error setting clock rate (%d)\n", ret); 1697 else 1698 host->mclk = clk_get_rate(host->clk); 1699 } 1700 host->clock_cache = ios->clock; 1701 1702 spin_lock_irqsave(&host->lock, flags); 1703 1704 if (host->ops && host->ops->set_clkreg) 1705 host->ops->set_clkreg(host, ios->clock); 1706 else 1707 mmci_set_clkreg(host, ios->clock); 1708 1709 if (host->ops && host->ops->set_pwrreg) 1710 host->ops->set_pwrreg(host, pwr); 1711 else 1712 mmci_write_pwrreg(host, pwr); 1713 1714 mmci_reg_delay(host); 1715 1716 spin_unlock_irqrestore(&host->lock, flags); 1717 } 1718 1719 static int mmci_get_cd(struct mmc_host *mmc) 1720 { 1721 struct mmci_host *host = mmc_priv(mmc); 1722 struct mmci_platform_data *plat = host->plat; 1723 unsigned int status = mmc_gpio_get_cd(mmc); 1724 1725 if (status == -ENOSYS) { 1726 if (!plat->status) 1727 return 1; /* Assume always present */ 1728 1729 status = plat->status(mmc_dev(host->mmc)); 1730 } 1731 return status; 1732 } 1733 1734 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1735 { 1736 int ret = 0; 1737 1738 if (!IS_ERR(mmc->supply.vqmmc)) { 1739 1740 switch (ios->signal_voltage) { 1741 case MMC_SIGNAL_VOLTAGE_330: 1742 ret = regulator_set_voltage(mmc->supply.vqmmc, 1743 2700000, 3600000); 1744 break; 1745 case MMC_SIGNAL_VOLTAGE_180: 1746 ret = regulator_set_voltage(mmc->supply.vqmmc, 1747 1700000, 1950000); 1748 break; 1749 case MMC_SIGNAL_VOLTAGE_120: 1750 ret = regulator_set_voltage(mmc->supply.vqmmc, 1751 1100000, 1300000); 1752 break; 1753 } 1754 1755 if (ret) 1756 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1757 } 1758 1759 return ret; 1760 } 1761 1762 static struct mmc_host_ops mmci_ops = { 1763 .request = mmci_request, 1764 .pre_req = mmci_pre_request, 1765 .post_req = mmci_post_request, 1766 .set_ios = mmci_set_ios, 1767 .get_ro = mmc_gpio_get_ro, 1768 .get_cd = mmci_get_cd, 1769 .start_signal_voltage_switch = mmci_sig_volt_switch, 1770 }; 1771 1772 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1773 { 1774 struct mmci_host *host = mmc_priv(mmc); 1775 int ret = mmc_of_parse(mmc); 1776 1777 if (ret) 1778 return ret; 1779 1780 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1781 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1782 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1783 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1784 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1785 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1786 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1787 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1788 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1789 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1790 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1791 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1792 if (of_get_property(np, "st,sig-dir", NULL)) 1793 host->pwr_reg_add |= MCI_STM32_DIRPOL; 1794 if (of_get_property(np, "st,neg-edge", NULL)) 1795 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 1796 if (of_get_property(np, "st,use-ckin", NULL)) 1797 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1798 1799 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1800 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1801 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1802 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1803 1804 return 0; 1805 } 1806 1807 static int mmci_probe(struct amba_device *dev, 1808 const struct amba_id *id) 1809 { 1810 struct mmci_platform_data *plat = dev->dev.platform_data; 1811 struct device_node *np = dev->dev.of_node; 1812 struct variant_data *variant = id->data; 1813 struct mmci_host *host; 1814 struct mmc_host *mmc; 1815 int ret; 1816 1817 /* Must have platform data or Device Tree. */ 1818 if (!plat && !np) { 1819 dev_err(&dev->dev, "No plat data or DT found\n"); 1820 return -EINVAL; 1821 } 1822 1823 if (!plat) { 1824 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1825 if (!plat) 1826 return -ENOMEM; 1827 } 1828 1829 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1830 if (!mmc) 1831 return -ENOMEM; 1832 1833 ret = mmci_of_parse(np, mmc); 1834 if (ret) 1835 goto host_free; 1836 1837 host = mmc_priv(mmc); 1838 host->mmc = mmc; 1839 1840 /* 1841 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1842 * pins can be set accordingly using pinctrl 1843 */ 1844 if (!variant->opendrain) { 1845 host->pinctrl = devm_pinctrl_get(&dev->dev); 1846 if (IS_ERR(host->pinctrl)) { 1847 dev_err(&dev->dev, "failed to get pinctrl"); 1848 ret = PTR_ERR(host->pinctrl); 1849 goto host_free; 1850 } 1851 1852 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1853 PINCTRL_STATE_DEFAULT); 1854 if (IS_ERR(host->pins_default)) { 1855 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1856 ret = PTR_ERR(host->pins_default); 1857 goto host_free; 1858 } 1859 1860 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1861 MMCI_PINCTRL_STATE_OPENDRAIN); 1862 if (IS_ERR(host->pins_opendrain)) { 1863 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1864 ret = PTR_ERR(host->pins_opendrain); 1865 goto host_free; 1866 } 1867 } 1868 1869 host->hw_designer = amba_manf(dev); 1870 host->hw_revision = amba_rev(dev); 1871 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1872 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1873 1874 host->clk = devm_clk_get(&dev->dev, NULL); 1875 if (IS_ERR(host->clk)) { 1876 ret = PTR_ERR(host->clk); 1877 goto host_free; 1878 } 1879 1880 ret = clk_prepare_enable(host->clk); 1881 if (ret) 1882 goto host_free; 1883 1884 if (variant->qcom_fifo) 1885 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1886 else 1887 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1888 1889 host->plat = plat; 1890 host->variant = variant; 1891 host->mclk = clk_get_rate(host->clk); 1892 /* 1893 * According to the spec, mclk is max 100 MHz, 1894 * so we try to adjust the clock down to this, 1895 * (if possible). 1896 */ 1897 if (host->mclk > variant->f_max) { 1898 ret = clk_set_rate(host->clk, variant->f_max); 1899 if (ret < 0) 1900 goto clk_disable; 1901 host->mclk = clk_get_rate(host->clk); 1902 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1903 host->mclk); 1904 } 1905 1906 host->phybase = dev->res.start; 1907 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1908 if (IS_ERR(host->base)) { 1909 ret = PTR_ERR(host->base); 1910 goto clk_disable; 1911 } 1912 1913 if (variant->init) 1914 variant->init(host); 1915 1916 /* 1917 * The ARM and ST versions of the block have slightly different 1918 * clock divider equations which means that the minimum divider 1919 * differs too. 1920 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1921 */ 1922 if (variant->st_clkdiv) 1923 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1924 else if (variant->stm32_clkdiv) 1925 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 1926 else if (variant->explicit_mclk_control) 1927 mmc->f_min = clk_round_rate(host->clk, 100000); 1928 else 1929 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1930 /* 1931 * If no maximum operating frequency is supplied, fall back to use 1932 * the module parameter, which has a (low) default value in case it 1933 * is not specified. Either value must not exceed the clock rate into 1934 * the block, of course. 1935 */ 1936 if (mmc->f_max) 1937 mmc->f_max = variant->explicit_mclk_control ? 1938 min(variant->f_max, mmc->f_max) : 1939 min(host->mclk, mmc->f_max); 1940 else 1941 mmc->f_max = variant->explicit_mclk_control ? 1942 fmax : min(host->mclk, fmax); 1943 1944 1945 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1946 1947 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 1948 if (IS_ERR(host->rst)) { 1949 ret = PTR_ERR(host->rst); 1950 goto clk_disable; 1951 } 1952 1953 /* Get regulators and the supported OCR mask */ 1954 ret = mmc_regulator_get_supply(mmc); 1955 if (ret) 1956 goto clk_disable; 1957 1958 if (!mmc->ocr_avail) 1959 mmc->ocr_avail = plat->ocr_mask; 1960 else if (plat->ocr_mask) 1961 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1962 1963 /* We support these capabilities. */ 1964 mmc->caps |= MMC_CAP_CMD23; 1965 1966 /* 1967 * Enable busy detection. 1968 */ 1969 if (variant->busy_detect) { 1970 mmci_ops.card_busy = mmci_card_busy; 1971 /* 1972 * Not all variants have a flag to enable busy detection 1973 * in the DPSM, but if they do, set it here. 1974 */ 1975 if (variant->busy_dpsm_flag) 1976 mmci_write_datactrlreg(host, 1977 host->variant->busy_dpsm_flag); 1978 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1979 mmc->max_busy_timeout = 0; 1980 } 1981 1982 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 1983 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 1984 host->stop_abort.arg = 0; 1985 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 1986 1987 mmc->ops = &mmci_ops; 1988 1989 /* We support these PM capabilities. */ 1990 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1991 1992 /* 1993 * We can do SGIO 1994 */ 1995 mmc->max_segs = NR_SG; 1996 1997 /* 1998 * Since only a certain number of bits are valid in the data length 1999 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2000 * single request. 2001 */ 2002 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2003 2004 /* 2005 * Set the maximum segment size. Since we aren't doing DMA 2006 * (yet) we are only limited by the data length register. 2007 */ 2008 mmc->max_seg_size = mmc->max_req_size; 2009 2010 /* 2011 * Block size can be up to 2048 bytes, but must be a power of two. 2012 */ 2013 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2014 2015 /* 2016 * Limit the number of blocks transferred so that we don't overflow 2017 * the maximum request size. 2018 */ 2019 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2020 2021 spin_lock_init(&host->lock); 2022 2023 writel(0, host->base + MMCIMASK0); 2024 2025 if (variant->mmcimask1) 2026 writel(0, host->base + MMCIMASK1); 2027 2028 writel(0xfff, host->base + MMCICLEAR); 2029 2030 /* 2031 * If: 2032 * - not using DT but using a descriptor table, or 2033 * - using a table of descriptors ALONGSIDE DT, or 2034 * look up these descriptors named "cd" and "wp" right here, fail 2035 * silently of these do not exist 2036 */ 2037 if (!np) { 2038 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 2039 if (ret == -EPROBE_DEFER) 2040 goto clk_disable; 2041 2042 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL); 2043 if (ret == -EPROBE_DEFER) 2044 goto clk_disable; 2045 } 2046 2047 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 2048 DRIVER_NAME " (cmd)", host); 2049 if (ret) 2050 goto clk_disable; 2051 2052 if (!dev->irq[1]) 2053 host->singleirq = true; 2054 else { 2055 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2056 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2057 if (ret) 2058 goto clk_disable; 2059 } 2060 2061 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2062 2063 amba_set_drvdata(dev, mmc); 2064 2065 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2066 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2067 amba_rev(dev), (unsigned long long)dev->res.start, 2068 dev->irq[0], dev->irq[1]); 2069 2070 mmci_dma_setup(host); 2071 2072 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2073 pm_runtime_use_autosuspend(&dev->dev); 2074 2075 mmc_add_host(mmc); 2076 2077 pm_runtime_put(&dev->dev); 2078 return 0; 2079 2080 clk_disable: 2081 clk_disable_unprepare(host->clk); 2082 host_free: 2083 mmc_free_host(mmc); 2084 return ret; 2085 } 2086 2087 static int mmci_remove(struct amba_device *dev) 2088 { 2089 struct mmc_host *mmc = amba_get_drvdata(dev); 2090 2091 if (mmc) { 2092 struct mmci_host *host = mmc_priv(mmc); 2093 struct variant_data *variant = host->variant; 2094 2095 /* 2096 * Undo pm_runtime_put() in probe. We use the _sync 2097 * version here so that we can access the primecell. 2098 */ 2099 pm_runtime_get_sync(&dev->dev); 2100 2101 mmc_remove_host(mmc); 2102 2103 writel(0, host->base + MMCIMASK0); 2104 2105 if (variant->mmcimask1) 2106 writel(0, host->base + MMCIMASK1); 2107 2108 writel(0, host->base + MMCICOMMAND); 2109 writel(0, host->base + MMCIDATACTRL); 2110 2111 mmci_dma_release(host); 2112 clk_disable_unprepare(host->clk); 2113 mmc_free_host(mmc); 2114 } 2115 2116 return 0; 2117 } 2118 2119 #ifdef CONFIG_PM 2120 static void mmci_save(struct mmci_host *host) 2121 { 2122 unsigned long flags; 2123 2124 spin_lock_irqsave(&host->lock, flags); 2125 2126 writel(0, host->base + MMCIMASK0); 2127 if (host->variant->pwrreg_nopower) { 2128 writel(0, host->base + MMCIDATACTRL); 2129 writel(0, host->base + MMCIPOWER); 2130 writel(0, host->base + MMCICLOCK); 2131 } 2132 mmci_reg_delay(host); 2133 2134 spin_unlock_irqrestore(&host->lock, flags); 2135 } 2136 2137 static void mmci_restore(struct mmci_host *host) 2138 { 2139 unsigned long flags; 2140 2141 spin_lock_irqsave(&host->lock, flags); 2142 2143 if (host->variant->pwrreg_nopower) { 2144 writel(host->clk_reg, host->base + MMCICLOCK); 2145 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2146 writel(host->pwr_reg, host->base + MMCIPOWER); 2147 } 2148 writel(MCI_IRQENABLE | host->variant->start_err, 2149 host->base + MMCIMASK0); 2150 mmci_reg_delay(host); 2151 2152 spin_unlock_irqrestore(&host->lock, flags); 2153 } 2154 2155 static int mmci_runtime_suspend(struct device *dev) 2156 { 2157 struct amba_device *adev = to_amba_device(dev); 2158 struct mmc_host *mmc = amba_get_drvdata(adev); 2159 2160 if (mmc) { 2161 struct mmci_host *host = mmc_priv(mmc); 2162 pinctrl_pm_select_sleep_state(dev); 2163 mmci_save(host); 2164 clk_disable_unprepare(host->clk); 2165 } 2166 2167 return 0; 2168 } 2169 2170 static int mmci_runtime_resume(struct device *dev) 2171 { 2172 struct amba_device *adev = to_amba_device(dev); 2173 struct mmc_host *mmc = amba_get_drvdata(adev); 2174 2175 if (mmc) { 2176 struct mmci_host *host = mmc_priv(mmc); 2177 clk_prepare_enable(host->clk); 2178 mmci_restore(host); 2179 pinctrl_pm_select_default_state(dev); 2180 } 2181 2182 return 0; 2183 } 2184 #endif 2185 2186 static const struct dev_pm_ops mmci_dev_pm_ops = { 2187 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2188 pm_runtime_force_resume) 2189 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2190 }; 2191 2192 static const struct amba_id mmci_ids[] = { 2193 { 2194 .id = 0x00041180, 2195 .mask = 0xff0fffff, 2196 .data = &variant_arm, 2197 }, 2198 { 2199 .id = 0x01041180, 2200 .mask = 0xff0fffff, 2201 .data = &variant_arm_extended_fifo, 2202 }, 2203 { 2204 .id = 0x02041180, 2205 .mask = 0xff0fffff, 2206 .data = &variant_arm_extended_fifo_hwfc, 2207 }, 2208 { 2209 .id = 0x00041181, 2210 .mask = 0x000fffff, 2211 .data = &variant_arm, 2212 }, 2213 /* ST Micro variants */ 2214 { 2215 .id = 0x00180180, 2216 .mask = 0x00ffffff, 2217 .data = &variant_u300, 2218 }, 2219 { 2220 .id = 0x10180180, 2221 .mask = 0xf0ffffff, 2222 .data = &variant_nomadik, 2223 }, 2224 { 2225 .id = 0x00280180, 2226 .mask = 0x00ffffff, 2227 .data = &variant_nomadik, 2228 }, 2229 { 2230 .id = 0x00480180, 2231 .mask = 0xf0ffffff, 2232 .data = &variant_ux500, 2233 }, 2234 { 2235 .id = 0x10480180, 2236 .mask = 0xf0ffffff, 2237 .data = &variant_ux500v2, 2238 }, 2239 { 2240 .id = 0x00880180, 2241 .mask = 0x00ffffff, 2242 .data = &variant_stm32, 2243 }, 2244 { 2245 .id = 0x10153180, 2246 .mask = 0xf0ffffff, 2247 .data = &variant_stm32_sdmmc, 2248 }, 2249 /* Qualcomm variants */ 2250 { 2251 .id = 0x00051180, 2252 .mask = 0x000fffff, 2253 .data = &variant_qcom, 2254 }, 2255 { 0, 0 }, 2256 }; 2257 2258 MODULE_DEVICE_TABLE(amba, mmci_ids); 2259 2260 static struct amba_driver mmci_driver = { 2261 .drv = { 2262 .name = DRIVER_NAME, 2263 .pm = &mmci_dev_pm_ops, 2264 }, 2265 .probe = mmci_probe, 2266 .remove = mmci_remove, 2267 .id_table = mmci_ids, 2268 }; 2269 2270 module_amba_driver(mmci_driver); 2271 2272 module_param(fmax, uint, 0444); 2273 2274 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2275 MODULE_LICENSE("GPL"); 2276