1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/slot-gpio.h> 26 #include <linux/amba/bus.h> 27 #include <linux/clk.h> 28 #include <linux/scatterlist.h> 29 #include <linux/of.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/dmaengine.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/amba/mmci.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/types.h> 36 #include <linux/pinctrl/consumer.h> 37 #include <linux/reset.h> 38 39 #include <asm/div64.h> 40 #include <asm/io.h> 41 42 #include "mmci.h" 43 44 #define DRIVER_NAME "mmci-pl18x" 45 46 static void mmci_variant_init(struct mmci_host *host); 47 static void ux500_variant_init(struct mmci_host *host); 48 static void ux500v2_variant_init(struct mmci_host *host); 49 50 static unsigned int fmax = 515633; 51 52 static struct variant_data variant_arm = { 53 .fifosize = 16 * 4, 54 .fifohalfsize = 8 * 4, 55 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 56 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 57 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 58 .cmdreg_srsp = MCI_CPSM_RESPONSE, 59 .datalength_bits = 16, 60 .datactrl_blocksz = 11, 61 .pwrreg_powerup = MCI_PWR_UP, 62 .f_max = 100000000, 63 .reversed_irq_handling = true, 64 .mmcimask1 = true, 65 .irq_pio_mask = MCI_IRQ_PIO_MASK, 66 .start_err = MCI_STARTBITERR, 67 .opendrain = MCI_ROD, 68 .init = mmci_variant_init, 69 }; 70 71 static struct variant_data variant_arm_extended_fifo = { 72 .fifosize = 128 * 4, 73 .fifohalfsize = 64 * 4, 74 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 75 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 76 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 77 .cmdreg_srsp = MCI_CPSM_RESPONSE, 78 .datalength_bits = 16, 79 .datactrl_blocksz = 11, 80 .pwrreg_powerup = MCI_PWR_UP, 81 .f_max = 100000000, 82 .mmcimask1 = true, 83 .irq_pio_mask = MCI_IRQ_PIO_MASK, 84 .start_err = MCI_STARTBITERR, 85 .opendrain = MCI_ROD, 86 .init = mmci_variant_init, 87 }; 88 89 static struct variant_data variant_arm_extended_fifo_hwfc = { 90 .fifosize = 128 * 4, 91 .fifohalfsize = 64 * 4, 92 .clkreg_enable = MCI_ARM_HWFCEN, 93 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 94 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 95 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 96 .cmdreg_srsp = MCI_CPSM_RESPONSE, 97 .datalength_bits = 16, 98 .datactrl_blocksz = 11, 99 .pwrreg_powerup = MCI_PWR_UP, 100 .f_max = 100000000, 101 .mmcimask1 = true, 102 .irq_pio_mask = MCI_IRQ_PIO_MASK, 103 .start_err = MCI_STARTBITERR, 104 .opendrain = MCI_ROD, 105 .init = mmci_variant_init, 106 }; 107 108 static struct variant_data variant_u300 = { 109 .fifosize = 16 * 4, 110 .fifohalfsize = 8 * 4, 111 .clkreg_enable = MCI_ST_U300_HWFCEN, 112 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 113 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 114 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 115 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 116 .cmdreg_srsp = MCI_CPSM_RESPONSE, 117 .datalength_bits = 16, 118 .datactrl_blocksz = 11, 119 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 120 .st_sdio = true, 121 .pwrreg_powerup = MCI_PWR_ON, 122 .f_max = 100000000, 123 .signal_direction = true, 124 .pwrreg_clkgate = true, 125 .pwrreg_nopower = true, 126 .mmcimask1 = true, 127 .irq_pio_mask = MCI_IRQ_PIO_MASK, 128 .start_err = MCI_STARTBITERR, 129 .opendrain = MCI_OD, 130 .init = mmci_variant_init, 131 }; 132 133 static struct variant_data variant_nomadik = { 134 .fifosize = 16 * 4, 135 .fifohalfsize = 8 * 4, 136 .clkreg = MCI_CLK_ENABLE, 137 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 138 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 139 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 140 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 141 .cmdreg_srsp = MCI_CPSM_RESPONSE, 142 .datalength_bits = 24, 143 .datactrl_blocksz = 11, 144 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 145 .st_sdio = true, 146 .st_clkdiv = true, 147 .pwrreg_powerup = MCI_PWR_ON, 148 .f_max = 100000000, 149 .signal_direction = true, 150 .pwrreg_clkgate = true, 151 .pwrreg_nopower = true, 152 .mmcimask1 = true, 153 .irq_pio_mask = MCI_IRQ_PIO_MASK, 154 .start_err = MCI_STARTBITERR, 155 .opendrain = MCI_OD, 156 .init = mmci_variant_init, 157 }; 158 159 static struct variant_data variant_ux500 = { 160 .fifosize = 30 * 4, 161 .fifohalfsize = 8 * 4, 162 .clkreg = MCI_CLK_ENABLE, 163 .clkreg_enable = MCI_ST_UX500_HWFCEN, 164 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 165 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 166 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 167 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 168 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 169 .cmdreg_srsp = MCI_CPSM_RESPONSE, 170 .datalength_bits = 24, 171 .datactrl_blocksz = 11, 172 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 173 .st_sdio = true, 174 .st_clkdiv = true, 175 .pwrreg_powerup = MCI_PWR_ON, 176 .f_max = 100000000, 177 .signal_direction = true, 178 .pwrreg_clkgate = true, 179 .busy_detect = true, 180 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 181 .busy_detect_flag = MCI_ST_CARDBUSY, 182 .busy_detect_mask = MCI_ST_BUSYENDMASK, 183 .pwrreg_nopower = true, 184 .mmcimask1 = true, 185 .irq_pio_mask = MCI_IRQ_PIO_MASK, 186 .start_err = MCI_STARTBITERR, 187 .opendrain = MCI_OD, 188 .init = ux500_variant_init, 189 }; 190 191 static struct variant_data variant_ux500v2 = { 192 .fifosize = 30 * 4, 193 .fifohalfsize = 8 * 4, 194 .clkreg = MCI_CLK_ENABLE, 195 .clkreg_enable = MCI_ST_UX500_HWFCEN, 196 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 197 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 198 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 199 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 200 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 201 .cmdreg_srsp = MCI_CPSM_RESPONSE, 202 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 203 .datalength_bits = 24, 204 .datactrl_blocksz = 11, 205 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 206 .st_sdio = true, 207 .st_clkdiv = true, 208 .pwrreg_powerup = MCI_PWR_ON, 209 .f_max = 100000000, 210 .signal_direction = true, 211 .pwrreg_clkgate = true, 212 .busy_detect = true, 213 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 214 .busy_detect_flag = MCI_ST_CARDBUSY, 215 .busy_detect_mask = MCI_ST_BUSYENDMASK, 216 .pwrreg_nopower = true, 217 .mmcimask1 = true, 218 .irq_pio_mask = MCI_IRQ_PIO_MASK, 219 .start_err = MCI_STARTBITERR, 220 .opendrain = MCI_OD, 221 .init = ux500v2_variant_init, 222 }; 223 224 static struct variant_data variant_stm32 = { 225 .fifosize = 32 * 4, 226 .fifohalfsize = 8 * 4, 227 .clkreg = MCI_CLK_ENABLE, 228 .clkreg_enable = MCI_ST_UX500_HWFCEN, 229 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 230 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 231 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 232 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 233 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 234 .cmdreg_srsp = MCI_CPSM_RESPONSE, 235 .irq_pio_mask = MCI_IRQ_PIO_MASK, 236 .datalength_bits = 24, 237 .datactrl_blocksz = 11, 238 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 239 .st_sdio = true, 240 .st_clkdiv = true, 241 .pwrreg_powerup = MCI_PWR_ON, 242 .f_max = 48000000, 243 .pwrreg_clkgate = true, 244 .pwrreg_nopower = true, 245 .init = mmci_variant_init, 246 }; 247 248 static struct variant_data variant_stm32_sdmmc = { 249 .fifosize = 16 * 4, 250 .fifohalfsize = 8 * 4, 251 .f_max = 208000000, 252 .stm32_clkdiv = true, 253 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 254 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 255 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 256 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 257 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 258 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 259 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 260 .datactrl_first = true, 261 .datacnt_useless = true, 262 .datalength_bits = 25, 263 .datactrl_blocksz = 14, 264 .stm32_idmabsize_mask = GENMASK(12, 5), 265 .busy_timeout = true, 266 .busy_detect = true, 267 .busy_detect_flag = MCI_STM32_BUSYD0, 268 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 269 .init = sdmmc_variant_init, 270 }; 271 272 static struct variant_data variant_qcom = { 273 .fifosize = 16 * 4, 274 .fifohalfsize = 8 * 4, 275 .clkreg = MCI_CLK_ENABLE, 276 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 277 MCI_QCOM_CLK_SELECT_IN_FBCLK, 278 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 279 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 280 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 281 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 282 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 283 .cmdreg_srsp = MCI_CPSM_RESPONSE, 284 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 285 .datalength_bits = 24, 286 .datactrl_blocksz = 11, 287 .pwrreg_powerup = MCI_PWR_UP, 288 .f_max = 208000000, 289 .explicit_mclk_control = true, 290 .qcom_fifo = true, 291 .qcom_dml = true, 292 .mmcimask1 = true, 293 .irq_pio_mask = MCI_IRQ_PIO_MASK, 294 .start_err = MCI_STARTBITERR, 295 .opendrain = MCI_ROD, 296 .init = qcom_variant_init, 297 }; 298 299 /* Busy detection for the ST Micro variant */ 300 static int mmci_card_busy(struct mmc_host *mmc) 301 { 302 struct mmci_host *host = mmc_priv(mmc); 303 unsigned long flags; 304 int busy = 0; 305 306 spin_lock_irqsave(&host->lock, flags); 307 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 308 busy = 1; 309 spin_unlock_irqrestore(&host->lock, flags); 310 311 return busy; 312 } 313 314 static void mmci_reg_delay(struct mmci_host *host) 315 { 316 /* 317 * According to the spec, at least three feedback clock cycles 318 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 319 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 320 * Worst delay time during card init is at 100 kHz => 30 us. 321 * Worst delay time when up and running is at 25 MHz => 120 ns. 322 */ 323 if (host->cclk < 25000000) 324 udelay(30); 325 else 326 ndelay(120); 327 } 328 329 /* 330 * This must be called with host->lock held 331 */ 332 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 333 { 334 if (host->clk_reg != clk) { 335 host->clk_reg = clk; 336 writel(clk, host->base + MMCICLOCK); 337 } 338 } 339 340 /* 341 * This must be called with host->lock held 342 */ 343 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 344 { 345 if (host->pwr_reg != pwr) { 346 host->pwr_reg = pwr; 347 writel(pwr, host->base + MMCIPOWER); 348 } 349 } 350 351 /* 352 * This must be called with host->lock held 353 */ 354 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 355 { 356 /* Keep busy mode in DPSM if enabled */ 357 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 358 359 if (host->datactrl_reg != datactrl) { 360 host->datactrl_reg = datactrl; 361 writel(datactrl, host->base + MMCIDATACTRL); 362 } 363 } 364 365 /* 366 * This must be called with host->lock held 367 */ 368 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 369 { 370 struct variant_data *variant = host->variant; 371 u32 clk = variant->clkreg; 372 373 /* Make sure cclk reflects the current calculated clock */ 374 host->cclk = 0; 375 376 if (desired) { 377 if (variant->explicit_mclk_control) { 378 host->cclk = host->mclk; 379 } else if (desired >= host->mclk) { 380 clk = MCI_CLK_BYPASS; 381 if (variant->st_clkdiv) 382 clk |= MCI_ST_UX500_NEG_EDGE; 383 host->cclk = host->mclk; 384 } else if (variant->st_clkdiv) { 385 /* 386 * DB8500 TRM says f = mclk / (clkdiv + 2) 387 * => clkdiv = (mclk / f) - 2 388 * Round the divider up so we don't exceed the max 389 * frequency 390 */ 391 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 392 if (clk >= 256) 393 clk = 255; 394 host->cclk = host->mclk / (clk + 2); 395 } else { 396 /* 397 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 398 * => clkdiv = mclk / (2 * f) - 1 399 */ 400 clk = host->mclk / (2 * desired) - 1; 401 if (clk >= 256) 402 clk = 255; 403 host->cclk = host->mclk / (2 * (clk + 1)); 404 } 405 406 clk |= variant->clkreg_enable; 407 clk |= MCI_CLK_ENABLE; 408 /* This hasn't proven to be worthwhile */ 409 /* clk |= MCI_CLK_PWRSAVE; */ 410 } 411 412 /* Set actual clock for debug */ 413 host->mmc->actual_clock = host->cclk; 414 415 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 416 clk |= MCI_4BIT_BUS; 417 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 418 clk |= variant->clkreg_8bit_bus_enable; 419 420 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 421 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 422 clk |= variant->clkreg_neg_edge_enable; 423 424 mmci_write_clkreg(host, clk); 425 } 426 427 static void mmci_dma_release(struct mmci_host *host) 428 { 429 if (host->ops && host->ops->dma_release) 430 host->ops->dma_release(host); 431 432 host->use_dma = false; 433 } 434 435 static void mmci_dma_setup(struct mmci_host *host) 436 { 437 if (!host->ops || !host->ops->dma_setup) 438 return; 439 440 if (host->ops->dma_setup(host)) 441 return; 442 443 /* initialize pre request cookie */ 444 host->next_cookie = 1; 445 446 host->use_dma = true; 447 } 448 449 /* 450 * Validate mmc prerequisites 451 */ 452 static int mmci_validate_data(struct mmci_host *host, 453 struct mmc_data *data) 454 { 455 if (!data) 456 return 0; 457 458 if (!is_power_of_2(data->blksz)) { 459 dev_err(mmc_dev(host->mmc), 460 "unsupported block size (%d bytes)\n", data->blksz); 461 return -EINVAL; 462 } 463 464 if (host->ops && host->ops->validate_data) 465 return host->ops->validate_data(host, data); 466 467 return 0; 468 } 469 470 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 471 { 472 int err; 473 474 if (!host->ops || !host->ops->prep_data) 475 return 0; 476 477 err = host->ops->prep_data(host, data, next); 478 479 if (next && !err) 480 data->host_cookie = ++host->next_cookie < 0 ? 481 1 : host->next_cookie; 482 483 return err; 484 } 485 486 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 487 int err) 488 { 489 if (host->ops && host->ops->unprep_data) 490 host->ops->unprep_data(host, data, err); 491 492 data->host_cookie = 0; 493 } 494 495 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 496 { 497 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 498 499 if (host->ops && host->ops->get_next_data) 500 host->ops->get_next_data(host, data); 501 } 502 503 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 504 { 505 struct mmc_data *data = host->data; 506 int ret; 507 508 if (!host->use_dma) 509 return -EINVAL; 510 511 ret = mmci_prep_data(host, data, false); 512 if (ret) 513 return ret; 514 515 if (!host->ops || !host->ops->dma_start) 516 return -EINVAL; 517 518 /* Okay, go for it. */ 519 dev_vdbg(mmc_dev(host->mmc), 520 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 521 data->sg_len, data->blksz, data->blocks, data->flags); 522 523 host->ops->dma_start(host, &datactrl); 524 525 /* Trigger the DMA transfer */ 526 mmci_write_datactrlreg(host, datactrl); 527 528 /* 529 * Let the MMCI say when the data is ended and it's time 530 * to fire next DMA request. When that happens, MMCI will 531 * call mmci_data_end() 532 */ 533 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 534 host->base + MMCIMASK0); 535 return 0; 536 } 537 538 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 539 { 540 if (!host->use_dma) 541 return; 542 543 if (host->ops && host->ops->dma_finalize) 544 host->ops->dma_finalize(host, data); 545 } 546 547 static void mmci_dma_error(struct mmci_host *host) 548 { 549 if (!host->use_dma) 550 return; 551 552 if (host->ops && host->ops->dma_error) 553 host->ops->dma_error(host); 554 } 555 556 static void 557 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 558 { 559 writel(0, host->base + MMCICOMMAND); 560 561 BUG_ON(host->data); 562 563 host->mrq = NULL; 564 host->cmd = NULL; 565 566 mmc_request_done(host->mmc, mrq); 567 } 568 569 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 570 { 571 void __iomem *base = host->base; 572 struct variant_data *variant = host->variant; 573 574 if (host->singleirq) { 575 unsigned int mask0 = readl(base + MMCIMASK0); 576 577 mask0 &= ~variant->irq_pio_mask; 578 mask0 |= mask; 579 580 writel(mask0, base + MMCIMASK0); 581 } 582 583 if (variant->mmcimask1) 584 writel(mask, base + MMCIMASK1); 585 586 host->mask1_reg = mask; 587 } 588 589 static void mmci_stop_data(struct mmci_host *host) 590 { 591 mmci_write_datactrlreg(host, 0); 592 mmci_set_mask1(host, 0); 593 host->data = NULL; 594 } 595 596 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 597 { 598 unsigned int flags = SG_MITER_ATOMIC; 599 600 if (data->flags & MMC_DATA_READ) 601 flags |= SG_MITER_TO_SG; 602 else 603 flags |= SG_MITER_FROM_SG; 604 605 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 606 } 607 608 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 609 { 610 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 611 } 612 613 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 614 { 615 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 616 } 617 618 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 619 { 620 void __iomem *base = host->base; 621 622 /* 623 * Before unmasking for the busy end IRQ, confirm that the 624 * command was sent successfully. To keep track of having a 625 * command in-progress, waiting for busy signaling to end, 626 * store the status in host->busy_status. 627 * 628 * Note that, the card may need a couple of clock cycles before 629 * it starts signaling busy on DAT0, hence re-read the 630 * MMCISTATUS register here, to allow the busy bit to be set. 631 * Potentially we may even need to poll the register for a 632 * while, to allow it to be set, but tests indicates that it 633 * isn't needed. 634 */ 635 if (!host->busy_status && !(status & err_msk) && 636 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 637 writel(readl(base + MMCIMASK0) | 638 host->variant->busy_detect_mask, 639 base + MMCIMASK0); 640 641 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 642 return false; 643 } 644 645 /* 646 * If there is a command in-progress that has been successfully 647 * sent, then bail out if busy status is set and wait for the 648 * busy end IRQ. 649 * 650 * Note that, the HW triggers an IRQ on both edges while 651 * monitoring DAT0 for busy completion, but there is only one 652 * status bit in MMCISTATUS for the busy state. Therefore 653 * both the start and the end interrupts needs to be cleared, 654 * one after the other. So, clear the busy start IRQ here. 655 */ 656 if (host->busy_status && 657 (status & host->variant->busy_detect_flag)) { 658 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 659 return false; 660 } 661 662 /* 663 * If there is a command in-progress that has been successfully 664 * sent and the busy bit isn't set, it means we have received 665 * the busy end IRQ. Clear and mask the IRQ, then continue to 666 * process the command. 667 */ 668 if (host->busy_status) { 669 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 670 671 writel(readl(base + MMCIMASK0) & 672 ~host->variant->busy_detect_mask, base + MMCIMASK0); 673 host->busy_status = 0; 674 } 675 676 return true; 677 } 678 679 /* 680 * All the DMA operation mode stuff goes inside this ifdef. 681 * This assumes that you have a generic DMA device interface, 682 * no custom DMA interfaces are supported. 683 */ 684 #ifdef CONFIG_DMA_ENGINE 685 struct mmci_dmae_next { 686 struct dma_async_tx_descriptor *desc; 687 struct dma_chan *chan; 688 }; 689 690 struct mmci_dmae_priv { 691 struct dma_chan *cur; 692 struct dma_chan *rx_channel; 693 struct dma_chan *tx_channel; 694 struct dma_async_tx_descriptor *desc_current; 695 struct mmci_dmae_next next_data; 696 }; 697 698 int mmci_dmae_setup(struct mmci_host *host) 699 { 700 const char *rxname, *txname; 701 struct mmci_dmae_priv *dmae; 702 703 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 704 if (!dmae) 705 return -ENOMEM; 706 707 host->dma_priv = dmae; 708 709 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 710 "rx"); 711 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 712 "tx"); 713 714 /* 715 * If only an RX channel is specified, the driver will 716 * attempt to use it bidirectionally, however if it is 717 * is specified but cannot be located, DMA will be disabled. 718 */ 719 if (dmae->rx_channel && !dmae->tx_channel) 720 dmae->tx_channel = dmae->rx_channel; 721 722 if (dmae->rx_channel) 723 rxname = dma_chan_name(dmae->rx_channel); 724 else 725 rxname = "none"; 726 727 if (dmae->tx_channel) 728 txname = dma_chan_name(dmae->tx_channel); 729 else 730 txname = "none"; 731 732 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 733 rxname, txname); 734 735 /* 736 * Limit the maximum segment size in any SG entry according to 737 * the parameters of the DMA engine device. 738 */ 739 if (dmae->tx_channel) { 740 struct device *dev = dmae->tx_channel->device->dev; 741 unsigned int max_seg_size = dma_get_max_seg_size(dev); 742 743 if (max_seg_size < host->mmc->max_seg_size) 744 host->mmc->max_seg_size = max_seg_size; 745 } 746 if (dmae->rx_channel) { 747 struct device *dev = dmae->rx_channel->device->dev; 748 unsigned int max_seg_size = dma_get_max_seg_size(dev); 749 750 if (max_seg_size < host->mmc->max_seg_size) 751 host->mmc->max_seg_size = max_seg_size; 752 } 753 754 if (!dmae->tx_channel || !dmae->rx_channel) { 755 mmci_dmae_release(host); 756 return -EINVAL; 757 } 758 759 return 0; 760 } 761 762 /* 763 * This is used in or so inline it 764 * so it can be discarded. 765 */ 766 void mmci_dmae_release(struct mmci_host *host) 767 { 768 struct mmci_dmae_priv *dmae = host->dma_priv; 769 770 if (dmae->rx_channel) 771 dma_release_channel(dmae->rx_channel); 772 if (dmae->tx_channel) 773 dma_release_channel(dmae->tx_channel); 774 dmae->rx_channel = dmae->tx_channel = NULL; 775 } 776 777 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 778 { 779 struct mmci_dmae_priv *dmae = host->dma_priv; 780 struct dma_chan *chan; 781 782 if (data->flags & MMC_DATA_READ) 783 chan = dmae->rx_channel; 784 else 785 chan = dmae->tx_channel; 786 787 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 788 mmc_get_dma_dir(data)); 789 } 790 791 void mmci_dmae_error(struct mmci_host *host) 792 { 793 struct mmci_dmae_priv *dmae = host->dma_priv; 794 795 if (!dma_inprogress(host)) 796 return; 797 798 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 799 dmaengine_terminate_all(dmae->cur); 800 host->dma_in_progress = false; 801 dmae->cur = NULL; 802 dmae->desc_current = NULL; 803 host->data->host_cookie = 0; 804 805 mmci_dma_unmap(host, host->data); 806 } 807 808 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 809 { 810 struct mmci_dmae_priv *dmae = host->dma_priv; 811 u32 status; 812 int i; 813 814 if (!dma_inprogress(host)) 815 return; 816 817 /* Wait up to 1ms for the DMA to complete */ 818 for (i = 0; ; i++) { 819 status = readl(host->base + MMCISTATUS); 820 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 821 break; 822 udelay(10); 823 } 824 825 /* 826 * Check to see whether we still have some data left in the FIFO - 827 * this catches DMA controllers which are unable to monitor the 828 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 829 * contiguous buffers. On TX, we'll get a FIFO underrun error. 830 */ 831 if (status & MCI_RXDATAAVLBLMASK) { 832 mmci_dma_error(host); 833 if (!data->error) 834 data->error = -EIO; 835 } else if (!data->host_cookie) { 836 mmci_dma_unmap(host, data); 837 } 838 839 /* 840 * Use of DMA with scatter-gather is impossible. 841 * Give up with DMA and switch back to PIO mode. 842 */ 843 if (status & MCI_RXDATAAVLBLMASK) { 844 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 845 mmci_dma_release(host); 846 } 847 848 host->dma_in_progress = false; 849 dmae->cur = NULL; 850 dmae->desc_current = NULL; 851 } 852 853 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 854 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 855 struct dma_chan **dma_chan, 856 struct dma_async_tx_descriptor **dma_desc) 857 { 858 struct mmci_dmae_priv *dmae = host->dma_priv; 859 struct variant_data *variant = host->variant; 860 struct dma_slave_config conf = { 861 .src_addr = host->phybase + MMCIFIFO, 862 .dst_addr = host->phybase + MMCIFIFO, 863 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 864 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 865 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 866 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 867 .device_fc = false, 868 }; 869 struct dma_chan *chan; 870 struct dma_device *device; 871 struct dma_async_tx_descriptor *desc; 872 int nr_sg; 873 unsigned long flags = DMA_CTRL_ACK; 874 875 if (data->flags & MMC_DATA_READ) { 876 conf.direction = DMA_DEV_TO_MEM; 877 chan = dmae->rx_channel; 878 } else { 879 conf.direction = DMA_MEM_TO_DEV; 880 chan = dmae->tx_channel; 881 } 882 883 /* If there's no DMA channel, fall back to PIO */ 884 if (!chan) 885 return -EINVAL; 886 887 /* If less than or equal to the fifo size, don't bother with DMA */ 888 if (data->blksz * data->blocks <= variant->fifosize) 889 return -EINVAL; 890 891 device = chan->device; 892 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 893 mmc_get_dma_dir(data)); 894 if (nr_sg == 0) 895 return -EINVAL; 896 897 if (host->variant->qcom_dml) 898 flags |= DMA_PREP_INTERRUPT; 899 900 dmaengine_slave_config(chan, &conf); 901 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 902 conf.direction, flags); 903 if (!desc) 904 goto unmap_exit; 905 906 *dma_chan = chan; 907 *dma_desc = desc; 908 909 return 0; 910 911 unmap_exit: 912 dma_unmap_sg(device->dev, data->sg, data->sg_len, 913 mmc_get_dma_dir(data)); 914 return -ENOMEM; 915 } 916 917 int mmci_dmae_prep_data(struct mmci_host *host, 918 struct mmc_data *data, 919 bool next) 920 { 921 struct mmci_dmae_priv *dmae = host->dma_priv; 922 struct mmci_dmae_next *nd = &dmae->next_data; 923 924 if (!host->use_dma) 925 return -EINVAL; 926 927 if (next) 928 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 929 /* Check if next job is already prepared. */ 930 if (dmae->cur && dmae->desc_current) 931 return 0; 932 933 /* No job were prepared thus do it now. */ 934 return _mmci_dmae_prep_data(host, data, &dmae->cur, 935 &dmae->desc_current); 936 } 937 938 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 939 { 940 struct mmci_dmae_priv *dmae = host->dma_priv; 941 942 host->dma_in_progress = true; 943 dmaengine_submit(dmae->desc_current); 944 dma_async_issue_pending(dmae->cur); 945 946 *datactrl |= MCI_DPSM_DMAENABLE; 947 948 return 0; 949 } 950 951 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 952 { 953 struct mmci_dmae_priv *dmae = host->dma_priv; 954 struct mmci_dmae_next *next = &dmae->next_data; 955 956 if (!host->use_dma) 957 return; 958 959 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 960 961 dmae->desc_current = next->desc; 962 dmae->cur = next->chan; 963 next->desc = NULL; 964 next->chan = NULL; 965 } 966 967 void mmci_dmae_unprep_data(struct mmci_host *host, 968 struct mmc_data *data, int err) 969 970 { 971 struct mmci_dmae_priv *dmae = host->dma_priv; 972 973 if (!host->use_dma) 974 return; 975 976 mmci_dma_unmap(host, data); 977 978 if (err) { 979 struct mmci_dmae_next *next = &dmae->next_data; 980 struct dma_chan *chan; 981 if (data->flags & MMC_DATA_READ) 982 chan = dmae->rx_channel; 983 else 984 chan = dmae->tx_channel; 985 dmaengine_terminate_all(chan); 986 987 if (dmae->desc_current == next->desc) 988 dmae->desc_current = NULL; 989 990 if (dmae->cur == next->chan) { 991 host->dma_in_progress = false; 992 dmae->cur = NULL; 993 } 994 995 next->desc = NULL; 996 next->chan = NULL; 997 } 998 } 999 1000 static struct mmci_host_ops mmci_variant_ops = { 1001 .prep_data = mmci_dmae_prep_data, 1002 .unprep_data = mmci_dmae_unprep_data, 1003 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1004 .get_next_data = mmci_dmae_get_next_data, 1005 .dma_setup = mmci_dmae_setup, 1006 .dma_release = mmci_dmae_release, 1007 .dma_start = mmci_dmae_start, 1008 .dma_finalize = mmci_dmae_finalize, 1009 .dma_error = mmci_dmae_error, 1010 }; 1011 #else 1012 static struct mmci_host_ops mmci_variant_ops = { 1013 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1014 }; 1015 #endif 1016 1017 static void mmci_variant_init(struct mmci_host *host) 1018 { 1019 host->ops = &mmci_variant_ops; 1020 } 1021 1022 static void ux500_variant_init(struct mmci_host *host) 1023 { 1024 host->ops = &mmci_variant_ops; 1025 host->ops->busy_complete = ux500_busy_complete; 1026 } 1027 1028 static void ux500v2_variant_init(struct mmci_host *host) 1029 { 1030 host->ops = &mmci_variant_ops; 1031 host->ops->busy_complete = ux500_busy_complete; 1032 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1033 } 1034 1035 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1036 { 1037 struct mmci_host *host = mmc_priv(mmc); 1038 struct mmc_data *data = mrq->data; 1039 1040 if (!data) 1041 return; 1042 1043 WARN_ON(data->host_cookie); 1044 1045 if (mmci_validate_data(host, data)) 1046 return; 1047 1048 mmci_prep_data(host, data, true); 1049 } 1050 1051 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1052 int err) 1053 { 1054 struct mmci_host *host = mmc_priv(mmc); 1055 struct mmc_data *data = mrq->data; 1056 1057 if (!data || !data->host_cookie) 1058 return; 1059 1060 mmci_unprep_data(host, data, err); 1061 } 1062 1063 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1064 { 1065 struct variant_data *variant = host->variant; 1066 unsigned int datactrl, timeout, irqmask; 1067 unsigned long long clks; 1068 void __iomem *base; 1069 1070 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1071 data->blksz, data->blocks, data->flags); 1072 1073 host->data = data; 1074 host->size = data->blksz * data->blocks; 1075 data->bytes_xfered = 0; 1076 1077 clks = (unsigned long long)data->timeout_ns * host->cclk; 1078 do_div(clks, NSEC_PER_SEC); 1079 1080 timeout = data->timeout_clks + (unsigned int)clks; 1081 1082 base = host->base; 1083 writel(timeout, base + MMCIDATATIMER); 1084 writel(host->size, base + MMCIDATALENGTH); 1085 1086 datactrl = host->ops->get_datactrl_cfg(host); 1087 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1088 1089 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1090 u32 clk; 1091 1092 datactrl |= variant->datactrl_mask_sdio; 1093 1094 /* 1095 * The ST Micro variant for SDIO small write transfers 1096 * needs to have clock H/W flow control disabled, 1097 * otherwise the transfer will not start. The threshold 1098 * depends on the rate of MCLK. 1099 */ 1100 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1101 (host->size < 8 || 1102 (host->size <= 8 && host->mclk > 50000000))) 1103 clk = host->clk_reg & ~variant->clkreg_enable; 1104 else 1105 clk = host->clk_reg | variant->clkreg_enable; 1106 1107 mmci_write_clkreg(host, clk); 1108 } 1109 1110 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1111 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1112 datactrl |= variant->datactrl_mask_ddrmode; 1113 1114 /* 1115 * Attempt to use DMA operation mode, if this 1116 * should fail, fall back to PIO mode 1117 */ 1118 if (!mmci_dma_start(host, datactrl)) 1119 return; 1120 1121 /* IRQ mode, map the SG list for CPU reading/writing */ 1122 mmci_init_sg(host, data); 1123 1124 if (data->flags & MMC_DATA_READ) { 1125 irqmask = MCI_RXFIFOHALFFULLMASK; 1126 1127 /* 1128 * If we have less than the fifo 'half-full' threshold to 1129 * transfer, trigger a PIO interrupt as soon as any data 1130 * is available. 1131 */ 1132 if (host->size < variant->fifohalfsize) 1133 irqmask |= MCI_RXDATAAVLBLMASK; 1134 } else { 1135 /* 1136 * We don't actually need to include "FIFO empty" here 1137 * since its implicit in "FIFO half empty". 1138 */ 1139 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1140 } 1141 1142 mmci_write_datactrlreg(host, datactrl); 1143 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1144 mmci_set_mask1(host, irqmask); 1145 } 1146 1147 static void 1148 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1149 { 1150 void __iomem *base = host->base; 1151 unsigned long long clks; 1152 1153 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1154 cmd->opcode, cmd->arg, cmd->flags); 1155 1156 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1157 writel(0, base + MMCICOMMAND); 1158 mmci_reg_delay(host); 1159 } 1160 1161 if (host->variant->cmdreg_stop && 1162 cmd->opcode == MMC_STOP_TRANSMISSION) 1163 c |= host->variant->cmdreg_stop; 1164 1165 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1166 if (cmd->flags & MMC_RSP_PRESENT) { 1167 if (cmd->flags & MMC_RSP_136) 1168 c |= host->variant->cmdreg_lrsp_crc; 1169 else if (cmd->flags & MMC_RSP_CRC) 1170 c |= host->variant->cmdreg_srsp_crc; 1171 else 1172 c |= host->variant->cmdreg_srsp; 1173 } 1174 1175 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1176 if (!cmd->busy_timeout) 1177 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1178 1179 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1180 do_div(clks, MSEC_PER_SEC); 1181 writel_relaxed(clks, host->base + MMCIDATATIMER); 1182 } 1183 1184 if (/*interrupt*/0) 1185 c |= MCI_CPSM_INTERRUPT; 1186 1187 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1188 c |= host->variant->data_cmd_enable; 1189 1190 host->cmd = cmd; 1191 1192 writel(cmd->arg, base + MMCIARGUMENT); 1193 writel(c, base + MMCICOMMAND); 1194 } 1195 1196 static void mmci_stop_command(struct mmci_host *host) 1197 { 1198 host->stop_abort.error = 0; 1199 mmci_start_command(host, &host->stop_abort, 0); 1200 } 1201 1202 static void 1203 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1204 unsigned int status) 1205 { 1206 unsigned int status_err; 1207 1208 /* Make sure we have data to handle */ 1209 if (!data) 1210 return; 1211 1212 /* First check for errors */ 1213 status_err = status & (host->variant->start_err | 1214 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1215 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1216 1217 if (status_err) { 1218 u32 remain, success; 1219 1220 /* Terminate the DMA transfer */ 1221 mmci_dma_error(host); 1222 1223 /* 1224 * Calculate how far we are into the transfer. Note that 1225 * the data counter gives the number of bytes transferred 1226 * on the MMC bus, not on the host side. On reads, this 1227 * can be as much as a FIFO-worth of data ahead. This 1228 * matters for FIFO overruns only. 1229 */ 1230 if (!host->variant->datacnt_useless) { 1231 remain = readl(host->base + MMCIDATACNT); 1232 success = data->blksz * data->blocks - remain; 1233 } else { 1234 success = 0; 1235 } 1236 1237 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1238 status_err, success); 1239 if (status_err & MCI_DATACRCFAIL) { 1240 /* Last block was not successful */ 1241 success -= 1; 1242 data->error = -EILSEQ; 1243 } else if (status_err & MCI_DATATIMEOUT) { 1244 data->error = -ETIMEDOUT; 1245 } else if (status_err & MCI_STARTBITERR) { 1246 data->error = -ECOMM; 1247 } else if (status_err & MCI_TXUNDERRUN) { 1248 data->error = -EIO; 1249 } else if (status_err & MCI_RXOVERRUN) { 1250 if (success > host->variant->fifosize) 1251 success -= host->variant->fifosize; 1252 else 1253 success = 0; 1254 data->error = -EIO; 1255 } 1256 data->bytes_xfered = round_down(success, data->blksz); 1257 } 1258 1259 if (status & MCI_DATABLOCKEND) 1260 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1261 1262 if (status & MCI_DATAEND || data->error) { 1263 mmci_dma_finalize(host, data); 1264 1265 mmci_stop_data(host); 1266 1267 if (!data->error) 1268 /* The error clause is handled above, success! */ 1269 data->bytes_xfered = data->blksz * data->blocks; 1270 1271 if (!data->stop) { 1272 if (host->variant->cmdreg_stop && data->error) 1273 mmci_stop_command(host); 1274 else 1275 mmci_request_end(host, data->mrq); 1276 } else if (host->mrq->sbc && !data->error) { 1277 mmci_request_end(host, data->mrq); 1278 } else { 1279 mmci_start_command(host, data->stop, 0); 1280 } 1281 } 1282 } 1283 1284 static void 1285 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1286 unsigned int status) 1287 { 1288 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1289 void __iomem *base = host->base; 1290 bool sbc, busy_resp; 1291 1292 if (!cmd) 1293 return; 1294 1295 sbc = (cmd == host->mrq->sbc); 1296 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1297 1298 /* 1299 * We need to be one of these interrupts to be considered worth 1300 * handling. Note that we tag on any latent IRQs postponed 1301 * due to waiting for busy status. 1302 */ 1303 if (host->variant->busy_timeout && busy_resp) 1304 err_msk |= MCI_DATATIMEOUT; 1305 1306 if (!((status | host->busy_status) & 1307 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1308 return; 1309 1310 /* Handle busy detection on DAT0 if the variant supports it. */ 1311 if (busy_resp && host->variant->busy_detect) 1312 if (!host->ops->busy_complete(host, status, err_msk)) 1313 return; 1314 1315 host->cmd = NULL; 1316 1317 if (status & MCI_CMDTIMEOUT) { 1318 cmd->error = -ETIMEDOUT; 1319 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1320 cmd->error = -EILSEQ; 1321 } else if (host->variant->busy_timeout && busy_resp && 1322 status & MCI_DATATIMEOUT) { 1323 cmd->error = -ETIMEDOUT; 1324 } else { 1325 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1326 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1327 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1328 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1329 } 1330 1331 if ((!sbc && !cmd->data) || cmd->error) { 1332 if (host->data) { 1333 /* Terminate the DMA transfer */ 1334 mmci_dma_error(host); 1335 1336 mmci_stop_data(host); 1337 if (host->variant->cmdreg_stop && cmd->error) { 1338 mmci_stop_command(host); 1339 return; 1340 } 1341 } 1342 mmci_request_end(host, host->mrq); 1343 } else if (sbc) { 1344 mmci_start_command(host, host->mrq->cmd, 0); 1345 } else if (!host->variant->datactrl_first && 1346 !(cmd->data->flags & MMC_DATA_READ)) { 1347 mmci_start_data(host, cmd->data); 1348 } 1349 } 1350 1351 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1352 { 1353 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1354 } 1355 1356 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1357 { 1358 /* 1359 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1360 * from the fifo range should be used 1361 */ 1362 if (status & MCI_RXFIFOHALFFULL) 1363 return host->variant->fifohalfsize; 1364 else if (status & MCI_RXDATAAVLBL) 1365 return 4; 1366 1367 return 0; 1368 } 1369 1370 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1371 { 1372 void __iomem *base = host->base; 1373 char *ptr = buffer; 1374 u32 status = readl(host->base + MMCISTATUS); 1375 int host_remain = host->size; 1376 1377 do { 1378 int count = host->get_rx_fifocnt(host, status, host_remain); 1379 1380 if (count > remain) 1381 count = remain; 1382 1383 if (count <= 0) 1384 break; 1385 1386 /* 1387 * SDIO especially may want to send something that is 1388 * not divisible by 4 (as opposed to card sectors 1389 * etc). Therefore make sure to always read the last bytes 1390 * while only doing full 32-bit reads towards the FIFO. 1391 */ 1392 if (unlikely(count & 0x3)) { 1393 if (count < 4) { 1394 unsigned char buf[4]; 1395 ioread32_rep(base + MMCIFIFO, buf, 1); 1396 memcpy(ptr, buf, count); 1397 } else { 1398 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1399 count &= ~0x3; 1400 } 1401 } else { 1402 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1403 } 1404 1405 ptr += count; 1406 remain -= count; 1407 host_remain -= count; 1408 1409 if (remain == 0) 1410 break; 1411 1412 status = readl(base + MMCISTATUS); 1413 } while (status & MCI_RXDATAAVLBL); 1414 1415 return ptr - buffer; 1416 } 1417 1418 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1419 { 1420 struct variant_data *variant = host->variant; 1421 void __iomem *base = host->base; 1422 char *ptr = buffer; 1423 1424 do { 1425 unsigned int count, maxcnt; 1426 1427 maxcnt = status & MCI_TXFIFOEMPTY ? 1428 variant->fifosize : variant->fifohalfsize; 1429 count = min(remain, maxcnt); 1430 1431 /* 1432 * SDIO especially may want to send something that is 1433 * not divisible by 4 (as opposed to card sectors 1434 * etc), and the FIFO only accept full 32-bit writes. 1435 * So compensate by adding +3 on the count, a single 1436 * byte become a 32bit write, 7 bytes will be two 1437 * 32bit writes etc. 1438 */ 1439 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1440 1441 ptr += count; 1442 remain -= count; 1443 1444 if (remain == 0) 1445 break; 1446 1447 status = readl(base + MMCISTATUS); 1448 } while (status & MCI_TXFIFOHALFEMPTY); 1449 1450 return ptr - buffer; 1451 } 1452 1453 /* 1454 * PIO data transfer IRQ handler. 1455 */ 1456 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1457 { 1458 struct mmci_host *host = dev_id; 1459 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1460 struct variant_data *variant = host->variant; 1461 void __iomem *base = host->base; 1462 u32 status; 1463 1464 status = readl(base + MMCISTATUS); 1465 1466 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1467 1468 do { 1469 unsigned int remain, len; 1470 char *buffer; 1471 1472 /* 1473 * For write, we only need to test the half-empty flag 1474 * here - if the FIFO is completely empty, then by 1475 * definition it is more than half empty. 1476 * 1477 * For read, check for data available. 1478 */ 1479 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1480 break; 1481 1482 if (!sg_miter_next(sg_miter)) 1483 break; 1484 1485 buffer = sg_miter->addr; 1486 remain = sg_miter->length; 1487 1488 len = 0; 1489 if (status & MCI_RXACTIVE) 1490 len = mmci_pio_read(host, buffer, remain); 1491 if (status & MCI_TXACTIVE) 1492 len = mmci_pio_write(host, buffer, remain, status); 1493 1494 sg_miter->consumed = len; 1495 1496 host->size -= len; 1497 remain -= len; 1498 1499 if (remain) 1500 break; 1501 1502 status = readl(base + MMCISTATUS); 1503 } while (1); 1504 1505 sg_miter_stop(sg_miter); 1506 1507 /* 1508 * If we have less than the fifo 'half-full' threshold to transfer, 1509 * trigger a PIO interrupt as soon as any data is available. 1510 */ 1511 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1512 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1513 1514 /* 1515 * If we run out of data, disable the data IRQs; this 1516 * prevents a race where the FIFO becomes empty before 1517 * the chip itself has disabled the data path, and 1518 * stops us racing with our data end IRQ. 1519 */ 1520 if (host->size == 0) { 1521 mmci_set_mask1(host, 0); 1522 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1523 } 1524 1525 return IRQ_HANDLED; 1526 } 1527 1528 /* 1529 * Handle completion of command and data transfers. 1530 */ 1531 static irqreturn_t mmci_irq(int irq, void *dev_id) 1532 { 1533 struct mmci_host *host = dev_id; 1534 u32 status; 1535 int ret = 0; 1536 1537 spin_lock(&host->lock); 1538 1539 do { 1540 status = readl(host->base + MMCISTATUS); 1541 1542 if (host->singleirq) { 1543 if (status & host->mask1_reg) 1544 mmci_pio_irq(irq, dev_id); 1545 1546 status &= ~host->variant->irq_pio_mask; 1547 } 1548 1549 /* 1550 * Busy detection is managed by mmci_cmd_irq(), including to 1551 * clear the corresponding IRQ. 1552 */ 1553 status &= readl(host->base + MMCIMASK0); 1554 if (host->variant->busy_detect) 1555 writel(status & ~host->variant->busy_detect_mask, 1556 host->base + MMCICLEAR); 1557 else 1558 writel(status, host->base + MMCICLEAR); 1559 1560 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1561 1562 if (host->variant->reversed_irq_handling) { 1563 mmci_data_irq(host, host->data, status); 1564 mmci_cmd_irq(host, host->cmd, status); 1565 } else { 1566 mmci_cmd_irq(host, host->cmd, status); 1567 mmci_data_irq(host, host->data, status); 1568 } 1569 1570 /* 1571 * Busy detection has been handled by mmci_cmd_irq() above. 1572 * Clear the status bit to prevent polling in IRQ context. 1573 */ 1574 if (host->variant->busy_detect_flag) 1575 status &= ~host->variant->busy_detect_flag; 1576 1577 ret = 1; 1578 } while (status); 1579 1580 spin_unlock(&host->lock); 1581 1582 return IRQ_RETVAL(ret); 1583 } 1584 1585 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1586 { 1587 struct mmci_host *host = mmc_priv(mmc); 1588 unsigned long flags; 1589 1590 WARN_ON(host->mrq != NULL); 1591 1592 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1593 if (mrq->cmd->error) { 1594 mmc_request_done(mmc, mrq); 1595 return; 1596 } 1597 1598 spin_lock_irqsave(&host->lock, flags); 1599 1600 host->mrq = mrq; 1601 1602 if (mrq->data) 1603 mmci_get_next_data(host, mrq->data); 1604 1605 if (mrq->data && 1606 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1607 mmci_start_data(host, mrq->data); 1608 1609 if (mrq->sbc) 1610 mmci_start_command(host, mrq->sbc, 0); 1611 else 1612 mmci_start_command(host, mrq->cmd, 0); 1613 1614 spin_unlock_irqrestore(&host->lock, flags); 1615 } 1616 1617 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1618 { 1619 struct mmci_host *host = mmc_priv(mmc); 1620 u32 max_busy_timeout = 0; 1621 1622 if (!host->variant->busy_detect) 1623 return; 1624 1625 if (host->variant->busy_timeout && mmc->actual_clock) 1626 max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC); 1627 1628 mmc->max_busy_timeout = max_busy_timeout; 1629 } 1630 1631 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1632 { 1633 struct mmci_host *host = mmc_priv(mmc); 1634 struct variant_data *variant = host->variant; 1635 u32 pwr = 0; 1636 unsigned long flags; 1637 int ret; 1638 1639 if (host->plat->ios_handler && 1640 host->plat->ios_handler(mmc_dev(mmc), ios)) 1641 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1642 1643 switch (ios->power_mode) { 1644 case MMC_POWER_OFF: 1645 if (!IS_ERR(mmc->supply.vmmc)) 1646 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1647 1648 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1649 regulator_disable(mmc->supply.vqmmc); 1650 host->vqmmc_enabled = false; 1651 } 1652 1653 break; 1654 case MMC_POWER_UP: 1655 if (!IS_ERR(mmc->supply.vmmc)) 1656 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1657 1658 /* 1659 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1660 * and instead uses MCI_PWR_ON so apply whatever value is 1661 * configured in the variant data. 1662 */ 1663 pwr |= variant->pwrreg_powerup; 1664 1665 break; 1666 case MMC_POWER_ON: 1667 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1668 ret = regulator_enable(mmc->supply.vqmmc); 1669 if (ret < 0) 1670 dev_err(mmc_dev(mmc), 1671 "failed to enable vqmmc regulator\n"); 1672 else 1673 host->vqmmc_enabled = true; 1674 } 1675 1676 pwr |= MCI_PWR_ON; 1677 break; 1678 } 1679 1680 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1681 /* 1682 * The ST Micro variant has some additional bits 1683 * indicating signal direction for the signals in 1684 * the SD/MMC bus and feedback-clock usage. 1685 */ 1686 pwr |= host->pwr_reg_add; 1687 1688 if (ios->bus_width == MMC_BUS_WIDTH_4) 1689 pwr &= ~MCI_ST_DATA74DIREN; 1690 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1691 pwr &= (~MCI_ST_DATA74DIREN & 1692 ~MCI_ST_DATA31DIREN & 1693 ~MCI_ST_DATA2DIREN); 1694 } 1695 1696 if (variant->opendrain) { 1697 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1698 pwr |= variant->opendrain; 1699 } else { 1700 /* 1701 * If the variant cannot configure the pads by its own, then we 1702 * expect the pinctrl to be able to do that for us 1703 */ 1704 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1705 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1706 else 1707 pinctrl_select_state(host->pinctrl, host->pins_default); 1708 } 1709 1710 /* 1711 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1712 * gating the clock, the MCI_PWR_ON bit is cleared. 1713 */ 1714 if (!ios->clock && variant->pwrreg_clkgate) 1715 pwr &= ~MCI_PWR_ON; 1716 1717 if (host->variant->explicit_mclk_control && 1718 ios->clock != host->clock_cache) { 1719 ret = clk_set_rate(host->clk, ios->clock); 1720 if (ret < 0) 1721 dev_err(mmc_dev(host->mmc), 1722 "Error setting clock rate (%d)\n", ret); 1723 else 1724 host->mclk = clk_get_rate(host->clk); 1725 } 1726 host->clock_cache = ios->clock; 1727 1728 spin_lock_irqsave(&host->lock, flags); 1729 1730 if (host->ops && host->ops->set_clkreg) 1731 host->ops->set_clkreg(host, ios->clock); 1732 else 1733 mmci_set_clkreg(host, ios->clock); 1734 1735 mmci_set_max_busy_timeout(mmc); 1736 1737 if (host->ops && host->ops->set_pwrreg) 1738 host->ops->set_pwrreg(host, pwr); 1739 else 1740 mmci_write_pwrreg(host, pwr); 1741 1742 mmci_reg_delay(host); 1743 1744 spin_unlock_irqrestore(&host->lock, flags); 1745 } 1746 1747 static int mmci_get_cd(struct mmc_host *mmc) 1748 { 1749 struct mmci_host *host = mmc_priv(mmc); 1750 struct mmci_platform_data *plat = host->plat; 1751 unsigned int status = mmc_gpio_get_cd(mmc); 1752 1753 if (status == -ENOSYS) { 1754 if (!plat->status) 1755 return 1; /* Assume always present */ 1756 1757 status = plat->status(mmc_dev(host->mmc)); 1758 } 1759 return status; 1760 } 1761 1762 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1763 { 1764 int ret = 0; 1765 1766 if (!IS_ERR(mmc->supply.vqmmc)) { 1767 1768 switch (ios->signal_voltage) { 1769 case MMC_SIGNAL_VOLTAGE_330: 1770 ret = regulator_set_voltage(mmc->supply.vqmmc, 1771 2700000, 3600000); 1772 break; 1773 case MMC_SIGNAL_VOLTAGE_180: 1774 ret = regulator_set_voltage(mmc->supply.vqmmc, 1775 1700000, 1950000); 1776 break; 1777 case MMC_SIGNAL_VOLTAGE_120: 1778 ret = regulator_set_voltage(mmc->supply.vqmmc, 1779 1100000, 1300000); 1780 break; 1781 } 1782 1783 if (ret) 1784 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1785 } 1786 1787 return ret; 1788 } 1789 1790 static struct mmc_host_ops mmci_ops = { 1791 .request = mmci_request, 1792 .pre_req = mmci_pre_request, 1793 .post_req = mmci_post_request, 1794 .set_ios = mmci_set_ios, 1795 .get_ro = mmc_gpio_get_ro, 1796 .get_cd = mmci_get_cd, 1797 .start_signal_voltage_switch = mmci_sig_volt_switch, 1798 }; 1799 1800 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1801 { 1802 struct mmci_host *host = mmc_priv(mmc); 1803 int ret = mmc_of_parse(mmc); 1804 1805 if (ret) 1806 return ret; 1807 1808 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1809 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1810 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1811 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1812 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1813 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1814 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1815 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1816 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1817 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1818 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1819 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1820 if (of_get_property(np, "st,sig-dir", NULL)) 1821 host->pwr_reg_add |= MCI_STM32_DIRPOL; 1822 if (of_get_property(np, "st,neg-edge", NULL)) 1823 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 1824 if (of_get_property(np, "st,use-ckin", NULL)) 1825 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1826 1827 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1828 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1829 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1830 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1831 1832 return 0; 1833 } 1834 1835 static int mmci_probe(struct amba_device *dev, 1836 const struct amba_id *id) 1837 { 1838 struct mmci_platform_data *plat = dev->dev.platform_data; 1839 struct device_node *np = dev->dev.of_node; 1840 struct variant_data *variant = id->data; 1841 struct mmci_host *host; 1842 struct mmc_host *mmc; 1843 int ret; 1844 1845 /* Must have platform data or Device Tree. */ 1846 if (!plat && !np) { 1847 dev_err(&dev->dev, "No plat data or DT found\n"); 1848 return -EINVAL; 1849 } 1850 1851 if (!plat) { 1852 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1853 if (!plat) 1854 return -ENOMEM; 1855 } 1856 1857 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1858 if (!mmc) 1859 return -ENOMEM; 1860 1861 ret = mmci_of_parse(np, mmc); 1862 if (ret) 1863 goto host_free; 1864 1865 host = mmc_priv(mmc); 1866 host->mmc = mmc; 1867 1868 /* 1869 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1870 * pins can be set accordingly using pinctrl 1871 */ 1872 if (!variant->opendrain) { 1873 host->pinctrl = devm_pinctrl_get(&dev->dev); 1874 if (IS_ERR(host->pinctrl)) { 1875 dev_err(&dev->dev, "failed to get pinctrl"); 1876 ret = PTR_ERR(host->pinctrl); 1877 goto host_free; 1878 } 1879 1880 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1881 PINCTRL_STATE_DEFAULT); 1882 if (IS_ERR(host->pins_default)) { 1883 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1884 ret = PTR_ERR(host->pins_default); 1885 goto host_free; 1886 } 1887 1888 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1889 MMCI_PINCTRL_STATE_OPENDRAIN); 1890 if (IS_ERR(host->pins_opendrain)) { 1891 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1892 ret = PTR_ERR(host->pins_opendrain); 1893 goto host_free; 1894 } 1895 } 1896 1897 host->hw_designer = amba_manf(dev); 1898 host->hw_revision = amba_rev(dev); 1899 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1900 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1901 1902 host->clk = devm_clk_get(&dev->dev, NULL); 1903 if (IS_ERR(host->clk)) { 1904 ret = PTR_ERR(host->clk); 1905 goto host_free; 1906 } 1907 1908 ret = clk_prepare_enable(host->clk); 1909 if (ret) 1910 goto host_free; 1911 1912 if (variant->qcom_fifo) 1913 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1914 else 1915 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1916 1917 host->plat = plat; 1918 host->variant = variant; 1919 host->mclk = clk_get_rate(host->clk); 1920 /* 1921 * According to the spec, mclk is max 100 MHz, 1922 * so we try to adjust the clock down to this, 1923 * (if possible). 1924 */ 1925 if (host->mclk > variant->f_max) { 1926 ret = clk_set_rate(host->clk, variant->f_max); 1927 if (ret < 0) 1928 goto clk_disable; 1929 host->mclk = clk_get_rate(host->clk); 1930 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1931 host->mclk); 1932 } 1933 1934 host->phybase = dev->res.start; 1935 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1936 if (IS_ERR(host->base)) { 1937 ret = PTR_ERR(host->base); 1938 goto clk_disable; 1939 } 1940 1941 if (variant->init) 1942 variant->init(host); 1943 1944 /* 1945 * The ARM and ST versions of the block have slightly different 1946 * clock divider equations which means that the minimum divider 1947 * differs too. 1948 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1949 */ 1950 if (variant->st_clkdiv) 1951 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1952 else if (variant->stm32_clkdiv) 1953 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 1954 else if (variant->explicit_mclk_control) 1955 mmc->f_min = clk_round_rate(host->clk, 100000); 1956 else 1957 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1958 /* 1959 * If no maximum operating frequency is supplied, fall back to use 1960 * the module parameter, which has a (low) default value in case it 1961 * is not specified. Either value must not exceed the clock rate into 1962 * the block, of course. 1963 */ 1964 if (mmc->f_max) 1965 mmc->f_max = variant->explicit_mclk_control ? 1966 min(variant->f_max, mmc->f_max) : 1967 min(host->mclk, mmc->f_max); 1968 else 1969 mmc->f_max = variant->explicit_mclk_control ? 1970 fmax : min(host->mclk, fmax); 1971 1972 1973 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1974 1975 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 1976 if (IS_ERR(host->rst)) { 1977 ret = PTR_ERR(host->rst); 1978 goto clk_disable; 1979 } 1980 1981 /* Get regulators and the supported OCR mask */ 1982 ret = mmc_regulator_get_supply(mmc); 1983 if (ret) 1984 goto clk_disable; 1985 1986 if (!mmc->ocr_avail) 1987 mmc->ocr_avail = plat->ocr_mask; 1988 else if (plat->ocr_mask) 1989 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1990 1991 /* We support these capabilities. */ 1992 mmc->caps |= MMC_CAP_CMD23; 1993 1994 /* 1995 * Enable busy detection. 1996 */ 1997 if (variant->busy_detect) { 1998 mmci_ops.card_busy = mmci_card_busy; 1999 /* 2000 * Not all variants have a flag to enable busy detection 2001 * in the DPSM, but if they do, set it here. 2002 */ 2003 if (variant->busy_dpsm_flag) 2004 mmci_write_datactrlreg(host, 2005 host->variant->busy_dpsm_flag); 2006 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2007 } 2008 2009 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2010 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2011 host->stop_abort.arg = 0; 2012 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2013 2014 mmc->ops = &mmci_ops; 2015 2016 /* We support these PM capabilities. */ 2017 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2018 2019 /* 2020 * We can do SGIO 2021 */ 2022 mmc->max_segs = NR_SG; 2023 2024 /* 2025 * Since only a certain number of bits are valid in the data length 2026 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2027 * single request. 2028 */ 2029 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2030 2031 /* 2032 * Set the maximum segment size. Since we aren't doing DMA 2033 * (yet) we are only limited by the data length register. 2034 */ 2035 mmc->max_seg_size = mmc->max_req_size; 2036 2037 /* 2038 * Block size can be up to 2048 bytes, but must be a power of two. 2039 */ 2040 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2041 2042 /* 2043 * Limit the number of blocks transferred so that we don't overflow 2044 * the maximum request size. 2045 */ 2046 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2047 2048 spin_lock_init(&host->lock); 2049 2050 writel(0, host->base + MMCIMASK0); 2051 2052 if (variant->mmcimask1) 2053 writel(0, host->base + MMCIMASK1); 2054 2055 writel(0xfff, host->base + MMCICLEAR); 2056 2057 /* 2058 * If: 2059 * - not using DT but using a descriptor table, or 2060 * - using a table of descriptors ALONGSIDE DT, or 2061 * look up these descriptors named "cd" and "wp" right here, fail 2062 * silently of these do not exist 2063 */ 2064 if (!np) { 2065 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 2066 if (ret == -EPROBE_DEFER) 2067 goto clk_disable; 2068 2069 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL); 2070 if (ret == -EPROBE_DEFER) 2071 goto clk_disable; 2072 } 2073 2074 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 2075 DRIVER_NAME " (cmd)", host); 2076 if (ret) 2077 goto clk_disable; 2078 2079 if (!dev->irq[1]) 2080 host->singleirq = true; 2081 else { 2082 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2083 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2084 if (ret) 2085 goto clk_disable; 2086 } 2087 2088 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2089 2090 amba_set_drvdata(dev, mmc); 2091 2092 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2093 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2094 amba_rev(dev), (unsigned long long)dev->res.start, 2095 dev->irq[0], dev->irq[1]); 2096 2097 mmci_dma_setup(host); 2098 2099 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2100 pm_runtime_use_autosuspend(&dev->dev); 2101 2102 mmc_add_host(mmc); 2103 2104 pm_runtime_put(&dev->dev); 2105 return 0; 2106 2107 clk_disable: 2108 clk_disable_unprepare(host->clk); 2109 host_free: 2110 mmc_free_host(mmc); 2111 return ret; 2112 } 2113 2114 static int mmci_remove(struct amba_device *dev) 2115 { 2116 struct mmc_host *mmc = amba_get_drvdata(dev); 2117 2118 if (mmc) { 2119 struct mmci_host *host = mmc_priv(mmc); 2120 struct variant_data *variant = host->variant; 2121 2122 /* 2123 * Undo pm_runtime_put() in probe. We use the _sync 2124 * version here so that we can access the primecell. 2125 */ 2126 pm_runtime_get_sync(&dev->dev); 2127 2128 mmc_remove_host(mmc); 2129 2130 writel(0, host->base + MMCIMASK0); 2131 2132 if (variant->mmcimask1) 2133 writel(0, host->base + MMCIMASK1); 2134 2135 writel(0, host->base + MMCICOMMAND); 2136 writel(0, host->base + MMCIDATACTRL); 2137 2138 mmci_dma_release(host); 2139 clk_disable_unprepare(host->clk); 2140 mmc_free_host(mmc); 2141 } 2142 2143 return 0; 2144 } 2145 2146 #ifdef CONFIG_PM 2147 static void mmci_save(struct mmci_host *host) 2148 { 2149 unsigned long flags; 2150 2151 spin_lock_irqsave(&host->lock, flags); 2152 2153 writel(0, host->base + MMCIMASK0); 2154 if (host->variant->pwrreg_nopower) { 2155 writel(0, host->base + MMCIDATACTRL); 2156 writel(0, host->base + MMCIPOWER); 2157 writel(0, host->base + MMCICLOCK); 2158 } 2159 mmci_reg_delay(host); 2160 2161 spin_unlock_irqrestore(&host->lock, flags); 2162 } 2163 2164 static void mmci_restore(struct mmci_host *host) 2165 { 2166 unsigned long flags; 2167 2168 spin_lock_irqsave(&host->lock, flags); 2169 2170 if (host->variant->pwrreg_nopower) { 2171 writel(host->clk_reg, host->base + MMCICLOCK); 2172 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2173 writel(host->pwr_reg, host->base + MMCIPOWER); 2174 } 2175 writel(MCI_IRQENABLE | host->variant->start_err, 2176 host->base + MMCIMASK0); 2177 mmci_reg_delay(host); 2178 2179 spin_unlock_irqrestore(&host->lock, flags); 2180 } 2181 2182 static int mmci_runtime_suspend(struct device *dev) 2183 { 2184 struct amba_device *adev = to_amba_device(dev); 2185 struct mmc_host *mmc = amba_get_drvdata(adev); 2186 2187 if (mmc) { 2188 struct mmci_host *host = mmc_priv(mmc); 2189 pinctrl_pm_select_sleep_state(dev); 2190 mmci_save(host); 2191 clk_disable_unprepare(host->clk); 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int mmci_runtime_resume(struct device *dev) 2198 { 2199 struct amba_device *adev = to_amba_device(dev); 2200 struct mmc_host *mmc = amba_get_drvdata(adev); 2201 2202 if (mmc) { 2203 struct mmci_host *host = mmc_priv(mmc); 2204 clk_prepare_enable(host->clk); 2205 mmci_restore(host); 2206 pinctrl_pm_select_default_state(dev); 2207 } 2208 2209 return 0; 2210 } 2211 #endif 2212 2213 static const struct dev_pm_ops mmci_dev_pm_ops = { 2214 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2215 pm_runtime_force_resume) 2216 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2217 }; 2218 2219 static const struct amba_id mmci_ids[] = { 2220 { 2221 .id = 0x00041180, 2222 .mask = 0xff0fffff, 2223 .data = &variant_arm, 2224 }, 2225 { 2226 .id = 0x01041180, 2227 .mask = 0xff0fffff, 2228 .data = &variant_arm_extended_fifo, 2229 }, 2230 { 2231 .id = 0x02041180, 2232 .mask = 0xff0fffff, 2233 .data = &variant_arm_extended_fifo_hwfc, 2234 }, 2235 { 2236 .id = 0x00041181, 2237 .mask = 0x000fffff, 2238 .data = &variant_arm, 2239 }, 2240 /* ST Micro variants */ 2241 { 2242 .id = 0x00180180, 2243 .mask = 0x00ffffff, 2244 .data = &variant_u300, 2245 }, 2246 { 2247 .id = 0x10180180, 2248 .mask = 0xf0ffffff, 2249 .data = &variant_nomadik, 2250 }, 2251 { 2252 .id = 0x00280180, 2253 .mask = 0x00ffffff, 2254 .data = &variant_nomadik, 2255 }, 2256 { 2257 .id = 0x00480180, 2258 .mask = 0xf0ffffff, 2259 .data = &variant_ux500, 2260 }, 2261 { 2262 .id = 0x10480180, 2263 .mask = 0xf0ffffff, 2264 .data = &variant_ux500v2, 2265 }, 2266 { 2267 .id = 0x00880180, 2268 .mask = 0x00ffffff, 2269 .data = &variant_stm32, 2270 }, 2271 { 2272 .id = 0x10153180, 2273 .mask = 0xf0ffffff, 2274 .data = &variant_stm32_sdmmc, 2275 }, 2276 /* Qualcomm variants */ 2277 { 2278 .id = 0x00051180, 2279 .mask = 0x000fffff, 2280 .data = &variant_qcom, 2281 }, 2282 { 0, 0 }, 2283 }; 2284 2285 MODULE_DEVICE_TABLE(amba, mmci_ids); 2286 2287 static struct amba_driver mmci_driver = { 2288 .drv = { 2289 .name = DRIVER_NAME, 2290 .pm = &mmci_dev_pm_ops, 2291 }, 2292 .probe = mmci_probe, 2293 .remove = mmci_remove, 2294 .id_table = mmci_ids, 2295 }; 2296 2297 module_amba_driver(mmci_driver); 2298 2299 module_param(fmax, uint, 0444); 2300 2301 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2302 MODULE_LICENSE("GPL"); 2303