xref: /openbmc/linux/drivers/mmc/host/mmci.c (revision ae3473231e77a3f1909d48cd144cebe5e1d049b3)
1 /*
2  *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3  *
4  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5  *  Copyright (C) 2010 ST-Ericsson SA
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
40 
41 #include <asm/div64.h>
42 #include <asm/io.h>
43 
44 #include "mmci.h"
45 #include "mmci_qcom_dml.h"
46 
47 #define DRIVER_NAME "mmci-pl18x"
48 
49 static unsigned int fmax = 515633;
50 
51 /**
52  * struct variant_data - MMCI variant-specific quirks
53  * @clkreg: default value for MCICLOCK register
54  * @clkreg_enable: enable value for MMCICLOCK register
55  * @clkreg_8bit_bus_enable: enable value for 8 bit bus
56  * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
57  * @datalength_bits: number of bits in the MMCIDATALENGTH register
58  * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
59  *	      is asserted (likewise for RX)
60  * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
61  *		  is asserted (likewise for RX)
62  * @data_cmd_enable: enable value for data commands.
63  * @st_sdio: enable ST specific SDIO logic
64  * @st_clkdiv: true if using a ST-specific clock divider algorithm
65  * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
66  * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
67  * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
68  *		     register
69  * @datactrl_mask_sdio: SDIO enable mask in datactrl register
70  * @pwrreg_powerup: power up value for MMCIPOWER register
71  * @f_max: maximum clk frequency supported by the controller.
72  * @signal_direction: input/out direction of bus signals can be indicated
73  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
74  * @busy_detect: true if the variant supports busy detection on DAT0.
75  * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
76  * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
77  *		      indicating that the card is busy
78  * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
79  *		      getting busy end detection interrupts
80  * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
81  * @explicit_mclk_control: enable explicit mclk control in driver.
82  * @qcom_fifo: enables qcom specific fifo pio read logic.
83  * @qcom_dml: enables qcom specific dma glue for dma transfers.
84  * @reversed_irq_handling: handle data irq before cmd irq.
85  */
86 struct variant_data {
87 	unsigned int		clkreg;
88 	unsigned int		clkreg_enable;
89 	unsigned int		clkreg_8bit_bus_enable;
90 	unsigned int		clkreg_neg_edge_enable;
91 	unsigned int		datalength_bits;
92 	unsigned int		fifosize;
93 	unsigned int		fifohalfsize;
94 	unsigned int		data_cmd_enable;
95 	unsigned int		datactrl_mask_ddrmode;
96 	unsigned int		datactrl_mask_sdio;
97 	bool			st_sdio;
98 	bool			st_clkdiv;
99 	bool			blksz_datactrl16;
100 	bool			blksz_datactrl4;
101 	u32			pwrreg_powerup;
102 	u32			f_max;
103 	bool			signal_direction;
104 	bool			pwrreg_clkgate;
105 	bool			busy_detect;
106 	u32			busy_dpsm_flag;
107 	u32			busy_detect_flag;
108 	u32			busy_detect_mask;
109 	bool			pwrreg_nopower;
110 	bool			explicit_mclk_control;
111 	bool			qcom_fifo;
112 	bool			qcom_dml;
113 	bool			reversed_irq_handling;
114 };
115 
116 static struct variant_data variant_arm = {
117 	.fifosize		= 16 * 4,
118 	.fifohalfsize		= 8 * 4,
119 	.datalength_bits	= 16,
120 	.pwrreg_powerup		= MCI_PWR_UP,
121 	.f_max			= 100000000,
122 	.reversed_irq_handling	= true,
123 };
124 
125 static struct variant_data variant_arm_extended_fifo = {
126 	.fifosize		= 128 * 4,
127 	.fifohalfsize		= 64 * 4,
128 	.datalength_bits	= 16,
129 	.pwrreg_powerup		= MCI_PWR_UP,
130 	.f_max			= 100000000,
131 };
132 
133 static struct variant_data variant_arm_extended_fifo_hwfc = {
134 	.fifosize		= 128 * 4,
135 	.fifohalfsize		= 64 * 4,
136 	.clkreg_enable		= MCI_ARM_HWFCEN,
137 	.datalength_bits	= 16,
138 	.pwrreg_powerup		= MCI_PWR_UP,
139 	.f_max			= 100000000,
140 };
141 
142 static struct variant_data variant_u300 = {
143 	.fifosize		= 16 * 4,
144 	.fifohalfsize		= 8 * 4,
145 	.clkreg_enable		= MCI_ST_U300_HWFCEN,
146 	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
147 	.datalength_bits	= 16,
148 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,
149 	.st_sdio			= true,
150 	.pwrreg_powerup		= MCI_PWR_ON,
151 	.f_max			= 100000000,
152 	.signal_direction	= true,
153 	.pwrreg_clkgate		= true,
154 	.pwrreg_nopower		= true,
155 };
156 
157 static struct variant_data variant_nomadik = {
158 	.fifosize		= 16 * 4,
159 	.fifohalfsize		= 8 * 4,
160 	.clkreg			= MCI_CLK_ENABLE,
161 	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
162 	.datalength_bits	= 24,
163 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,
164 	.st_sdio		= true,
165 	.st_clkdiv		= true,
166 	.pwrreg_powerup		= MCI_PWR_ON,
167 	.f_max			= 100000000,
168 	.signal_direction	= true,
169 	.pwrreg_clkgate		= true,
170 	.pwrreg_nopower		= true,
171 };
172 
173 static struct variant_data variant_ux500 = {
174 	.fifosize		= 30 * 4,
175 	.fifohalfsize		= 8 * 4,
176 	.clkreg			= MCI_CLK_ENABLE,
177 	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
178 	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
179 	.clkreg_neg_edge_enable	= MCI_ST_UX500_NEG_EDGE,
180 	.datalength_bits	= 24,
181 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,
182 	.st_sdio		= true,
183 	.st_clkdiv		= true,
184 	.pwrreg_powerup		= MCI_PWR_ON,
185 	.f_max			= 100000000,
186 	.signal_direction	= true,
187 	.pwrreg_clkgate		= true,
188 	.busy_detect		= true,
189 	.busy_dpsm_flag		= MCI_DPSM_ST_BUSYMODE,
190 	.busy_detect_flag	= MCI_ST_CARDBUSY,
191 	.busy_detect_mask	= MCI_ST_BUSYENDMASK,
192 	.pwrreg_nopower		= true,
193 };
194 
195 static struct variant_data variant_ux500v2 = {
196 	.fifosize		= 30 * 4,
197 	.fifohalfsize		= 8 * 4,
198 	.clkreg			= MCI_CLK_ENABLE,
199 	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
200 	.clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
201 	.clkreg_neg_edge_enable	= MCI_ST_UX500_NEG_EDGE,
202 	.datactrl_mask_ddrmode	= MCI_DPSM_ST_DDRMODE,
203 	.datalength_bits	= 24,
204 	.datactrl_mask_sdio	= MCI_DPSM_ST_SDIOEN,
205 	.st_sdio		= true,
206 	.st_clkdiv		= true,
207 	.blksz_datactrl16	= true,
208 	.pwrreg_powerup		= MCI_PWR_ON,
209 	.f_max			= 100000000,
210 	.signal_direction	= true,
211 	.pwrreg_clkgate		= true,
212 	.busy_detect		= true,
213 	.busy_dpsm_flag		= MCI_DPSM_ST_BUSYMODE,
214 	.busy_detect_flag	= MCI_ST_CARDBUSY,
215 	.busy_detect_mask	= MCI_ST_BUSYENDMASK,
216 	.pwrreg_nopower		= true,
217 };
218 
219 static struct variant_data variant_qcom = {
220 	.fifosize		= 16 * 4,
221 	.fifohalfsize		= 8 * 4,
222 	.clkreg			= MCI_CLK_ENABLE,
223 	.clkreg_enable		= MCI_QCOM_CLK_FLOWENA |
224 				  MCI_QCOM_CLK_SELECT_IN_FBCLK,
225 	.clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
226 	.datactrl_mask_ddrmode	= MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
227 	.data_cmd_enable	= MCI_CPSM_QCOM_DATCMD,
228 	.blksz_datactrl4	= true,
229 	.datalength_bits	= 24,
230 	.pwrreg_powerup		= MCI_PWR_UP,
231 	.f_max			= 208000000,
232 	.explicit_mclk_control	= true,
233 	.qcom_fifo		= true,
234 	.qcom_dml		= true,
235 };
236 
237 /* Busy detection for the ST Micro variant */
238 static int mmci_card_busy(struct mmc_host *mmc)
239 {
240 	struct mmci_host *host = mmc_priv(mmc);
241 	unsigned long flags;
242 	int busy = 0;
243 
244 	spin_lock_irqsave(&host->lock, flags);
245 	if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
246 		busy = 1;
247 	spin_unlock_irqrestore(&host->lock, flags);
248 
249 	return busy;
250 }
251 
252 /*
253  * Validate mmc prerequisites
254  */
255 static int mmci_validate_data(struct mmci_host *host,
256 			      struct mmc_data *data)
257 {
258 	if (!data)
259 		return 0;
260 
261 	if (!is_power_of_2(data->blksz)) {
262 		dev_err(mmc_dev(host->mmc),
263 			"unsupported block size (%d bytes)\n", data->blksz);
264 		return -EINVAL;
265 	}
266 
267 	return 0;
268 }
269 
270 static void mmci_reg_delay(struct mmci_host *host)
271 {
272 	/*
273 	 * According to the spec, at least three feedback clock cycles
274 	 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
275 	 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
276 	 * Worst delay time during card init is at 100 kHz => 30 us.
277 	 * Worst delay time when up and running is at 25 MHz => 120 ns.
278 	 */
279 	if (host->cclk < 25000000)
280 		udelay(30);
281 	else
282 		ndelay(120);
283 }
284 
285 /*
286  * This must be called with host->lock held
287  */
288 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
289 {
290 	if (host->clk_reg != clk) {
291 		host->clk_reg = clk;
292 		writel(clk, host->base + MMCICLOCK);
293 	}
294 }
295 
296 /*
297  * This must be called with host->lock held
298  */
299 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
300 {
301 	if (host->pwr_reg != pwr) {
302 		host->pwr_reg = pwr;
303 		writel(pwr, host->base + MMCIPOWER);
304 	}
305 }
306 
307 /*
308  * This must be called with host->lock held
309  */
310 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
311 {
312 	/* Keep busy mode in DPSM if enabled */
313 	datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
314 
315 	if (host->datactrl_reg != datactrl) {
316 		host->datactrl_reg = datactrl;
317 		writel(datactrl, host->base + MMCIDATACTRL);
318 	}
319 }
320 
321 /*
322  * This must be called with host->lock held
323  */
324 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
325 {
326 	struct variant_data *variant = host->variant;
327 	u32 clk = variant->clkreg;
328 
329 	/* Make sure cclk reflects the current calculated clock */
330 	host->cclk = 0;
331 
332 	if (desired) {
333 		if (variant->explicit_mclk_control) {
334 			host->cclk = host->mclk;
335 		} else if (desired >= host->mclk) {
336 			clk = MCI_CLK_BYPASS;
337 			if (variant->st_clkdiv)
338 				clk |= MCI_ST_UX500_NEG_EDGE;
339 			host->cclk = host->mclk;
340 		} else if (variant->st_clkdiv) {
341 			/*
342 			 * DB8500 TRM says f = mclk / (clkdiv + 2)
343 			 * => clkdiv = (mclk / f) - 2
344 			 * Round the divider up so we don't exceed the max
345 			 * frequency
346 			 */
347 			clk = DIV_ROUND_UP(host->mclk, desired) - 2;
348 			if (clk >= 256)
349 				clk = 255;
350 			host->cclk = host->mclk / (clk + 2);
351 		} else {
352 			/*
353 			 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
354 			 * => clkdiv = mclk / (2 * f) - 1
355 			 */
356 			clk = host->mclk / (2 * desired) - 1;
357 			if (clk >= 256)
358 				clk = 255;
359 			host->cclk = host->mclk / (2 * (clk + 1));
360 		}
361 
362 		clk |= variant->clkreg_enable;
363 		clk |= MCI_CLK_ENABLE;
364 		/* This hasn't proven to be worthwhile */
365 		/* clk |= MCI_CLK_PWRSAVE; */
366 	}
367 
368 	/* Set actual clock for debug */
369 	host->mmc->actual_clock = host->cclk;
370 
371 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
372 		clk |= MCI_4BIT_BUS;
373 	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
374 		clk |= variant->clkreg_8bit_bus_enable;
375 
376 	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
377 	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
378 		clk |= variant->clkreg_neg_edge_enable;
379 
380 	mmci_write_clkreg(host, clk);
381 }
382 
383 static void
384 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
385 {
386 	writel(0, host->base + MMCICOMMAND);
387 
388 	BUG_ON(host->data);
389 
390 	host->mrq = NULL;
391 	host->cmd = NULL;
392 
393 	mmc_request_done(host->mmc, mrq);
394 }
395 
396 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
397 {
398 	void __iomem *base = host->base;
399 
400 	if (host->singleirq) {
401 		unsigned int mask0 = readl(base + MMCIMASK0);
402 
403 		mask0 &= ~MCI_IRQ1MASK;
404 		mask0 |= mask;
405 
406 		writel(mask0, base + MMCIMASK0);
407 	}
408 
409 	writel(mask, base + MMCIMASK1);
410 }
411 
412 static void mmci_stop_data(struct mmci_host *host)
413 {
414 	mmci_write_datactrlreg(host, 0);
415 	mmci_set_mask1(host, 0);
416 	host->data = NULL;
417 }
418 
419 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
420 {
421 	unsigned int flags = SG_MITER_ATOMIC;
422 
423 	if (data->flags & MMC_DATA_READ)
424 		flags |= SG_MITER_TO_SG;
425 	else
426 		flags |= SG_MITER_FROM_SG;
427 
428 	sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
429 }
430 
431 /*
432  * All the DMA operation mode stuff goes inside this ifdef.
433  * This assumes that you have a generic DMA device interface,
434  * no custom DMA interfaces are supported.
435  */
436 #ifdef CONFIG_DMA_ENGINE
437 static void mmci_dma_setup(struct mmci_host *host)
438 {
439 	const char *rxname, *txname;
440 	struct variant_data *variant = host->variant;
441 
442 	host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
443 	host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
444 
445 	/* initialize pre request cookie */
446 	host->next_data.cookie = 1;
447 
448 	/*
449 	 * If only an RX channel is specified, the driver will
450 	 * attempt to use it bidirectionally, however if it is
451 	 * is specified but cannot be located, DMA will be disabled.
452 	 */
453 	if (host->dma_rx_channel && !host->dma_tx_channel)
454 		host->dma_tx_channel = host->dma_rx_channel;
455 
456 	if (host->dma_rx_channel)
457 		rxname = dma_chan_name(host->dma_rx_channel);
458 	else
459 		rxname = "none";
460 
461 	if (host->dma_tx_channel)
462 		txname = dma_chan_name(host->dma_tx_channel);
463 	else
464 		txname = "none";
465 
466 	dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
467 		 rxname, txname);
468 
469 	/*
470 	 * Limit the maximum segment size in any SG entry according to
471 	 * the parameters of the DMA engine device.
472 	 */
473 	if (host->dma_tx_channel) {
474 		struct device *dev = host->dma_tx_channel->device->dev;
475 		unsigned int max_seg_size = dma_get_max_seg_size(dev);
476 
477 		if (max_seg_size < host->mmc->max_seg_size)
478 			host->mmc->max_seg_size = max_seg_size;
479 	}
480 	if (host->dma_rx_channel) {
481 		struct device *dev = host->dma_rx_channel->device->dev;
482 		unsigned int max_seg_size = dma_get_max_seg_size(dev);
483 
484 		if (max_seg_size < host->mmc->max_seg_size)
485 			host->mmc->max_seg_size = max_seg_size;
486 	}
487 
488 	if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel)
489 		if (dml_hw_init(host, host->mmc->parent->of_node))
490 			variant->qcom_dml = false;
491 }
492 
493 /*
494  * This is used in or so inline it
495  * so it can be discarded.
496  */
497 static inline void mmci_dma_release(struct mmci_host *host)
498 {
499 	if (host->dma_rx_channel)
500 		dma_release_channel(host->dma_rx_channel);
501 	if (host->dma_tx_channel)
502 		dma_release_channel(host->dma_tx_channel);
503 	host->dma_rx_channel = host->dma_tx_channel = NULL;
504 }
505 
506 static void mmci_dma_data_error(struct mmci_host *host)
507 {
508 	dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
509 	dmaengine_terminate_all(host->dma_current);
510 	host->dma_current = NULL;
511 	host->dma_desc_current = NULL;
512 	host->data->host_cookie = 0;
513 }
514 
515 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
516 {
517 	struct dma_chan *chan;
518 	enum dma_data_direction dir;
519 
520 	if (data->flags & MMC_DATA_READ) {
521 		dir = DMA_FROM_DEVICE;
522 		chan = host->dma_rx_channel;
523 	} else {
524 		dir = DMA_TO_DEVICE;
525 		chan = host->dma_tx_channel;
526 	}
527 
528 	dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
529 }
530 
531 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
532 {
533 	u32 status;
534 	int i;
535 
536 	/* Wait up to 1ms for the DMA to complete */
537 	for (i = 0; ; i++) {
538 		status = readl(host->base + MMCISTATUS);
539 		if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
540 			break;
541 		udelay(10);
542 	}
543 
544 	/*
545 	 * Check to see whether we still have some data left in the FIFO -
546 	 * this catches DMA controllers which are unable to monitor the
547 	 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
548 	 * contiguous buffers.  On TX, we'll get a FIFO underrun error.
549 	 */
550 	if (status & MCI_RXDATAAVLBLMASK) {
551 		mmci_dma_data_error(host);
552 		if (!data->error)
553 			data->error = -EIO;
554 	}
555 
556 	if (!data->host_cookie)
557 		mmci_dma_unmap(host, data);
558 
559 	/*
560 	 * Use of DMA with scatter-gather is impossible.
561 	 * Give up with DMA and switch back to PIO mode.
562 	 */
563 	if (status & MCI_RXDATAAVLBLMASK) {
564 		dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
565 		mmci_dma_release(host);
566 	}
567 
568 	host->dma_current = NULL;
569 	host->dma_desc_current = NULL;
570 }
571 
572 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
573 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
574 				struct dma_chan **dma_chan,
575 				struct dma_async_tx_descriptor **dma_desc)
576 {
577 	struct variant_data *variant = host->variant;
578 	struct dma_slave_config conf = {
579 		.src_addr = host->phybase + MMCIFIFO,
580 		.dst_addr = host->phybase + MMCIFIFO,
581 		.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
582 		.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
583 		.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
584 		.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
585 		.device_fc = false,
586 	};
587 	struct dma_chan *chan;
588 	struct dma_device *device;
589 	struct dma_async_tx_descriptor *desc;
590 	enum dma_data_direction buffer_dirn;
591 	int nr_sg;
592 	unsigned long flags = DMA_CTRL_ACK;
593 
594 	if (data->flags & MMC_DATA_READ) {
595 		conf.direction = DMA_DEV_TO_MEM;
596 		buffer_dirn = DMA_FROM_DEVICE;
597 		chan = host->dma_rx_channel;
598 	} else {
599 		conf.direction = DMA_MEM_TO_DEV;
600 		buffer_dirn = DMA_TO_DEVICE;
601 		chan = host->dma_tx_channel;
602 	}
603 
604 	/* If there's no DMA channel, fall back to PIO */
605 	if (!chan)
606 		return -EINVAL;
607 
608 	/* If less than or equal to the fifo size, don't bother with DMA */
609 	if (data->blksz * data->blocks <= variant->fifosize)
610 		return -EINVAL;
611 
612 	device = chan->device;
613 	nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
614 	if (nr_sg == 0)
615 		return -EINVAL;
616 
617 	if (host->variant->qcom_dml)
618 		flags |= DMA_PREP_INTERRUPT;
619 
620 	dmaengine_slave_config(chan, &conf);
621 	desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
622 					    conf.direction, flags);
623 	if (!desc)
624 		goto unmap_exit;
625 
626 	*dma_chan = chan;
627 	*dma_desc = desc;
628 
629 	return 0;
630 
631  unmap_exit:
632 	dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
633 	return -ENOMEM;
634 }
635 
636 static inline int mmci_dma_prep_data(struct mmci_host *host,
637 				     struct mmc_data *data)
638 {
639 	/* Check if next job is already prepared. */
640 	if (host->dma_current && host->dma_desc_current)
641 		return 0;
642 
643 	/* No job were prepared thus do it now. */
644 	return __mmci_dma_prep_data(host, data, &host->dma_current,
645 				    &host->dma_desc_current);
646 }
647 
648 static inline int mmci_dma_prep_next(struct mmci_host *host,
649 				     struct mmc_data *data)
650 {
651 	struct mmci_host_next *nd = &host->next_data;
652 	return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
653 }
654 
655 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
656 {
657 	int ret;
658 	struct mmc_data *data = host->data;
659 
660 	ret = mmci_dma_prep_data(host, host->data);
661 	if (ret)
662 		return ret;
663 
664 	/* Okay, go for it. */
665 	dev_vdbg(mmc_dev(host->mmc),
666 		 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
667 		 data->sg_len, data->blksz, data->blocks, data->flags);
668 	dmaengine_submit(host->dma_desc_current);
669 	dma_async_issue_pending(host->dma_current);
670 
671 	if (host->variant->qcom_dml)
672 		dml_start_xfer(host, data);
673 
674 	datactrl |= MCI_DPSM_DMAENABLE;
675 
676 	/* Trigger the DMA transfer */
677 	mmci_write_datactrlreg(host, datactrl);
678 
679 	/*
680 	 * Let the MMCI say when the data is ended and it's time
681 	 * to fire next DMA request. When that happens, MMCI will
682 	 * call mmci_data_end()
683 	 */
684 	writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
685 	       host->base + MMCIMASK0);
686 	return 0;
687 }
688 
689 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
690 {
691 	struct mmci_host_next *next = &host->next_data;
692 
693 	WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
694 	WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
695 
696 	host->dma_desc_current = next->dma_desc;
697 	host->dma_current = next->dma_chan;
698 	next->dma_desc = NULL;
699 	next->dma_chan = NULL;
700 }
701 
702 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
703 {
704 	struct mmci_host *host = mmc_priv(mmc);
705 	struct mmc_data *data = mrq->data;
706 	struct mmci_host_next *nd = &host->next_data;
707 
708 	if (!data)
709 		return;
710 
711 	BUG_ON(data->host_cookie);
712 
713 	if (mmci_validate_data(host, data))
714 		return;
715 
716 	if (!mmci_dma_prep_next(host, data))
717 		data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
718 }
719 
720 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
721 			      int err)
722 {
723 	struct mmci_host *host = mmc_priv(mmc);
724 	struct mmc_data *data = mrq->data;
725 
726 	if (!data || !data->host_cookie)
727 		return;
728 
729 	mmci_dma_unmap(host, data);
730 
731 	if (err) {
732 		struct mmci_host_next *next = &host->next_data;
733 		struct dma_chan *chan;
734 		if (data->flags & MMC_DATA_READ)
735 			chan = host->dma_rx_channel;
736 		else
737 			chan = host->dma_tx_channel;
738 		dmaengine_terminate_all(chan);
739 
740 		if (host->dma_desc_current == next->dma_desc)
741 			host->dma_desc_current = NULL;
742 
743 		if (host->dma_current == next->dma_chan)
744 			host->dma_current = NULL;
745 
746 		next->dma_desc = NULL;
747 		next->dma_chan = NULL;
748 		data->host_cookie = 0;
749 	}
750 }
751 
752 #else
753 /* Blank functions if the DMA engine is not available */
754 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
755 {
756 }
757 static inline void mmci_dma_setup(struct mmci_host *host)
758 {
759 }
760 
761 static inline void mmci_dma_release(struct mmci_host *host)
762 {
763 }
764 
765 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
766 {
767 }
768 
769 static inline void mmci_dma_finalize(struct mmci_host *host,
770 				     struct mmc_data *data)
771 {
772 }
773 
774 static inline void mmci_dma_data_error(struct mmci_host *host)
775 {
776 }
777 
778 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
779 {
780 	return -ENOSYS;
781 }
782 
783 #define mmci_pre_request NULL
784 #define mmci_post_request NULL
785 
786 #endif
787 
788 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
789 {
790 	struct variant_data *variant = host->variant;
791 	unsigned int datactrl, timeout, irqmask;
792 	unsigned long long clks;
793 	void __iomem *base;
794 	int blksz_bits;
795 
796 	dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
797 		data->blksz, data->blocks, data->flags);
798 
799 	host->data = data;
800 	host->size = data->blksz * data->blocks;
801 	data->bytes_xfered = 0;
802 
803 	clks = (unsigned long long)data->timeout_ns * host->cclk;
804 	do_div(clks, NSEC_PER_SEC);
805 
806 	timeout = data->timeout_clks + (unsigned int)clks;
807 
808 	base = host->base;
809 	writel(timeout, base + MMCIDATATIMER);
810 	writel(host->size, base + MMCIDATALENGTH);
811 
812 	blksz_bits = ffs(data->blksz) - 1;
813 	BUG_ON(1 << blksz_bits != data->blksz);
814 
815 	if (variant->blksz_datactrl16)
816 		datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
817 	else if (variant->blksz_datactrl4)
818 		datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
819 	else
820 		datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
821 
822 	if (data->flags & MMC_DATA_READ)
823 		datactrl |= MCI_DPSM_DIRECTION;
824 
825 	if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
826 		u32 clk;
827 
828 		datactrl |= variant->datactrl_mask_sdio;
829 
830 		/*
831 		 * The ST Micro variant for SDIO small write transfers
832 		 * needs to have clock H/W flow control disabled,
833 		 * otherwise the transfer will not start. The threshold
834 		 * depends on the rate of MCLK.
835 		 */
836 		if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
837 		    (host->size < 8 ||
838 		     (host->size <= 8 && host->mclk > 50000000)))
839 			clk = host->clk_reg & ~variant->clkreg_enable;
840 		else
841 			clk = host->clk_reg | variant->clkreg_enable;
842 
843 		mmci_write_clkreg(host, clk);
844 	}
845 
846 	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
847 	    host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
848 		datactrl |= variant->datactrl_mask_ddrmode;
849 
850 	/*
851 	 * Attempt to use DMA operation mode, if this
852 	 * should fail, fall back to PIO mode
853 	 */
854 	if (!mmci_dma_start_data(host, datactrl))
855 		return;
856 
857 	/* IRQ mode, map the SG list for CPU reading/writing */
858 	mmci_init_sg(host, data);
859 
860 	if (data->flags & MMC_DATA_READ) {
861 		irqmask = MCI_RXFIFOHALFFULLMASK;
862 
863 		/*
864 		 * If we have less than the fifo 'half-full' threshold to
865 		 * transfer, trigger a PIO interrupt as soon as any data
866 		 * is available.
867 		 */
868 		if (host->size < variant->fifohalfsize)
869 			irqmask |= MCI_RXDATAAVLBLMASK;
870 	} else {
871 		/*
872 		 * We don't actually need to include "FIFO empty" here
873 		 * since its implicit in "FIFO half empty".
874 		 */
875 		irqmask = MCI_TXFIFOHALFEMPTYMASK;
876 	}
877 
878 	mmci_write_datactrlreg(host, datactrl);
879 	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
880 	mmci_set_mask1(host, irqmask);
881 }
882 
883 static void
884 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
885 {
886 	void __iomem *base = host->base;
887 
888 	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
889 	    cmd->opcode, cmd->arg, cmd->flags);
890 
891 	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
892 		writel(0, base + MMCICOMMAND);
893 		mmci_reg_delay(host);
894 	}
895 
896 	c |= cmd->opcode | MCI_CPSM_ENABLE;
897 	if (cmd->flags & MMC_RSP_PRESENT) {
898 		if (cmd->flags & MMC_RSP_136)
899 			c |= MCI_CPSM_LONGRSP;
900 		c |= MCI_CPSM_RESPONSE;
901 	}
902 	if (/*interrupt*/0)
903 		c |= MCI_CPSM_INTERRUPT;
904 
905 	if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
906 		c |= host->variant->data_cmd_enable;
907 
908 	host->cmd = cmd;
909 
910 	writel(cmd->arg, base + MMCIARGUMENT);
911 	writel(c, base + MMCICOMMAND);
912 }
913 
914 static void
915 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
916 	      unsigned int status)
917 {
918 	/* Make sure we have data to handle */
919 	if (!data)
920 		return;
921 
922 	/* First check for errors */
923 	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
924 		      MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
925 		u32 remain, success;
926 
927 		/* Terminate the DMA transfer */
928 		if (dma_inprogress(host)) {
929 			mmci_dma_data_error(host);
930 			mmci_dma_unmap(host, data);
931 		}
932 
933 		/*
934 		 * Calculate how far we are into the transfer.  Note that
935 		 * the data counter gives the number of bytes transferred
936 		 * on the MMC bus, not on the host side.  On reads, this
937 		 * can be as much as a FIFO-worth of data ahead.  This
938 		 * matters for FIFO overruns only.
939 		 */
940 		remain = readl(host->base + MMCIDATACNT);
941 		success = data->blksz * data->blocks - remain;
942 
943 		dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
944 			status, success);
945 		if (status & MCI_DATACRCFAIL) {
946 			/* Last block was not successful */
947 			success -= 1;
948 			data->error = -EILSEQ;
949 		} else if (status & MCI_DATATIMEOUT) {
950 			data->error = -ETIMEDOUT;
951 		} else if (status & MCI_STARTBITERR) {
952 			data->error = -ECOMM;
953 		} else if (status & MCI_TXUNDERRUN) {
954 			data->error = -EIO;
955 		} else if (status & MCI_RXOVERRUN) {
956 			if (success > host->variant->fifosize)
957 				success -= host->variant->fifosize;
958 			else
959 				success = 0;
960 			data->error = -EIO;
961 		}
962 		data->bytes_xfered = round_down(success, data->blksz);
963 	}
964 
965 	if (status & MCI_DATABLOCKEND)
966 		dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
967 
968 	if (status & MCI_DATAEND || data->error) {
969 		if (dma_inprogress(host))
970 			mmci_dma_finalize(host, data);
971 		mmci_stop_data(host);
972 
973 		if (!data->error)
974 			/* The error clause is handled above, success! */
975 			data->bytes_xfered = data->blksz * data->blocks;
976 
977 		if (!data->stop || host->mrq->sbc) {
978 			mmci_request_end(host, data->mrq);
979 		} else {
980 			mmci_start_command(host, data->stop, 0);
981 		}
982 	}
983 }
984 
985 static void
986 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
987 	     unsigned int status)
988 {
989 	void __iomem *base = host->base;
990 	bool sbc;
991 
992 	if (!cmd)
993 		return;
994 
995 	sbc = (cmd == host->mrq->sbc);
996 
997 	/*
998 	 * We need to be one of these interrupts to be considered worth
999 	 * handling. Note that we tag on any latent IRQs postponed
1000 	 * due to waiting for busy status.
1001 	 */
1002 	if (!((status|host->busy_status) &
1003 	      (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
1004 		return;
1005 
1006 	/*
1007 	 * ST Micro variant: handle busy detection.
1008 	 */
1009 	if (host->variant->busy_detect) {
1010 		bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
1011 
1012 		/* We are busy with a command, return */
1013 		if (host->busy_status &&
1014 		    (status & host->variant->busy_detect_flag))
1015 			return;
1016 
1017 		/*
1018 		 * We were not busy, but we now got a busy response on
1019 		 * something that was not an error, and we double-check
1020 		 * that the special busy status bit is still set before
1021 		 * proceeding.
1022 		 */
1023 		if (!host->busy_status && busy_resp &&
1024 		    !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1025 		    (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1026 			/* Unmask the busy IRQ */
1027 			writel(readl(base + MMCIMASK0) |
1028 			       host->variant->busy_detect_mask,
1029 			       base + MMCIMASK0);
1030 			/*
1031 			 * Now cache the last response status code (until
1032 			 * the busy bit goes low), and return.
1033 			 */
1034 			host->busy_status =
1035 				status & (MCI_CMDSENT|MCI_CMDRESPEND);
1036 			return;
1037 		}
1038 
1039 		/*
1040 		 * At this point we are not busy with a command, we have
1041 		 * not received a new busy request, mask the busy IRQ and
1042 		 * fall through to process the IRQ.
1043 		 */
1044 		if (host->busy_status) {
1045 			writel(readl(base + MMCIMASK0) &
1046 			       ~host->variant->busy_detect_mask,
1047 			       base + MMCIMASK0);
1048 			host->busy_status = 0;
1049 		}
1050 	}
1051 
1052 	host->cmd = NULL;
1053 
1054 	if (status & MCI_CMDTIMEOUT) {
1055 		cmd->error = -ETIMEDOUT;
1056 	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1057 		cmd->error = -EILSEQ;
1058 	} else {
1059 		cmd->resp[0] = readl(base + MMCIRESPONSE0);
1060 		cmd->resp[1] = readl(base + MMCIRESPONSE1);
1061 		cmd->resp[2] = readl(base + MMCIRESPONSE2);
1062 		cmd->resp[3] = readl(base + MMCIRESPONSE3);
1063 	}
1064 
1065 	if ((!sbc && !cmd->data) || cmd->error) {
1066 		if (host->data) {
1067 			/* Terminate the DMA transfer */
1068 			if (dma_inprogress(host)) {
1069 				mmci_dma_data_error(host);
1070 				mmci_dma_unmap(host, host->data);
1071 			}
1072 			mmci_stop_data(host);
1073 		}
1074 		mmci_request_end(host, host->mrq);
1075 	} else if (sbc) {
1076 		mmci_start_command(host, host->mrq->cmd, 0);
1077 	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
1078 		mmci_start_data(host, cmd->data);
1079 	}
1080 }
1081 
1082 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1083 {
1084 	return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1085 }
1086 
1087 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1088 {
1089 	/*
1090 	 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1091 	 * from the fifo range should be used
1092 	 */
1093 	if (status & MCI_RXFIFOHALFFULL)
1094 		return host->variant->fifohalfsize;
1095 	else if (status & MCI_RXDATAAVLBL)
1096 		return 4;
1097 
1098 	return 0;
1099 }
1100 
1101 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1102 {
1103 	void __iomem *base = host->base;
1104 	char *ptr = buffer;
1105 	u32 status = readl(host->base + MMCISTATUS);
1106 	int host_remain = host->size;
1107 
1108 	do {
1109 		int count = host->get_rx_fifocnt(host, status, host_remain);
1110 
1111 		if (count > remain)
1112 			count = remain;
1113 
1114 		if (count <= 0)
1115 			break;
1116 
1117 		/*
1118 		 * SDIO especially may want to send something that is
1119 		 * not divisible by 4 (as opposed to card sectors
1120 		 * etc). Therefore make sure to always read the last bytes
1121 		 * while only doing full 32-bit reads towards the FIFO.
1122 		 */
1123 		if (unlikely(count & 0x3)) {
1124 			if (count < 4) {
1125 				unsigned char buf[4];
1126 				ioread32_rep(base + MMCIFIFO, buf, 1);
1127 				memcpy(ptr, buf, count);
1128 			} else {
1129 				ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1130 				count &= ~0x3;
1131 			}
1132 		} else {
1133 			ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1134 		}
1135 
1136 		ptr += count;
1137 		remain -= count;
1138 		host_remain -= count;
1139 
1140 		if (remain == 0)
1141 			break;
1142 
1143 		status = readl(base + MMCISTATUS);
1144 	} while (status & MCI_RXDATAAVLBL);
1145 
1146 	return ptr - buffer;
1147 }
1148 
1149 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1150 {
1151 	struct variant_data *variant = host->variant;
1152 	void __iomem *base = host->base;
1153 	char *ptr = buffer;
1154 
1155 	do {
1156 		unsigned int count, maxcnt;
1157 
1158 		maxcnt = status & MCI_TXFIFOEMPTY ?
1159 			 variant->fifosize : variant->fifohalfsize;
1160 		count = min(remain, maxcnt);
1161 
1162 		/*
1163 		 * SDIO especially may want to send something that is
1164 		 * not divisible by 4 (as opposed to card sectors
1165 		 * etc), and the FIFO only accept full 32-bit writes.
1166 		 * So compensate by adding +3 on the count, a single
1167 		 * byte become a 32bit write, 7 bytes will be two
1168 		 * 32bit writes etc.
1169 		 */
1170 		iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1171 
1172 		ptr += count;
1173 		remain -= count;
1174 
1175 		if (remain == 0)
1176 			break;
1177 
1178 		status = readl(base + MMCISTATUS);
1179 	} while (status & MCI_TXFIFOHALFEMPTY);
1180 
1181 	return ptr - buffer;
1182 }
1183 
1184 /*
1185  * PIO data transfer IRQ handler.
1186  */
1187 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1188 {
1189 	struct mmci_host *host = dev_id;
1190 	struct sg_mapping_iter *sg_miter = &host->sg_miter;
1191 	struct variant_data *variant = host->variant;
1192 	void __iomem *base = host->base;
1193 	unsigned long flags;
1194 	u32 status;
1195 
1196 	status = readl(base + MMCISTATUS);
1197 
1198 	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1199 
1200 	local_irq_save(flags);
1201 
1202 	do {
1203 		unsigned int remain, len;
1204 		char *buffer;
1205 
1206 		/*
1207 		 * For write, we only need to test the half-empty flag
1208 		 * here - if the FIFO is completely empty, then by
1209 		 * definition it is more than half empty.
1210 		 *
1211 		 * For read, check for data available.
1212 		 */
1213 		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1214 			break;
1215 
1216 		if (!sg_miter_next(sg_miter))
1217 			break;
1218 
1219 		buffer = sg_miter->addr;
1220 		remain = sg_miter->length;
1221 
1222 		len = 0;
1223 		if (status & MCI_RXACTIVE)
1224 			len = mmci_pio_read(host, buffer, remain);
1225 		if (status & MCI_TXACTIVE)
1226 			len = mmci_pio_write(host, buffer, remain, status);
1227 
1228 		sg_miter->consumed = len;
1229 
1230 		host->size -= len;
1231 		remain -= len;
1232 
1233 		if (remain)
1234 			break;
1235 
1236 		status = readl(base + MMCISTATUS);
1237 	} while (1);
1238 
1239 	sg_miter_stop(sg_miter);
1240 
1241 	local_irq_restore(flags);
1242 
1243 	/*
1244 	 * If we have less than the fifo 'half-full' threshold to transfer,
1245 	 * trigger a PIO interrupt as soon as any data is available.
1246 	 */
1247 	if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1248 		mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1249 
1250 	/*
1251 	 * If we run out of data, disable the data IRQs; this
1252 	 * prevents a race where the FIFO becomes empty before
1253 	 * the chip itself has disabled the data path, and
1254 	 * stops us racing with our data end IRQ.
1255 	 */
1256 	if (host->size == 0) {
1257 		mmci_set_mask1(host, 0);
1258 		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1259 	}
1260 
1261 	return IRQ_HANDLED;
1262 }
1263 
1264 /*
1265  * Handle completion of command and data transfers.
1266  */
1267 static irqreturn_t mmci_irq(int irq, void *dev_id)
1268 {
1269 	struct mmci_host *host = dev_id;
1270 	u32 status;
1271 	int ret = 0;
1272 
1273 	spin_lock(&host->lock);
1274 
1275 	do {
1276 		status = readl(host->base + MMCISTATUS);
1277 
1278 		if (host->singleirq) {
1279 			if (status & readl(host->base + MMCIMASK1))
1280 				mmci_pio_irq(irq, dev_id);
1281 
1282 			status &= ~MCI_IRQ1MASK;
1283 		}
1284 
1285 		/*
1286 		 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1287 		 * enabled) since the HW seems to be triggering the IRQ on both
1288 		 * edges while monitoring DAT0 for busy completion.
1289 		 */
1290 		status &= readl(host->base + MMCIMASK0);
1291 		writel(status, host->base + MMCICLEAR);
1292 
1293 		dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1294 
1295 		if (host->variant->reversed_irq_handling) {
1296 			mmci_data_irq(host, host->data, status);
1297 			mmci_cmd_irq(host, host->cmd, status);
1298 		} else {
1299 			mmci_cmd_irq(host, host->cmd, status);
1300 			mmci_data_irq(host, host->data, status);
1301 		}
1302 
1303 		/*
1304 		 * Don't poll for busy completion in irq context.
1305 		 */
1306 		if (host->variant->busy_detect && host->busy_status)
1307 			status &= ~host->variant->busy_detect_flag;
1308 
1309 		ret = 1;
1310 	} while (status);
1311 
1312 	spin_unlock(&host->lock);
1313 
1314 	return IRQ_RETVAL(ret);
1315 }
1316 
1317 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1318 {
1319 	struct mmci_host *host = mmc_priv(mmc);
1320 	unsigned long flags;
1321 
1322 	WARN_ON(host->mrq != NULL);
1323 
1324 	mrq->cmd->error = mmci_validate_data(host, mrq->data);
1325 	if (mrq->cmd->error) {
1326 		mmc_request_done(mmc, mrq);
1327 		return;
1328 	}
1329 
1330 	spin_lock_irqsave(&host->lock, flags);
1331 
1332 	host->mrq = mrq;
1333 
1334 	if (mrq->data)
1335 		mmci_get_next_data(host, mrq->data);
1336 
1337 	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1338 		mmci_start_data(host, mrq->data);
1339 
1340 	if (mrq->sbc)
1341 		mmci_start_command(host, mrq->sbc, 0);
1342 	else
1343 		mmci_start_command(host, mrq->cmd, 0);
1344 
1345 	spin_unlock_irqrestore(&host->lock, flags);
1346 }
1347 
1348 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1349 {
1350 	struct mmci_host *host = mmc_priv(mmc);
1351 	struct variant_data *variant = host->variant;
1352 	u32 pwr = 0;
1353 	unsigned long flags;
1354 	int ret;
1355 
1356 	if (host->plat->ios_handler &&
1357 		host->plat->ios_handler(mmc_dev(mmc), ios))
1358 			dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1359 
1360 	switch (ios->power_mode) {
1361 	case MMC_POWER_OFF:
1362 		if (!IS_ERR(mmc->supply.vmmc))
1363 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1364 
1365 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1366 			regulator_disable(mmc->supply.vqmmc);
1367 			host->vqmmc_enabled = false;
1368 		}
1369 
1370 		break;
1371 	case MMC_POWER_UP:
1372 		if (!IS_ERR(mmc->supply.vmmc))
1373 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1374 
1375 		/*
1376 		 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1377 		 * and instead uses MCI_PWR_ON so apply whatever value is
1378 		 * configured in the variant data.
1379 		 */
1380 		pwr |= variant->pwrreg_powerup;
1381 
1382 		break;
1383 	case MMC_POWER_ON:
1384 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1385 			ret = regulator_enable(mmc->supply.vqmmc);
1386 			if (ret < 0)
1387 				dev_err(mmc_dev(mmc),
1388 					"failed to enable vqmmc regulator\n");
1389 			else
1390 				host->vqmmc_enabled = true;
1391 		}
1392 
1393 		pwr |= MCI_PWR_ON;
1394 		break;
1395 	}
1396 
1397 	if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1398 		/*
1399 		 * The ST Micro variant has some additional bits
1400 		 * indicating signal direction for the signals in
1401 		 * the SD/MMC bus and feedback-clock usage.
1402 		 */
1403 		pwr |= host->pwr_reg_add;
1404 
1405 		if (ios->bus_width == MMC_BUS_WIDTH_4)
1406 			pwr &= ~MCI_ST_DATA74DIREN;
1407 		else if (ios->bus_width == MMC_BUS_WIDTH_1)
1408 			pwr &= (~MCI_ST_DATA74DIREN &
1409 				~MCI_ST_DATA31DIREN &
1410 				~MCI_ST_DATA2DIREN);
1411 	}
1412 
1413 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1414 		if (host->hw_designer != AMBA_VENDOR_ST)
1415 			pwr |= MCI_ROD;
1416 		else {
1417 			/*
1418 			 * The ST Micro variant use the ROD bit for something
1419 			 * else and only has OD (Open Drain).
1420 			 */
1421 			pwr |= MCI_OD;
1422 		}
1423 	}
1424 
1425 	/*
1426 	 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1427 	 * gating the clock, the MCI_PWR_ON bit is cleared.
1428 	 */
1429 	if (!ios->clock && variant->pwrreg_clkgate)
1430 		pwr &= ~MCI_PWR_ON;
1431 
1432 	if (host->variant->explicit_mclk_control &&
1433 	    ios->clock != host->clock_cache) {
1434 		ret = clk_set_rate(host->clk, ios->clock);
1435 		if (ret < 0)
1436 			dev_err(mmc_dev(host->mmc),
1437 				"Error setting clock rate (%d)\n", ret);
1438 		else
1439 			host->mclk = clk_get_rate(host->clk);
1440 	}
1441 	host->clock_cache = ios->clock;
1442 
1443 	spin_lock_irqsave(&host->lock, flags);
1444 
1445 	mmci_set_clkreg(host, ios->clock);
1446 	mmci_write_pwrreg(host, pwr);
1447 	mmci_reg_delay(host);
1448 
1449 	spin_unlock_irqrestore(&host->lock, flags);
1450 }
1451 
1452 static int mmci_get_cd(struct mmc_host *mmc)
1453 {
1454 	struct mmci_host *host = mmc_priv(mmc);
1455 	struct mmci_platform_data *plat = host->plat;
1456 	unsigned int status = mmc_gpio_get_cd(mmc);
1457 
1458 	if (status == -ENOSYS) {
1459 		if (!plat->status)
1460 			return 1; /* Assume always present */
1461 
1462 		status = plat->status(mmc_dev(host->mmc));
1463 	}
1464 	return status;
1465 }
1466 
1467 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1468 {
1469 	int ret = 0;
1470 
1471 	if (!IS_ERR(mmc->supply.vqmmc)) {
1472 
1473 		switch (ios->signal_voltage) {
1474 		case MMC_SIGNAL_VOLTAGE_330:
1475 			ret = regulator_set_voltage(mmc->supply.vqmmc,
1476 						2700000, 3600000);
1477 			break;
1478 		case MMC_SIGNAL_VOLTAGE_180:
1479 			ret = regulator_set_voltage(mmc->supply.vqmmc,
1480 						1700000, 1950000);
1481 			break;
1482 		case MMC_SIGNAL_VOLTAGE_120:
1483 			ret = regulator_set_voltage(mmc->supply.vqmmc,
1484 						1100000, 1300000);
1485 			break;
1486 		}
1487 
1488 		if (ret)
1489 			dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1490 	}
1491 
1492 	return ret;
1493 }
1494 
1495 static struct mmc_host_ops mmci_ops = {
1496 	.request	= mmci_request,
1497 	.pre_req	= mmci_pre_request,
1498 	.post_req	= mmci_post_request,
1499 	.set_ios	= mmci_set_ios,
1500 	.get_ro		= mmc_gpio_get_ro,
1501 	.get_cd		= mmci_get_cd,
1502 	.start_signal_voltage_switch = mmci_sig_volt_switch,
1503 };
1504 
1505 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1506 {
1507 	struct mmci_host *host = mmc_priv(mmc);
1508 	int ret = mmc_of_parse(mmc);
1509 
1510 	if (ret)
1511 		return ret;
1512 
1513 	if (of_get_property(np, "st,sig-dir-dat0", NULL))
1514 		host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1515 	if (of_get_property(np, "st,sig-dir-dat2", NULL))
1516 		host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1517 	if (of_get_property(np, "st,sig-dir-dat31", NULL))
1518 		host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1519 	if (of_get_property(np, "st,sig-dir-dat74", NULL))
1520 		host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1521 	if (of_get_property(np, "st,sig-dir-cmd", NULL))
1522 		host->pwr_reg_add |= MCI_ST_CMDDIREN;
1523 	if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1524 		host->pwr_reg_add |= MCI_ST_FBCLKEN;
1525 
1526 	if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1527 		mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1528 	if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1529 		mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1530 
1531 	return 0;
1532 }
1533 
1534 static int mmci_probe(struct amba_device *dev,
1535 	const struct amba_id *id)
1536 {
1537 	struct mmci_platform_data *plat = dev->dev.platform_data;
1538 	struct device_node *np = dev->dev.of_node;
1539 	struct variant_data *variant = id->data;
1540 	struct mmci_host *host;
1541 	struct mmc_host *mmc;
1542 	int ret;
1543 
1544 	/* Must have platform data or Device Tree. */
1545 	if (!plat && !np) {
1546 		dev_err(&dev->dev, "No plat data or DT found\n");
1547 		return -EINVAL;
1548 	}
1549 
1550 	if (!plat) {
1551 		plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1552 		if (!plat)
1553 			return -ENOMEM;
1554 	}
1555 
1556 	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1557 	if (!mmc)
1558 		return -ENOMEM;
1559 
1560 	ret = mmci_of_parse(np, mmc);
1561 	if (ret)
1562 		goto host_free;
1563 
1564 	host = mmc_priv(mmc);
1565 	host->mmc = mmc;
1566 
1567 	host->hw_designer = amba_manf(dev);
1568 	host->hw_revision = amba_rev(dev);
1569 	dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1570 	dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1571 
1572 	host->clk = devm_clk_get(&dev->dev, NULL);
1573 	if (IS_ERR(host->clk)) {
1574 		ret = PTR_ERR(host->clk);
1575 		goto host_free;
1576 	}
1577 
1578 	ret = clk_prepare_enable(host->clk);
1579 	if (ret)
1580 		goto host_free;
1581 
1582 	if (variant->qcom_fifo)
1583 		host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1584 	else
1585 		host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1586 
1587 	host->plat = plat;
1588 	host->variant = variant;
1589 	host->mclk = clk_get_rate(host->clk);
1590 	/*
1591 	 * According to the spec, mclk is max 100 MHz,
1592 	 * so we try to adjust the clock down to this,
1593 	 * (if possible).
1594 	 */
1595 	if (host->mclk > variant->f_max) {
1596 		ret = clk_set_rate(host->clk, variant->f_max);
1597 		if (ret < 0)
1598 			goto clk_disable;
1599 		host->mclk = clk_get_rate(host->clk);
1600 		dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1601 			host->mclk);
1602 	}
1603 
1604 	host->phybase = dev->res.start;
1605 	host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1606 	if (IS_ERR(host->base)) {
1607 		ret = PTR_ERR(host->base);
1608 		goto clk_disable;
1609 	}
1610 
1611 	/*
1612 	 * The ARM and ST versions of the block have slightly different
1613 	 * clock divider equations which means that the minimum divider
1614 	 * differs too.
1615 	 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1616 	 */
1617 	if (variant->st_clkdiv)
1618 		mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1619 	else if (variant->explicit_mclk_control)
1620 		mmc->f_min = clk_round_rate(host->clk, 100000);
1621 	else
1622 		mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1623 	/*
1624 	 * If no maximum operating frequency is supplied, fall back to use
1625 	 * the module parameter, which has a (low) default value in case it
1626 	 * is not specified. Either value must not exceed the clock rate into
1627 	 * the block, of course.
1628 	 */
1629 	if (mmc->f_max)
1630 		mmc->f_max = variant->explicit_mclk_control ?
1631 				min(variant->f_max, mmc->f_max) :
1632 				min(host->mclk, mmc->f_max);
1633 	else
1634 		mmc->f_max = variant->explicit_mclk_control ?
1635 				fmax : min(host->mclk, fmax);
1636 
1637 
1638 	dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1639 
1640 	/* Get regulators and the supported OCR mask */
1641 	ret = mmc_regulator_get_supply(mmc);
1642 	if (ret == -EPROBE_DEFER)
1643 		goto clk_disable;
1644 
1645 	if (!mmc->ocr_avail)
1646 		mmc->ocr_avail = plat->ocr_mask;
1647 	else if (plat->ocr_mask)
1648 		dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1649 
1650 	/* DT takes precedence over platform data. */
1651 	if (!np) {
1652 		if (!plat->cd_invert)
1653 			mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1654 		mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1655 	}
1656 
1657 	/* We support these capabilities. */
1658 	mmc->caps |= MMC_CAP_CMD23;
1659 
1660 	/*
1661 	 * Enable busy detection.
1662 	 */
1663 	if (variant->busy_detect) {
1664 		mmci_ops.card_busy = mmci_card_busy;
1665 		/*
1666 		 * Not all variants have a flag to enable busy detection
1667 		 * in the DPSM, but if they do, set it here.
1668 		 */
1669 		if (variant->busy_dpsm_flag)
1670 			mmci_write_datactrlreg(host,
1671 					       host->variant->busy_dpsm_flag);
1672 		mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1673 		mmc->max_busy_timeout = 0;
1674 	}
1675 
1676 	mmc->ops = &mmci_ops;
1677 
1678 	/* We support these PM capabilities. */
1679 	mmc->pm_caps |= MMC_PM_KEEP_POWER;
1680 
1681 	/*
1682 	 * We can do SGIO
1683 	 */
1684 	mmc->max_segs = NR_SG;
1685 
1686 	/*
1687 	 * Since only a certain number of bits are valid in the data length
1688 	 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1689 	 * single request.
1690 	 */
1691 	mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1692 
1693 	/*
1694 	 * Set the maximum segment size.  Since we aren't doing DMA
1695 	 * (yet) we are only limited by the data length register.
1696 	 */
1697 	mmc->max_seg_size = mmc->max_req_size;
1698 
1699 	/*
1700 	 * Block size can be up to 2048 bytes, but must be a power of two.
1701 	 */
1702 	mmc->max_blk_size = 1 << 11;
1703 
1704 	/*
1705 	 * Limit the number of blocks transferred so that we don't overflow
1706 	 * the maximum request size.
1707 	 */
1708 	mmc->max_blk_count = mmc->max_req_size >> 11;
1709 
1710 	spin_lock_init(&host->lock);
1711 
1712 	writel(0, host->base + MMCIMASK0);
1713 	writel(0, host->base + MMCIMASK1);
1714 	writel(0xfff, host->base + MMCICLEAR);
1715 
1716 	/*
1717 	 * If:
1718 	 * - not using DT but using a descriptor table, or
1719 	 * - using a table of descriptors ALONGSIDE DT, or
1720 	 * look up these descriptors named "cd" and "wp" right here, fail
1721 	 * silently of these do not exist and proceed to try platform data
1722 	 */
1723 	if (!np) {
1724 		ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1725 		if (ret < 0) {
1726 			if (ret == -EPROBE_DEFER)
1727 				goto clk_disable;
1728 			else if (gpio_is_valid(plat->gpio_cd)) {
1729 				ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1730 				if (ret)
1731 					goto clk_disable;
1732 			}
1733 		}
1734 
1735 		ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
1736 		if (ret < 0) {
1737 			if (ret == -EPROBE_DEFER)
1738 				goto clk_disable;
1739 			else if (gpio_is_valid(plat->gpio_wp)) {
1740 				ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1741 				if (ret)
1742 					goto clk_disable;
1743 			}
1744 		}
1745 	}
1746 
1747 	ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1748 			DRIVER_NAME " (cmd)", host);
1749 	if (ret)
1750 		goto clk_disable;
1751 
1752 	if (!dev->irq[1])
1753 		host->singleirq = true;
1754 	else {
1755 		ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1756 				IRQF_SHARED, DRIVER_NAME " (pio)", host);
1757 		if (ret)
1758 			goto clk_disable;
1759 	}
1760 
1761 	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1762 
1763 	amba_set_drvdata(dev, mmc);
1764 
1765 	dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1766 		 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1767 		 amba_rev(dev), (unsigned long long)dev->res.start,
1768 		 dev->irq[0], dev->irq[1]);
1769 
1770 	mmci_dma_setup(host);
1771 
1772 	pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1773 	pm_runtime_use_autosuspend(&dev->dev);
1774 
1775 	mmc_add_host(mmc);
1776 
1777 	pm_runtime_put(&dev->dev);
1778 	return 0;
1779 
1780  clk_disable:
1781 	clk_disable_unprepare(host->clk);
1782  host_free:
1783 	mmc_free_host(mmc);
1784 	return ret;
1785 }
1786 
1787 static int mmci_remove(struct amba_device *dev)
1788 {
1789 	struct mmc_host *mmc = amba_get_drvdata(dev);
1790 
1791 	if (mmc) {
1792 		struct mmci_host *host = mmc_priv(mmc);
1793 
1794 		/*
1795 		 * Undo pm_runtime_put() in probe.  We use the _sync
1796 		 * version here so that we can access the primecell.
1797 		 */
1798 		pm_runtime_get_sync(&dev->dev);
1799 
1800 		mmc_remove_host(mmc);
1801 
1802 		writel(0, host->base + MMCIMASK0);
1803 		writel(0, host->base + MMCIMASK1);
1804 
1805 		writel(0, host->base + MMCICOMMAND);
1806 		writel(0, host->base + MMCIDATACTRL);
1807 
1808 		mmci_dma_release(host);
1809 		clk_disable_unprepare(host->clk);
1810 		mmc_free_host(mmc);
1811 	}
1812 
1813 	return 0;
1814 }
1815 
1816 #ifdef CONFIG_PM
1817 static void mmci_save(struct mmci_host *host)
1818 {
1819 	unsigned long flags;
1820 
1821 	spin_lock_irqsave(&host->lock, flags);
1822 
1823 	writel(0, host->base + MMCIMASK0);
1824 	if (host->variant->pwrreg_nopower) {
1825 		writel(0, host->base + MMCIDATACTRL);
1826 		writel(0, host->base + MMCIPOWER);
1827 		writel(0, host->base + MMCICLOCK);
1828 	}
1829 	mmci_reg_delay(host);
1830 
1831 	spin_unlock_irqrestore(&host->lock, flags);
1832 }
1833 
1834 static void mmci_restore(struct mmci_host *host)
1835 {
1836 	unsigned long flags;
1837 
1838 	spin_lock_irqsave(&host->lock, flags);
1839 
1840 	if (host->variant->pwrreg_nopower) {
1841 		writel(host->clk_reg, host->base + MMCICLOCK);
1842 		writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1843 		writel(host->pwr_reg, host->base + MMCIPOWER);
1844 	}
1845 	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1846 	mmci_reg_delay(host);
1847 
1848 	spin_unlock_irqrestore(&host->lock, flags);
1849 }
1850 
1851 static int mmci_runtime_suspend(struct device *dev)
1852 {
1853 	struct amba_device *adev = to_amba_device(dev);
1854 	struct mmc_host *mmc = amba_get_drvdata(adev);
1855 
1856 	if (mmc) {
1857 		struct mmci_host *host = mmc_priv(mmc);
1858 		pinctrl_pm_select_sleep_state(dev);
1859 		mmci_save(host);
1860 		clk_disable_unprepare(host->clk);
1861 	}
1862 
1863 	return 0;
1864 }
1865 
1866 static int mmci_runtime_resume(struct device *dev)
1867 {
1868 	struct amba_device *adev = to_amba_device(dev);
1869 	struct mmc_host *mmc = amba_get_drvdata(adev);
1870 
1871 	if (mmc) {
1872 		struct mmci_host *host = mmc_priv(mmc);
1873 		clk_prepare_enable(host->clk);
1874 		mmci_restore(host);
1875 		pinctrl_pm_select_default_state(dev);
1876 	}
1877 
1878 	return 0;
1879 }
1880 #endif
1881 
1882 static const struct dev_pm_ops mmci_dev_pm_ops = {
1883 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1884 				pm_runtime_force_resume)
1885 	SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1886 };
1887 
1888 static struct amba_id mmci_ids[] = {
1889 	{
1890 		.id	= 0x00041180,
1891 		.mask	= 0xff0fffff,
1892 		.data	= &variant_arm,
1893 	},
1894 	{
1895 		.id	= 0x01041180,
1896 		.mask	= 0xff0fffff,
1897 		.data	= &variant_arm_extended_fifo,
1898 	},
1899 	{
1900 		.id	= 0x02041180,
1901 		.mask	= 0xff0fffff,
1902 		.data	= &variant_arm_extended_fifo_hwfc,
1903 	},
1904 	{
1905 		.id	= 0x00041181,
1906 		.mask	= 0x000fffff,
1907 		.data	= &variant_arm,
1908 	},
1909 	/* ST Micro variants */
1910 	{
1911 		.id     = 0x00180180,
1912 		.mask   = 0x00ffffff,
1913 		.data	= &variant_u300,
1914 	},
1915 	{
1916 		.id     = 0x10180180,
1917 		.mask   = 0xf0ffffff,
1918 		.data	= &variant_nomadik,
1919 	},
1920 	{
1921 		.id     = 0x00280180,
1922 		.mask   = 0x00ffffff,
1923 		.data	= &variant_nomadik,
1924 	},
1925 	{
1926 		.id     = 0x00480180,
1927 		.mask   = 0xf0ffffff,
1928 		.data	= &variant_ux500,
1929 	},
1930 	{
1931 		.id     = 0x10480180,
1932 		.mask   = 0xf0ffffff,
1933 		.data	= &variant_ux500v2,
1934 	},
1935 	/* Qualcomm variants */
1936 	{
1937 		.id     = 0x00051180,
1938 		.mask	= 0x000fffff,
1939 		.data	= &variant_qcom,
1940 	},
1941 	{ 0, 0 },
1942 };
1943 
1944 MODULE_DEVICE_TABLE(amba, mmci_ids);
1945 
1946 static struct amba_driver mmci_driver = {
1947 	.drv		= {
1948 		.name	= DRIVER_NAME,
1949 		.pm	= &mmci_dev_pm_ops,
1950 	},
1951 	.probe		= mmci_probe,
1952 	.remove		= mmci_remove,
1953 	.id_table	= mmci_ids,
1954 };
1955 
1956 module_amba_driver(mmci_driver);
1957 
1958 module_param(fmax, uint, 0444);
1959 
1960 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1961 MODULE_LICENSE("GPL");
1962