1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/of.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/amba/mmci.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/types.h> 38 #include <linux/pinctrl/consumer.h> 39 40 #include <asm/div64.h> 41 #include <asm/io.h> 42 43 #include "mmci.h" 44 #include "mmci_qcom_dml.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 #ifdef CONFIG_DMA_ENGINE 49 void mmci_variant_init(struct mmci_host *host); 50 #else 51 static inline void mmci_variant_init(struct mmci_host *host) {} 52 #endif 53 54 static unsigned int fmax = 515633; 55 56 static struct variant_data variant_arm = { 57 .fifosize = 16 * 4, 58 .fifohalfsize = 8 * 4, 59 .datalength_bits = 16, 60 .pwrreg_powerup = MCI_PWR_UP, 61 .f_max = 100000000, 62 .reversed_irq_handling = true, 63 .mmcimask1 = true, 64 .start_err = MCI_STARTBITERR, 65 .opendrain = MCI_ROD, 66 .init = mmci_variant_init, 67 }; 68 69 static struct variant_data variant_arm_extended_fifo = { 70 .fifosize = 128 * 4, 71 .fifohalfsize = 64 * 4, 72 .datalength_bits = 16, 73 .pwrreg_powerup = MCI_PWR_UP, 74 .f_max = 100000000, 75 .mmcimask1 = true, 76 .start_err = MCI_STARTBITERR, 77 .opendrain = MCI_ROD, 78 .init = mmci_variant_init, 79 }; 80 81 static struct variant_data variant_arm_extended_fifo_hwfc = { 82 .fifosize = 128 * 4, 83 .fifohalfsize = 64 * 4, 84 .clkreg_enable = MCI_ARM_HWFCEN, 85 .datalength_bits = 16, 86 .pwrreg_powerup = MCI_PWR_UP, 87 .f_max = 100000000, 88 .mmcimask1 = true, 89 .start_err = MCI_STARTBITERR, 90 .opendrain = MCI_ROD, 91 .init = mmci_variant_init, 92 }; 93 94 static struct variant_data variant_u300 = { 95 .fifosize = 16 * 4, 96 .fifohalfsize = 8 * 4, 97 .clkreg_enable = MCI_ST_U300_HWFCEN, 98 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 99 .datalength_bits = 16, 100 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 101 .st_sdio = true, 102 .pwrreg_powerup = MCI_PWR_ON, 103 .f_max = 100000000, 104 .signal_direction = true, 105 .pwrreg_clkgate = true, 106 .pwrreg_nopower = true, 107 .mmcimask1 = true, 108 .start_err = MCI_STARTBITERR, 109 .opendrain = MCI_OD, 110 .init = mmci_variant_init, 111 }; 112 113 static struct variant_data variant_nomadik = { 114 .fifosize = 16 * 4, 115 .fifohalfsize = 8 * 4, 116 .clkreg = MCI_CLK_ENABLE, 117 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 118 .datalength_bits = 24, 119 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 120 .st_sdio = true, 121 .st_clkdiv = true, 122 .pwrreg_powerup = MCI_PWR_ON, 123 .f_max = 100000000, 124 .signal_direction = true, 125 .pwrreg_clkgate = true, 126 .pwrreg_nopower = true, 127 .mmcimask1 = true, 128 .start_err = MCI_STARTBITERR, 129 .opendrain = MCI_OD, 130 .init = mmci_variant_init, 131 }; 132 133 static struct variant_data variant_ux500 = { 134 .fifosize = 30 * 4, 135 .fifohalfsize = 8 * 4, 136 .clkreg = MCI_CLK_ENABLE, 137 .clkreg_enable = MCI_ST_UX500_HWFCEN, 138 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 139 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 140 .datalength_bits = 24, 141 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 142 .st_sdio = true, 143 .st_clkdiv = true, 144 .pwrreg_powerup = MCI_PWR_ON, 145 .f_max = 100000000, 146 .signal_direction = true, 147 .pwrreg_clkgate = true, 148 .busy_detect = true, 149 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 150 .busy_detect_flag = MCI_ST_CARDBUSY, 151 .busy_detect_mask = MCI_ST_BUSYENDMASK, 152 .pwrreg_nopower = true, 153 .mmcimask1 = true, 154 .start_err = MCI_STARTBITERR, 155 .opendrain = MCI_OD, 156 .init = mmci_variant_init, 157 }; 158 159 static struct variant_data variant_ux500v2 = { 160 .fifosize = 30 * 4, 161 .fifohalfsize = 8 * 4, 162 .clkreg = MCI_CLK_ENABLE, 163 .clkreg_enable = MCI_ST_UX500_HWFCEN, 164 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 165 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 166 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 167 .datalength_bits = 24, 168 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 169 .st_sdio = true, 170 .st_clkdiv = true, 171 .blksz_datactrl16 = true, 172 .pwrreg_powerup = MCI_PWR_ON, 173 .f_max = 100000000, 174 .signal_direction = true, 175 .pwrreg_clkgate = true, 176 .busy_detect = true, 177 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 178 .busy_detect_flag = MCI_ST_CARDBUSY, 179 .busy_detect_mask = MCI_ST_BUSYENDMASK, 180 .pwrreg_nopower = true, 181 .mmcimask1 = true, 182 .start_err = MCI_STARTBITERR, 183 .opendrain = MCI_OD, 184 .init = mmci_variant_init, 185 }; 186 187 static struct variant_data variant_stm32 = { 188 .fifosize = 32 * 4, 189 .fifohalfsize = 8 * 4, 190 .clkreg = MCI_CLK_ENABLE, 191 .clkreg_enable = MCI_ST_UX500_HWFCEN, 192 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 193 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 194 .datalength_bits = 24, 195 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 196 .st_sdio = true, 197 .st_clkdiv = true, 198 .pwrreg_powerup = MCI_PWR_ON, 199 .f_max = 48000000, 200 .pwrreg_clkgate = true, 201 .pwrreg_nopower = true, 202 .init = mmci_variant_init, 203 }; 204 205 static struct variant_data variant_qcom = { 206 .fifosize = 16 * 4, 207 .fifohalfsize = 8 * 4, 208 .clkreg = MCI_CLK_ENABLE, 209 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 210 MCI_QCOM_CLK_SELECT_IN_FBCLK, 211 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 212 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 213 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 214 .blksz_datactrl4 = true, 215 .datalength_bits = 24, 216 .pwrreg_powerup = MCI_PWR_UP, 217 .f_max = 208000000, 218 .explicit_mclk_control = true, 219 .qcom_fifo = true, 220 .qcom_dml = true, 221 .mmcimask1 = true, 222 .start_err = MCI_STARTBITERR, 223 .opendrain = MCI_ROD, 224 .init = qcom_variant_init, 225 }; 226 227 /* Busy detection for the ST Micro variant */ 228 static int mmci_card_busy(struct mmc_host *mmc) 229 { 230 struct mmci_host *host = mmc_priv(mmc); 231 unsigned long flags; 232 int busy = 0; 233 234 spin_lock_irqsave(&host->lock, flags); 235 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 236 busy = 1; 237 spin_unlock_irqrestore(&host->lock, flags); 238 239 return busy; 240 } 241 242 /* 243 * Validate mmc prerequisites 244 */ 245 static int mmci_validate_data(struct mmci_host *host, 246 struct mmc_data *data) 247 { 248 if (!data) 249 return 0; 250 251 if (!is_power_of_2(data->blksz)) { 252 dev_err(mmc_dev(host->mmc), 253 "unsupported block size (%d bytes)\n", data->blksz); 254 return -EINVAL; 255 } 256 257 return 0; 258 } 259 260 static void mmci_reg_delay(struct mmci_host *host) 261 { 262 /* 263 * According to the spec, at least three feedback clock cycles 264 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 265 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 266 * Worst delay time during card init is at 100 kHz => 30 us. 267 * Worst delay time when up and running is at 25 MHz => 120 ns. 268 */ 269 if (host->cclk < 25000000) 270 udelay(30); 271 else 272 ndelay(120); 273 } 274 275 /* 276 * This must be called with host->lock held 277 */ 278 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 279 { 280 if (host->clk_reg != clk) { 281 host->clk_reg = clk; 282 writel(clk, host->base + MMCICLOCK); 283 } 284 } 285 286 /* 287 * This must be called with host->lock held 288 */ 289 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 290 { 291 if (host->pwr_reg != pwr) { 292 host->pwr_reg = pwr; 293 writel(pwr, host->base + MMCIPOWER); 294 } 295 } 296 297 /* 298 * This must be called with host->lock held 299 */ 300 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 301 { 302 /* Keep busy mode in DPSM if enabled */ 303 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 304 305 if (host->datactrl_reg != datactrl) { 306 host->datactrl_reg = datactrl; 307 writel(datactrl, host->base + MMCIDATACTRL); 308 } 309 } 310 311 /* 312 * This must be called with host->lock held 313 */ 314 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 315 { 316 struct variant_data *variant = host->variant; 317 u32 clk = variant->clkreg; 318 319 /* Make sure cclk reflects the current calculated clock */ 320 host->cclk = 0; 321 322 if (desired) { 323 if (variant->explicit_mclk_control) { 324 host->cclk = host->mclk; 325 } else if (desired >= host->mclk) { 326 clk = MCI_CLK_BYPASS; 327 if (variant->st_clkdiv) 328 clk |= MCI_ST_UX500_NEG_EDGE; 329 host->cclk = host->mclk; 330 } else if (variant->st_clkdiv) { 331 /* 332 * DB8500 TRM says f = mclk / (clkdiv + 2) 333 * => clkdiv = (mclk / f) - 2 334 * Round the divider up so we don't exceed the max 335 * frequency 336 */ 337 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 338 if (clk >= 256) 339 clk = 255; 340 host->cclk = host->mclk / (clk + 2); 341 } else { 342 /* 343 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 344 * => clkdiv = mclk / (2 * f) - 1 345 */ 346 clk = host->mclk / (2 * desired) - 1; 347 if (clk >= 256) 348 clk = 255; 349 host->cclk = host->mclk / (2 * (clk + 1)); 350 } 351 352 clk |= variant->clkreg_enable; 353 clk |= MCI_CLK_ENABLE; 354 /* This hasn't proven to be worthwhile */ 355 /* clk |= MCI_CLK_PWRSAVE; */ 356 } 357 358 /* Set actual clock for debug */ 359 host->mmc->actual_clock = host->cclk; 360 361 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 362 clk |= MCI_4BIT_BUS; 363 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 364 clk |= variant->clkreg_8bit_bus_enable; 365 366 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 367 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 368 clk |= variant->clkreg_neg_edge_enable; 369 370 mmci_write_clkreg(host, clk); 371 } 372 373 void mmci_dma_release(struct mmci_host *host) 374 { 375 if (host->ops && host->ops->dma_release) 376 host->ops->dma_release(host); 377 378 host->use_dma = false; 379 } 380 381 void mmci_dma_setup(struct mmci_host *host) 382 { 383 if (!host->ops || !host->ops->dma_setup) 384 return; 385 386 if (host->ops->dma_setup(host)) 387 return; 388 389 /* initialize pre request cookie */ 390 host->next_cookie = 1; 391 392 host->use_dma = true; 393 } 394 395 static void 396 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 397 { 398 writel(0, host->base + MMCICOMMAND); 399 400 BUG_ON(host->data); 401 402 host->mrq = NULL; 403 host->cmd = NULL; 404 405 mmc_request_done(host->mmc, mrq); 406 } 407 408 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 409 { 410 void __iomem *base = host->base; 411 struct variant_data *variant = host->variant; 412 413 if (host->singleirq) { 414 unsigned int mask0 = readl(base + MMCIMASK0); 415 416 mask0 &= ~MCI_IRQ1MASK; 417 mask0 |= mask; 418 419 writel(mask0, base + MMCIMASK0); 420 } 421 422 if (variant->mmcimask1) 423 writel(mask, base + MMCIMASK1); 424 425 host->mask1_reg = mask; 426 } 427 428 static void mmci_stop_data(struct mmci_host *host) 429 { 430 mmci_write_datactrlreg(host, 0); 431 mmci_set_mask1(host, 0); 432 host->data = NULL; 433 } 434 435 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 436 { 437 unsigned int flags = SG_MITER_ATOMIC; 438 439 if (data->flags & MMC_DATA_READ) 440 flags |= SG_MITER_TO_SG; 441 else 442 flags |= SG_MITER_FROM_SG; 443 444 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 445 } 446 447 /* 448 * All the DMA operation mode stuff goes inside this ifdef. 449 * This assumes that you have a generic DMA device interface, 450 * no custom DMA interfaces are supported. 451 */ 452 #ifdef CONFIG_DMA_ENGINE 453 struct mmci_dmae_next { 454 struct dma_async_tx_descriptor *desc; 455 struct dma_chan *chan; 456 }; 457 458 struct mmci_dmae_priv { 459 struct dma_chan *cur; 460 struct dma_chan *rx_channel; 461 struct dma_chan *tx_channel; 462 struct dma_async_tx_descriptor *desc_current; 463 struct mmci_dmae_next next_data; 464 }; 465 466 int mmci_dmae_setup(struct mmci_host *host) 467 { 468 const char *rxname, *txname; 469 struct mmci_dmae_priv *dmae; 470 471 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 472 if (!dmae) 473 return -ENOMEM; 474 475 host->dma_priv = dmae; 476 477 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 478 "rx"); 479 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 480 "tx"); 481 482 /* 483 * If only an RX channel is specified, the driver will 484 * attempt to use it bidirectionally, however if it is 485 * is specified but cannot be located, DMA will be disabled. 486 */ 487 if (dmae->rx_channel && !dmae->tx_channel) 488 dmae->tx_channel = dmae->rx_channel; 489 490 if (dmae->rx_channel) 491 rxname = dma_chan_name(dmae->rx_channel); 492 else 493 rxname = "none"; 494 495 if (dmae->tx_channel) 496 txname = dma_chan_name(dmae->tx_channel); 497 else 498 txname = "none"; 499 500 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 501 rxname, txname); 502 503 /* 504 * Limit the maximum segment size in any SG entry according to 505 * the parameters of the DMA engine device. 506 */ 507 if (dmae->tx_channel) { 508 struct device *dev = dmae->tx_channel->device->dev; 509 unsigned int max_seg_size = dma_get_max_seg_size(dev); 510 511 if (max_seg_size < host->mmc->max_seg_size) 512 host->mmc->max_seg_size = max_seg_size; 513 } 514 if (dmae->rx_channel) { 515 struct device *dev = dmae->rx_channel->device->dev; 516 unsigned int max_seg_size = dma_get_max_seg_size(dev); 517 518 if (max_seg_size < host->mmc->max_seg_size) 519 host->mmc->max_seg_size = max_seg_size; 520 } 521 522 if (!dmae->tx_channel || !dmae->rx_channel) { 523 mmci_dmae_release(host); 524 return -EINVAL; 525 } 526 527 return 0; 528 } 529 530 /* 531 * This is used in or so inline it 532 * so it can be discarded. 533 */ 534 void mmci_dmae_release(struct mmci_host *host) 535 { 536 struct mmci_dmae_priv *dmae = host->dma_priv; 537 538 if (dmae->rx_channel) 539 dma_release_channel(dmae->rx_channel); 540 if (dmae->tx_channel) 541 dma_release_channel(dmae->tx_channel); 542 dmae->rx_channel = dmae->tx_channel = NULL; 543 } 544 545 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 546 { 547 struct mmci_dmae_priv *dmae = host->dma_priv; 548 struct dma_chan *chan; 549 550 if (data->flags & MMC_DATA_READ) 551 chan = dmae->rx_channel; 552 else 553 chan = dmae->tx_channel; 554 555 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 556 mmc_get_dma_dir(data)); 557 } 558 559 static void mmci_dma_data_error(struct mmci_host *host) 560 { 561 struct mmci_dmae_priv *dmae = host->dma_priv; 562 563 if (!host->use_dma || !dma_inprogress(host)) 564 return; 565 566 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 567 dmaengine_terminate_all(dmae->cur); 568 host->dma_in_progress = false; 569 dmae->cur = NULL; 570 dmae->desc_current = NULL; 571 host->data->host_cookie = 0; 572 573 mmci_dma_unmap(host, host->data); 574 } 575 576 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 577 { 578 struct mmci_dmae_priv *dmae = host->dma_priv; 579 u32 status; 580 int i; 581 582 if (!host->use_dma || !dma_inprogress(host)) 583 return; 584 585 /* Wait up to 1ms for the DMA to complete */ 586 for (i = 0; ; i++) { 587 status = readl(host->base + MMCISTATUS); 588 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 589 break; 590 udelay(10); 591 } 592 593 /* 594 * Check to see whether we still have some data left in the FIFO - 595 * this catches DMA controllers which are unable to monitor the 596 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 597 * contiguous buffers. On TX, we'll get a FIFO underrun error. 598 */ 599 if (status & MCI_RXDATAAVLBLMASK) { 600 mmci_dma_data_error(host); 601 if (!data->error) 602 data->error = -EIO; 603 } else if (!data->host_cookie) { 604 mmci_dma_unmap(host, data); 605 } 606 607 /* 608 * Use of DMA with scatter-gather is impossible. 609 * Give up with DMA and switch back to PIO mode. 610 */ 611 if (status & MCI_RXDATAAVLBLMASK) { 612 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 613 mmci_dma_release(host); 614 } 615 616 host->dma_in_progress = false; 617 dmae->cur = NULL; 618 dmae->desc_current = NULL; 619 } 620 621 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 622 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 623 struct dma_chan **dma_chan, 624 struct dma_async_tx_descriptor **dma_desc) 625 { 626 struct mmci_dmae_priv *dmae = host->dma_priv; 627 struct variant_data *variant = host->variant; 628 struct dma_slave_config conf = { 629 .src_addr = host->phybase + MMCIFIFO, 630 .dst_addr = host->phybase + MMCIFIFO, 631 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 632 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 633 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 634 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 635 .device_fc = false, 636 }; 637 struct dma_chan *chan; 638 struct dma_device *device; 639 struct dma_async_tx_descriptor *desc; 640 int nr_sg; 641 unsigned long flags = DMA_CTRL_ACK; 642 643 if (data->flags & MMC_DATA_READ) { 644 conf.direction = DMA_DEV_TO_MEM; 645 chan = dmae->rx_channel; 646 } else { 647 conf.direction = DMA_MEM_TO_DEV; 648 chan = dmae->tx_channel; 649 } 650 651 /* If there's no DMA channel, fall back to PIO */ 652 if (!chan) 653 return -EINVAL; 654 655 /* If less than or equal to the fifo size, don't bother with DMA */ 656 if (data->blksz * data->blocks <= variant->fifosize) 657 return -EINVAL; 658 659 device = chan->device; 660 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 661 mmc_get_dma_dir(data)); 662 if (nr_sg == 0) 663 return -EINVAL; 664 665 if (host->variant->qcom_dml) 666 flags |= DMA_PREP_INTERRUPT; 667 668 dmaengine_slave_config(chan, &conf); 669 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 670 conf.direction, flags); 671 if (!desc) 672 goto unmap_exit; 673 674 *dma_chan = chan; 675 *dma_desc = desc; 676 677 return 0; 678 679 unmap_exit: 680 dma_unmap_sg(device->dev, data->sg, data->sg_len, 681 mmc_get_dma_dir(data)); 682 return -ENOMEM; 683 } 684 685 static inline int mmci_dma_prep_data(struct mmci_host *host, 686 struct mmc_data *data, 687 bool next) 688 { 689 struct mmci_dmae_priv *dmae = host->dma_priv; 690 struct mmci_dmae_next *nd = &dmae->next_data; 691 692 if (next) 693 return __mmci_dma_prep_data(host, data, &nd->chan, &nd->desc); 694 /* Check if next job is already prepared. */ 695 if (dmae->cur && dmae->desc_current) 696 return 0; 697 698 /* No job were prepared thus do it now. */ 699 return __mmci_dma_prep_data(host, data, &dmae->cur, 700 &dmae->desc_current); 701 } 702 703 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 704 { 705 int ret; 706 struct mmci_dmae_priv *dmae = host->dma_priv; 707 struct mmc_data *data = host->data; 708 709 if (!host->use_dma) 710 return -EINVAL; 711 712 ret = mmci_dma_prep_data(host, host->data, false); 713 if (ret) 714 return ret; 715 716 /* Okay, go for it. */ 717 dev_vdbg(mmc_dev(host->mmc), 718 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 719 data->sg_len, data->blksz, data->blocks, data->flags); 720 host->dma_in_progress = true; 721 dmaengine_submit(dmae->desc_current); 722 dma_async_issue_pending(dmae->cur); 723 724 if (host->variant->qcom_dml) 725 dml_start_xfer(host, data); 726 727 datactrl |= MCI_DPSM_DMAENABLE; 728 729 /* Trigger the DMA transfer */ 730 mmci_write_datactrlreg(host, datactrl); 731 732 /* 733 * Let the MMCI say when the data is ended and it's time 734 * to fire next DMA request. When that happens, MMCI will 735 * call mmci_data_end() 736 */ 737 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 738 host->base + MMCIMASK0); 739 return 0; 740 } 741 742 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 743 { 744 struct mmci_dmae_priv *dmae = host->dma_priv; 745 struct mmci_dmae_next *next = &dmae->next_data; 746 747 if (!host->use_dma) 748 return; 749 750 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 751 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 752 753 dmae->desc_current = next->desc; 754 dmae->cur = next->chan; 755 next->desc = NULL; 756 next->chan = NULL; 757 } 758 759 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 760 { 761 struct mmci_host *host = mmc_priv(mmc); 762 struct mmc_data *data = mrq->data; 763 764 if (!host->use_dma || !data) 765 return; 766 767 BUG_ON(data->host_cookie); 768 769 if (mmci_validate_data(host, data)) 770 return; 771 772 if (!mmci_dma_prep_data(host, data, true)) 773 data->host_cookie = ++host->next_cookie < 0 ? 774 1 : host->next_cookie; 775 } 776 777 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 778 int err) 779 { 780 struct mmci_host *host = mmc_priv(mmc); 781 struct mmci_dmae_priv *dmae = host->dma_priv; 782 struct mmc_data *data = mrq->data; 783 784 if (!host->use_dma || !data || !data->host_cookie) 785 return; 786 787 mmci_dma_unmap(host, data); 788 789 if (err) { 790 struct mmci_dmae_next *next = &dmae->next_data; 791 struct dma_chan *chan; 792 if (data->flags & MMC_DATA_READ) 793 chan = dmae->rx_channel; 794 else 795 chan = dmae->tx_channel; 796 dmaengine_terminate_all(chan); 797 798 if (dmae->desc_current == next->desc) 799 dmae->desc_current = NULL; 800 801 if (dmae->cur == next->chan) { 802 host->dma_in_progress = false; 803 dmae->cur = NULL; 804 } 805 806 next->desc = NULL; 807 next->chan = NULL; 808 data->host_cookie = 0; 809 } 810 } 811 812 static struct mmci_host_ops mmci_variant_ops = { 813 .dma_setup = mmci_dmae_setup, 814 .dma_release = mmci_dmae_release, 815 }; 816 817 void mmci_variant_init(struct mmci_host *host) 818 { 819 host->ops = &mmci_variant_ops; 820 } 821 #else 822 /* Blank functions if the DMA engine is not available */ 823 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 824 { 825 } 826 827 static inline void mmci_dma_finalize(struct mmci_host *host, 828 struct mmc_data *data) 829 { 830 } 831 832 static inline void mmci_dma_data_error(struct mmci_host *host) 833 { 834 } 835 836 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 837 { 838 return -ENOSYS; 839 } 840 841 #define mmci_pre_request NULL 842 #define mmci_post_request NULL 843 844 #endif 845 846 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 847 { 848 struct variant_data *variant = host->variant; 849 unsigned int datactrl, timeout, irqmask; 850 unsigned long long clks; 851 void __iomem *base; 852 int blksz_bits; 853 854 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 855 data->blksz, data->blocks, data->flags); 856 857 host->data = data; 858 host->size = data->blksz * data->blocks; 859 data->bytes_xfered = 0; 860 861 clks = (unsigned long long)data->timeout_ns * host->cclk; 862 do_div(clks, NSEC_PER_SEC); 863 864 timeout = data->timeout_clks + (unsigned int)clks; 865 866 base = host->base; 867 writel(timeout, base + MMCIDATATIMER); 868 writel(host->size, base + MMCIDATALENGTH); 869 870 blksz_bits = ffs(data->blksz) - 1; 871 BUG_ON(1 << blksz_bits != data->blksz); 872 873 if (variant->blksz_datactrl16) 874 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 875 else if (variant->blksz_datactrl4) 876 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 877 else 878 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 879 880 if (data->flags & MMC_DATA_READ) 881 datactrl |= MCI_DPSM_DIRECTION; 882 883 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 884 u32 clk; 885 886 datactrl |= variant->datactrl_mask_sdio; 887 888 /* 889 * The ST Micro variant for SDIO small write transfers 890 * needs to have clock H/W flow control disabled, 891 * otherwise the transfer will not start. The threshold 892 * depends on the rate of MCLK. 893 */ 894 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 895 (host->size < 8 || 896 (host->size <= 8 && host->mclk > 50000000))) 897 clk = host->clk_reg & ~variant->clkreg_enable; 898 else 899 clk = host->clk_reg | variant->clkreg_enable; 900 901 mmci_write_clkreg(host, clk); 902 } 903 904 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 905 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 906 datactrl |= variant->datactrl_mask_ddrmode; 907 908 /* 909 * Attempt to use DMA operation mode, if this 910 * should fail, fall back to PIO mode 911 */ 912 if (!mmci_dma_start_data(host, datactrl)) 913 return; 914 915 /* IRQ mode, map the SG list for CPU reading/writing */ 916 mmci_init_sg(host, data); 917 918 if (data->flags & MMC_DATA_READ) { 919 irqmask = MCI_RXFIFOHALFFULLMASK; 920 921 /* 922 * If we have less than the fifo 'half-full' threshold to 923 * transfer, trigger a PIO interrupt as soon as any data 924 * is available. 925 */ 926 if (host->size < variant->fifohalfsize) 927 irqmask |= MCI_RXDATAAVLBLMASK; 928 } else { 929 /* 930 * We don't actually need to include "FIFO empty" here 931 * since its implicit in "FIFO half empty". 932 */ 933 irqmask = MCI_TXFIFOHALFEMPTYMASK; 934 } 935 936 mmci_write_datactrlreg(host, datactrl); 937 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 938 mmci_set_mask1(host, irqmask); 939 } 940 941 static void 942 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 943 { 944 void __iomem *base = host->base; 945 946 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 947 cmd->opcode, cmd->arg, cmd->flags); 948 949 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 950 writel(0, base + MMCICOMMAND); 951 mmci_reg_delay(host); 952 } 953 954 c |= cmd->opcode | MCI_CPSM_ENABLE; 955 if (cmd->flags & MMC_RSP_PRESENT) { 956 if (cmd->flags & MMC_RSP_136) 957 c |= MCI_CPSM_LONGRSP; 958 c |= MCI_CPSM_RESPONSE; 959 } 960 if (/*interrupt*/0) 961 c |= MCI_CPSM_INTERRUPT; 962 963 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 964 c |= host->variant->data_cmd_enable; 965 966 host->cmd = cmd; 967 968 writel(cmd->arg, base + MMCIARGUMENT); 969 writel(c, base + MMCICOMMAND); 970 } 971 972 static void 973 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 974 unsigned int status) 975 { 976 /* Make sure we have data to handle */ 977 if (!data) 978 return; 979 980 /* First check for errors */ 981 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT | 982 host->variant->start_err | 983 MCI_TXUNDERRUN | MCI_RXOVERRUN)) { 984 u32 remain, success; 985 986 /* Terminate the DMA transfer */ 987 mmci_dma_data_error(host); 988 989 /* 990 * Calculate how far we are into the transfer. Note that 991 * the data counter gives the number of bytes transferred 992 * on the MMC bus, not on the host side. On reads, this 993 * can be as much as a FIFO-worth of data ahead. This 994 * matters for FIFO overruns only. 995 */ 996 remain = readl(host->base + MMCIDATACNT); 997 success = data->blksz * data->blocks - remain; 998 999 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1000 status, success); 1001 if (status & MCI_DATACRCFAIL) { 1002 /* Last block was not successful */ 1003 success -= 1; 1004 data->error = -EILSEQ; 1005 } else if (status & MCI_DATATIMEOUT) { 1006 data->error = -ETIMEDOUT; 1007 } else if (status & MCI_STARTBITERR) { 1008 data->error = -ECOMM; 1009 } else if (status & MCI_TXUNDERRUN) { 1010 data->error = -EIO; 1011 } else if (status & MCI_RXOVERRUN) { 1012 if (success > host->variant->fifosize) 1013 success -= host->variant->fifosize; 1014 else 1015 success = 0; 1016 data->error = -EIO; 1017 } 1018 data->bytes_xfered = round_down(success, data->blksz); 1019 } 1020 1021 if (status & MCI_DATABLOCKEND) 1022 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1023 1024 if (status & MCI_DATAEND || data->error) { 1025 mmci_dma_finalize(host, data); 1026 1027 mmci_stop_data(host); 1028 1029 if (!data->error) 1030 /* The error clause is handled above, success! */ 1031 data->bytes_xfered = data->blksz * data->blocks; 1032 1033 if (!data->stop || host->mrq->sbc) { 1034 mmci_request_end(host, data->mrq); 1035 } else { 1036 mmci_start_command(host, data->stop, 0); 1037 } 1038 } 1039 } 1040 1041 static void 1042 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1043 unsigned int status) 1044 { 1045 void __iomem *base = host->base; 1046 bool sbc; 1047 1048 if (!cmd) 1049 return; 1050 1051 sbc = (cmd == host->mrq->sbc); 1052 1053 /* 1054 * We need to be one of these interrupts to be considered worth 1055 * handling. Note that we tag on any latent IRQs postponed 1056 * due to waiting for busy status. 1057 */ 1058 if (!((status|host->busy_status) & 1059 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1060 return; 1061 1062 /* 1063 * ST Micro variant: handle busy detection. 1064 */ 1065 if (host->variant->busy_detect) { 1066 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1067 1068 /* We are busy with a command, return */ 1069 if (host->busy_status && 1070 (status & host->variant->busy_detect_flag)) 1071 return; 1072 1073 /* 1074 * We were not busy, but we now got a busy response on 1075 * something that was not an error, and we double-check 1076 * that the special busy status bit is still set before 1077 * proceeding. 1078 */ 1079 if (!host->busy_status && busy_resp && 1080 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1081 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1082 1083 /* Clear the busy start IRQ */ 1084 writel(host->variant->busy_detect_mask, 1085 host->base + MMCICLEAR); 1086 1087 /* Unmask the busy end IRQ */ 1088 writel(readl(base + MMCIMASK0) | 1089 host->variant->busy_detect_mask, 1090 base + MMCIMASK0); 1091 /* 1092 * Now cache the last response status code (until 1093 * the busy bit goes low), and return. 1094 */ 1095 host->busy_status = 1096 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1097 return; 1098 } 1099 1100 /* 1101 * At this point we are not busy with a command, we have 1102 * not received a new busy request, clear and mask the busy 1103 * end IRQ and fall through to process the IRQ. 1104 */ 1105 if (host->busy_status) { 1106 1107 writel(host->variant->busy_detect_mask, 1108 host->base + MMCICLEAR); 1109 1110 writel(readl(base + MMCIMASK0) & 1111 ~host->variant->busy_detect_mask, 1112 base + MMCIMASK0); 1113 host->busy_status = 0; 1114 } 1115 } 1116 1117 host->cmd = NULL; 1118 1119 if (status & MCI_CMDTIMEOUT) { 1120 cmd->error = -ETIMEDOUT; 1121 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1122 cmd->error = -EILSEQ; 1123 } else { 1124 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1125 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1126 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1127 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1128 } 1129 1130 if ((!sbc && !cmd->data) || cmd->error) { 1131 if (host->data) { 1132 /* Terminate the DMA transfer */ 1133 mmci_dma_data_error(host); 1134 1135 mmci_stop_data(host); 1136 } 1137 mmci_request_end(host, host->mrq); 1138 } else if (sbc) { 1139 mmci_start_command(host, host->mrq->cmd, 0); 1140 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 1141 mmci_start_data(host, cmd->data); 1142 } 1143 } 1144 1145 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1146 { 1147 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1148 } 1149 1150 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1151 { 1152 /* 1153 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1154 * from the fifo range should be used 1155 */ 1156 if (status & MCI_RXFIFOHALFFULL) 1157 return host->variant->fifohalfsize; 1158 else if (status & MCI_RXDATAAVLBL) 1159 return 4; 1160 1161 return 0; 1162 } 1163 1164 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1165 { 1166 void __iomem *base = host->base; 1167 char *ptr = buffer; 1168 u32 status = readl(host->base + MMCISTATUS); 1169 int host_remain = host->size; 1170 1171 do { 1172 int count = host->get_rx_fifocnt(host, status, host_remain); 1173 1174 if (count > remain) 1175 count = remain; 1176 1177 if (count <= 0) 1178 break; 1179 1180 /* 1181 * SDIO especially may want to send something that is 1182 * not divisible by 4 (as opposed to card sectors 1183 * etc). Therefore make sure to always read the last bytes 1184 * while only doing full 32-bit reads towards the FIFO. 1185 */ 1186 if (unlikely(count & 0x3)) { 1187 if (count < 4) { 1188 unsigned char buf[4]; 1189 ioread32_rep(base + MMCIFIFO, buf, 1); 1190 memcpy(ptr, buf, count); 1191 } else { 1192 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1193 count &= ~0x3; 1194 } 1195 } else { 1196 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1197 } 1198 1199 ptr += count; 1200 remain -= count; 1201 host_remain -= count; 1202 1203 if (remain == 0) 1204 break; 1205 1206 status = readl(base + MMCISTATUS); 1207 } while (status & MCI_RXDATAAVLBL); 1208 1209 return ptr - buffer; 1210 } 1211 1212 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1213 { 1214 struct variant_data *variant = host->variant; 1215 void __iomem *base = host->base; 1216 char *ptr = buffer; 1217 1218 do { 1219 unsigned int count, maxcnt; 1220 1221 maxcnt = status & MCI_TXFIFOEMPTY ? 1222 variant->fifosize : variant->fifohalfsize; 1223 count = min(remain, maxcnt); 1224 1225 /* 1226 * SDIO especially may want to send something that is 1227 * not divisible by 4 (as opposed to card sectors 1228 * etc), and the FIFO only accept full 32-bit writes. 1229 * So compensate by adding +3 on the count, a single 1230 * byte become a 32bit write, 7 bytes will be two 1231 * 32bit writes etc. 1232 */ 1233 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1234 1235 ptr += count; 1236 remain -= count; 1237 1238 if (remain == 0) 1239 break; 1240 1241 status = readl(base + MMCISTATUS); 1242 } while (status & MCI_TXFIFOHALFEMPTY); 1243 1244 return ptr - buffer; 1245 } 1246 1247 /* 1248 * PIO data transfer IRQ handler. 1249 */ 1250 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1251 { 1252 struct mmci_host *host = dev_id; 1253 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1254 struct variant_data *variant = host->variant; 1255 void __iomem *base = host->base; 1256 u32 status; 1257 1258 status = readl(base + MMCISTATUS); 1259 1260 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1261 1262 do { 1263 unsigned int remain, len; 1264 char *buffer; 1265 1266 /* 1267 * For write, we only need to test the half-empty flag 1268 * here - if the FIFO is completely empty, then by 1269 * definition it is more than half empty. 1270 * 1271 * For read, check for data available. 1272 */ 1273 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1274 break; 1275 1276 if (!sg_miter_next(sg_miter)) 1277 break; 1278 1279 buffer = sg_miter->addr; 1280 remain = sg_miter->length; 1281 1282 len = 0; 1283 if (status & MCI_RXACTIVE) 1284 len = mmci_pio_read(host, buffer, remain); 1285 if (status & MCI_TXACTIVE) 1286 len = mmci_pio_write(host, buffer, remain, status); 1287 1288 sg_miter->consumed = len; 1289 1290 host->size -= len; 1291 remain -= len; 1292 1293 if (remain) 1294 break; 1295 1296 status = readl(base + MMCISTATUS); 1297 } while (1); 1298 1299 sg_miter_stop(sg_miter); 1300 1301 /* 1302 * If we have less than the fifo 'half-full' threshold to transfer, 1303 * trigger a PIO interrupt as soon as any data is available. 1304 */ 1305 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1306 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1307 1308 /* 1309 * If we run out of data, disable the data IRQs; this 1310 * prevents a race where the FIFO becomes empty before 1311 * the chip itself has disabled the data path, and 1312 * stops us racing with our data end IRQ. 1313 */ 1314 if (host->size == 0) { 1315 mmci_set_mask1(host, 0); 1316 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1317 } 1318 1319 return IRQ_HANDLED; 1320 } 1321 1322 /* 1323 * Handle completion of command and data transfers. 1324 */ 1325 static irqreturn_t mmci_irq(int irq, void *dev_id) 1326 { 1327 struct mmci_host *host = dev_id; 1328 u32 status; 1329 int ret = 0; 1330 1331 spin_lock(&host->lock); 1332 1333 do { 1334 status = readl(host->base + MMCISTATUS); 1335 1336 if (host->singleirq) { 1337 if (status & host->mask1_reg) 1338 mmci_pio_irq(irq, dev_id); 1339 1340 status &= ~MCI_IRQ1MASK; 1341 } 1342 1343 /* 1344 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1345 * enabled) in mmci_cmd_irq() function where ST Micro busy 1346 * detection variant is handled. Considering the HW seems to be 1347 * triggering the IRQ on both edges while monitoring DAT0 for 1348 * busy completion and that same status bit is used to monitor 1349 * start and end of busy detection, special care must be taken 1350 * to make sure that both start and end interrupts are always 1351 * cleared one after the other. 1352 */ 1353 status &= readl(host->base + MMCIMASK0); 1354 if (host->variant->busy_detect) 1355 writel(status & ~host->variant->busy_detect_mask, 1356 host->base + MMCICLEAR); 1357 else 1358 writel(status, host->base + MMCICLEAR); 1359 1360 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1361 1362 if (host->variant->reversed_irq_handling) { 1363 mmci_data_irq(host, host->data, status); 1364 mmci_cmd_irq(host, host->cmd, status); 1365 } else { 1366 mmci_cmd_irq(host, host->cmd, status); 1367 mmci_data_irq(host, host->data, status); 1368 } 1369 1370 /* 1371 * Don't poll for busy completion in irq context. 1372 */ 1373 if (host->variant->busy_detect && host->busy_status) 1374 status &= ~host->variant->busy_detect_flag; 1375 1376 ret = 1; 1377 } while (status); 1378 1379 spin_unlock(&host->lock); 1380 1381 return IRQ_RETVAL(ret); 1382 } 1383 1384 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1385 { 1386 struct mmci_host *host = mmc_priv(mmc); 1387 unsigned long flags; 1388 1389 WARN_ON(host->mrq != NULL); 1390 1391 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1392 if (mrq->cmd->error) { 1393 mmc_request_done(mmc, mrq); 1394 return; 1395 } 1396 1397 spin_lock_irqsave(&host->lock, flags); 1398 1399 host->mrq = mrq; 1400 1401 if (mrq->data) 1402 mmci_get_next_data(host, mrq->data); 1403 1404 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1405 mmci_start_data(host, mrq->data); 1406 1407 if (mrq->sbc) 1408 mmci_start_command(host, mrq->sbc, 0); 1409 else 1410 mmci_start_command(host, mrq->cmd, 0); 1411 1412 spin_unlock_irqrestore(&host->lock, flags); 1413 } 1414 1415 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1416 { 1417 struct mmci_host *host = mmc_priv(mmc); 1418 struct variant_data *variant = host->variant; 1419 u32 pwr = 0; 1420 unsigned long flags; 1421 int ret; 1422 1423 if (host->plat->ios_handler && 1424 host->plat->ios_handler(mmc_dev(mmc), ios)) 1425 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1426 1427 switch (ios->power_mode) { 1428 case MMC_POWER_OFF: 1429 if (!IS_ERR(mmc->supply.vmmc)) 1430 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1431 1432 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1433 regulator_disable(mmc->supply.vqmmc); 1434 host->vqmmc_enabled = false; 1435 } 1436 1437 break; 1438 case MMC_POWER_UP: 1439 if (!IS_ERR(mmc->supply.vmmc)) 1440 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1441 1442 /* 1443 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1444 * and instead uses MCI_PWR_ON so apply whatever value is 1445 * configured in the variant data. 1446 */ 1447 pwr |= variant->pwrreg_powerup; 1448 1449 break; 1450 case MMC_POWER_ON: 1451 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1452 ret = regulator_enable(mmc->supply.vqmmc); 1453 if (ret < 0) 1454 dev_err(mmc_dev(mmc), 1455 "failed to enable vqmmc regulator\n"); 1456 else 1457 host->vqmmc_enabled = true; 1458 } 1459 1460 pwr |= MCI_PWR_ON; 1461 break; 1462 } 1463 1464 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1465 /* 1466 * The ST Micro variant has some additional bits 1467 * indicating signal direction for the signals in 1468 * the SD/MMC bus and feedback-clock usage. 1469 */ 1470 pwr |= host->pwr_reg_add; 1471 1472 if (ios->bus_width == MMC_BUS_WIDTH_4) 1473 pwr &= ~MCI_ST_DATA74DIREN; 1474 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1475 pwr &= (~MCI_ST_DATA74DIREN & 1476 ~MCI_ST_DATA31DIREN & 1477 ~MCI_ST_DATA2DIREN); 1478 } 1479 1480 if (variant->opendrain) { 1481 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1482 pwr |= variant->opendrain; 1483 } else { 1484 /* 1485 * If the variant cannot configure the pads by its own, then we 1486 * expect the pinctrl to be able to do that for us 1487 */ 1488 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1489 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1490 else 1491 pinctrl_select_state(host->pinctrl, host->pins_default); 1492 } 1493 1494 /* 1495 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1496 * gating the clock, the MCI_PWR_ON bit is cleared. 1497 */ 1498 if (!ios->clock && variant->pwrreg_clkgate) 1499 pwr &= ~MCI_PWR_ON; 1500 1501 if (host->variant->explicit_mclk_control && 1502 ios->clock != host->clock_cache) { 1503 ret = clk_set_rate(host->clk, ios->clock); 1504 if (ret < 0) 1505 dev_err(mmc_dev(host->mmc), 1506 "Error setting clock rate (%d)\n", ret); 1507 else 1508 host->mclk = clk_get_rate(host->clk); 1509 } 1510 host->clock_cache = ios->clock; 1511 1512 spin_lock_irqsave(&host->lock, flags); 1513 1514 mmci_set_clkreg(host, ios->clock); 1515 mmci_write_pwrreg(host, pwr); 1516 mmci_reg_delay(host); 1517 1518 spin_unlock_irqrestore(&host->lock, flags); 1519 } 1520 1521 static int mmci_get_cd(struct mmc_host *mmc) 1522 { 1523 struct mmci_host *host = mmc_priv(mmc); 1524 struct mmci_platform_data *plat = host->plat; 1525 unsigned int status = mmc_gpio_get_cd(mmc); 1526 1527 if (status == -ENOSYS) { 1528 if (!plat->status) 1529 return 1; /* Assume always present */ 1530 1531 status = plat->status(mmc_dev(host->mmc)); 1532 } 1533 return status; 1534 } 1535 1536 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1537 { 1538 int ret = 0; 1539 1540 if (!IS_ERR(mmc->supply.vqmmc)) { 1541 1542 switch (ios->signal_voltage) { 1543 case MMC_SIGNAL_VOLTAGE_330: 1544 ret = regulator_set_voltage(mmc->supply.vqmmc, 1545 2700000, 3600000); 1546 break; 1547 case MMC_SIGNAL_VOLTAGE_180: 1548 ret = regulator_set_voltage(mmc->supply.vqmmc, 1549 1700000, 1950000); 1550 break; 1551 case MMC_SIGNAL_VOLTAGE_120: 1552 ret = regulator_set_voltage(mmc->supply.vqmmc, 1553 1100000, 1300000); 1554 break; 1555 } 1556 1557 if (ret) 1558 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1559 } 1560 1561 return ret; 1562 } 1563 1564 static struct mmc_host_ops mmci_ops = { 1565 .request = mmci_request, 1566 .pre_req = mmci_pre_request, 1567 .post_req = mmci_post_request, 1568 .set_ios = mmci_set_ios, 1569 .get_ro = mmc_gpio_get_ro, 1570 .get_cd = mmci_get_cd, 1571 .start_signal_voltage_switch = mmci_sig_volt_switch, 1572 }; 1573 1574 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1575 { 1576 struct mmci_host *host = mmc_priv(mmc); 1577 int ret = mmc_of_parse(mmc); 1578 1579 if (ret) 1580 return ret; 1581 1582 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1583 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1584 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1585 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1586 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1587 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1588 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1589 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1590 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1591 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1592 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1593 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1594 1595 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1596 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1597 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1598 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1599 1600 return 0; 1601 } 1602 1603 static int mmci_probe(struct amba_device *dev, 1604 const struct amba_id *id) 1605 { 1606 struct mmci_platform_data *plat = dev->dev.platform_data; 1607 struct device_node *np = dev->dev.of_node; 1608 struct variant_data *variant = id->data; 1609 struct mmci_host *host; 1610 struct mmc_host *mmc; 1611 int ret; 1612 1613 /* Must have platform data or Device Tree. */ 1614 if (!plat && !np) { 1615 dev_err(&dev->dev, "No plat data or DT found\n"); 1616 return -EINVAL; 1617 } 1618 1619 if (!plat) { 1620 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1621 if (!plat) 1622 return -ENOMEM; 1623 } 1624 1625 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1626 if (!mmc) 1627 return -ENOMEM; 1628 1629 ret = mmci_of_parse(np, mmc); 1630 if (ret) 1631 goto host_free; 1632 1633 host = mmc_priv(mmc); 1634 host->mmc = mmc; 1635 1636 /* 1637 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1638 * pins can be set accordingly using pinctrl 1639 */ 1640 if (!variant->opendrain) { 1641 host->pinctrl = devm_pinctrl_get(&dev->dev); 1642 if (IS_ERR(host->pinctrl)) { 1643 dev_err(&dev->dev, "failed to get pinctrl"); 1644 ret = PTR_ERR(host->pinctrl); 1645 goto host_free; 1646 } 1647 1648 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1649 PINCTRL_STATE_DEFAULT); 1650 if (IS_ERR(host->pins_default)) { 1651 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1652 ret = PTR_ERR(host->pins_default); 1653 goto host_free; 1654 } 1655 1656 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1657 MMCI_PINCTRL_STATE_OPENDRAIN); 1658 if (IS_ERR(host->pins_opendrain)) { 1659 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1660 ret = PTR_ERR(host->pins_opendrain); 1661 goto host_free; 1662 } 1663 } 1664 1665 host->hw_designer = amba_manf(dev); 1666 host->hw_revision = amba_rev(dev); 1667 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1668 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1669 1670 host->clk = devm_clk_get(&dev->dev, NULL); 1671 if (IS_ERR(host->clk)) { 1672 ret = PTR_ERR(host->clk); 1673 goto host_free; 1674 } 1675 1676 ret = clk_prepare_enable(host->clk); 1677 if (ret) 1678 goto host_free; 1679 1680 if (variant->qcom_fifo) 1681 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1682 else 1683 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1684 1685 host->plat = plat; 1686 host->variant = variant; 1687 host->mclk = clk_get_rate(host->clk); 1688 /* 1689 * According to the spec, mclk is max 100 MHz, 1690 * so we try to adjust the clock down to this, 1691 * (if possible). 1692 */ 1693 if (host->mclk > variant->f_max) { 1694 ret = clk_set_rate(host->clk, variant->f_max); 1695 if (ret < 0) 1696 goto clk_disable; 1697 host->mclk = clk_get_rate(host->clk); 1698 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1699 host->mclk); 1700 } 1701 1702 host->phybase = dev->res.start; 1703 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1704 if (IS_ERR(host->base)) { 1705 ret = PTR_ERR(host->base); 1706 goto clk_disable; 1707 } 1708 1709 if (variant->init) 1710 variant->init(host); 1711 1712 /* 1713 * The ARM and ST versions of the block have slightly different 1714 * clock divider equations which means that the minimum divider 1715 * differs too. 1716 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1717 */ 1718 if (variant->st_clkdiv) 1719 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1720 else if (variant->explicit_mclk_control) 1721 mmc->f_min = clk_round_rate(host->clk, 100000); 1722 else 1723 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1724 /* 1725 * If no maximum operating frequency is supplied, fall back to use 1726 * the module parameter, which has a (low) default value in case it 1727 * is not specified. Either value must not exceed the clock rate into 1728 * the block, of course. 1729 */ 1730 if (mmc->f_max) 1731 mmc->f_max = variant->explicit_mclk_control ? 1732 min(variant->f_max, mmc->f_max) : 1733 min(host->mclk, mmc->f_max); 1734 else 1735 mmc->f_max = variant->explicit_mclk_control ? 1736 fmax : min(host->mclk, fmax); 1737 1738 1739 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1740 1741 /* Get regulators and the supported OCR mask */ 1742 ret = mmc_regulator_get_supply(mmc); 1743 if (ret) 1744 goto clk_disable; 1745 1746 if (!mmc->ocr_avail) 1747 mmc->ocr_avail = plat->ocr_mask; 1748 else if (plat->ocr_mask) 1749 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1750 1751 /* We support these capabilities. */ 1752 mmc->caps |= MMC_CAP_CMD23; 1753 1754 /* 1755 * Enable busy detection. 1756 */ 1757 if (variant->busy_detect) { 1758 mmci_ops.card_busy = mmci_card_busy; 1759 /* 1760 * Not all variants have a flag to enable busy detection 1761 * in the DPSM, but if they do, set it here. 1762 */ 1763 if (variant->busy_dpsm_flag) 1764 mmci_write_datactrlreg(host, 1765 host->variant->busy_dpsm_flag); 1766 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1767 mmc->max_busy_timeout = 0; 1768 } 1769 1770 mmc->ops = &mmci_ops; 1771 1772 /* We support these PM capabilities. */ 1773 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1774 1775 /* 1776 * We can do SGIO 1777 */ 1778 mmc->max_segs = NR_SG; 1779 1780 /* 1781 * Since only a certain number of bits are valid in the data length 1782 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1783 * single request. 1784 */ 1785 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1786 1787 /* 1788 * Set the maximum segment size. Since we aren't doing DMA 1789 * (yet) we are only limited by the data length register. 1790 */ 1791 mmc->max_seg_size = mmc->max_req_size; 1792 1793 /* 1794 * Block size can be up to 2048 bytes, but must be a power of two. 1795 */ 1796 mmc->max_blk_size = 1 << 11; 1797 1798 /* 1799 * Limit the number of blocks transferred so that we don't overflow 1800 * the maximum request size. 1801 */ 1802 mmc->max_blk_count = mmc->max_req_size >> 11; 1803 1804 spin_lock_init(&host->lock); 1805 1806 writel(0, host->base + MMCIMASK0); 1807 1808 if (variant->mmcimask1) 1809 writel(0, host->base + MMCIMASK1); 1810 1811 writel(0xfff, host->base + MMCICLEAR); 1812 1813 /* 1814 * If: 1815 * - not using DT but using a descriptor table, or 1816 * - using a table of descriptors ALONGSIDE DT, or 1817 * look up these descriptors named "cd" and "wp" right here, fail 1818 * silently of these do not exist 1819 */ 1820 if (!np) { 1821 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1822 if (ret == -EPROBE_DEFER) 1823 goto clk_disable; 1824 1825 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1826 if (ret == -EPROBE_DEFER) 1827 goto clk_disable; 1828 } 1829 1830 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1831 DRIVER_NAME " (cmd)", host); 1832 if (ret) 1833 goto clk_disable; 1834 1835 if (!dev->irq[1]) 1836 host->singleirq = true; 1837 else { 1838 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1839 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1840 if (ret) 1841 goto clk_disable; 1842 } 1843 1844 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1845 1846 amba_set_drvdata(dev, mmc); 1847 1848 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1849 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1850 amba_rev(dev), (unsigned long long)dev->res.start, 1851 dev->irq[0], dev->irq[1]); 1852 1853 mmci_dma_setup(host); 1854 1855 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1856 pm_runtime_use_autosuspend(&dev->dev); 1857 1858 mmc_add_host(mmc); 1859 1860 pm_runtime_put(&dev->dev); 1861 return 0; 1862 1863 clk_disable: 1864 clk_disable_unprepare(host->clk); 1865 host_free: 1866 mmc_free_host(mmc); 1867 return ret; 1868 } 1869 1870 static int mmci_remove(struct amba_device *dev) 1871 { 1872 struct mmc_host *mmc = amba_get_drvdata(dev); 1873 1874 if (mmc) { 1875 struct mmci_host *host = mmc_priv(mmc); 1876 struct variant_data *variant = host->variant; 1877 1878 /* 1879 * Undo pm_runtime_put() in probe. We use the _sync 1880 * version here so that we can access the primecell. 1881 */ 1882 pm_runtime_get_sync(&dev->dev); 1883 1884 mmc_remove_host(mmc); 1885 1886 writel(0, host->base + MMCIMASK0); 1887 1888 if (variant->mmcimask1) 1889 writel(0, host->base + MMCIMASK1); 1890 1891 writel(0, host->base + MMCICOMMAND); 1892 writel(0, host->base + MMCIDATACTRL); 1893 1894 mmci_dma_release(host); 1895 clk_disable_unprepare(host->clk); 1896 mmc_free_host(mmc); 1897 } 1898 1899 return 0; 1900 } 1901 1902 #ifdef CONFIG_PM 1903 static void mmci_save(struct mmci_host *host) 1904 { 1905 unsigned long flags; 1906 1907 spin_lock_irqsave(&host->lock, flags); 1908 1909 writel(0, host->base + MMCIMASK0); 1910 if (host->variant->pwrreg_nopower) { 1911 writel(0, host->base + MMCIDATACTRL); 1912 writel(0, host->base + MMCIPOWER); 1913 writel(0, host->base + MMCICLOCK); 1914 } 1915 mmci_reg_delay(host); 1916 1917 spin_unlock_irqrestore(&host->lock, flags); 1918 } 1919 1920 static void mmci_restore(struct mmci_host *host) 1921 { 1922 unsigned long flags; 1923 1924 spin_lock_irqsave(&host->lock, flags); 1925 1926 if (host->variant->pwrreg_nopower) { 1927 writel(host->clk_reg, host->base + MMCICLOCK); 1928 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1929 writel(host->pwr_reg, host->base + MMCIPOWER); 1930 } 1931 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1932 mmci_reg_delay(host); 1933 1934 spin_unlock_irqrestore(&host->lock, flags); 1935 } 1936 1937 static int mmci_runtime_suspend(struct device *dev) 1938 { 1939 struct amba_device *adev = to_amba_device(dev); 1940 struct mmc_host *mmc = amba_get_drvdata(adev); 1941 1942 if (mmc) { 1943 struct mmci_host *host = mmc_priv(mmc); 1944 pinctrl_pm_select_sleep_state(dev); 1945 mmci_save(host); 1946 clk_disable_unprepare(host->clk); 1947 } 1948 1949 return 0; 1950 } 1951 1952 static int mmci_runtime_resume(struct device *dev) 1953 { 1954 struct amba_device *adev = to_amba_device(dev); 1955 struct mmc_host *mmc = amba_get_drvdata(adev); 1956 1957 if (mmc) { 1958 struct mmci_host *host = mmc_priv(mmc); 1959 clk_prepare_enable(host->clk); 1960 mmci_restore(host); 1961 pinctrl_pm_select_default_state(dev); 1962 } 1963 1964 return 0; 1965 } 1966 #endif 1967 1968 static const struct dev_pm_ops mmci_dev_pm_ops = { 1969 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1970 pm_runtime_force_resume) 1971 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1972 }; 1973 1974 static const struct amba_id mmci_ids[] = { 1975 { 1976 .id = 0x00041180, 1977 .mask = 0xff0fffff, 1978 .data = &variant_arm, 1979 }, 1980 { 1981 .id = 0x01041180, 1982 .mask = 0xff0fffff, 1983 .data = &variant_arm_extended_fifo, 1984 }, 1985 { 1986 .id = 0x02041180, 1987 .mask = 0xff0fffff, 1988 .data = &variant_arm_extended_fifo_hwfc, 1989 }, 1990 { 1991 .id = 0x00041181, 1992 .mask = 0x000fffff, 1993 .data = &variant_arm, 1994 }, 1995 /* ST Micro variants */ 1996 { 1997 .id = 0x00180180, 1998 .mask = 0x00ffffff, 1999 .data = &variant_u300, 2000 }, 2001 { 2002 .id = 0x10180180, 2003 .mask = 0xf0ffffff, 2004 .data = &variant_nomadik, 2005 }, 2006 { 2007 .id = 0x00280180, 2008 .mask = 0x00ffffff, 2009 .data = &variant_nomadik, 2010 }, 2011 { 2012 .id = 0x00480180, 2013 .mask = 0xf0ffffff, 2014 .data = &variant_ux500, 2015 }, 2016 { 2017 .id = 0x10480180, 2018 .mask = 0xf0ffffff, 2019 .data = &variant_ux500v2, 2020 }, 2021 { 2022 .id = 0x00880180, 2023 .mask = 0x00ffffff, 2024 .data = &variant_stm32, 2025 }, 2026 /* Qualcomm variants */ 2027 { 2028 .id = 0x00051180, 2029 .mask = 0x000fffff, 2030 .data = &variant_qcom, 2031 }, 2032 { 0, 0 }, 2033 }; 2034 2035 MODULE_DEVICE_TABLE(amba, mmci_ids); 2036 2037 static struct amba_driver mmci_driver = { 2038 .drv = { 2039 .name = DRIVER_NAME, 2040 .pm = &mmci_dev_pm_ops, 2041 }, 2042 .probe = mmci_probe, 2043 .remove = mmci_remove, 2044 .id_table = mmci_ids, 2045 }; 2046 2047 module_amba_driver(mmci_driver); 2048 2049 module_param(fmax, uint, 0444); 2050 2051 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2052 MODULE_LICENSE("GPL"); 2053