1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/amba/mmci.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/types.h> 39 #include <linux/pinctrl/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 #include <asm/sizes.h> 44 45 #include "mmci.h" 46 #include "mmci_qcom_dml.h" 47 48 #define DRIVER_NAME "mmci-pl18x" 49 50 static unsigned int fmax = 515633; 51 52 /** 53 * struct variant_data - MMCI variant-specific quirks 54 * @clkreg: default value for MCICLOCK register 55 * @clkreg_enable: enable value for MMCICLOCK register 56 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 57 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 58 * @datalength_bits: number of bits in the MMCIDATALENGTH register 59 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 60 * is asserted (likewise for RX) 61 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 62 * is asserted (likewise for RX) 63 * @data_cmd_enable: enable value for data commands. 64 * @st_sdio: enable ST specific SDIO logic 65 * @st_clkdiv: true if using a ST-specific clock divider algorithm 66 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 67 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 68 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 69 * register 70 * @datactrl_mask_sdio: SDIO enable mask in datactrl register 71 * @pwrreg_powerup: power up value for MMCIPOWER register 72 * @f_max: maximum clk frequency supported by the controller. 73 * @signal_direction: input/out direction of bus signals can be indicated 74 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 75 * @busy_detect: true if busy detection on dat0 is supported 76 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 77 * @explicit_mclk_control: enable explicit mclk control in driver. 78 * @qcom_fifo: enables qcom specific fifo pio read logic. 79 * @qcom_dml: enables qcom specific dma glue for dma transfers. 80 * @reversed_irq_handling: handle data irq before cmd irq. 81 */ 82 struct variant_data { 83 unsigned int clkreg; 84 unsigned int clkreg_enable; 85 unsigned int clkreg_8bit_bus_enable; 86 unsigned int clkreg_neg_edge_enable; 87 unsigned int datalength_bits; 88 unsigned int fifosize; 89 unsigned int fifohalfsize; 90 unsigned int data_cmd_enable; 91 unsigned int datactrl_mask_ddrmode; 92 unsigned int datactrl_mask_sdio; 93 bool st_sdio; 94 bool st_clkdiv; 95 bool blksz_datactrl16; 96 bool blksz_datactrl4; 97 u32 pwrreg_powerup; 98 u32 f_max; 99 bool signal_direction; 100 bool pwrreg_clkgate; 101 bool busy_detect; 102 bool pwrreg_nopower; 103 bool explicit_mclk_control; 104 bool qcom_fifo; 105 bool qcom_dml; 106 bool reversed_irq_handling; 107 }; 108 109 static struct variant_data variant_arm = { 110 .fifosize = 16 * 4, 111 .fifohalfsize = 8 * 4, 112 .datalength_bits = 16, 113 .pwrreg_powerup = MCI_PWR_UP, 114 .f_max = 100000000, 115 .reversed_irq_handling = true, 116 }; 117 118 static struct variant_data variant_arm_extended_fifo = { 119 .fifosize = 128 * 4, 120 .fifohalfsize = 64 * 4, 121 .datalength_bits = 16, 122 .pwrreg_powerup = MCI_PWR_UP, 123 .f_max = 100000000, 124 }; 125 126 static struct variant_data variant_arm_extended_fifo_hwfc = { 127 .fifosize = 128 * 4, 128 .fifohalfsize = 64 * 4, 129 .clkreg_enable = MCI_ARM_HWFCEN, 130 .datalength_bits = 16, 131 .pwrreg_powerup = MCI_PWR_UP, 132 .f_max = 100000000, 133 }; 134 135 static struct variant_data variant_u300 = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg_enable = MCI_ST_U300_HWFCEN, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .datalength_bits = 16, 141 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 142 .st_sdio = true, 143 .pwrreg_powerup = MCI_PWR_ON, 144 .f_max = 100000000, 145 .signal_direction = true, 146 .pwrreg_clkgate = true, 147 .pwrreg_nopower = true, 148 }; 149 150 static struct variant_data variant_nomadik = { 151 .fifosize = 16 * 4, 152 .fifohalfsize = 8 * 4, 153 .clkreg = MCI_CLK_ENABLE, 154 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 155 .datalength_bits = 24, 156 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 157 .st_sdio = true, 158 .st_clkdiv = true, 159 .pwrreg_powerup = MCI_PWR_ON, 160 .f_max = 100000000, 161 .signal_direction = true, 162 .pwrreg_clkgate = true, 163 .pwrreg_nopower = true, 164 }; 165 166 static struct variant_data variant_ux500 = { 167 .fifosize = 30 * 4, 168 .fifohalfsize = 8 * 4, 169 .clkreg = MCI_CLK_ENABLE, 170 .clkreg_enable = MCI_ST_UX500_HWFCEN, 171 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 172 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 173 .datalength_bits = 24, 174 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 175 .st_sdio = true, 176 .st_clkdiv = true, 177 .pwrreg_powerup = MCI_PWR_ON, 178 .f_max = 100000000, 179 .signal_direction = true, 180 .pwrreg_clkgate = true, 181 .busy_detect = true, 182 .pwrreg_nopower = true, 183 }; 184 185 static struct variant_data variant_ux500v2 = { 186 .fifosize = 30 * 4, 187 .fifohalfsize = 8 * 4, 188 .clkreg = MCI_CLK_ENABLE, 189 .clkreg_enable = MCI_ST_UX500_HWFCEN, 190 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 191 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 192 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, 193 .datalength_bits = 24, 194 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 195 .st_sdio = true, 196 .st_clkdiv = true, 197 .blksz_datactrl16 = true, 198 .pwrreg_powerup = MCI_PWR_ON, 199 .f_max = 100000000, 200 .signal_direction = true, 201 .pwrreg_clkgate = true, 202 .busy_detect = true, 203 .pwrreg_nopower = true, 204 }; 205 206 static struct variant_data variant_qcom = { 207 .fifosize = 16 * 4, 208 .fifohalfsize = 8 * 4, 209 .clkreg = MCI_CLK_ENABLE, 210 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 211 MCI_QCOM_CLK_SELECT_IN_FBCLK, 212 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 213 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 214 .data_cmd_enable = MCI_QCOM_CSPM_DATCMD, 215 .blksz_datactrl4 = true, 216 .datalength_bits = 24, 217 .pwrreg_powerup = MCI_PWR_UP, 218 .f_max = 208000000, 219 .explicit_mclk_control = true, 220 .qcom_fifo = true, 221 .qcom_dml = true, 222 }; 223 224 static int mmci_card_busy(struct mmc_host *mmc) 225 { 226 struct mmci_host *host = mmc_priv(mmc); 227 unsigned long flags; 228 int busy = 0; 229 230 pm_runtime_get_sync(mmc_dev(mmc)); 231 232 spin_lock_irqsave(&host->lock, flags); 233 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 234 busy = 1; 235 spin_unlock_irqrestore(&host->lock, flags); 236 237 pm_runtime_mark_last_busy(mmc_dev(mmc)); 238 pm_runtime_put_autosuspend(mmc_dev(mmc)); 239 240 return busy; 241 } 242 243 /* 244 * Validate mmc prerequisites 245 */ 246 static int mmci_validate_data(struct mmci_host *host, 247 struct mmc_data *data) 248 { 249 if (!data) 250 return 0; 251 252 if (!is_power_of_2(data->blksz)) { 253 dev_err(mmc_dev(host->mmc), 254 "unsupported block size (%d bytes)\n", data->blksz); 255 return -EINVAL; 256 } 257 258 return 0; 259 } 260 261 static void mmci_reg_delay(struct mmci_host *host) 262 { 263 /* 264 * According to the spec, at least three feedback clock cycles 265 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 266 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 267 * Worst delay time during card init is at 100 kHz => 30 us. 268 * Worst delay time when up and running is at 25 MHz => 120 ns. 269 */ 270 if (host->cclk < 25000000) 271 udelay(30); 272 else 273 ndelay(120); 274 } 275 276 /* 277 * This must be called with host->lock held 278 */ 279 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 280 { 281 if (host->clk_reg != clk) { 282 host->clk_reg = clk; 283 writel(clk, host->base + MMCICLOCK); 284 } 285 } 286 287 /* 288 * This must be called with host->lock held 289 */ 290 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 291 { 292 if (host->pwr_reg != pwr) { 293 host->pwr_reg = pwr; 294 writel(pwr, host->base + MMCIPOWER); 295 } 296 } 297 298 /* 299 * This must be called with host->lock held 300 */ 301 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 302 { 303 /* Keep ST Micro busy mode if enabled */ 304 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 305 306 if (host->datactrl_reg != datactrl) { 307 host->datactrl_reg = datactrl; 308 writel(datactrl, host->base + MMCIDATACTRL); 309 } 310 } 311 312 /* 313 * This must be called with host->lock held 314 */ 315 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 316 { 317 struct variant_data *variant = host->variant; 318 u32 clk = variant->clkreg; 319 320 /* Make sure cclk reflects the current calculated clock */ 321 host->cclk = 0; 322 323 if (desired) { 324 if (variant->explicit_mclk_control) { 325 host->cclk = host->mclk; 326 } else if (desired >= host->mclk) { 327 clk = MCI_CLK_BYPASS; 328 if (variant->st_clkdiv) 329 clk |= MCI_ST_UX500_NEG_EDGE; 330 host->cclk = host->mclk; 331 } else if (variant->st_clkdiv) { 332 /* 333 * DB8500 TRM says f = mclk / (clkdiv + 2) 334 * => clkdiv = (mclk / f) - 2 335 * Round the divider up so we don't exceed the max 336 * frequency 337 */ 338 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 339 if (clk >= 256) 340 clk = 255; 341 host->cclk = host->mclk / (clk + 2); 342 } else { 343 /* 344 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 345 * => clkdiv = mclk / (2 * f) - 1 346 */ 347 clk = host->mclk / (2 * desired) - 1; 348 if (clk >= 256) 349 clk = 255; 350 host->cclk = host->mclk / (2 * (clk + 1)); 351 } 352 353 clk |= variant->clkreg_enable; 354 clk |= MCI_CLK_ENABLE; 355 /* This hasn't proven to be worthwhile */ 356 /* clk |= MCI_CLK_PWRSAVE; */ 357 } 358 359 /* Set actual clock for debug */ 360 host->mmc->actual_clock = host->cclk; 361 362 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 363 clk |= MCI_4BIT_BUS; 364 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 365 clk |= variant->clkreg_8bit_bus_enable; 366 367 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 368 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 369 clk |= variant->clkreg_neg_edge_enable; 370 371 mmci_write_clkreg(host, clk); 372 } 373 374 static void 375 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 376 { 377 writel(0, host->base + MMCICOMMAND); 378 379 BUG_ON(host->data); 380 381 host->mrq = NULL; 382 host->cmd = NULL; 383 384 mmc_request_done(host->mmc, mrq); 385 386 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 387 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 388 } 389 390 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 391 { 392 void __iomem *base = host->base; 393 394 if (host->singleirq) { 395 unsigned int mask0 = readl(base + MMCIMASK0); 396 397 mask0 &= ~MCI_IRQ1MASK; 398 mask0 |= mask; 399 400 writel(mask0, base + MMCIMASK0); 401 } 402 403 writel(mask, base + MMCIMASK1); 404 } 405 406 static void mmci_stop_data(struct mmci_host *host) 407 { 408 mmci_write_datactrlreg(host, 0); 409 mmci_set_mask1(host, 0); 410 host->data = NULL; 411 } 412 413 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 414 { 415 unsigned int flags = SG_MITER_ATOMIC; 416 417 if (data->flags & MMC_DATA_READ) 418 flags |= SG_MITER_TO_SG; 419 else 420 flags |= SG_MITER_FROM_SG; 421 422 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 423 } 424 425 /* 426 * All the DMA operation mode stuff goes inside this ifdef. 427 * This assumes that you have a generic DMA device interface, 428 * no custom DMA interfaces are supported. 429 */ 430 #ifdef CONFIG_DMA_ENGINE 431 static void mmci_dma_setup(struct mmci_host *host) 432 { 433 const char *rxname, *txname; 434 struct variant_data *variant = host->variant; 435 436 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 437 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 438 439 /* initialize pre request cookie */ 440 host->next_data.cookie = 1; 441 442 /* 443 * If only an RX channel is specified, the driver will 444 * attempt to use it bidirectionally, however if it is 445 * is specified but cannot be located, DMA will be disabled. 446 */ 447 if (host->dma_rx_channel && !host->dma_tx_channel) 448 host->dma_tx_channel = host->dma_rx_channel; 449 450 if (host->dma_rx_channel) 451 rxname = dma_chan_name(host->dma_rx_channel); 452 else 453 rxname = "none"; 454 455 if (host->dma_tx_channel) 456 txname = dma_chan_name(host->dma_tx_channel); 457 else 458 txname = "none"; 459 460 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 461 rxname, txname); 462 463 /* 464 * Limit the maximum segment size in any SG entry according to 465 * the parameters of the DMA engine device. 466 */ 467 if (host->dma_tx_channel) { 468 struct device *dev = host->dma_tx_channel->device->dev; 469 unsigned int max_seg_size = dma_get_max_seg_size(dev); 470 471 if (max_seg_size < host->mmc->max_seg_size) 472 host->mmc->max_seg_size = max_seg_size; 473 } 474 if (host->dma_rx_channel) { 475 struct device *dev = host->dma_rx_channel->device->dev; 476 unsigned int max_seg_size = dma_get_max_seg_size(dev); 477 478 if (max_seg_size < host->mmc->max_seg_size) 479 host->mmc->max_seg_size = max_seg_size; 480 } 481 482 if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) 483 if (dml_hw_init(host, host->mmc->parent->of_node)) 484 variant->qcom_dml = false; 485 } 486 487 /* 488 * This is used in or so inline it 489 * so it can be discarded. 490 */ 491 static inline void mmci_dma_release(struct mmci_host *host) 492 { 493 if (host->dma_rx_channel) 494 dma_release_channel(host->dma_rx_channel); 495 if (host->dma_tx_channel) 496 dma_release_channel(host->dma_tx_channel); 497 host->dma_rx_channel = host->dma_tx_channel = NULL; 498 } 499 500 static void mmci_dma_data_error(struct mmci_host *host) 501 { 502 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 503 dmaengine_terminate_all(host->dma_current); 504 host->dma_current = NULL; 505 host->dma_desc_current = NULL; 506 host->data->host_cookie = 0; 507 } 508 509 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 510 { 511 struct dma_chan *chan; 512 enum dma_data_direction dir; 513 514 if (data->flags & MMC_DATA_READ) { 515 dir = DMA_FROM_DEVICE; 516 chan = host->dma_rx_channel; 517 } else { 518 dir = DMA_TO_DEVICE; 519 chan = host->dma_tx_channel; 520 } 521 522 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 523 } 524 525 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 526 { 527 u32 status; 528 int i; 529 530 /* Wait up to 1ms for the DMA to complete */ 531 for (i = 0; ; i++) { 532 status = readl(host->base + MMCISTATUS); 533 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 534 break; 535 udelay(10); 536 } 537 538 /* 539 * Check to see whether we still have some data left in the FIFO - 540 * this catches DMA controllers which are unable to monitor the 541 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 542 * contiguous buffers. On TX, we'll get a FIFO underrun error. 543 */ 544 if (status & MCI_RXDATAAVLBLMASK) { 545 mmci_dma_data_error(host); 546 if (!data->error) 547 data->error = -EIO; 548 } 549 550 if (!data->host_cookie) 551 mmci_dma_unmap(host, data); 552 553 /* 554 * Use of DMA with scatter-gather is impossible. 555 * Give up with DMA and switch back to PIO mode. 556 */ 557 if (status & MCI_RXDATAAVLBLMASK) { 558 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 559 mmci_dma_release(host); 560 } 561 562 host->dma_current = NULL; 563 host->dma_desc_current = NULL; 564 } 565 566 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 567 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 568 struct dma_chan **dma_chan, 569 struct dma_async_tx_descriptor **dma_desc) 570 { 571 struct variant_data *variant = host->variant; 572 struct dma_slave_config conf = { 573 .src_addr = host->phybase + MMCIFIFO, 574 .dst_addr = host->phybase + MMCIFIFO, 575 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 576 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 577 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 578 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 579 .device_fc = false, 580 }; 581 struct dma_chan *chan; 582 struct dma_device *device; 583 struct dma_async_tx_descriptor *desc; 584 enum dma_data_direction buffer_dirn; 585 int nr_sg; 586 unsigned long flags = DMA_CTRL_ACK; 587 588 if (data->flags & MMC_DATA_READ) { 589 conf.direction = DMA_DEV_TO_MEM; 590 buffer_dirn = DMA_FROM_DEVICE; 591 chan = host->dma_rx_channel; 592 } else { 593 conf.direction = DMA_MEM_TO_DEV; 594 buffer_dirn = DMA_TO_DEVICE; 595 chan = host->dma_tx_channel; 596 } 597 598 /* If there's no DMA channel, fall back to PIO */ 599 if (!chan) 600 return -EINVAL; 601 602 /* If less than or equal to the fifo size, don't bother with DMA */ 603 if (data->blksz * data->blocks <= variant->fifosize) 604 return -EINVAL; 605 606 device = chan->device; 607 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 608 if (nr_sg == 0) 609 return -EINVAL; 610 611 if (host->variant->qcom_dml) 612 flags |= DMA_PREP_INTERRUPT; 613 614 dmaengine_slave_config(chan, &conf); 615 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 616 conf.direction, flags); 617 if (!desc) 618 goto unmap_exit; 619 620 *dma_chan = chan; 621 *dma_desc = desc; 622 623 return 0; 624 625 unmap_exit: 626 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 627 return -ENOMEM; 628 } 629 630 static inline int mmci_dma_prep_data(struct mmci_host *host, 631 struct mmc_data *data) 632 { 633 /* Check if next job is already prepared. */ 634 if (host->dma_current && host->dma_desc_current) 635 return 0; 636 637 /* No job were prepared thus do it now. */ 638 return __mmci_dma_prep_data(host, data, &host->dma_current, 639 &host->dma_desc_current); 640 } 641 642 static inline int mmci_dma_prep_next(struct mmci_host *host, 643 struct mmc_data *data) 644 { 645 struct mmci_host_next *nd = &host->next_data; 646 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 647 } 648 649 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 650 { 651 int ret; 652 struct mmc_data *data = host->data; 653 654 ret = mmci_dma_prep_data(host, host->data); 655 if (ret) 656 return ret; 657 658 /* Okay, go for it. */ 659 dev_vdbg(mmc_dev(host->mmc), 660 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 661 data->sg_len, data->blksz, data->blocks, data->flags); 662 dmaengine_submit(host->dma_desc_current); 663 dma_async_issue_pending(host->dma_current); 664 665 if (host->variant->qcom_dml) 666 dml_start_xfer(host, data); 667 668 datactrl |= MCI_DPSM_DMAENABLE; 669 670 /* Trigger the DMA transfer */ 671 mmci_write_datactrlreg(host, datactrl); 672 673 /* 674 * Let the MMCI say when the data is ended and it's time 675 * to fire next DMA request. When that happens, MMCI will 676 * call mmci_data_end() 677 */ 678 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 679 host->base + MMCIMASK0); 680 return 0; 681 } 682 683 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 684 { 685 struct mmci_host_next *next = &host->next_data; 686 687 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 688 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 689 690 host->dma_desc_current = next->dma_desc; 691 host->dma_current = next->dma_chan; 692 next->dma_desc = NULL; 693 next->dma_chan = NULL; 694 } 695 696 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 697 bool is_first_req) 698 { 699 struct mmci_host *host = mmc_priv(mmc); 700 struct mmc_data *data = mrq->data; 701 struct mmci_host_next *nd = &host->next_data; 702 703 if (!data) 704 return; 705 706 BUG_ON(data->host_cookie); 707 708 if (mmci_validate_data(host, data)) 709 return; 710 711 if (!mmci_dma_prep_next(host, data)) 712 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 713 } 714 715 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 716 int err) 717 { 718 struct mmci_host *host = mmc_priv(mmc); 719 struct mmc_data *data = mrq->data; 720 721 if (!data || !data->host_cookie) 722 return; 723 724 mmci_dma_unmap(host, data); 725 726 if (err) { 727 struct mmci_host_next *next = &host->next_data; 728 struct dma_chan *chan; 729 if (data->flags & MMC_DATA_READ) 730 chan = host->dma_rx_channel; 731 else 732 chan = host->dma_tx_channel; 733 dmaengine_terminate_all(chan); 734 735 if (host->dma_desc_current == next->dma_desc) 736 host->dma_desc_current = NULL; 737 738 if (host->dma_current == next->dma_chan) 739 host->dma_current = NULL; 740 741 next->dma_desc = NULL; 742 next->dma_chan = NULL; 743 data->host_cookie = 0; 744 } 745 } 746 747 #else 748 /* Blank functions if the DMA engine is not available */ 749 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 750 { 751 } 752 static inline void mmci_dma_setup(struct mmci_host *host) 753 { 754 } 755 756 static inline void mmci_dma_release(struct mmci_host *host) 757 { 758 } 759 760 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 761 { 762 } 763 764 static inline void mmci_dma_finalize(struct mmci_host *host, 765 struct mmc_data *data) 766 { 767 } 768 769 static inline void mmci_dma_data_error(struct mmci_host *host) 770 { 771 } 772 773 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 774 { 775 return -ENOSYS; 776 } 777 778 #define mmci_pre_request NULL 779 #define mmci_post_request NULL 780 781 #endif 782 783 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 784 { 785 struct variant_data *variant = host->variant; 786 unsigned int datactrl, timeout, irqmask; 787 unsigned long long clks; 788 void __iomem *base; 789 int blksz_bits; 790 791 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 792 data->blksz, data->blocks, data->flags); 793 794 host->data = data; 795 host->size = data->blksz * data->blocks; 796 data->bytes_xfered = 0; 797 798 clks = (unsigned long long)data->timeout_ns * host->cclk; 799 do_div(clks, NSEC_PER_SEC); 800 801 timeout = data->timeout_clks + (unsigned int)clks; 802 803 base = host->base; 804 writel(timeout, base + MMCIDATATIMER); 805 writel(host->size, base + MMCIDATALENGTH); 806 807 blksz_bits = ffs(data->blksz) - 1; 808 BUG_ON(1 << blksz_bits != data->blksz); 809 810 if (variant->blksz_datactrl16) 811 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 812 else if (variant->blksz_datactrl4) 813 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 814 else 815 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 816 817 if (data->flags & MMC_DATA_READ) 818 datactrl |= MCI_DPSM_DIRECTION; 819 820 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 821 u32 clk; 822 823 datactrl |= variant->datactrl_mask_sdio; 824 825 /* 826 * The ST Micro variant for SDIO small write transfers 827 * needs to have clock H/W flow control disabled, 828 * otherwise the transfer will not start. The threshold 829 * depends on the rate of MCLK. 830 */ 831 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 832 (host->size < 8 || 833 (host->size <= 8 && host->mclk > 50000000))) 834 clk = host->clk_reg & ~variant->clkreg_enable; 835 else 836 clk = host->clk_reg | variant->clkreg_enable; 837 838 mmci_write_clkreg(host, clk); 839 } 840 841 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 842 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 843 datactrl |= variant->datactrl_mask_ddrmode; 844 845 /* 846 * Attempt to use DMA operation mode, if this 847 * should fail, fall back to PIO mode 848 */ 849 if (!mmci_dma_start_data(host, datactrl)) 850 return; 851 852 /* IRQ mode, map the SG list for CPU reading/writing */ 853 mmci_init_sg(host, data); 854 855 if (data->flags & MMC_DATA_READ) { 856 irqmask = MCI_RXFIFOHALFFULLMASK; 857 858 /* 859 * If we have less than the fifo 'half-full' threshold to 860 * transfer, trigger a PIO interrupt as soon as any data 861 * is available. 862 */ 863 if (host->size < variant->fifohalfsize) 864 irqmask |= MCI_RXDATAAVLBLMASK; 865 } else { 866 /* 867 * We don't actually need to include "FIFO empty" here 868 * since its implicit in "FIFO half empty". 869 */ 870 irqmask = MCI_TXFIFOHALFEMPTYMASK; 871 } 872 873 mmci_write_datactrlreg(host, datactrl); 874 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 875 mmci_set_mask1(host, irqmask); 876 } 877 878 static void 879 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 880 { 881 void __iomem *base = host->base; 882 883 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 884 cmd->opcode, cmd->arg, cmd->flags); 885 886 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 887 writel(0, base + MMCICOMMAND); 888 mmci_reg_delay(host); 889 } 890 891 c |= cmd->opcode | MCI_CPSM_ENABLE; 892 if (cmd->flags & MMC_RSP_PRESENT) { 893 if (cmd->flags & MMC_RSP_136) 894 c |= MCI_CPSM_LONGRSP; 895 c |= MCI_CPSM_RESPONSE; 896 } 897 if (/*interrupt*/0) 898 c |= MCI_CPSM_INTERRUPT; 899 900 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 901 c |= host->variant->data_cmd_enable; 902 903 host->cmd = cmd; 904 905 writel(cmd->arg, base + MMCIARGUMENT); 906 writel(c, base + MMCICOMMAND); 907 } 908 909 static void 910 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 911 unsigned int status) 912 { 913 /* Make sure we have data to handle */ 914 if (!data) 915 return; 916 917 /* First check for errors */ 918 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 919 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 920 u32 remain, success; 921 922 /* Terminate the DMA transfer */ 923 if (dma_inprogress(host)) { 924 mmci_dma_data_error(host); 925 mmci_dma_unmap(host, data); 926 } 927 928 /* 929 * Calculate how far we are into the transfer. Note that 930 * the data counter gives the number of bytes transferred 931 * on the MMC bus, not on the host side. On reads, this 932 * can be as much as a FIFO-worth of data ahead. This 933 * matters for FIFO overruns only. 934 */ 935 remain = readl(host->base + MMCIDATACNT); 936 success = data->blksz * data->blocks - remain; 937 938 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 939 status, success); 940 if (status & MCI_DATACRCFAIL) { 941 /* Last block was not successful */ 942 success -= 1; 943 data->error = -EILSEQ; 944 } else if (status & MCI_DATATIMEOUT) { 945 data->error = -ETIMEDOUT; 946 } else if (status & MCI_STARTBITERR) { 947 data->error = -ECOMM; 948 } else if (status & MCI_TXUNDERRUN) { 949 data->error = -EIO; 950 } else if (status & MCI_RXOVERRUN) { 951 if (success > host->variant->fifosize) 952 success -= host->variant->fifosize; 953 else 954 success = 0; 955 data->error = -EIO; 956 } 957 data->bytes_xfered = round_down(success, data->blksz); 958 } 959 960 if (status & MCI_DATABLOCKEND) 961 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 962 963 if (status & MCI_DATAEND || data->error) { 964 if (dma_inprogress(host)) 965 mmci_dma_finalize(host, data); 966 mmci_stop_data(host); 967 968 if (!data->error) 969 /* The error clause is handled above, success! */ 970 data->bytes_xfered = data->blksz * data->blocks; 971 972 if (!data->stop || host->mrq->sbc) { 973 mmci_request_end(host, data->mrq); 974 } else { 975 mmci_start_command(host, data->stop, 0); 976 } 977 } 978 } 979 980 static void 981 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 982 unsigned int status) 983 { 984 void __iomem *base = host->base; 985 bool sbc, busy_resp; 986 987 if (!cmd) 988 return; 989 990 sbc = (cmd == host->mrq->sbc); 991 busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY); 992 993 if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 994 MCI_CMDSENT|MCI_CMDRESPEND))) 995 return; 996 997 /* Check if we need to wait for busy completion. */ 998 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 999 return; 1000 1001 /* Enable busy completion if needed and supported. */ 1002 if (!host->busy_status && busy_resp && 1003 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1004 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 1005 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 1006 base + MMCIMASK0); 1007 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 1008 return; 1009 } 1010 1011 /* At busy completion, mask the IRQ and complete the request. */ 1012 if (host->busy_status) { 1013 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 1014 base + MMCIMASK0); 1015 host->busy_status = 0; 1016 } 1017 1018 host->cmd = NULL; 1019 1020 if (status & MCI_CMDTIMEOUT) { 1021 cmd->error = -ETIMEDOUT; 1022 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1023 cmd->error = -EILSEQ; 1024 } else { 1025 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1026 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1027 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1028 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1029 } 1030 1031 if ((!sbc && !cmd->data) || cmd->error) { 1032 if (host->data) { 1033 /* Terminate the DMA transfer */ 1034 if (dma_inprogress(host)) { 1035 mmci_dma_data_error(host); 1036 mmci_dma_unmap(host, host->data); 1037 } 1038 mmci_stop_data(host); 1039 } 1040 mmci_request_end(host, host->mrq); 1041 } else if (sbc) { 1042 mmci_start_command(host, host->mrq->cmd, 0); 1043 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 1044 mmci_start_data(host, cmd->data); 1045 } 1046 } 1047 1048 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1049 { 1050 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1051 } 1052 1053 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1054 { 1055 /* 1056 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1057 * from the fifo range should be used 1058 */ 1059 if (status & MCI_RXFIFOHALFFULL) 1060 return host->variant->fifohalfsize; 1061 else if (status & MCI_RXDATAAVLBL) 1062 return 4; 1063 1064 return 0; 1065 } 1066 1067 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1068 { 1069 void __iomem *base = host->base; 1070 char *ptr = buffer; 1071 u32 status = readl(host->base + MMCISTATUS); 1072 int host_remain = host->size; 1073 1074 do { 1075 int count = host->get_rx_fifocnt(host, status, host_remain); 1076 1077 if (count > remain) 1078 count = remain; 1079 1080 if (count <= 0) 1081 break; 1082 1083 /* 1084 * SDIO especially may want to send something that is 1085 * not divisible by 4 (as opposed to card sectors 1086 * etc). Therefore make sure to always read the last bytes 1087 * while only doing full 32-bit reads towards the FIFO. 1088 */ 1089 if (unlikely(count & 0x3)) { 1090 if (count < 4) { 1091 unsigned char buf[4]; 1092 ioread32_rep(base + MMCIFIFO, buf, 1); 1093 memcpy(ptr, buf, count); 1094 } else { 1095 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1096 count &= ~0x3; 1097 } 1098 } else { 1099 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1100 } 1101 1102 ptr += count; 1103 remain -= count; 1104 host_remain -= count; 1105 1106 if (remain == 0) 1107 break; 1108 1109 status = readl(base + MMCISTATUS); 1110 } while (status & MCI_RXDATAAVLBL); 1111 1112 return ptr - buffer; 1113 } 1114 1115 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1116 { 1117 struct variant_data *variant = host->variant; 1118 void __iomem *base = host->base; 1119 char *ptr = buffer; 1120 1121 do { 1122 unsigned int count, maxcnt; 1123 1124 maxcnt = status & MCI_TXFIFOEMPTY ? 1125 variant->fifosize : variant->fifohalfsize; 1126 count = min(remain, maxcnt); 1127 1128 /* 1129 * SDIO especially may want to send something that is 1130 * not divisible by 4 (as opposed to card sectors 1131 * etc), and the FIFO only accept full 32-bit writes. 1132 * So compensate by adding +3 on the count, a single 1133 * byte become a 32bit write, 7 bytes will be two 1134 * 32bit writes etc. 1135 */ 1136 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1137 1138 ptr += count; 1139 remain -= count; 1140 1141 if (remain == 0) 1142 break; 1143 1144 status = readl(base + MMCISTATUS); 1145 } while (status & MCI_TXFIFOHALFEMPTY); 1146 1147 return ptr - buffer; 1148 } 1149 1150 /* 1151 * PIO data transfer IRQ handler. 1152 */ 1153 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1154 { 1155 struct mmci_host *host = dev_id; 1156 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1157 struct variant_data *variant = host->variant; 1158 void __iomem *base = host->base; 1159 unsigned long flags; 1160 u32 status; 1161 1162 status = readl(base + MMCISTATUS); 1163 1164 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1165 1166 local_irq_save(flags); 1167 1168 do { 1169 unsigned int remain, len; 1170 char *buffer; 1171 1172 /* 1173 * For write, we only need to test the half-empty flag 1174 * here - if the FIFO is completely empty, then by 1175 * definition it is more than half empty. 1176 * 1177 * For read, check for data available. 1178 */ 1179 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1180 break; 1181 1182 if (!sg_miter_next(sg_miter)) 1183 break; 1184 1185 buffer = sg_miter->addr; 1186 remain = sg_miter->length; 1187 1188 len = 0; 1189 if (status & MCI_RXACTIVE) 1190 len = mmci_pio_read(host, buffer, remain); 1191 if (status & MCI_TXACTIVE) 1192 len = mmci_pio_write(host, buffer, remain, status); 1193 1194 sg_miter->consumed = len; 1195 1196 host->size -= len; 1197 remain -= len; 1198 1199 if (remain) 1200 break; 1201 1202 status = readl(base + MMCISTATUS); 1203 } while (1); 1204 1205 sg_miter_stop(sg_miter); 1206 1207 local_irq_restore(flags); 1208 1209 /* 1210 * If we have less than the fifo 'half-full' threshold to transfer, 1211 * trigger a PIO interrupt as soon as any data is available. 1212 */ 1213 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1214 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1215 1216 /* 1217 * If we run out of data, disable the data IRQs; this 1218 * prevents a race where the FIFO becomes empty before 1219 * the chip itself has disabled the data path, and 1220 * stops us racing with our data end IRQ. 1221 */ 1222 if (host->size == 0) { 1223 mmci_set_mask1(host, 0); 1224 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1225 } 1226 1227 return IRQ_HANDLED; 1228 } 1229 1230 /* 1231 * Handle completion of command and data transfers. 1232 */ 1233 static irqreturn_t mmci_irq(int irq, void *dev_id) 1234 { 1235 struct mmci_host *host = dev_id; 1236 u32 status; 1237 int ret = 0; 1238 1239 spin_lock(&host->lock); 1240 1241 do { 1242 status = readl(host->base + MMCISTATUS); 1243 1244 if (host->singleirq) { 1245 if (status & readl(host->base + MMCIMASK1)) 1246 mmci_pio_irq(irq, dev_id); 1247 1248 status &= ~MCI_IRQ1MASK; 1249 } 1250 1251 /* 1252 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1253 * enabled) since the HW seems to be triggering the IRQ on both 1254 * edges while monitoring DAT0 for busy completion. 1255 */ 1256 status &= readl(host->base + MMCIMASK0); 1257 writel(status, host->base + MMCICLEAR); 1258 1259 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1260 1261 if (host->variant->reversed_irq_handling) { 1262 mmci_data_irq(host, host->data, status); 1263 mmci_cmd_irq(host, host->cmd, status); 1264 } else { 1265 mmci_cmd_irq(host, host->cmd, status); 1266 mmci_data_irq(host, host->data, status); 1267 } 1268 1269 /* Don't poll for busy completion in irq context. */ 1270 if (host->busy_status) 1271 status &= ~MCI_ST_CARDBUSY; 1272 1273 ret = 1; 1274 } while (status); 1275 1276 spin_unlock(&host->lock); 1277 1278 return IRQ_RETVAL(ret); 1279 } 1280 1281 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1282 { 1283 struct mmci_host *host = mmc_priv(mmc); 1284 unsigned long flags; 1285 1286 WARN_ON(host->mrq != NULL); 1287 1288 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1289 if (mrq->cmd->error) { 1290 mmc_request_done(mmc, mrq); 1291 return; 1292 } 1293 1294 pm_runtime_get_sync(mmc_dev(mmc)); 1295 1296 spin_lock_irqsave(&host->lock, flags); 1297 1298 host->mrq = mrq; 1299 1300 if (mrq->data) 1301 mmci_get_next_data(host, mrq->data); 1302 1303 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1304 mmci_start_data(host, mrq->data); 1305 1306 if (mrq->sbc) 1307 mmci_start_command(host, mrq->sbc, 0); 1308 else 1309 mmci_start_command(host, mrq->cmd, 0); 1310 1311 spin_unlock_irqrestore(&host->lock, flags); 1312 } 1313 1314 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1315 { 1316 struct mmci_host *host = mmc_priv(mmc); 1317 struct variant_data *variant = host->variant; 1318 u32 pwr = 0; 1319 unsigned long flags; 1320 int ret; 1321 1322 pm_runtime_get_sync(mmc_dev(mmc)); 1323 1324 if (host->plat->ios_handler && 1325 host->plat->ios_handler(mmc_dev(mmc), ios)) 1326 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1327 1328 switch (ios->power_mode) { 1329 case MMC_POWER_OFF: 1330 if (!IS_ERR(mmc->supply.vmmc)) 1331 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1332 1333 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1334 regulator_disable(mmc->supply.vqmmc); 1335 host->vqmmc_enabled = false; 1336 } 1337 1338 break; 1339 case MMC_POWER_UP: 1340 if (!IS_ERR(mmc->supply.vmmc)) 1341 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1342 1343 /* 1344 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1345 * and instead uses MCI_PWR_ON so apply whatever value is 1346 * configured in the variant data. 1347 */ 1348 pwr |= variant->pwrreg_powerup; 1349 1350 break; 1351 case MMC_POWER_ON: 1352 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1353 ret = regulator_enable(mmc->supply.vqmmc); 1354 if (ret < 0) 1355 dev_err(mmc_dev(mmc), 1356 "failed to enable vqmmc regulator\n"); 1357 else 1358 host->vqmmc_enabled = true; 1359 } 1360 1361 pwr |= MCI_PWR_ON; 1362 break; 1363 } 1364 1365 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1366 /* 1367 * The ST Micro variant has some additional bits 1368 * indicating signal direction for the signals in 1369 * the SD/MMC bus and feedback-clock usage. 1370 */ 1371 pwr |= host->pwr_reg_add; 1372 1373 if (ios->bus_width == MMC_BUS_WIDTH_4) 1374 pwr &= ~MCI_ST_DATA74DIREN; 1375 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1376 pwr &= (~MCI_ST_DATA74DIREN & 1377 ~MCI_ST_DATA31DIREN & 1378 ~MCI_ST_DATA2DIREN); 1379 } 1380 1381 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1382 if (host->hw_designer != AMBA_VENDOR_ST) 1383 pwr |= MCI_ROD; 1384 else { 1385 /* 1386 * The ST Micro variant use the ROD bit for something 1387 * else and only has OD (Open Drain). 1388 */ 1389 pwr |= MCI_OD; 1390 } 1391 } 1392 1393 /* 1394 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1395 * gating the clock, the MCI_PWR_ON bit is cleared. 1396 */ 1397 if (!ios->clock && variant->pwrreg_clkgate) 1398 pwr &= ~MCI_PWR_ON; 1399 1400 if (host->variant->explicit_mclk_control && 1401 ios->clock != host->clock_cache) { 1402 ret = clk_set_rate(host->clk, ios->clock); 1403 if (ret < 0) 1404 dev_err(mmc_dev(host->mmc), 1405 "Error setting clock rate (%d)\n", ret); 1406 else 1407 host->mclk = clk_get_rate(host->clk); 1408 } 1409 host->clock_cache = ios->clock; 1410 1411 spin_lock_irqsave(&host->lock, flags); 1412 1413 mmci_set_clkreg(host, ios->clock); 1414 mmci_write_pwrreg(host, pwr); 1415 mmci_reg_delay(host); 1416 1417 spin_unlock_irqrestore(&host->lock, flags); 1418 1419 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1420 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1421 } 1422 1423 static int mmci_get_cd(struct mmc_host *mmc) 1424 { 1425 struct mmci_host *host = mmc_priv(mmc); 1426 struct mmci_platform_data *plat = host->plat; 1427 unsigned int status = mmc_gpio_get_cd(mmc); 1428 1429 if (status == -ENOSYS) { 1430 if (!plat->status) 1431 return 1; /* Assume always present */ 1432 1433 status = plat->status(mmc_dev(host->mmc)); 1434 } 1435 return status; 1436 } 1437 1438 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1439 { 1440 int ret = 0; 1441 1442 if (!IS_ERR(mmc->supply.vqmmc)) { 1443 1444 pm_runtime_get_sync(mmc_dev(mmc)); 1445 1446 switch (ios->signal_voltage) { 1447 case MMC_SIGNAL_VOLTAGE_330: 1448 ret = regulator_set_voltage(mmc->supply.vqmmc, 1449 2700000, 3600000); 1450 break; 1451 case MMC_SIGNAL_VOLTAGE_180: 1452 ret = regulator_set_voltage(mmc->supply.vqmmc, 1453 1700000, 1950000); 1454 break; 1455 case MMC_SIGNAL_VOLTAGE_120: 1456 ret = regulator_set_voltage(mmc->supply.vqmmc, 1457 1100000, 1300000); 1458 break; 1459 } 1460 1461 if (ret) 1462 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1463 1464 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1465 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1466 } 1467 1468 return ret; 1469 } 1470 1471 static struct mmc_host_ops mmci_ops = { 1472 .request = mmci_request, 1473 .pre_req = mmci_pre_request, 1474 .post_req = mmci_post_request, 1475 .set_ios = mmci_set_ios, 1476 .get_ro = mmc_gpio_get_ro, 1477 .get_cd = mmci_get_cd, 1478 .start_signal_voltage_switch = mmci_sig_volt_switch, 1479 }; 1480 1481 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1482 { 1483 struct mmci_host *host = mmc_priv(mmc); 1484 int ret = mmc_of_parse(mmc); 1485 1486 if (ret) 1487 return ret; 1488 1489 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1490 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1491 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1492 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1493 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1494 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1495 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1496 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1497 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1498 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1499 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1500 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1501 1502 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1503 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1504 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1505 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1506 1507 return 0; 1508 } 1509 1510 static int mmci_probe(struct amba_device *dev, 1511 const struct amba_id *id) 1512 { 1513 struct mmci_platform_data *plat = dev->dev.platform_data; 1514 struct device_node *np = dev->dev.of_node; 1515 struct variant_data *variant = id->data; 1516 struct mmci_host *host; 1517 struct mmc_host *mmc; 1518 int ret; 1519 1520 /* Must have platform data or Device Tree. */ 1521 if (!plat && !np) { 1522 dev_err(&dev->dev, "No plat data or DT found\n"); 1523 return -EINVAL; 1524 } 1525 1526 if (!plat) { 1527 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1528 if (!plat) 1529 return -ENOMEM; 1530 } 1531 1532 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1533 if (!mmc) 1534 return -ENOMEM; 1535 1536 ret = mmci_of_parse(np, mmc); 1537 if (ret) 1538 goto host_free; 1539 1540 host = mmc_priv(mmc); 1541 host->mmc = mmc; 1542 1543 host->hw_designer = amba_manf(dev); 1544 host->hw_revision = amba_rev(dev); 1545 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1546 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1547 1548 host->clk = devm_clk_get(&dev->dev, NULL); 1549 if (IS_ERR(host->clk)) { 1550 ret = PTR_ERR(host->clk); 1551 goto host_free; 1552 } 1553 1554 ret = clk_prepare_enable(host->clk); 1555 if (ret) 1556 goto host_free; 1557 1558 if (variant->qcom_fifo) 1559 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1560 else 1561 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1562 1563 host->plat = plat; 1564 host->variant = variant; 1565 host->mclk = clk_get_rate(host->clk); 1566 /* 1567 * According to the spec, mclk is max 100 MHz, 1568 * so we try to adjust the clock down to this, 1569 * (if possible). 1570 */ 1571 if (host->mclk > variant->f_max) { 1572 ret = clk_set_rate(host->clk, variant->f_max); 1573 if (ret < 0) 1574 goto clk_disable; 1575 host->mclk = clk_get_rate(host->clk); 1576 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1577 host->mclk); 1578 } 1579 1580 host->phybase = dev->res.start; 1581 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1582 if (IS_ERR(host->base)) { 1583 ret = PTR_ERR(host->base); 1584 goto clk_disable; 1585 } 1586 1587 /* 1588 * The ARM and ST versions of the block have slightly different 1589 * clock divider equations which means that the minimum divider 1590 * differs too. 1591 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1592 */ 1593 if (variant->st_clkdiv) 1594 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1595 else if (variant->explicit_mclk_control) 1596 mmc->f_min = clk_round_rate(host->clk, 100000); 1597 else 1598 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1599 /* 1600 * If no maximum operating frequency is supplied, fall back to use 1601 * the module parameter, which has a (low) default value in case it 1602 * is not specified. Either value must not exceed the clock rate into 1603 * the block, of course. 1604 */ 1605 if (mmc->f_max) 1606 mmc->f_max = variant->explicit_mclk_control ? 1607 min(variant->f_max, mmc->f_max) : 1608 min(host->mclk, mmc->f_max); 1609 else 1610 mmc->f_max = variant->explicit_mclk_control ? 1611 fmax : min(host->mclk, fmax); 1612 1613 1614 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1615 1616 /* Get regulators and the supported OCR mask */ 1617 ret = mmc_regulator_get_supply(mmc); 1618 if (ret == -EPROBE_DEFER) 1619 goto clk_disable; 1620 1621 if (!mmc->ocr_avail) 1622 mmc->ocr_avail = plat->ocr_mask; 1623 else if (plat->ocr_mask) 1624 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1625 1626 /* DT takes precedence over platform data. */ 1627 if (!np) { 1628 if (!plat->cd_invert) 1629 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1630 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1631 } 1632 1633 /* We support these capabilities. */ 1634 mmc->caps |= MMC_CAP_CMD23; 1635 1636 if (variant->busy_detect) { 1637 mmci_ops.card_busy = mmci_card_busy; 1638 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1639 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1640 mmc->max_busy_timeout = 0; 1641 } 1642 1643 mmc->ops = &mmci_ops; 1644 1645 /* We support these PM capabilities. */ 1646 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1647 1648 /* 1649 * We can do SGIO 1650 */ 1651 mmc->max_segs = NR_SG; 1652 1653 /* 1654 * Since only a certain number of bits are valid in the data length 1655 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1656 * single request. 1657 */ 1658 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1659 1660 /* 1661 * Set the maximum segment size. Since we aren't doing DMA 1662 * (yet) we are only limited by the data length register. 1663 */ 1664 mmc->max_seg_size = mmc->max_req_size; 1665 1666 /* 1667 * Block size can be up to 2048 bytes, but must be a power of two. 1668 */ 1669 mmc->max_blk_size = 1 << 11; 1670 1671 /* 1672 * Limit the number of blocks transferred so that we don't overflow 1673 * the maximum request size. 1674 */ 1675 mmc->max_blk_count = mmc->max_req_size >> 11; 1676 1677 spin_lock_init(&host->lock); 1678 1679 writel(0, host->base + MMCIMASK0); 1680 writel(0, host->base + MMCIMASK1); 1681 writel(0xfff, host->base + MMCICLEAR); 1682 1683 /* 1684 * If: 1685 * - not using DT but using a descriptor table, or 1686 * - using a table of descriptors ALONGSIDE DT, or 1687 * look up these descriptors named "cd" and "wp" right here, fail 1688 * silently of these do not exist and proceed to try platform data 1689 */ 1690 if (!np) { 1691 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1692 if (ret < 0) { 1693 if (ret == -EPROBE_DEFER) 1694 goto clk_disable; 1695 else if (gpio_is_valid(plat->gpio_cd)) { 1696 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1697 if (ret) 1698 goto clk_disable; 1699 } 1700 } 1701 1702 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1703 if (ret < 0) { 1704 if (ret == -EPROBE_DEFER) 1705 goto clk_disable; 1706 else if (gpio_is_valid(plat->gpio_wp)) { 1707 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1708 if (ret) 1709 goto clk_disable; 1710 } 1711 } 1712 } 1713 1714 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1715 DRIVER_NAME " (cmd)", host); 1716 if (ret) 1717 goto clk_disable; 1718 1719 if (!dev->irq[1]) 1720 host->singleirq = true; 1721 else { 1722 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1723 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1724 if (ret) 1725 goto clk_disable; 1726 } 1727 1728 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1729 1730 amba_set_drvdata(dev, mmc); 1731 1732 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1733 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1734 amba_rev(dev), (unsigned long long)dev->res.start, 1735 dev->irq[0], dev->irq[1]); 1736 1737 mmci_dma_setup(host); 1738 1739 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1740 pm_runtime_use_autosuspend(&dev->dev); 1741 1742 mmc_add_host(mmc); 1743 1744 pm_runtime_put(&dev->dev); 1745 return 0; 1746 1747 clk_disable: 1748 clk_disable_unprepare(host->clk); 1749 host_free: 1750 mmc_free_host(mmc); 1751 return ret; 1752 } 1753 1754 static int mmci_remove(struct amba_device *dev) 1755 { 1756 struct mmc_host *mmc = amba_get_drvdata(dev); 1757 1758 if (mmc) { 1759 struct mmci_host *host = mmc_priv(mmc); 1760 1761 /* 1762 * Undo pm_runtime_put() in probe. We use the _sync 1763 * version here so that we can access the primecell. 1764 */ 1765 pm_runtime_get_sync(&dev->dev); 1766 1767 mmc_remove_host(mmc); 1768 1769 writel(0, host->base + MMCIMASK0); 1770 writel(0, host->base + MMCIMASK1); 1771 1772 writel(0, host->base + MMCICOMMAND); 1773 writel(0, host->base + MMCIDATACTRL); 1774 1775 mmci_dma_release(host); 1776 clk_disable_unprepare(host->clk); 1777 mmc_free_host(mmc); 1778 } 1779 1780 return 0; 1781 } 1782 1783 #ifdef CONFIG_PM 1784 static void mmci_save(struct mmci_host *host) 1785 { 1786 unsigned long flags; 1787 1788 spin_lock_irqsave(&host->lock, flags); 1789 1790 writel(0, host->base + MMCIMASK0); 1791 if (host->variant->pwrreg_nopower) { 1792 writel(0, host->base + MMCIDATACTRL); 1793 writel(0, host->base + MMCIPOWER); 1794 writel(0, host->base + MMCICLOCK); 1795 } 1796 mmci_reg_delay(host); 1797 1798 spin_unlock_irqrestore(&host->lock, flags); 1799 } 1800 1801 static void mmci_restore(struct mmci_host *host) 1802 { 1803 unsigned long flags; 1804 1805 spin_lock_irqsave(&host->lock, flags); 1806 1807 if (host->variant->pwrreg_nopower) { 1808 writel(host->clk_reg, host->base + MMCICLOCK); 1809 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1810 writel(host->pwr_reg, host->base + MMCIPOWER); 1811 } 1812 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1813 mmci_reg_delay(host); 1814 1815 spin_unlock_irqrestore(&host->lock, flags); 1816 } 1817 1818 static int mmci_runtime_suspend(struct device *dev) 1819 { 1820 struct amba_device *adev = to_amba_device(dev); 1821 struct mmc_host *mmc = amba_get_drvdata(adev); 1822 1823 if (mmc) { 1824 struct mmci_host *host = mmc_priv(mmc); 1825 pinctrl_pm_select_sleep_state(dev); 1826 mmci_save(host); 1827 clk_disable_unprepare(host->clk); 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int mmci_runtime_resume(struct device *dev) 1834 { 1835 struct amba_device *adev = to_amba_device(dev); 1836 struct mmc_host *mmc = amba_get_drvdata(adev); 1837 1838 if (mmc) { 1839 struct mmci_host *host = mmc_priv(mmc); 1840 clk_prepare_enable(host->clk); 1841 mmci_restore(host); 1842 pinctrl_pm_select_default_state(dev); 1843 } 1844 1845 return 0; 1846 } 1847 #endif 1848 1849 static const struct dev_pm_ops mmci_dev_pm_ops = { 1850 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1851 pm_runtime_force_resume) 1852 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1853 }; 1854 1855 static struct amba_id mmci_ids[] = { 1856 { 1857 .id = 0x00041180, 1858 .mask = 0xff0fffff, 1859 .data = &variant_arm, 1860 }, 1861 { 1862 .id = 0x01041180, 1863 .mask = 0xff0fffff, 1864 .data = &variant_arm_extended_fifo, 1865 }, 1866 { 1867 .id = 0x02041180, 1868 .mask = 0xff0fffff, 1869 .data = &variant_arm_extended_fifo_hwfc, 1870 }, 1871 { 1872 .id = 0x00041181, 1873 .mask = 0x000fffff, 1874 .data = &variant_arm, 1875 }, 1876 /* ST Micro variants */ 1877 { 1878 .id = 0x00180180, 1879 .mask = 0x00ffffff, 1880 .data = &variant_u300, 1881 }, 1882 { 1883 .id = 0x10180180, 1884 .mask = 0xf0ffffff, 1885 .data = &variant_nomadik, 1886 }, 1887 { 1888 .id = 0x00280180, 1889 .mask = 0x00ffffff, 1890 .data = &variant_nomadik, 1891 }, 1892 { 1893 .id = 0x00480180, 1894 .mask = 0xf0ffffff, 1895 .data = &variant_ux500, 1896 }, 1897 { 1898 .id = 0x10480180, 1899 .mask = 0xf0ffffff, 1900 .data = &variant_ux500v2, 1901 }, 1902 /* Qualcomm variants */ 1903 { 1904 .id = 0x00051180, 1905 .mask = 0x000fffff, 1906 .data = &variant_qcom, 1907 }, 1908 { 0, 0 }, 1909 }; 1910 1911 MODULE_DEVICE_TABLE(amba, mmci_ids); 1912 1913 static struct amba_driver mmci_driver = { 1914 .drv = { 1915 .name = DRIVER_NAME, 1916 .pm = &mmci_dev_pm_ops, 1917 }, 1918 .probe = mmci_probe, 1919 .remove = mmci_remove, 1920 .id_table = mmci_ids, 1921 }; 1922 1923 module_amba_driver(mmci_driver); 1924 1925 module_param(fmax, uint, 0444); 1926 1927 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1928 MODULE_LICENSE("GPL"); 1929