1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/moduleparam.h> 12 #include <linux/init.h> 13 #include <linux/ioport.h> 14 #include <linux/device.h> 15 #include <linux/interrupt.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/highmem.h> 19 #include <linux/log2.h> 20 #include <linux/mmc/host.h> 21 #include <linux/amba/bus.h> 22 #include <linux/clk.h> 23 #include <linux/scatterlist.h> 24 25 #include <asm/cacheflush.h> 26 #include <asm/div64.h> 27 #include <asm/io.h> 28 #include <asm/sizes.h> 29 #include <asm/mach/mmc.h> 30 31 #include "mmci.h" 32 33 #define DRIVER_NAME "mmci-pl18x" 34 35 #define DBG(host,fmt,args...) \ 36 pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) 37 38 static unsigned int fmax = 515633; 39 40 static void 41 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 42 { 43 writel(0, host->base + MMCICOMMAND); 44 45 BUG_ON(host->data); 46 47 host->mrq = NULL; 48 host->cmd = NULL; 49 50 if (mrq->data) 51 mrq->data->bytes_xfered = host->data_xfered; 52 53 /* 54 * Need to drop the host lock here; mmc_request_done may call 55 * back into the driver... 56 */ 57 spin_unlock(&host->lock); 58 mmc_request_done(host->mmc, mrq); 59 spin_lock(&host->lock); 60 } 61 62 static void mmci_stop_data(struct mmci_host *host) 63 { 64 writel(0, host->base + MMCIDATACTRL); 65 writel(0, host->base + MMCIMASK1); 66 host->data = NULL; 67 } 68 69 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 70 { 71 unsigned int datactrl, timeout, irqmask; 72 unsigned long long clks; 73 void __iomem *base; 74 int blksz_bits; 75 76 DBG(host, "blksz %04x blks %04x flags %08x\n", 77 data->blksz, data->blocks, data->flags); 78 79 host->data = data; 80 host->size = data->blksz; 81 host->data_xfered = 0; 82 83 mmci_init_sg(host, data); 84 85 clks = (unsigned long long)data->timeout_ns * host->cclk; 86 do_div(clks, 1000000000UL); 87 88 timeout = data->timeout_clks + (unsigned int)clks; 89 90 base = host->base; 91 writel(timeout, base + MMCIDATATIMER); 92 writel(host->size, base + MMCIDATALENGTH); 93 94 blksz_bits = ffs(data->blksz) - 1; 95 BUG_ON(1 << blksz_bits != data->blksz); 96 97 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 98 if (data->flags & MMC_DATA_READ) { 99 datactrl |= MCI_DPSM_DIRECTION; 100 irqmask = MCI_RXFIFOHALFFULLMASK; 101 102 /* 103 * If we have less than a FIFOSIZE of bytes to transfer, 104 * trigger a PIO interrupt as soon as any data is available. 105 */ 106 if (host->size < MCI_FIFOSIZE) 107 irqmask |= MCI_RXDATAAVLBLMASK; 108 } else { 109 /* 110 * We don't actually need to include "FIFO empty" here 111 * since its implicit in "FIFO half empty". 112 */ 113 irqmask = MCI_TXFIFOHALFEMPTYMASK; 114 } 115 116 writel(datactrl, base + MMCIDATACTRL); 117 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 118 writel(irqmask, base + MMCIMASK1); 119 } 120 121 static void 122 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 123 { 124 void __iomem *base = host->base; 125 126 DBG(host, "op %02x arg %08x flags %08x\n", 127 cmd->opcode, cmd->arg, cmd->flags); 128 129 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 130 writel(0, base + MMCICOMMAND); 131 udelay(1); 132 } 133 134 c |= cmd->opcode | MCI_CPSM_ENABLE; 135 if (cmd->flags & MMC_RSP_PRESENT) { 136 if (cmd->flags & MMC_RSP_136) 137 c |= MCI_CPSM_LONGRSP; 138 c |= MCI_CPSM_RESPONSE; 139 } 140 if (/*interrupt*/0) 141 c |= MCI_CPSM_INTERRUPT; 142 143 host->cmd = cmd; 144 145 writel(cmd->arg, base + MMCIARGUMENT); 146 writel(c, base + MMCICOMMAND); 147 } 148 149 static void 150 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 151 unsigned int status) 152 { 153 if (status & MCI_DATABLOCKEND) { 154 host->data_xfered += data->blksz; 155 } 156 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 157 if (status & MCI_DATACRCFAIL) 158 data->error = -EILSEQ; 159 else if (status & MCI_DATATIMEOUT) 160 data->error = -ETIMEDOUT; 161 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) 162 data->error = -EIO; 163 status |= MCI_DATAEND; 164 165 /* 166 * We hit an error condition. Ensure that any data 167 * partially written to a page is properly coherent. 168 */ 169 if (host->sg_len && data->flags & MMC_DATA_READ) 170 flush_dcache_page(sg_page(host->sg_ptr)); 171 } 172 if (status & MCI_DATAEND) { 173 mmci_stop_data(host); 174 175 if (!data->stop) { 176 mmci_request_end(host, data->mrq); 177 } else { 178 mmci_start_command(host, data->stop, 0); 179 } 180 } 181 } 182 183 static void 184 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 185 unsigned int status) 186 { 187 void __iomem *base = host->base; 188 189 host->cmd = NULL; 190 191 cmd->resp[0] = readl(base + MMCIRESPONSE0); 192 cmd->resp[1] = readl(base + MMCIRESPONSE1); 193 cmd->resp[2] = readl(base + MMCIRESPONSE2); 194 cmd->resp[3] = readl(base + MMCIRESPONSE3); 195 196 if (status & MCI_CMDTIMEOUT) { 197 cmd->error = -ETIMEDOUT; 198 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 199 cmd->error = -EILSEQ; 200 } 201 202 if (!cmd->data || cmd->error) { 203 if (host->data) 204 mmci_stop_data(host); 205 mmci_request_end(host, cmd->mrq); 206 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 207 mmci_start_data(host, cmd->data); 208 } 209 } 210 211 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 212 { 213 void __iomem *base = host->base; 214 char *ptr = buffer; 215 u32 status; 216 int host_remain = host->size; 217 218 do { 219 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 220 221 if (count > remain) 222 count = remain; 223 224 if (count <= 0) 225 break; 226 227 readsl(base + MMCIFIFO, ptr, count >> 2); 228 229 ptr += count; 230 remain -= count; 231 host_remain -= count; 232 233 if (remain == 0) 234 break; 235 236 status = readl(base + MMCISTATUS); 237 } while (status & MCI_RXDATAAVLBL); 238 239 return ptr - buffer; 240 } 241 242 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 243 { 244 void __iomem *base = host->base; 245 char *ptr = buffer; 246 247 do { 248 unsigned int count, maxcnt; 249 250 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; 251 count = min(remain, maxcnt); 252 253 writesl(base + MMCIFIFO, ptr, count >> 2); 254 255 ptr += count; 256 remain -= count; 257 258 if (remain == 0) 259 break; 260 261 status = readl(base + MMCISTATUS); 262 } while (status & MCI_TXFIFOHALFEMPTY); 263 264 return ptr - buffer; 265 } 266 267 /* 268 * PIO data transfer IRQ handler. 269 */ 270 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 271 { 272 struct mmci_host *host = dev_id; 273 void __iomem *base = host->base; 274 u32 status; 275 276 status = readl(base + MMCISTATUS); 277 278 DBG(host, "irq1 %08x\n", status); 279 280 do { 281 unsigned long flags; 282 unsigned int remain, len; 283 char *buffer; 284 285 /* 286 * For write, we only need to test the half-empty flag 287 * here - if the FIFO is completely empty, then by 288 * definition it is more than half empty. 289 * 290 * For read, check for data available. 291 */ 292 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 293 break; 294 295 /* 296 * Map the current scatter buffer. 297 */ 298 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; 299 remain = host->sg_ptr->length - host->sg_off; 300 301 len = 0; 302 if (status & MCI_RXACTIVE) 303 len = mmci_pio_read(host, buffer, remain); 304 if (status & MCI_TXACTIVE) 305 len = mmci_pio_write(host, buffer, remain, status); 306 307 /* 308 * Unmap the buffer. 309 */ 310 mmci_kunmap_atomic(host, buffer, &flags); 311 312 host->sg_off += len; 313 host->size -= len; 314 remain -= len; 315 316 if (remain) 317 break; 318 319 /* 320 * If we were reading, and we have completed this 321 * page, ensure that the data cache is coherent. 322 */ 323 if (status & MCI_RXACTIVE) 324 flush_dcache_page(sg_page(host->sg_ptr)); 325 326 if (!mmci_next_sg(host)) 327 break; 328 329 status = readl(base + MMCISTATUS); 330 } while (1); 331 332 /* 333 * If we're nearing the end of the read, switch to 334 * "any data available" mode. 335 */ 336 if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) 337 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); 338 339 /* 340 * If we run out of data, disable the data IRQs; this 341 * prevents a race where the FIFO becomes empty before 342 * the chip itself has disabled the data path, and 343 * stops us racing with our data end IRQ. 344 */ 345 if (host->size == 0) { 346 writel(0, base + MMCIMASK1); 347 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 348 } 349 350 return IRQ_HANDLED; 351 } 352 353 /* 354 * Handle completion of command and data transfers. 355 */ 356 static irqreturn_t mmci_irq(int irq, void *dev_id) 357 { 358 struct mmci_host *host = dev_id; 359 u32 status; 360 int ret = 0; 361 362 spin_lock(&host->lock); 363 364 do { 365 struct mmc_command *cmd; 366 struct mmc_data *data; 367 368 status = readl(host->base + MMCISTATUS); 369 status &= readl(host->base + MMCIMASK0); 370 writel(status, host->base + MMCICLEAR); 371 372 DBG(host, "irq0 %08x\n", status); 373 374 data = host->data; 375 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 376 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 377 mmci_data_irq(host, data, status); 378 379 cmd = host->cmd; 380 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 381 mmci_cmd_irq(host, cmd, status); 382 383 ret = 1; 384 } while (status); 385 386 spin_unlock(&host->lock); 387 388 return IRQ_RETVAL(ret); 389 } 390 391 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 392 { 393 struct mmci_host *host = mmc_priv(mmc); 394 unsigned long flags; 395 396 WARN_ON(host->mrq != NULL); 397 398 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 399 printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n", 400 mmc_hostname(mmc), mrq->data->blksz); 401 mrq->cmd->error = -EINVAL; 402 mmc_request_done(mmc, mrq); 403 return; 404 } 405 406 spin_lock_irqsave(&host->lock, flags); 407 408 host->mrq = mrq; 409 410 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 411 mmci_start_data(host, mrq->data); 412 413 mmci_start_command(host, mrq->cmd, 0); 414 415 spin_unlock_irqrestore(&host->lock, flags); 416 } 417 418 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 419 { 420 struct mmci_host *host = mmc_priv(mmc); 421 u32 clk = 0, pwr = 0; 422 423 if (ios->clock) { 424 if (ios->clock >= host->mclk) { 425 clk = MCI_CLK_BYPASS; 426 host->cclk = host->mclk; 427 } else { 428 clk = host->mclk / (2 * ios->clock) - 1; 429 if (clk >= 256) 430 clk = 255; 431 host->cclk = host->mclk / (2 * (clk + 1)); 432 } 433 clk |= MCI_CLK_ENABLE; 434 } 435 436 if (host->plat->translate_vdd) 437 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); 438 439 switch (ios->power_mode) { 440 case MMC_POWER_OFF: 441 break; 442 case MMC_POWER_UP: 443 pwr |= MCI_PWR_UP; 444 break; 445 case MMC_POWER_ON: 446 pwr |= MCI_PWR_ON; 447 break; 448 } 449 450 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 451 pwr |= MCI_ROD; 452 453 writel(clk, host->base + MMCICLOCK); 454 455 if (host->pwr != pwr) { 456 host->pwr = pwr; 457 writel(pwr, host->base + MMCIPOWER); 458 } 459 } 460 461 static const struct mmc_host_ops mmci_ops = { 462 .request = mmci_request, 463 .set_ios = mmci_set_ios, 464 }; 465 466 static void mmci_check_status(unsigned long data) 467 { 468 struct mmci_host *host = (struct mmci_host *)data; 469 unsigned int status; 470 471 status = host->plat->status(mmc_dev(host->mmc)); 472 if (status ^ host->oldstat) 473 mmc_detect_change(host->mmc, 0); 474 475 host->oldstat = status; 476 mod_timer(&host->timer, jiffies + HZ); 477 } 478 479 static int mmci_probe(struct amba_device *dev, void *id) 480 { 481 struct mmc_platform_data *plat = dev->dev.platform_data; 482 struct mmci_host *host; 483 struct mmc_host *mmc; 484 int ret; 485 486 /* must have platform data */ 487 if (!plat) { 488 ret = -EINVAL; 489 goto out; 490 } 491 492 ret = amba_request_regions(dev, DRIVER_NAME); 493 if (ret) 494 goto out; 495 496 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 497 if (!mmc) { 498 ret = -ENOMEM; 499 goto rel_regions; 500 } 501 502 host = mmc_priv(mmc); 503 host->clk = clk_get(&dev->dev, "MCLK"); 504 if (IS_ERR(host->clk)) { 505 ret = PTR_ERR(host->clk); 506 host->clk = NULL; 507 goto host_free; 508 } 509 510 ret = clk_enable(host->clk); 511 if (ret) 512 goto clk_free; 513 514 host->plat = plat; 515 host->mclk = clk_get_rate(host->clk); 516 /* 517 * According to the spec, mclk is max 100 MHz, 518 * so we try to adjust the clock down to this, 519 * (if possible). 520 */ 521 if (host->mclk > 100000000) { 522 ret = clk_set_rate(host->clk, 100000000); 523 if (ret < 0) 524 goto clk_disable; 525 host->mclk = clk_get_rate(host->clk); 526 DBG(host, "eventual mclk rate: %u Hz\n", host->mclk); 527 } 528 host->mmc = mmc; 529 host->base = ioremap(dev->res.start, SZ_4K); 530 if (!host->base) { 531 ret = -ENOMEM; 532 goto clk_disable; 533 } 534 535 mmc->ops = &mmci_ops; 536 mmc->f_min = (host->mclk + 511) / 512; 537 mmc->f_max = min(host->mclk, fmax); 538 mmc->ocr_avail = plat->ocr_mask; 539 540 /* 541 * We can do SGIO 542 */ 543 mmc->max_hw_segs = 16; 544 mmc->max_phys_segs = NR_SG; 545 546 /* 547 * Since we only have a 16-bit data length register, we must 548 * ensure that we don't exceed 2^16-1 bytes in a single request. 549 */ 550 mmc->max_req_size = 65535; 551 552 /* 553 * Set the maximum segment size. Since we aren't doing DMA 554 * (yet) we are only limited by the data length register. 555 */ 556 mmc->max_seg_size = mmc->max_req_size; 557 558 /* 559 * Block size can be up to 2048 bytes, but must be a power of two. 560 */ 561 mmc->max_blk_size = 2048; 562 563 /* 564 * No limit on the number of blocks transferred. 565 */ 566 mmc->max_blk_count = mmc->max_req_size; 567 568 spin_lock_init(&host->lock); 569 570 writel(0, host->base + MMCIMASK0); 571 writel(0, host->base + MMCIMASK1); 572 writel(0xfff, host->base + MMCICLEAR); 573 574 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 575 if (ret) 576 goto unmap; 577 578 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); 579 if (ret) 580 goto irq0_free; 581 582 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 583 584 amba_set_drvdata(dev, mmc); 585 586 mmc_add_host(mmc); 587 588 printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", 589 mmc_hostname(mmc), amba_rev(dev), amba_config(dev), 590 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 591 592 init_timer(&host->timer); 593 host->timer.data = (unsigned long)host; 594 host->timer.function = mmci_check_status; 595 host->timer.expires = jiffies + HZ; 596 add_timer(&host->timer); 597 598 return 0; 599 600 irq0_free: 601 free_irq(dev->irq[0], host); 602 unmap: 603 iounmap(host->base); 604 clk_disable: 605 clk_disable(host->clk); 606 clk_free: 607 clk_put(host->clk); 608 host_free: 609 mmc_free_host(mmc); 610 rel_regions: 611 amba_release_regions(dev); 612 out: 613 return ret; 614 } 615 616 static int mmci_remove(struct amba_device *dev) 617 { 618 struct mmc_host *mmc = amba_get_drvdata(dev); 619 620 amba_set_drvdata(dev, NULL); 621 622 if (mmc) { 623 struct mmci_host *host = mmc_priv(mmc); 624 625 del_timer_sync(&host->timer); 626 627 mmc_remove_host(mmc); 628 629 writel(0, host->base + MMCIMASK0); 630 writel(0, host->base + MMCIMASK1); 631 632 writel(0, host->base + MMCICOMMAND); 633 writel(0, host->base + MMCIDATACTRL); 634 635 free_irq(dev->irq[0], host); 636 free_irq(dev->irq[1], host); 637 638 iounmap(host->base); 639 clk_disable(host->clk); 640 clk_put(host->clk); 641 642 mmc_free_host(mmc); 643 644 amba_release_regions(dev); 645 } 646 647 return 0; 648 } 649 650 #ifdef CONFIG_PM 651 static int mmci_suspend(struct amba_device *dev, pm_message_t state) 652 { 653 struct mmc_host *mmc = amba_get_drvdata(dev); 654 int ret = 0; 655 656 if (mmc) { 657 struct mmci_host *host = mmc_priv(mmc); 658 659 ret = mmc_suspend_host(mmc, state); 660 if (ret == 0) 661 writel(0, host->base + MMCIMASK0); 662 } 663 664 return ret; 665 } 666 667 static int mmci_resume(struct amba_device *dev) 668 { 669 struct mmc_host *mmc = amba_get_drvdata(dev); 670 int ret = 0; 671 672 if (mmc) { 673 struct mmci_host *host = mmc_priv(mmc); 674 675 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 676 677 ret = mmc_resume_host(mmc); 678 } 679 680 return ret; 681 } 682 #else 683 #define mmci_suspend NULL 684 #define mmci_resume NULL 685 #endif 686 687 static struct amba_id mmci_ids[] = { 688 { 689 .id = 0x00041180, 690 .mask = 0x000fffff, 691 }, 692 { 693 .id = 0x00041181, 694 .mask = 0x000fffff, 695 }, 696 { 0, 0 }, 697 }; 698 699 static struct amba_driver mmci_driver = { 700 .drv = { 701 .name = DRIVER_NAME, 702 }, 703 .probe = mmci_probe, 704 .remove = mmci_remove, 705 .suspend = mmci_suspend, 706 .resume = mmci_resume, 707 .id_table = mmci_ids, 708 }; 709 710 static int __init mmci_init(void) 711 { 712 return amba_driver_register(&mmci_driver); 713 } 714 715 static void __exit mmci_exit(void) 716 { 717 amba_driver_unregister(&mmci_driver); 718 } 719 720 module_init(mmci_init); 721 module_exit(mmci_exit); 722 module_param(fmax, uint, 0444); 723 724 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 725 MODULE_LICENSE("GPL"); 726