1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/of.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 #include <linux/reset.h> 39 40 #include <asm/div64.h> 41 #include <asm/io.h> 42 43 #include "mmci.h" 44 45 #define DRIVER_NAME "mmci-pl18x" 46 47 static void mmci_variant_init(struct mmci_host *host); 48 static void ux500_variant_init(struct mmci_host *host); 49 static void ux500v2_variant_init(struct mmci_host *host); 50 51 static unsigned int fmax = 515633; 52 53 static struct variant_data variant_arm = { 54 .fifosize = 16 * 4, 55 .fifohalfsize = 8 * 4, 56 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 57 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 58 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 59 .cmdreg_srsp = MCI_CPSM_RESPONSE, 60 .datalength_bits = 16, 61 .datactrl_blocksz = 11, 62 .pwrreg_powerup = MCI_PWR_UP, 63 .f_max = 100000000, 64 .reversed_irq_handling = true, 65 .mmcimask1 = true, 66 .irq_pio_mask = MCI_IRQ_PIO_MASK, 67 .start_err = MCI_STARTBITERR, 68 .opendrain = MCI_ROD, 69 .init = mmci_variant_init, 70 }; 71 72 static struct variant_data variant_arm_extended_fifo = { 73 .fifosize = 128 * 4, 74 .fifohalfsize = 64 * 4, 75 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 76 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 77 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 78 .cmdreg_srsp = MCI_CPSM_RESPONSE, 79 .datalength_bits = 16, 80 .datactrl_blocksz = 11, 81 .pwrreg_powerup = MCI_PWR_UP, 82 .f_max = 100000000, 83 .mmcimask1 = true, 84 .irq_pio_mask = MCI_IRQ_PIO_MASK, 85 .start_err = MCI_STARTBITERR, 86 .opendrain = MCI_ROD, 87 .init = mmci_variant_init, 88 }; 89 90 static struct variant_data variant_arm_extended_fifo_hwfc = { 91 .fifosize = 128 * 4, 92 .fifohalfsize = 64 * 4, 93 .clkreg_enable = MCI_ARM_HWFCEN, 94 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 95 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 96 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 97 .cmdreg_srsp = MCI_CPSM_RESPONSE, 98 .datalength_bits = 16, 99 .datactrl_blocksz = 11, 100 .pwrreg_powerup = MCI_PWR_UP, 101 .f_max = 100000000, 102 .mmcimask1 = true, 103 .irq_pio_mask = MCI_IRQ_PIO_MASK, 104 .start_err = MCI_STARTBITERR, 105 .opendrain = MCI_ROD, 106 .init = mmci_variant_init, 107 }; 108 109 static struct variant_data variant_u300 = { 110 .fifosize = 16 * 4, 111 .fifohalfsize = 8 * 4, 112 .clkreg_enable = MCI_ST_U300_HWFCEN, 113 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 114 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 115 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 116 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 117 .cmdreg_srsp = MCI_CPSM_RESPONSE, 118 .datalength_bits = 16, 119 .datactrl_blocksz = 11, 120 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 121 .st_sdio = true, 122 .pwrreg_powerup = MCI_PWR_ON, 123 .f_max = 100000000, 124 .signal_direction = true, 125 .pwrreg_clkgate = true, 126 .pwrreg_nopower = true, 127 .mmcimask1 = true, 128 .irq_pio_mask = MCI_IRQ_PIO_MASK, 129 .start_err = MCI_STARTBITERR, 130 .opendrain = MCI_OD, 131 .init = mmci_variant_init, 132 }; 133 134 static struct variant_data variant_nomadik = { 135 .fifosize = 16 * 4, 136 .fifohalfsize = 8 * 4, 137 .clkreg = MCI_CLK_ENABLE, 138 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 139 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 140 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 141 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 142 .cmdreg_srsp = MCI_CPSM_RESPONSE, 143 .datalength_bits = 24, 144 .datactrl_blocksz = 11, 145 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 146 .st_sdio = true, 147 .st_clkdiv = true, 148 .pwrreg_powerup = MCI_PWR_ON, 149 .f_max = 100000000, 150 .signal_direction = true, 151 .pwrreg_clkgate = true, 152 .pwrreg_nopower = true, 153 .mmcimask1 = true, 154 .irq_pio_mask = MCI_IRQ_PIO_MASK, 155 .start_err = MCI_STARTBITERR, 156 .opendrain = MCI_OD, 157 .init = mmci_variant_init, 158 }; 159 160 static struct variant_data variant_ux500 = { 161 .fifosize = 30 * 4, 162 .fifohalfsize = 8 * 4, 163 .clkreg = MCI_CLK_ENABLE, 164 .clkreg_enable = MCI_ST_UX500_HWFCEN, 165 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 166 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 167 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 168 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 169 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 170 .cmdreg_srsp = MCI_CPSM_RESPONSE, 171 .datalength_bits = 24, 172 .datactrl_blocksz = 11, 173 .datactrl_any_blocksz = true, 174 .dma_power_of_2 = true, 175 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 176 .st_sdio = true, 177 .st_clkdiv = true, 178 .pwrreg_powerup = MCI_PWR_ON, 179 .f_max = 100000000, 180 .signal_direction = true, 181 .pwrreg_clkgate = true, 182 .busy_detect = true, 183 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 184 .busy_detect_flag = MCI_ST_CARDBUSY, 185 .busy_detect_mask = MCI_ST_BUSYENDMASK, 186 .pwrreg_nopower = true, 187 .mmcimask1 = true, 188 .irq_pio_mask = MCI_IRQ_PIO_MASK, 189 .start_err = MCI_STARTBITERR, 190 .opendrain = MCI_OD, 191 .init = ux500_variant_init, 192 }; 193 194 static struct variant_data variant_ux500v2 = { 195 .fifosize = 30 * 4, 196 .fifohalfsize = 8 * 4, 197 .clkreg = MCI_CLK_ENABLE, 198 .clkreg_enable = MCI_ST_UX500_HWFCEN, 199 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 200 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 201 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 202 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 203 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 204 .cmdreg_srsp = MCI_CPSM_RESPONSE, 205 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 206 .datalength_bits = 24, 207 .datactrl_blocksz = 11, 208 .datactrl_any_blocksz = true, 209 .dma_power_of_2 = true, 210 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 211 .st_sdio = true, 212 .st_clkdiv = true, 213 .pwrreg_powerup = MCI_PWR_ON, 214 .f_max = 100000000, 215 .signal_direction = true, 216 .pwrreg_clkgate = true, 217 .busy_detect = true, 218 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 219 .busy_detect_flag = MCI_ST_CARDBUSY, 220 .busy_detect_mask = MCI_ST_BUSYENDMASK, 221 .pwrreg_nopower = true, 222 .mmcimask1 = true, 223 .irq_pio_mask = MCI_IRQ_PIO_MASK, 224 .start_err = MCI_STARTBITERR, 225 .opendrain = MCI_OD, 226 .init = ux500v2_variant_init, 227 }; 228 229 static struct variant_data variant_stm32 = { 230 .fifosize = 32 * 4, 231 .fifohalfsize = 8 * 4, 232 .clkreg = MCI_CLK_ENABLE, 233 .clkreg_enable = MCI_ST_UX500_HWFCEN, 234 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 235 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 236 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 237 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 238 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 239 .cmdreg_srsp = MCI_CPSM_RESPONSE, 240 .irq_pio_mask = MCI_IRQ_PIO_MASK, 241 .datalength_bits = 24, 242 .datactrl_blocksz = 11, 243 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 244 .st_sdio = true, 245 .st_clkdiv = true, 246 .pwrreg_powerup = MCI_PWR_ON, 247 .f_max = 48000000, 248 .pwrreg_clkgate = true, 249 .pwrreg_nopower = true, 250 .init = mmci_variant_init, 251 }; 252 253 static struct variant_data variant_stm32_sdmmc = { 254 .fifosize = 16 * 4, 255 .fifohalfsize = 8 * 4, 256 .f_max = 208000000, 257 .stm32_clkdiv = true, 258 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 259 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 260 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 261 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 262 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 263 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 264 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 265 .datactrl_first = true, 266 .datacnt_useless = true, 267 .datalength_bits = 25, 268 .datactrl_blocksz = 14, 269 .datactrl_any_blocksz = true, 270 .stm32_idmabsize_mask = GENMASK(12, 5), 271 .busy_timeout = true, 272 .busy_detect = true, 273 .busy_detect_flag = MCI_STM32_BUSYD0, 274 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 275 .init = sdmmc_variant_init, 276 }; 277 278 static struct variant_data variant_stm32_sdmmcv2 = { 279 .fifosize = 16 * 4, 280 .fifohalfsize = 8 * 4, 281 .f_max = 208000000, 282 .stm32_clkdiv = true, 283 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 284 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 285 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 286 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 287 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 288 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 289 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 290 .datactrl_first = true, 291 .datacnt_useless = true, 292 .datalength_bits = 25, 293 .datactrl_blocksz = 14, 294 .datactrl_any_blocksz = true, 295 .stm32_idmabsize_mask = GENMASK(16, 5), 296 .dma_lli = true, 297 .busy_timeout = true, 298 .busy_detect = true, 299 .busy_detect_flag = MCI_STM32_BUSYD0, 300 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 301 .init = sdmmc_variant_init, 302 }; 303 304 static struct variant_data variant_qcom = { 305 .fifosize = 16 * 4, 306 .fifohalfsize = 8 * 4, 307 .clkreg = MCI_CLK_ENABLE, 308 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 309 MCI_QCOM_CLK_SELECT_IN_FBCLK, 310 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 311 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 312 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 313 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 314 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 315 .cmdreg_srsp = MCI_CPSM_RESPONSE, 316 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 317 .datalength_bits = 24, 318 .datactrl_blocksz = 11, 319 .datactrl_any_blocksz = true, 320 .pwrreg_powerup = MCI_PWR_UP, 321 .f_max = 208000000, 322 .explicit_mclk_control = true, 323 .qcom_fifo = true, 324 .qcom_dml = true, 325 .mmcimask1 = true, 326 .irq_pio_mask = MCI_IRQ_PIO_MASK, 327 .start_err = MCI_STARTBITERR, 328 .opendrain = MCI_ROD, 329 .init = qcom_variant_init, 330 }; 331 332 /* Busy detection for the ST Micro variant */ 333 static int mmci_card_busy(struct mmc_host *mmc) 334 { 335 struct mmci_host *host = mmc_priv(mmc); 336 unsigned long flags; 337 int busy = 0; 338 339 spin_lock_irqsave(&host->lock, flags); 340 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 341 busy = 1; 342 spin_unlock_irqrestore(&host->lock, flags); 343 344 return busy; 345 } 346 347 static void mmci_reg_delay(struct mmci_host *host) 348 { 349 /* 350 * According to the spec, at least three feedback clock cycles 351 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 352 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 353 * Worst delay time during card init is at 100 kHz => 30 us. 354 * Worst delay time when up and running is at 25 MHz => 120 ns. 355 */ 356 if (host->cclk < 25000000) 357 udelay(30); 358 else 359 ndelay(120); 360 } 361 362 /* 363 * This must be called with host->lock held 364 */ 365 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 366 { 367 if (host->clk_reg != clk) { 368 host->clk_reg = clk; 369 writel(clk, host->base + MMCICLOCK); 370 } 371 } 372 373 /* 374 * This must be called with host->lock held 375 */ 376 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 377 { 378 if (host->pwr_reg != pwr) { 379 host->pwr_reg = pwr; 380 writel(pwr, host->base + MMCIPOWER); 381 } 382 } 383 384 /* 385 * This must be called with host->lock held 386 */ 387 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 388 { 389 /* Keep busy mode in DPSM if enabled */ 390 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 391 392 if (host->datactrl_reg != datactrl) { 393 host->datactrl_reg = datactrl; 394 writel(datactrl, host->base + MMCIDATACTRL); 395 } 396 } 397 398 /* 399 * This must be called with host->lock held 400 */ 401 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 402 { 403 struct variant_data *variant = host->variant; 404 u32 clk = variant->clkreg; 405 406 /* Make sure cclk reflects the current calculated clock */ 407 host->cclk = 0; 408 409 if (desired) { 410 if (variant->explicit_mclk_control) { 411 host->cclk = host->mclk; 412 } else if (desired >= host->mclk) { 413 clk = MCI_CLK_BYPASS; 414 if (variant->st_clkdiv) 415 clk |= MCI_ST_UX500_NEG_EDGE; 416 host->cclk = host->mclk; 417 } else if (variant->st_clkdiv) { 418 /* 419 * DB8500 TRM says f = mclk / (clkdiv + 2) 420 * => clkdiv = (mclk / f) - 2 421 * Round the divider up so we don't exceed the max 422 * frequency 423 */ 424 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 425 if (clk >= 256) 426 clk = 255; 427 host->cclk = host->mclk / (clk + 2); 428 } else { 429 /* 430 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 431 * => clkdiv = mclk / (2 * f) - 1 432 */ 433 clk = host->mclk / (2 * desired) - 1; 434 if (clk >= 256) 435 clk = 255; 436 host->cclk = host->mclk / (2 * (clk + 1)); 437 } 438 439 clk |= variant->clkreg_enable; 440 clk |= MCI_CLK_ENABLE; 441 /* This hasn't proven to be worthwhile */ 442 /* clk |= MCI_CLK_PWRSAVE; */ 443 } 444 445 /* Set actual clock for debug */ 446 host->mmc->actual_clock = host->cclk; 447 448 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 449 clk |= MCI_4BIT_BUS; 450 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 451 clk |= variant->clkreg_8bit_bus_enable; 452 453 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 454 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 455 clk |= variant->clkreg_neg_edge_enable; 456 457 mmci_write_clkreg(host, clk); 458 } 459 460 static void mmci_dma_release(struct mmci_host *host) 461 { 462 if (host->ops && host->ops->dma_release) 463 host->ops->dma_release(host); 464 465 host->use_dma = false; 466 } 467 468 static void mmci_dma_setup(struct mmci_host *host) 469 { 470 if (!host->ops || !host->ops->dma_setup) 471 return; 472 473 if (host->ops->dma_setup(host)) 474 return; 475 476 /* initialize pre request cookie */ 477 host->next_cookie = 1; 478 479 host->use_dma = true; 480 } 481 482 /* 483 * Validate mmc prerequisites 484 */ 485 static int mmci_validate_data(struct mmci_host *host, 486 struct mmc_data *data) 487 { 488 struct variant_data *variant = host->variant; 489 490 if (!data) 491 return 0; 492 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { 493 dev_err(mmc_dev(host->mmc), 494 "unsupported block size (%d bytes)\n", data->blksz); 495 return -EINVAL; 496 } 497 498 if (host->ops && host->ops->validate_data) 499 return host->ops->validate_data(host, data); 500 501 return 0; 502 } 503 504 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 505 { 506 int err; 507 508 if (!host->ops || !host->ops->prep_data) 509 return 0; 510 511 err = host->ops->prep_data(host, data, next); 512 513 if (next && !err) 514 data->host_cookie = ++host->next_cookie < 0 ? 515 1 : host->next_cookie; 516 517 return err; 518 } 519 520 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 521 int err) 522 { 523 if (host->ops && host->ops->unprep_data) 524 host->ops->unprep_data(host, data, err); 525 526 data->host_cookie = 0; 527 } 528 529 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 530 { 531 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 532 533 if (host->ops && host->ops->get_next_data) 534 host->ops->get_next_data(host, data); 535 } 536 537 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 538 { 539 struct mmc_data *data = host->data; 540 int ret; 541 542 if (!host->use_dma) 543 return -EINVAL; 544 545 ret = mmci_prep_data(host, data, false); 546 if (ret) 547 return ret; 548 549 if (!host->ops || !host->ops->dma_start) 550 return -EINVAL; 551 552 /* Okay, go for it. */ 553 dev_vdbg(mmc_dev(host->mmc), 554 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 555 data->sg_len, data->blksz, data->blocks, data->flags); 556 557 ret = host->ops->dma_start(host, &datactrl); 558 if (ret) 559 return ret; 560 561 /* Trigger the DMA transfer */ 562 mmci_write_datactrlreg(host, datactrl); 563 564 /* 565 * Let the MMCI say when the data is ended and it's time 566 * to fire next DMA request. When that happens, MMCI will 567 * call mmci_data_end() 568 */ 569 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 570 host->base + MMCIMASK0); 571 return 0; 572 } 573 574 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 575 { 576 if (!host->use_dma) 577 return; 578 579 if (host->ops && host->ops->dma_finalize) 580 host->ops->dma_finalize(host, data); 581 } 582 583 static void mmci_dma_error(struct mmci_host *host) 584 { 585 if (!host->use_dma) 586 return; 587 588 if (host->ops && host->ops->dma_error) 589 host->ops->dma_error(host); 590 } 591 592 static void 593 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 594 { 595 writel(0, host->base + MMCICOMMAND); 596 597 BUG_ON(host->data); 598 599 host->mrq = NULL; 600 host->cmd = NULL; 601 602 mmc_request_done(host->mmc, mrq); 603 } 604 605 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 606 { 607 void __iomem *base = host->base; 608 struct variant_data *variant = host->variant; 609 610 if (host->singleirq) { 611 unsigned int mask0 = readl(base + MMCIMASK0); 612 613 mask0 &= ~variant->irq_pio_mask; 614 mask0 |= mask; 615 616 writel(mask0, base + MMCIMASK0); 617 } 618 619 if (variant->mmcimask1) 620 writel(mask, base + MMCIMASK1); 621 622 host->mask1_reg = mask; 623 } 624 625 static void mmci_stop_data(struct mmci_host *host) 626 { 627 mmci_write_datactrlreg(host, 0); 628 mmci_set_mask1(host, 0); 629 host->data = NULL; 630 } 631 632 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 633 { 634 unsigned int flags = SG_MITER_ATOMIC; 635 636 if (data->flags & MMC_DATA_READ) 637 flags |= SG_MITER_TO_SG; 638 else 639 flags |= SG_MITER_FROM_SG; 640 641 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 642 } 643 644 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 645 { 646 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 647 } 648 649 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 650 { 651 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 652 } 653 654 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 655 { 656 void __iomem *base = host->base; 657 658 /* 659 * Before unmasking for the busy end IRQ, confirm that the 660 * command was sent successfully. To keep track of having a 661 * command in-progress, waiting for busy signaling to end, 662 * store the status in host->busy_status. 663 * 664 * Note that, the card may need a couple of clock cycles before 665 * it starts signaling busy on DAT0, hence re-read the 666 * MMCISTATUS register here, to allow the busy bit to be set. 667 * Potentially we may even need to poll the register for a 668 * while, to allow it to be set, but tests indicates that it 669 * isn't needed. 670 */ 671 if (!host->busy_status && !(status & err_msk) && 672 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 673 writel(readl(base + MMCIMASK0) | 674 host->variant->busy_detect_mask, 675 base + MMCIMASK0); 676 677 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 678 return false; 679 } 680 681 /* 682 * If there is a command in-progress that has been successfully 683 * sent, then bail out if busy status is set and wait for the 684 * busy end IRQ. 685 * 686 * Note that, the HW triggers an IRQ on both edges while 687 * monitoring DAT0 for busy completion, but there is only one 688 * status bit in MMCISTATUS for the busy state. Therefore 689 * both the start and the end interrupts needs to be cleared, 690 * one after the other. So, clear the busy start IRQ here. 691 */ 692 if (host->busy_status && 693 (status & host->variant->busy_detect_flag)) { 694 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 695 return false; 696 } 697 698 /* 699 * If there is a command in-progress that has been successfully 700 * sent and the busy bit isn't set, it means we have received 701 * the busy end IRQ. Clear and mask the IRQ, then continue to 702 * process the command. 703 */ 704 if (host->busy_status) { 705 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 706 707 writel(readl(base + MMCIMASK0) & 708 ~host->variant->busy_detect_mask, base + MMCIMASK0); 709 host->busy_status = 0; 710 } 711 712 return true; 713 } 714 715 /* 716 * All the DMA operation mode stuff goes inside this ifdef. 717 * This assumes that you have a generic DMA device interface, 718 * no custom DMA interfaces are supported. 719 */ 720 #ifdef CONFIG_DMA_ENGINE 721 struct mmci_dmae_next { 722 struct dma_async_tx_descriptor *desc; 723 struct dma_chan *chan; 724 }; 725 726 struct mmci_dmae_priv { 727 struct dma_chan *cur; 728 struct dma_chan *rx_channel; 729 struct dma_chan *tx_channel; 730 struct dma_async_tx_descriptor *desc_current; 731 struct mmci_dmae_next next_data; 732 }; 733 734 int mmci_dmae_setup(struct mmci_host *host) 735 { 736 const char *rxname, *txname; 737 struct mmci_dmae_priv *dmae; 738 739 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 740 if (!dmae) 741 return -ENOMEM; 742 743 host->dma_priv = dmae; 744 745 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); 746 if (IS_ERR(dmae->rx_channel)) { 747 int ret = PTR_ERR(dmae->rx_channel); 748 dmae->rx_channel = NULL; 749 return ret; 750 } 751 752 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); 753 if (IS_ERR(dmae->tx_channel)) { 754 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) 755 dev_warn(mmc_dev(host->mmc), 756 "Deferred probe for TX channel ignored\n"); 757 dmae->tx_channel = NULL; 758 } 759 760 /* 761 * If only an RX channel is specified, the driver will 762 * attempt to use it bidirectionally, however if it is 763 * is specified but cannot be located, DMA will be disabled. 764 */ 765 if (dmae->rx_channel && !dmae->tx_channel) 766 dmae->tx_channel = dmae->rx_channel; 767 768 if (dmae->rx_channel) 769 rxname = dma_chan_name(dmae->rx_channel); 770 else 771 rxname = "none"; 772 773 if (dmae->tx_channel) 774 txname = dma_chan_name(dmae->tx_channel); 775 else 776 txname = "none"; 777 778 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 779 rxname, txname); 780 781 /* 782 * Limit the maximum segment size in any SG entry according to 783 * the parameters of the DMA engine device. 784 */ 785 if (dmae->tx_channel) { 786 struct device *dev = dmae->tx_channel->device->dev; 787 unsigned int max_seg_size = dma_get_max_seg_size(dev); 788 789 if (max_seg_size < host->mmc->max_seg_size) 790 host->mmc->max_seg_size = max_seg_size; 791 } 792 if (dmae->rx_channel) { 793 struct device *dev = dmae->rx_channel->device->dev; 794 unsigned int max_seg_size = dma_get_max_seg_size(dev); 795 796 if (max_seg_size < host->mmc->max_seg_size) 797 host->mmc->max_seg_size = max_seg_size; 798 } 799 800 if (!dmae->tx_channel || !dmae->rx_channel) { 801 mmci_dmae_release(host); 802 return -EINVAL; 803 } 804 805 return 0; 806 } 807 808 /* 809 * This is used in or so inline it 810 * so it can be discarded. 811 */ 812 void mmci_dmae_release(struct mmci_host *host) 813 { 814 struct mmci_dmae_priv *dmae = host->dma_priv; 815 816 if (dmae->rx_channel) 817 dma_release_channel(dmae->rx_channel); 818 if (dmae->tx_channel) 819 dma_release_channel(dmae->tx_channel); 820 dmae->rx_channel = dmae->tx_channel = NULL; 821 } 822 823 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 824 { 825 struct mmci_dmae_priv *dmae = host->dma_priv; 826 struct dma_chan *chan; 827 828 if (data->flags & MMC_DATA_READ) 829 chan = dmae->rx_channel; 830 else 831 chan = dmae->tx_channel; 832 833 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 834 mmc_get_dma_dir(data)); 835 } 836 837 void mmci_dmae_error(struct mmci_host *host) 838 { 839 struct mmci_dmae_priv *dmae = host->dma_priv; 840 841 if (!dma_inprogress(host)) 842 return; 843 844 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 845 dmaengine_terminate_all(dmae->cur); 846 host->dma_in_progress = false; 847 dmae->cur = NULL; 848 dmae->desc_current = NULL; 849 host->data->host_cookie = 0; 850 851 mmci_dma_unmap(host, host->data); 852 } 853 854 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 855 { 856 struct mmci_dmae_priv *dmae = host->dma_priv; 857 u32 status; 858 int i; 859 860 if (!dma_inprogress(host)) 861 return; 862 863 /* Wait up to 1ms for the DMA to complete */ 864 for (i = 0; ; i++) { 865 status = readl(host->base + MMCISTATUS); 866 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 867 break; 868 udelay(10); 869 } 870 871 /* 872 * Check to see whether we still have some data left in the FIFO - 873 * this catches DMA controllers which are unable to monitor the 874 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 875 * contiguous buffers. On TX, we'll get a FIFO underrun error. 876 */ 877 if (status & MCI_RXDATAAVLBLMASK) { 878 mmci_dma_error(host); 879 if (!data->error) 880 data->error = -EIO; 881 } else if (!data->host_cookie) { 882 mmci_dma_unmap(host, data); 883 } 884 885 /* 886 * Use of DMA with scatter-gather is impossible. 887 * Give up with DMA and switch back to PIO mode. 888 */ 889 if (status & MCI_RXDATAAVLBLMASK) { 890 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 891 mmci_dma_release(host); 892 } 893 894 host->dma_in_progress = false; 895 dmae->cur = NULL; 896 dmae->desc_current = NULL; 897 } 898 899 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 900 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 901 struct dma_chan **dma_chan, 902 struct dma_async_tx_descriptor **dma_desc) 903 { 904 struct mmci_dmae_priv *dmae = host->dma_priv; 905 struct variant_data *variant = host->variant; 906 struct dma_slave_config conf = { 907 .src_addr = host->phybase + MMCIFIFO, 908 .dst_addr = host->phybase + MMCIFIFO, 909 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 910 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 911 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 912 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 913 .device_fc = false, 914 }; 915 struct dma_chan *chan; 916 struct dma_device *device; 917 struct dma_async_tx_descriptor *desc; 918 int nr_sg; 919 unsigned long flags = DMA_CTRL_ACK; 920 921 if (data->flags & MMC_DATA_READ) { 922 conf.direction = DMA_DEV_TO_MEM; 923 chan = dmae->rx_channel; 924 } else { 925 conf.direction = DMA_MEM_TO_DEV; 926 chan = dmae->tx_channel; 927 } 928 929 /* If there's no DMA channel, fall back to PIO */ 930 if (!chan) 931 return -EINVAL; 932 933 /* If less than or equal to the fifo size, don't bother with DMA */ 934 if (data->blksz * data->blocks <= variant->fifosize) 935 return -EINVAL; 936 937 /* 938 * This is necessary to get SDIO working on the Ux500. We do not yet 939 * know if this is a bug in: 940 * - The Ux500 DMA controller (DMA40) 941 * - The MMCI DMA interface on the Ux500 942 * some power of two blocks (such as 64 bytes) are sent regularly 943 * during SDIO traffic and those work fine so for these we enable DMA 944 * transfers. 945 */ 946 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) 947 return -EINVAL; 948 949 device = chan->device; 950 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 951 mmc_get_dma_dir(data)); 952 if (nr_sg == 0) 953 return -EINVAL; 954 955 if (host->variant->qcom_dml) 956 flags |= DMA_PREP_INTERRUPT; 957 958 dmaengine_slave_config(chan, &conf); 959 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 960 conf.direction, flags); 961 if (!desc) 962 goto unmap_exit; 963 964 *dma_chan = chan; 965 *dma_desc = desc; 966 967 return 0; 968 969 unmap_exit: 970 dma_unmap_sg(device->dev, data->sg, data->sg_len, 971 mmc_get_dma_dir(data)); 972 return -ENOMEM; 973 } 974 975 int mmci_dmae_prep_data(struct mmci_host *host, 976 struct mmc_data *data, 977 bool next) 978 { 979 struct mmci_dmae_priv *dmae = host->dma_priv; 980 struct mmci_dmae_next *nd = &dmae->next_data; 981 982 if (!host->use_dma) 983 return -EINVAL; 984 985 if (next) 986 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 987 /* Check if next job is already prepared. */ 988 if (dmae->cur && dmae->desc_current) 989 return 0; 990 991 /* No job were prepared thus do it now. */ 992 return _mmci_dmae_prep_data(host, data, &dmae->cur, 993 &dmae->desc_current); 994 } 995 996 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 997 { 998 struct mmci_dmae_priv *dmae = host->dma_priv; 999 int ret; 1000 1001 host->dma_in_progress = true; 1002 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); 1003 if (ret < 0) { 1004 host->dma_in_progress = false; 1005 return ret; 1006 } 1007 dma_async_issue_pending(dmae->cur); 1008 1009 *datactrl |= MCI_DPSM_DMAENABLE; 1010 1011 return 0; 1012 } 1013 1014 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 1015 { 1016 struct mmci_dmae_priv *dmae = host->dma_priv; 1017 struct mmci_dmae_next *next = &dmae->next_data; 1018 1019 if (!host->use_dma) 1020 return; 1021 1022 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 1023 1024 dmae->desc_current = next->desc; 1025 dmae->cur = next->chan; 1026 next->desc = NULL; 1027 next->chan = NULL; 1028 } 1029 1030 void mmci_dmae_unprep_data(struct mmci_host *host, 1031 struct mmc_data *data, int err) 1032 1033 { 1034 struct mmci_dmae_priv *dmae = host->dma_priv; 1035 1036 if (!host->use_dma) 1037 return; 1038 1039 mmci_dma_unmap(host, data); 1040 1041 if (err) { 1042 struct mmci_dmae_next *next = &dmae->next_data; 1043 struct dma_chan *chan; 1044 if (data->flags & MMC_DATA_READ) 1045 chan = dmae->rx_channel; 1046 else 1047 chan = dmae->tx_channel; 1048 dmaengine_terminate_all(chan); 1049 1050 if (dmae->desc_current == next->desc) 1051 dmae->desc_current = NULL; 1052 1053 if (dmae->cur == next->chan) { 1054 host->dma_in_progress = false; 1055 dmae->cur = NULL; 1056 } 1057 1058 next->desc = NULL; 1059 next->chan = NULL; 1060 } 1061 } 1062 1063 static struct mmci_host_ops mmci_variant_ops = { 1064 .prep_data = mmci_dmae_prep_data, 1065 .unprep_data = mmci_dmae_unprep_data, 1066 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1067 .get_next_data = mmci_dmae_get_next_data, 1068 .dma_setup = mmci_dmae_setup, 1069 .dma_release = mmci_dmae_release, 1070 .dma_start = mmci_dmae_start, 1071 .dma_finalize = mmci_dmae_finalize, 1072 .dma_error = mmci_dmae_error, 1073 }; 1074 #else 1075 static struct mmci_host_ops mmci_variant_ops = { 1076 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1077 }; 1078 #endif 1079 1080 static void mmci_variant_init(struct mmci_host *host) 1081 { 1082 host->ops = &mmci_variant_ops; 1083 } 1084 1085 static void ux500_variant_init(struct mmci_host *host) 1086 { 1087 host->ops = &mmci_variant_ops; 1088 host->ops->busy_complete = ux500_busy_complete; 1089 } 1090 1091 static void ux500v2_variant_init(struct mmci_host *host) 1092 { 1093 host->ops = &mmci_variant_ops; 1094 host->ops->busy_complete = ux500_busy_complete; 1095 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1096 } 1097 1098 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1099 { 1100 struct mmci_host *host = mmc_priv(mmc); 1101 struct mmc_data *data = mrq->data; 1102 1103 if (!data) 1104 return; 1105 1106 WARN_ON(data->host_cookie); 1107 1108 if (mmci_validate_data(host, data)) 1109 return; 1110 1111 mmci_prep_data(host, data, true); 1112 } 1113 1114 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1115 int err) 1116 { 1117 struct mmci_host *host = mmc_priv(mmc); 1118 struct mmc_data *data = mrq->data; 1119 1120 if (!data || !data->host_cookie) 1121 return; 1122 1123 mmci_unprep_data(host, data, err); 1124 } 1125 1126 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1127 { 1128 struct variant_data *variant = host->variant; 1129 unsigned int datactrl, timeout, irqmask; 1130 unsigned long long clks; 1131 void __iomem *base; 1132 1133 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1134 data->blksz, data->blocks, data->flags); 1135 1136 host->data = data; 1137 host->size = data->blksz * data->blocks; 1138 data->bytes_xfered = 0; 1139 1140 clks = (unsigned long long)data->timeout_ns * host->cclk; 1141 do_div(clks, NSEC_PER_SEC); 1142 1143 timeout = data->timeout_clks + (unsigned int)clks; 1144 1145 base = host->base; 1146 writel(timeout, base + MMCIDATATIMER); 1147 writel(host->size, base + MMCIDATALENGTH); 1148 1149 datactrl = host->ops->get_datactrl_cfg(host); 1150 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1151 1152 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1153 u32 clk; 1154 1155 datactrl |= variant->datactrl_mask_sdio; 1156 1157 /* 1158 * The ST Micro variant for SDIO small write transfers 1159 * needs to have clock H/W flow control disabled, 1160 * otherwise the transfer will not start. The threshold 1161 * depends on the rate of MCLK. 1162 */ 1163 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1164 (host->size < 8 || 1165 (host->size <= 8 && host->mclk > 50000000))) 1166 clk = host->clk_reg & ~variant->clkreg_enable; 1167 else 1168 clk = host->clk_reg | variant->clkreg_enable; 1169 1170 mmci_write_clkreg(host, clk); 1171 } 1172 1173 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1174 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1175 datactrl |= variant->datactrl_mask_ddrmode; 1176 1177 /* 1178 * Attempt to use DMA operation mode, if this 1179 * should fail, fall back to PIO mode 1180 */ 1181 if (!mmci_dma_start(host, datactrl)) 1182 return; 1183 1184 /* IRQ mode, map the SG list for CPU reading/writing */ 1185 mmci_init_sg(host, data); 1186 1187 if (data->flags & MMC_DATA_READ) { 1188 irqmask = MCI_RXFIFOHALFFULLMASK; 1189 1190 /* 1191 * If we have less than the fifo 'half-full' threshold to 1192 * transfer, trigger a PIO interrupt as soon as any data 1193 * is available. 1194 */ 1195 if (host->size < variant->fifohalfsize) 1196 irqmask |= MCI_RXDATAAVLBLMASK; 1197 } else { 1198 /* 1199 * We don't actually need to include "FIFO empty" here 1200 * since its implicit in "FIFO half empty". 1201 */ 1202 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1203 } 1204 1205 mmci_write_datactrlreg(host, datactrl); 1206 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1207 mmci_set_mask1(host, irqmask); 1208 } 1209 1210 static void 1211 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1212 { 1213 void __iomem *base = host->base; 1214 unsigned long long clks; 1215 1216 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1217 cmd->opcode, cmd->arg, cmd->flags); 1218 1219 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1220 writel(0, base + MMCICOMMAND); 1221 mmci_reg_delay(host); 1222 } 1223 1224 if (host->variant->cmdreg_stop && 1225 cmd->opcode == MMC_STOP_TRANSMISSION) 1226 c |= host->variant->cmdreg_stop; 1227 1228 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1229 if (cmd->flags & MMC_RSP_PRESENT) { 1230 if (cmd->flags & MMC_RSP_136) 1231 c |= host->variant->cmdreg_lrsp_crc; 1232 else if (cmd->flags & MMC_RSP_CRC) 1233 c |= host->variant->cmdreg_srsp_crc; 1234 else 1235 c |= host->variant->cmdreg_srsp; 1236 } 1237 1238 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1239 if (!cmd->busy_timeout) 1240 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1241 1242 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1243 do_div(clks, MSEC_PER_SEC); 1244 writel_relaxed(clks, host->base + MMCIDATATIMER); 1245 } 1246 1247 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) 1248 host->ops->pre_sig_volt_switch(host); 1249 1250 if (/*interrupt*/0) 1251 c |= MCI_CPSM_INTERRUPT; 1252 1253 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1254 c |= host->variant->data_cmd_enable; 1255 1256 host->cmd = cmd; 1257 1258 writel(cmd->arg, base + MMCIARGUMENT); 1259 writel(c, base + MMCICOMMAND); 1260 } 1261 1262 static void mmci_stop_command(struct mmci_host *host) 1263 { 1264 host->stop_abort.error = 0; 1265 mmci_start_command(host, &host->stop_abort, 0); 1266 } 1267 1268 static void 1269 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1270 unsigned int status) 1271 { 1272 unsigned int status_err; 1273 1274 /* Make sure we have data to handle */ 1275 if (!data) 1276 return; 1277 1278 /* First check for errors */ 1279 status_err = status & (host->variant->start_err | 1280 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1281 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1282 1283 if (status_err) { 1284 u32 remain, success; 1285 1286 /* Terminate the DMA transfer */ 1287 mmci_dma_error(host); 1288 1289 /* 1290 * Calculate how far we are into the transfer. Note that 1291 * the data counter gives the number of bytes transferred 1292 * on the MMC bus, not on the host side. On reads, this 1293 * can be as much as a FIFO-worth of data ahead. This 1294 * matters for FIFO overruns only. 1295 */ 1296 if (!host->variant->datacnt_useless) { 1297 remain = readl(host->base + MMCIDATACNT); 1298 success = data->blksz * data->blocks - remain; 1299 } else { 1300 success = 0; 1301 } 1302 1303 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1304 status_err, success); 1305 if (status_err & MCI_DATACRCFAIL) { 1306 /* Last block was not successful */ 1307 success -= 1; 1308 data->error = -EILSEQ; 1309 } else if (status_err & MCI_DATATIMEOUT) { 1310 data->error = -ETIMEDOUT; 1311 } else if (status_err & MCI_STARTBITERR) { 1312 data->error = -ECOMM; 1313 } else if (status_err & MCI_TXUNDERRUN) { 1314 data->error = -EIO; 1315 } else if (status_err & MCI_RXOVERRUN) { 1316 if (success > host->variant->fifosize) 1317 success -= host->variant->fifosize; 1318 else 1319 success = 0; 1320 data->error = -EIO; 1321 } 1322 data->bytes_xfered = round_down(success, data->blksz); 1323 } 1324 1325 if (status & MCI_DATABLOCKEND) 1326 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1327 1328 if (status & MCI_DATAEND || data->error) { 1329 mmci_dma_finalize(host, data); 1330 1331 mmci_stop_data(host); 1332 1333 if (!data->error) 1334 /* The error clause is handled above, success! */ 1335 data->bytes_xfered = data->blksz * data->blocks; 1336 1337 if (!data->stop) { 1338 if (host->variant->cmdreg_stop && data->error) 1339 mmci_stop_command(host); 1340 else 1341 mmci_request_end(host, data->mrq); 1342 } else if (host->mrq->sbc && !data->error) { 1343 mmci_request_end(host, data->mrq); 1344 } else { 1345 mmci_start_command(host, data->stop, 0); 1346 } 1347 } 1348 } 1349 1350 static void 1351 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1352 unsigned int status) 1353 { 1354 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1355 void __iomem *base = host->base; 1356 bool sbc, busy_resp; 1357 1358 if (!cmd) 1359 return; 1360 1361 sbc = (cmd == host->mrq->sbc); 1362 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1363 1364 /* 1365 * We need to be one of these interrupts to be considered worth 1366 * handling. Note that we tag on any latent IRQs postponed 1367 * due to waiting for busy status. 1368 */ 1369 if (host->variant->busy_timeout && busy_resp) 1370 err_msk |= MCI_DATATIMEOUT; 1371 1372 if (!((status | host->busy_status) & 1373 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1374 return; 1375 1376 /* Handle busy detection on DAT0 if the variant supports it. */ 1377 if (busy_resp && host->variant->busy_detect) 1378 if (!host->ops->busy_complete(host, status, err_msk)) 1379 return; 1380 1381 host->cmd = NULL; 1382 1383 if (status & MCI_CMDTIMEOUT) { 1384 cmd->error = -ETIMEDOUT; 1385 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1386 cmd->error = -EILSEQ; 1387 } else if (host->variant->busy_timeout && busy_resp && 1388 status & MCI_DATATIMEOUT) { 1389 cmd->error = -ETIMEDOUT; 1390 host->irq_action = IRQ_WAKE_THREAD; 1391 } else { 1392 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1393 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1394 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1395 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1396 } 1397 1398 if ((!sbc && !cmd->data) || cmd->error) { 1399 if (host->data) { 1400 /* Terminate the DMA transfer */ 1401 mmci_dma_error(host); 1402 1403 mmci_stop_data(host); 1404 if (host->variant->cmdreg_stop && cmd->error) { 1405 mmci_stop_command(host); 1406 return; 1407 } 1408 } 1409 1410 if (host->irq_action != IRQ_WAKE_THREAD) 1411 mmci_request_end(host, host->mrq); 1412 1413 } else if (sbc) { 1414 mmci_start_command(host, host->mrq->cmd, 0); 1415 } else if (!host->variant->datactrl_first && 1416 !(cmd->data->flags & MMC_DATA_READ)) { 1417 mmci_start_data(host, cmd->data); 1418 } 1419 } 1420 1421 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1422 { 1423 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1424 } 1425 1426 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1427 { 1428 /* 1429 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1430 * from the fifo range should be used 1431 */ 1432 if (status & MCI_RXFIFOHALFFULL) 1433 return host->variant->fifohalfsize; 1434 else if (status & MCI_RXDATAAVLBL) 1435 return 4; 1436 1437 return 0; 1438 } 1439 1440 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1441 { 1442 void __iomem *base = host->base; 1443 char *ptr = buffer; 1444 u32 status = readl(host->base + MMCISTATUS); 1445 int host_remain = host->size; 1446 1447 do { 1448 int count = host->get_rx_fifocnt(host, status, host_remain); 1449 1450 if (count > remain) 1451 count = remain; 1452 1453 if (count <= 0) 1454 break; 1455 1456 /* 1457 * SDIO especially may want to send something that is 1458 * not divisible by 4 (as opposed to card sectors 1459 * etc). Therefore make sure to always read the last bytes 1460 * while only doing full 32-bit reads towards the FIFO. 1461 */ 1462 if (unlikely(count & 0x3)) { 1463 if (count < 4) { 1464 unsigned char buf[4]; 1465 ioread32_rep(base + MMCIFIFO, buf, 1); 1466 memcpy(ptr, buf, count); 1467 } else { 1468 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1469 count &= ~0x3; 1470 } 1471 } else { 1472 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1473 } 1474 1475 ptr += count; 1476 remain -= count; 1477 host_remain -= count; 1478 1479 if (remain == 0) 1480 break; 1481 1482 status = readl(base + MMCISTATUS); 1483 } while (status & MCI_RXDATAAVLBL); 1484 1485 return ptr - buffer; 1486 } 1487 1488 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1489 { 1490 struct variant_data *variant = host->variant; 1491 void __iomem *base = host->base; 1492 char *ptr = buffer; 1493 1494 do { 1495 unsigned int count, maxcnt; 1496 1497 maxcnt = status & MCI_TXFIFOEMPTY ? 1498 variant->fifosize : variant->fifohalfsize; 1499 count = min(remain, maxcnt); 1500 1501 /* 1502 * SDIO especially may want to send something that is 1503 * not divisible by 4 (as opposed to card sectors 1504 * etc), and the FIFO only accept full 32-bit writes. 1505 * So compensate by adding +3 on the count, a single 1506 * byte become a 32bit write, 7 bytes will be two 1507 * 32bit writes etc. 1508 */ 1509 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1510 1511 ptr += count; 1512 remain -= count; 1513 1514 if (remain == 0) 1515 break; 1516 1517 status = readl(base + MMCISTATUS); 1518 } while (status & MCI_TXFIFOHALFEMPTY); 1519 1520 return ptr - buffer; 1521 } 1522 1523 /* 1524 * PIO data transfer IRQ handler. 1525 */ 1526 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1527 { 1528 struct mmci_host *host = dev_id; 1529 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1530 struct variant_data *variant = host->variant; 1531 void __iomem *base = host->base; 1532 u32 status; 1533 1534 status = readl(base + MMCISTATUS); 1535 1536 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1537 1538 do { 1539 unsigned int remain, len; 1540 char *buffer; 1541 1542 /* 1543 * For write, we only need to test the half-empty flag 1544 * here - if the FIFO is completely empty, then by 1545 * definition it is more than half empty. 1546 * 1547 * For read, check for data available. 1548 */ 1549 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1550 break; 1551 1552 if (!sg_miter_next(sg_miter)) 1553 break; 1554 1555 buffer = sg_miter->addr; 1556 remain = sg_miter->length; 1557 1558 len = 0; 1559 if (status & MCI_RXACTIVE) 1560 len = mmci_pio_read(host, buffer, remain); 1561 if (status & MCI_TXACTIVE) 1562 len = mmci_pio_write(host, buffer, remain, status); 1563 1564 sg_miter->consumed = len; 1565 1566 host->size -= len; 1567 remain -= len; 1568 1569 if (remain) 1570 break; 1571 1572 status = readl(base + MMCISTATUS); 1573 } while (1); 1574 1575 sg_miter_stop(sg_miter); 1576 1577 /* 1578 * If we have less than the fifo 'half-full' threshold to transfer, 1579 * trigger a PIO interrupt as soon as any data is available. 1580 */ 1581 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1582 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1583 1584 /* 1585 * If we run out of data, disable the data IRQs; this 1586 * prevents a race where the FIFO becomes empty before 1587 * the chip itself has disabled the data path, and 1588 * stops us racing with our data end IRQ. 1589 */ 1590 if (host->size == 0) { 1591 mmci_set_mask1(host, 0); 1592 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1593 } 1594 1595 return IRQ_HANDLED; 1596 } 1597 1598 /* 1599 * Handle completion of command and data transfers. 1600 */ 1601 static irqreturn_t mmci_irq(int irq, void *dev_id) 1602 { 1603 struct mmci_host *host = dev_id; 1604 u32 status; 1605 1606 spin_lock(&host->lock); 1607 host->irq_action = IRQ_HANDLED; 1608 1609 do { 1610 status = readl(host->base + MMCISTATUS); 1611 1612 if (host->singleirq) { 1613 if (status & host->mask1_reg) 1614 mmci_pio_irq(irq, dev_id); 1615 1616 status &= ~host->variant->irq_pio_mask; 1617 } 1618 1619 /* 1620 * Busy detection is managed by mmci_cmd_irq(), including to 1621 * clear the corresponding IRQ. 1622 */ 1623 status &= readl(host->base + MMCIMASK0); 1624 if (host->variant->busy_detect) 1625 writel(status & ~host->variant->busy_detect_mask, 1626 host->base + MMCICLEAR); 1627 else 1628 writel(status, host->base + MMCICLEAR); 1629 1630 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1631 1632 if (host->variant->reversed_irq_handling) { 1633 mmci_data_irq(host, host->data, status); 1634 mmci_cmd_irq(host, host->cmd, status); 1635 } else { 1636 mmci_cmd_irq(host, host->cmd, status); 1637 mmci_data_irq(host, host->data, status); 1638 } 1639 1640 /* 1641 * Busy detection has been handled by mmci_cmd_irq() above. 1642 * Clear the status bit to prevent polling in IRQ context. 1643 */ 1644 if (host->variant->busy_detect_flag) 1645 status &= ~host->variant->busy_detect_flag; 1646 1647 } while (status); 1648 1649 spin_unlock(&host->lock); 1650 1651 return host->irq_action; 1652 } 1653 1654 /* 1655 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. 1656 * 1657 * A reset is needed for some variants, where a datatimeout for a R1B request 1658 * causes the DPSM to stay busy (non-functional). 1659 */ 1660 static irqreturn_t mmci_irq_thread(int irq, void *dev_id) 1661 { 1662 struct mmci_host *host = dev_id; 1663 unsigned long flags; 1664 1665 if (host->rst) { 1666 reset_control_assert(host->rst); 1667 udelay(2); 1668 reset_control_deassert(host->rst); 1669 } 1670 1671 spin_lock_irqsave(&host->lock, flags); 1672 writel(host->clk_reg, host->base + MMCICLOCK); 1673 writel(host->pwr_reg, host->base + MMCIPOWER); 1674 writel(MCI_IRQENABLE | host->variant->start_err, 1675 host->base + MMCIMASK0); 1676 1677 host->irq_action = IRQ_HANDLED; 1678 mmci_request_end(host, host->mrq); 1679 spin_unlock_irqrestore(&host->lock, flags); 1680 1681 return host->irq_action; 1682 } 1683 1684 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1685 { 1686 struct mmci_host *host = mmc_priv(mmc); 1687 unsigned long flags; 1688 1689 WARN_ON(host->mrq != NULL); 1690 1691 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1692 if (mrq->cmd->error) { 1693 mmc_request_done(mmc, mrq); 1694 return; 1695 } 1696 1697 spin_lock_irqsave(&host->lock, flags); 1698 1699 host->mrq = mrq; 1700 1701 if (mrq->data) 1702 mmci_get_next_data(host, mrq->data); 1703 1704 if (mrq->data && 1705 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1706 mmci_start_data(host, mrq->data); 1707 1708 if (mrq->sbc) 1709 mmci_start_command(host, mrq->sbc, 0); 1710 else 1711 mmci_start_command(host, mrq->cmd, 0); 1712 1713 spin_unlock_irqrestore(&host->lock, flags); 1714 } 1715 1716 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1717 { 1718 struct mmci_host *host = mmc_priv(mmc); 1719 u32 max_busy_timeout = 0; 1720 1721 if (!host->variant->busy_detect) 1722 return; 1723 1724 if (host->variant->busy_timeout && mmc->actual_clock) 1725 max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC); 1726 1727 mmc->max_busy_timeout = max_busy_timeout; 1728 } 1729 1730 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1731 { 1732 struct mmci_host *host = mmc_priv(mmc); 1733 struct variant_data *variant = host->variant; 1734 u32 pwr = 0; 1735 unsigned long flags; 1736 int ret; 1737 1738 if (host->plat->ios_handler && 1739 host->plat->ios_handler(mmc_dev(mmc), ios)) 1740 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1741 1742 switch (ios->power_mode) { 1743 case MMC_POWER_OFF: 1744 if (!IS_ERR(mmc->supply.vmmc)) 1745 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1746 1747 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1748 regulator_disable(mmc->supply.vqmmc); 1749 host->vqmmc_enabled = false; 1750 } 1751 1752 break; 1753 case MMC_POWER_UP: 1754 if (!IS_ERR(mmc->supply.vmmc)) 1755 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1756 1757 /* 1758 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1759 * and instead uses MCI_PWR_ON so apply whatever value is 1760 * configured in the variant data. 1761 */ 1762 pwr |= variant->pwrreg_powerup; 1763 1764 break; 1765 case MMC_POWER_ON: 1766 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1767 ret = regulator_enable(mmc->supply.vqmmc); 1768 if (ret < 0) 1769 dev_err(mmc_dev(mmc), 1770 "failed to enable vqmmc regulator\n"); 1771 else 1772 host->vqmmc_enabled = true; 1773 } 1774 1775 pwr |= MCI_PWR_ON; 1776 break; 1777 } 1778 1779 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1780 /* 1781 * The ST Micro variant has some additional bits 1782 * indicating signal direction for the signals in 1783 * the SD/MMC bus and feedback-clock usage. 1784 */ 1785 pwr |= host->pwr_reg_add; 1786 1787 if (ios->bus_width == MMC_BUS_WIDTH_4) 1788 pwr &= ~MCI_ST_DATA74DIREN; 1789 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1790 pwr &= (~MCI_ST_DATA74DIREN & 1791 ~MCI_ST_DATA31DIREN & 1792 ~MCI_ST_DATA2DIREN); 1793 } 1794 1795 if (variant->opendrain) { 1796 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1797 pwr |= variant->opendrain; 1798 } else { 1799 /* 1800 * If the variant cannot configure the pads by its own, then we 1801 * expect the pinctrl to be able to do that for us 1802 */ 1803 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1804 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1805 else 1806 pinctrl_select_default_state(mmc_dev(mmc)); 1807 } 1808 1809 /* 1810 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1811 * gating the clock, the MCI_PWR_ON bit is cleared. 1812 */ 1813 if (!ios->clock && variant->pwrreg_clkgate) 1814 pwr &= ~MCI_PWR_ON; 1815 1816 if (host->variant->explicit_mclk_control && 1817 ios->clock != host->clock_cache) { 1818 ret = clk_set_rate(host->clk, ios->clock); 1819 if (ret < 0) 1820 dev_err(mmc_dev(host->mmc), 1821 "Error setting clock rate (%d)\n", ret); 1822 else 1823 host->mclk = clk_get_rate(host->clk); 1824 } 1825 host->clock_cache = ios->clock; 1826 1827 spin_lock_irqsave(&host->lock, flags); 1828 1829 if (host->ops && host->ops->set_clkreg) 1830 host->ops->set_clkreg(host, ios->clock); 1831 else 1832 mmci_set_clkreg(host, ios->clock); 1833 1834 mmci_set_max_busy_timeout(mmc); 1835 1836 if (host->ops && host->ops->set_pwrreg) 1837 host->ops->set_pwrreg(host, pwr); 1838 else 1839 mmci_write_pwrreg(host, pwr); 1840 1841 mmci_reg_delay(host); 1842 1843 spin_unlock_irqrestore(&host->lock, flags); 1844 } 1845 1846 static int mmci_get_cd(struct mmc_host *mmc) 1847 { 1848 struct mmci_host *host = mmc_priv(mmc); 1849 struct mmci_platform_data *plat = host->plat; 1850 unsigned int status = mmc_gpio_get_cd(mmc); 1851 1852 if (status == -ENOSYS) { 1853 if (!plat->status) 1854 return 1; /* Assume always present */ 1855 1856 status = plat->status(mmc_dev(host->mmc)); 1857 } 1858 return status; 1859 } 1860 1861 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1862 { 1863 struct mmci_host *host = mmc_priv(mmc); 1864 int ret = 0; 1865 1866 if (!IS_ERR(mmc->supply.vqmmc)) { 1867 1868 switch (ios->signal_voltage) { 1869 case MMC_SIGNAL_VOLTAGE_330: 1870 ret = regulator_set_voltage(mmc->supply.vqmmc, 1871 2700000, 3600000); 1872 break; 1873 case MMC_SIGNAL_VOLTAGE_180: 1874 ret = regulator_set_voltage(mmc->supply.vqmmc, 1875 1700000, 1950000); 1876 break; 1877 case MMC_SIGNAL_VOLTAGE_120: 1878 ret = regulator_set_voltage(mmc->supply.vqmmc, 1879 1100000, 1300000); 1880 break; 1881 } 1882 1883 if (!ret && host->ops && host->ops->post_sig_volt_switch) 1884 ret = host->ops->post_sig_volt_switch(host, ios); 1885 1886 if (ret) 1887 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1888 } 1889 1890 return ret; 1891 } 1892 1893 static struct mmc_host_ops mmci_ops = { 1894 .request = mmci_request, 1895 .pre_req = mmci_pre_request, 1896 .post_req = mmci_post_request, 1897 .set_ios = mmci_set_ios, 1898 .get_ro = mmc_gpio_get_ro, 1899 .get_cd = mmci_get_cd, 1900 .start_signal_voltage_switch = mmci_sig_volt_switch, 1901 }; 1902 1903 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1904 { 1905 struct mmci_host *host = mmc_priv(mmc); 1906 int ret = mmc_of_parse(mmc); 1907 1908 if (ret) 1909 return ret; 1910 1911 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1912 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1913 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1914 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1915 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1916 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1917 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1918 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1919 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1920 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1921 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1922 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1923 if (of_get_property(np, "st,sig-dir", NULL)) 1924 host->pwr_reg_add |= MCI_STM32_DIRPOL; 1925 if (of_get_property(np, "st,neg-edge", NULL)) 1926 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 1927 if (of_get_property(np, "st,use-ckin", NULL)) 1928 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1929 1930 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1931 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1932 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1933 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1934 1935 return 0; 1936 } 1937 1938 static int mmci_probe(struct amba_device *dev, 1939 const struct amba_id *id) 1940 { 1941 struct mmci_platform_data *plat = dev->dev.platform_data; 1942 struct device_node *np = dev->dev.of_node; 1943 struct variant_data *variant = id->data; 1944 struct mmci_host *host; 1945 struct mmc_host *mmc; 1946 int ret; 1947 1948 /* Must have platform data or Device Tree. */ 1949 if (!plat && !np) { 1950 dev_err(&dev->dev, "No plat data or DT found\n"); 1951 return -EINVAL; 1952 } 1953 1954 if (!plat) { 1955 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1956 if (!plat) 1957 return -ENOMEM; 1958 } 1959 1960 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1961 if (!mmc) 1962 return -ENOMEM; 1963 1964 ret = mmci_of_parse(np, mmc); 1965 if (ret) 1966 goto host_free; 1967 1968 host = mmc_priv(mmc); 1969 host->mmc = mmc; 1970 host->mmc_ops = &mmci_ops; 1971 mmc->ops = &mmci_ops; 1972 1973 /* 1974 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1975 * pins can be set accordingly using pinctrl 1976 */ 1977 if (!variant->opendrain) { 1978 host->pinctrl = devm_pinctrl_get(&dev->dev); 1979 if (IS_ERR(host->pinctrl)) { 1980 dev_err(&dev->dev, "failed to get pinctrl"); 1981 ret = PTR_ERR(host->pinctrl); 1982 goto host_free; 1983 } 1984 1985 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1986 MMCI_PINCTRL_STATE_OPENDRAIN); 1987 if (IS_ERR(host->pins_opendrain)) { 1988 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1989 ret = PTR_ERR(host->pins_opendrain); 1990 goto host_free; 1991 } 1992 } 1993 1994 host->hw_designer = amba_manf(dev); 1995 host->hw_revision = amba_rev(dev); 1996 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1997 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1998 1999 host->clk = devm_clk_get(&dev->dev, NULL); 2000 if (IS_ERR(host->clk)) { 2001 ret = PTR_ERR(host->clk); 2002 goto host_free; 2003 } 2004 2005 ret = clk_prepare_enable(host->clk); 2006 if (ret) 2007 goto host_free; 2008 2009 if (variant->qcom_fifo) 2010 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 2011 else 2012 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 2013 2014 host->plat = plat; 2015 host->variant = variant; 2016 host->mclk = clk_get_rate(host->clk); 2017 /* 2018 * According to the spec, mclk is max 100 MHz, 2019 * so we try to adjust the clock down to this, 2020 * (if possible). 2021 */ 2022 if (host->mclk > variant->f_max) { 2023 ret = clk_set_rate(host->clk, variant->f_max); 2024 if (ret < 0) 2025 goto clk_disable; 2026 host->mclk = clk_get_rate(host->clk); 2027 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 2028 host->mclk); 2029 } 2030 2031 host->phybase = dev->res.start; 2032 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 2033 if (IS_ERR(host->base)) { 2034 ret = PTR_ERR(host->base); 2035 goto clk_disable; 2036 } 2037 2038 if (variant->init) 2039 variant->init(host); 2040 2041 /* 2042 * The ARM and ST versions of the block have slightly different 2043 * clock divider equations which means that the minimum divider 2044 * differs too. 2045 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 2046 */ 2047 if (variant->st_clkdiv) 2048 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 2049 else if (variant->stm32_clkdiv) 2050 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 2051 else if (variant->explicit_mclk_control) 2052 mmc->f_min = clk_round_rate(host->clk, 100000); 2053 else 2054 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 2055 /* 2056 * If no maximum operating frequency is supplied, fall back to use 2057 * the module parameter, which has a (low) default value in case it 2058 * is not specified. Either value must not exceed the clock rate into 2059 * the block, of course. 2060 */ 2061 if (mmc->f_max) 2062 mmc->f_max = variant->explicit_mclk_control ? 2063 min(variant->f_max, mmc->f_max) : 2064 min(host->mclk, mmc->f_max); 2065 else 2066 mmc->f_max = variant->explicit_mclk_control ? 2067 fmax : min(host->mclk, fmax); 2068 2069 2070 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 2071 2072 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 2073 if (IS_ERR(host->rst)) { 2074 ret = PTR_ERR(host->rst); 2075 goto clk_disable; 2076 } 2077 2078 /* Get regulators and the supported OCR mask */ 2079 ret = mmc_regulator_get_supply(mmc); 2080 if (ret) 2081 goto clk_disable; 2082 2083 if (!mmc->ocr_avail) 2084 mmc->ocr_avail = plat->ocr_mask; 2085 else if (plat->ocr_mask) 2086 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 2087 2088 /* We support these capabilities. */ 2089 mmc->caps |= MMC_CAP_CMD23; 2090 2091 /* 2092 * Enable busy detection. 2093 */ 2094 if (variant->busy_detect) { 2095 mmci_ops.card_busy = mmci_card_busy; 2096 /* 2097 * Not all variants have a flag to enable busy detection 2098 * in the DPSM, but if they do, set it here. 2099 */ 2100 if (variant->busy_dpsm_flag) 2101 mmci_write_datactrlreg(host, 2102 host->variant->busy_dpsm_flag); 2103 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2104 } 2105 2106 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2107 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2108 host->stop_abort.arg = 0; 2109 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2110 2111 /* We support these PM capabilities. */ 2112 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2113 2114 /* 2115 * We can do SGIO 2116 */ 2117 mmc->max_segs = NR_SG; 2118 2119 /* 2120 * Since only a certain number of bits are valid in the data length 2121 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2122 * single request. 2123 */ 2124 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2125 2126 /* 2127 * Set the maximum segment size. Since we aren't doing DMA 2128 * (yet) we are only limited by the data length register. 2129 */ 2130 mmc->max_seg_size = mmc->max_req_size; 2131 2132 /* 2133 * Block size can be up to 2048 bytes, but must be a power of two. 2134 */ 2135 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2136 2137 /* 2138 * Limit the number of blocks transferred so that we don't overflow 2139 * the maximum request size. 2140 */ 2141 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2142 2143 spin_lock_init(&host->lock); 2144 2145 writel(0, host->base + MMCIMASK0); 2146 2147 if (variant->mmcimask1) 2148 writel(0, host->base + MMCIMASK1); 2149 2150 writel(0xfff, host->base + MMCICLEAR); 2151 2152 /* 2153 * If: 2154 * - not using DT but using a descriptor table, or 2155 * - using a table of descriptors ALONGSIDE DT, or 2156 * look up these descriptors named "cd" and "wp" right here, fail 2157 * silently of these do not exist 2158 */ 2159 if (!np) { 2160 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 2161 if (ret == -EPROBE_DEFER) 2162 goto clk_disable; 2163 2164 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 2165 if (ret == -EPROBE_DEFER) 2166 goto clk_disable; 2167 } 2168 2169 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, 2170 mmci_irq_thread, IRQF_SHARED, 2171 DRIVER_NAME " (cmd)", host); 2172 if (ret) 2173 goto clk_disable; 2174 2175 if (!dev->irq[1]) 2176 host->singleirq = true; 2177 else { 2178 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2179 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2180 if (ret) 2181 goto clk_disable; 2182 } 2183 2184 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2185 2186 amba_set_drvdata(dev, mmc); 2187 2188 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2189 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2190 amba_rev(dev), (unsigned long long)dev->res.start, 2191 dev->irq[0], dev->irq[1]); 2192 2193 mmci_dma_setup(host); 2194 2195 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2196 pm_runtime_use_autosuspend(&dev->dev); 2197 2198 mmc_add_host(mmc); 2199 2200 pm_runtime_put(&dev->dev); 2201 return 0; 2202 2203 clk_disable: 2204 clk_disable_unprepare(host->clk); 2205 host_free: 2206 mmc_free_host(mmc); 2207 return ret; 2208 } 2209 2210 static int mmci_remove(struct amba_device *dev) 2211 { 2212 struct mmc_host *mmc = amba_get_drvdata(dev); 2213 2214 if (mmc) { 2215 struct mmci_host *host = mmc_priv(mmc); 2216 struct variant_data *variant = host->variant; 2217 2218 /* 2219 * Undo pm_runtime_put() in probe. We use the _sync 2220 * version here so that we can access the primecell. 2221 */ 2222 pm_runtime_get_sync(&dev->dev); 2223 2224 mmc_remove_host(mmc); 2225 2226 writel(0, host->base + MMCIMASK0); 2227 2228 if (variant->mmcimask1) 2229 writel(0, host->base + MMCIMASK1); 2230 2231 writel(0, host->base + MMCICOMMAND); 2232 writel(0, host->base + MMCIDATACTRL); 2233 2234 mmci_dma_release(host); 2235 clk_disable_unprepare(host->clk); 2236 mmc_free_host(mmc); 2237 } 2238 2239 return 0; 2240 } 2241 2242 #ifdef CONFIG_PM 2243 static void mmci_save(struct mmci_host *host) 2244 { 2245 unsigned long flags; 2246 2247 spin_lock_irqsave(&host->lock, flags); 2248 2249 writel(0, host->base + MMCIMASK0); 2250 if (host->variant->pwrreg_nopower) { 2251 writel(0, host->base + MMCIDATACTRL); 2252 writel(0, host->base + MMCIPOWER); 2253 writel(0, host->base + MMCICLOCK); 2254 } 2255 mmci_reg_delay(host); 2256 2257 spin_unlock_irqrestore(&host->lock, flags); 2258 } 2259 2260 static void mmci_restore(struct mmci_host *host) 2261 { 2262 unsigned long flags; 2263 2264 spin_lock_irqsave(&host->lock, flags); 2265 2266 if (host->variant->pwrreg_nopower) { 2267 writel(host->clk_reg, host->base + MMCICLOCK); 2268 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2269 writel(host->pwr_reg, host->base + MMCIPOWER); 2270 } 2271 writel(MCI_IRQENABLE | host->variant->start_err, 2272 host->base + MMCIMASK0); 2273 mmci_reg_delay(host); 2274 2275 spin_unlock_irqrestore(&host->lock, flags); 2276 } 2277 2278 static int mmci_runtime_suspend(struct device *dev) 2279 { 2280 struct amba_device *adev = to_amba_device(dev); 2281 struct mmc_host *mmc = amba_get_drvdata(adev); 2282 2283 if (mmc) { 2284 struct mmci_host *host = mmc_priv(mmc); 2285 pinctrl_pm_select_sleep_state(dev); 2286 mmci_save(host); 2287 clk_disable_unprepare(host->clk); 2288 } 2289 2290 return 0; 2291 } 2292 2293 static int mmci_runtime_resume(struct device *dev) 2294 { 2295 struct amba_device *adev = to_amba_device(dev); 2296 struct mmc_host *mmc = amba_get_drvdata(adev); 2297 2298 if (mmc) { 2299 struct mmci_host *host = mmc_priv(mmc); 2300 clk_prepare_enable(host->clk); 2301 mmci_restore(host); 2302 pinctrl_select_default_state(dev); 2303 } 2304 2305 return 0; 2306 } 2307 #endif 2308 2309 static const struct dev_pm_ops mmci_dev_pm_ops = { 2310 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2311 pm_runtime_force_resume) 2312 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2313 }; 2314 2315 static const struct amba_id mmci_ids[] = { 2316 { 2317 .id = 0x00041180, 2318 .mask = 0xff0fffff, 2319 .data = &variant_arm, 2320 }, 2321 { 2322 .id = 0x01041180, 2323 .mask = 0xff0fffff, 2324 .data = &variant_arm_extended_fifo, 2325 }, 2326 { 2327 .id = 0x02041180, 2328 .mask = 0xff0fffff, 2329 .data = &variant_arm_extended_fifo_hwfc, 2330 }, 2331 { 2332 .id = 0x00041181, 2333 .mask = 0x000fffff, 2334 .data = &variant_arm, 2335 }, 2336 /* ST Micro variants */ 2337 { 2338 .id = 0x00180180, 2339 .mask = 0x00ffffff, 2340 .data = &variant_u300, 2341 }, 2342 { 2343 .id = 0x10180180, 2344 .mask = 0xf0ffffff, 2345 .data = &variant_nomadik, 2346 }, 2347 { 2348 .id = 0x00280180, 2349 .mask = 0x00ffffff, 2350 .data = &variant_nomadik, 2351 }, 2352 { 2353 .id = 0x00480180, 2354 .mask = 0xf0ffffff, 2355 .data = &variant_ux500, 2356 }, 2357 { 2358 .id = 0x10480180, 2359 .mask = 0xf0ffffff, 2360 .data = &variant_ux500v2, 2361 }, 2362 { 2363 .id = 0x00880180, 2364 .mask = 0x00ffffff, 2365 .data = &variant_stm32, 2366 }, 2367 { 2368 .id = 0x10153180, 2369 .mask = 0xf0ffffff, 2370 .data = &variant_stm32_sdmmc, 2371 }, 2372 { 2373 .id = 0x00253180, 2374 .mask = 0xf0ffffff, 2375 .data = &variant_stm32_sdmmcv2, 2376 }, 2377 /* Qualcomm variants */ 2378 { 2379 .id = 0x00051180, 2380 .mask = 0x000fffff, 2381 .data = &variant_qcom, 2382 }, 2383 { 0, 0 }, 2384 }; 2385 2386 MODULE_DEVICE_TABLE(amba, mmci_ids); 2387 2388 static struct amba_driver mmci_driver = { 2389 .drv = { 2390 .name = DRIVER_NAME, 2391 .pm = &mmci_dev_pm_ops, 2392 }, 2393 .probe = mmci_probe, 2394 .remove = mmci_remove, 2395 .id_table = mmci_ids, 2396 }; 2397 2398 module_amba_driver(mmci_driver); 2399 2400 module_param(fmax, uint, 0444); 2401 2402 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2403 MODULE_LICENSE("GPL"); 2404