1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/err.h> 21 #include <linux/highmem.h> 22 #include <linux/log2.h> 23 #include <linux/mmc/pm.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/card.h> 26 #include <linux/amba/bus.h> 27 #include <linux/clk.h> 28 #include <linux/scatterlist.h> 29 #include <linux/gpio.h> 30 #include <linux/of_gpio.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 39 #include <asm/div64.h> 40 #include <asm/io.h> 41 #include <asm/sizes.h> 42 43 #include "mmci.h" 44 45 #define DRIVER_NAME "mmci-pl18x" 46 47 static unsigned int fmax = 515633; 48 49 /** 50 * struct variant_data - MMCI variant-specific quirks 51 * @clkreg: default value for MCICLOCK register 52 * @clkreg_enable: enable value for MMCICLOCK register 53 * @datalength_bits: number of bits in the MMCIDATALENGTH register 54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 55 * is asserted (likewise for RX) 56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 57 * is asserted (likewise for RX) 58 * @sdio: variant supports SDIO 59 * @st_clkdiv: true if using a ST-specific clock divider algorithm 60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 61 * @pwrreg_powerup: power up value for MMCIPOWER register 62 * @signal_direction: input/out direction of bus signals can be indicated 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 64 */ 65 struct variant_data { 66 unsigned int clkreg; 67 unsigned int clkreg_enable; 68 unsigned int datalength_bits; 69 unsigned int fifosize; 70 unsigned int fifohalfsize; 71 bool sdio; 72 bool st_clkdiv; 73 bool blksz_datactrl16; 74 u32 pwrreg_powerup; 75 bool signal_direction; 76 bool pwrreg_clkgate; 77 }; 78 79 static struct variant_data variant_arm = { 80 .fifosize = 16 * 4, 81 .fifohalfsize = 8 * 4, 82 .datalength_bits = 16, 83 .pwrreg_powerup = MCI_PWR_UP, 84 }; 85 86 static struct variant_data variant_arm_extended_fifo = { 87 .fifosize = 128 * 4, 88 .fifohalfsize = 64 * 4, 89 .datalength_bits = 16, 90 .pwrreg_powerup = MCI_PWR_UP, 91 }; 92 93 static struct variant_data variant_arm_extended_fifo_hwfc = { 94 .fifosize = 128 * 4, 95 .fifohalfsize = 64 * 4, 96 .clkreg_enable = MCI_ARM_HWFCEN, 97 .datalength_bits = 16, 98 .pwrreg_powerup = MCI_PWR_UP, 99 }; 100 101 static struct variant_data variant_u300 = { 102 .fifosize = 16 * 4, 103 .fifohalfsize = 8 * 4, 104 .clkreg_enable = MCI_ST_U300_HWFCEN, 105 .datalength_bits = 16, 106 .sdio = true, 107 .pwrreg_powerup = MCI_PWR_ON, 108 .signal_direction = true, 109 .pwrreg_clkgate = true, 110 }; 111 112 static struct variant_data variant_nomadik = { 113 .fifosize = 16 * 4, 114 .fifohalfsize = 8 * 4, 115 .clkreg = MCI_CLK_ENABLE, 116 .datalength_bits = 24, 117 .sdio = true, 118 .st_clkdiv = true, 119 .pwrreg_powerup = MCI_PWR_ON, 120 .signal_direction = true, 121 .pwrreg_clkgate = true, 122 }; 123 124 static struct variant_data variant_ux500 = { 125 .fifosize = 30 * 4, 126 .fifohalfsize = 8 * 4, 127 .clkreg = MCI_CLK_ENABLE, 128 .clkreg_enable = MCI_ST_UX500_HWFCEN, 129 .datalength_bits = 24, 130 .sdio = true, 131 .st_clkdiv = true, 132 .pwrreg_powerup = MCI_PWR_ON, 133 .signal_direction = true, 134 .pwrreg_clkgate = true, 135 }; 136 137 static struct variant_data variant_ux500v2 = { 138 .fifosize = 30 * 4, 139 .fifohalfsize = 8 * 4, 140 .clkreg = MCI_CLK_ENABLE, 141 .clkreg_enable = MCI_ST_UX500_HWFCEN, 142 .datalength_bits = 24, 143 .sdio = true, 144 .st_clkdiv = true, 145 .blksz_datactrl16 = true, 146 .pwrreg_powerup = MCI_PWR_ON, 147 .signal_direction = true, 148 .pwrreg_clkgate = true, 149 }; 150 151 /* 152 * Validate mmc prerequisites 153 */ 154 static int mmci_validate_data(struct mmci_host *host, 155 struct mmc_data *data) 156 { 157 if (!data) 158 return 0; 159 160 if (!is_power_of_2(data->blksz)) { 161 dev_err(mmc_dev(host->mmc), 162 "unsupported block size (%d bytes)\n", data->blksz); 163 return -EINVAL; 164 } 165 166 return 0; 167 } 168 169 /* 170 * This must be called with host->lock held 171 */ 172 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 173 { 174 if (host->clk_reg != clk) { 175 host->clk_reg = clk; 176 writel(clk, host->base + MMCICLOCK); 177 } 178 } 179 180 /* 181 * This must be called with host->lock held 182 */ 183 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 184 { 185 if (host->pwr_reg != pwr) { 186 host->pwr_reg = pwr; 187 writel(pwr, host->base + MMCIPOWER); 188 } 189 } 190 191 /* 192 * This must be called with host->lock held 193 */ 194 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 195 { 196 struct variant_data *variant = host->variant; 197 u32 clk = variant->clkreg; 198 199 /* Make sure cclk reflects the current calculated clock */ 200 host->cclk = 0; 201 202 if (desired) { 203 if (desired >= host->mclk) { 204 clk = MCI_CLK_BYPASS; 205 if (variant->st_clkdiv) 206 clk |= MCI_ST_UX500_NEG_EDGE; 207 host->cclk = host->mclk; 208 } else if (variant->st_clkdiv) { 209 /* 210 * DB8500 TRM says f = mclk / (clkdiv + 2) 211 * => clkdiv = (mclk / f) - 2 212 * Round the divider up so we don't exceed the max 213 * frequency 214 */ 215 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 216 if (clk >= 256) 217 clk = 255; 218 host->cclk = host->mclk / (clk + 2); 219 } else { 220 /* 221 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 222 * => clkdiv = mclk / (2 * f) - 1 223 */ 224 clk = host->mclk / (2 * desired) - 1; 225 if (clk >= 256) 226 clk = 255; 227 host->cclk = host->mclk / (2 * (clk + 1)); 228 } 229 230 clk |= variant->clkreg_enable; 231 clk |= MCI_CLK_ENABLE; 232 /* This hasn't proven to be worthwhile */ 233 /* clk |= MCI_CLK_PWRSAVE; */ 234 } 235 236 /* Set actual clock for debug */ 237 host->mmc->actual_clock = host->cclk; 238 239 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 240 clk |= MCI_4BIT_BUS; 241 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 242 clk |= MCI_ST_8BIT_BUS; 243 244 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 245 clk |= MCI_ST_UX500_NEG_EDGE; 246 247 mmci_write_clkreg(host, clk); 248 } 249 250 static void 251 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 252 { 253 writel(0, host->base + MMCICOMMAND); 254 255 BUG_ON(host->data); 256 257 host->mrq = NULL; 258 host->cmd = NULL; 259 260 mmc_request_done(host->mmc, mrq); 261 262 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 263 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 264 } 265 266 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 267 { 268 void __iomem *base = host->base; 269 270 if (host->singleirq) { 271 unsigned int mask0 = readl(base + MMCIMASK0); 272 273 mask0 &= ~MCI_IRQ1MASK; 274 mask0 |= mask; 275 276 writel(mask0, base + MMCIMASK0); 277 } 278 279 writel(mask, base + MMCIMASK1); 280 } 281 282 static void mmci_stop_data(struct mmci_host *host) 283 { 284 writel(0, host->base + MMCIDATACTRL); 285 mmci_set_mask1(host, 0); 286 host->data = NULL; 287 } 288 289 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 290 { 291 unsigned int flags = SG_MITER_ATOMIC; 292 293 if (data->flags & MMC_DATA_READ) 294 flags |= SG_MITER_TO_SG; 295 else 296 flags |= SG_MITER_FROM_SG; 297 298 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 299 } 300 301 /* 302 * All the DMA operation mode stuff goes inside this ifdef. 303 * This assumes that you have a generic DMA device interface, 304 * no custom DMA interfaces are supported. 305 */ 306 #ifdef CONFIG_DMA_ENGINE 307 static void mmci_dma_setup(struct mmci_host *host) 308 { 309 struct mmci_platform_data *plat = host->plat; 310 const char *rxname, *txname; 311 dma_cap_mask_t mask; 312 313 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 314 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 315 316 /* initialize pre request cookie */ 317 host->next_data.cookie = 1; 318 319 /* Try to acquire a generic DMA engine slave channel */ 320 dma_cap_zero(mask); 321 dma_cap_set(DMA_SLAVE, mask); 322 323 if (plat && plat->dma_filter) { 324 if (!host->dma_rx_channel && plat->dma_rx_param) { 325 host->dma_rx_channel = dma_request_channel(mask, 326 plat->dma_filter, 327 plat->dma_rx_param); 328 /* E.g if no DMA hardware is present */ 329 if (!host->dma_rx_channel) 330 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 331 } 332 333 if (!host->dma_tx_channel && plat->dma_tx_param) { 334 host->dma_tx_channel = dma_request_channel(mask, 335 plat->dma_filter, 336 plat->dma_tx_param); 337 if (!host->dma_tx_channel) 338 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 339 } 340 } 341 342 /* 343 * If only an RX channel is specified, the driver will 344 * attempt to use it bidirectionally, however if it is 345 * is specified but cannot be located, DMA will be disabled. 346 */ 347 if (host->dma_rx_channel && !host->dma_tx_channel) 348 host->dma_tx_channel = host->dma_rx_channel; 349 350 if (host->dma_rx_channel) 351 rxname = dma_chan_name(host->dma_rx_channel); 352 else 353 rxname = "none"; 354 355 if (host->dma_tx_channel) 356 txname = dma_chan_name(host->dma_tx_channel); 357 else 358 txname = "none"; 359 360 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 361 rxname, txname); 362 363 /* 364 * Limit the maximum segment size in any SG entry according to 365 * the parameters of the DMA engine device. 366 */ 367 if (host->dma_tx_channel) { 368 struct device *dev = host->dma_tx_channel->device->dev; 369 unsigned int max_seg_size = dma_get_max_seg_size(dev); 370 371 if (max_seg_size < host->mmc->max_seg_size) 372 host->mmc->max_seg_size = max_seg_size; 373 } 374 if (host->dma_rx_channel) { 375 struct device *dev = host->dma_rx_channel->device->dev; 376 unsigned int max_seg_size = dma_get_max_seg_size(dev); 377 378 if (max_seg_size < host->mmc->max_seg_size) 379 host->mmc->max_seg_size = max_seg_size; 380 } 381 } 382 383 /* 384 * This is used in or so inline it 385 * so it can be discarded. 386 */ 387 static inline void mmci_dma_release(struct mmci_host *host) 388 { 389 struct mmci_platform_data *plat = host->plat; 390 391 if (host->dma_rx_channel) 392 dma_release_channel(host->dma_rx_channel); 393 if (host->dma_tx_channel && plat->dma_tx_param) 394 dma_release_channel(host->dma_tx_channel); 395 host->dma_rx_channel = host->dma_tx_channel = NULL; 396 } 397 398 static void mmci_dma_data_error(struct mmci_host *host) 399 { 400 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 401 dmaengine_terminate_all(host->dma_current); 402 host->dma_current = NULL; 403 host->dma_desc_current = NULL; 404 host->data->host_cookie = 0; 405 } 406 407 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 408 { 409 struct dma_chan *chan; 410 enum dma_data_direction dir; 411 412 if (data->flags & MMC_DATA_READ) { 413 dir = DMA_FROM_DEVICE; 414 chan = host->dma_rx_channel; 415 } else { 416 dir = DMA_TO_DEVICE; 417 chan = host->dma_tx_channel; 418 } 419 420 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 421 } 422 423 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 424 { 425 u32 status; 426 int i; 427 428 /* Wait up to 1ms for the DMA to complete */ 429 for (i = 0; ; i++) { 430 status = readl(host->base + MMCISTATUS); 431 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 432 break; 433 udelay(10); 434 } 435 436 /* 437 * Check to see whether we still have some data left in the FIFO - 438 * this catches DMA controllers which are unable to monitor the 439 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 440 * contiguous buffers. On TX, we'll get a FIFO underrun error. 441 */ 442 if (status & MCI_RXDATAAVLBLMASK) { 443 mmci_dma_data_error(host); 444 if (!data->error) 445 data->error = -EIO; 446 } 447 448 if (!data->host_cookie) 449 mmci_dma_unmap(host, data); 450 451 /* 452 * Use of DMA with scatter-gather is impossible. 453 * Give up with DMA and switch back to PIO mode. 454 */ 455 if (status & MCI_RXDATAAVLBLMASK) { 456 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 457 mmci_dma_release(host); 458 } 459 460 host->dma_current = NULL; 461 host->dma_desc_current = NULL; 462 } 463 464 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 465 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 466 struct dma_chan **dma_chan, 467 struct dma_async_tx_descriptor **dma_desc) 468 { 469 struct variant_data *variant = host->variant; 470 struct dma_slave_config conf = { 471 .src_addr = host->phybase + MMCIFIFO, 472 .dst_addr = host->phybase + MMCIFIFO, 473 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 474 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 475 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 476 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 477 .device_fc = false, 478 }; 479 struct dma_chan *chan; 480 struct dma_device *device; 481 struct dma_async_tx_descriptor *desc; 482 enum dma_data_direction buffer_dirn; 483 int nr_sg; 484 485 if (data->flags & MMC_DATA_READ) { 486 conf.direction = DMA_DEV_TO_MEM; 487 buffer_dirn = DMA_FROM_DEVICE; 488 chan = host->dma_rx_channel; 489 } else { 490 conf.direction = DMA_MEM_TO_DEV; 491 buffer_dirn = DMA_TO_DEVICE; 492 chan = host->dma_tx_channel; 493 } 494 495 /* If there's no DMA channel, fall back to PIO */ 496 if (!chan) 497 return -EINVAL; 498 499 /* If less than or equal to the fifo size, don't bother with DMA */ 500 if (data->blksz * data->blocks <= variant->fifosize) 501 return -EINVAL; 502 503 device = chan->device; 504 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 505 if (nr_sg == 0) 506 return -EINVAL; 507 508 dmaengine_slave_config(chan, &conf); 509 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 510 conf.direction, DMA_CTRL_ACK); 511 if (!desc) 512 goto unmap_exit; 513 514 *dma_chan = chan; 515 *dma_desc = desc; 516 517 return 0; 518 519 unmap_exit: 520 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 521 return -ENOMEM; 522 } 523 524 static inline int mmci_dma_prep_data(struct mmci_host *host, 525 struct mmc_data *data) 526 { 527 /* Check if next job is already prepared. */ 528 if (host->dma_current && host->dma_desc_current) 529 return 0; 530 531 /* No job were prepared thus do it now. */ 532 return __mmci_dma_prep_data(host, data, &host->dma_current, 533 &host->dma_desc_current); 534 } 535 536 static inline int mmci_dma_prep_next(struct mmci_host *host, 537 struct mmc_data *data) 538 { 539 struct mmci_host_next *nd = &host->next_data; 540 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 541 } 542 543 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 544 { 545 int ret; 546 struct mmc_data *data = host->data; 547 548 ret = mmci_dma_prep_data(host, host->data); 549 if (ret) 550 return ret; 551 552 /* Okay, go for it. */ 553 dev_vdbg(mmc_dev(host->mmc), 554 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 555 data->sg_len, data->blksz, data->blocks, data->flags); 556 dmaengine_submit(host->dma_desc_current); 557 dma_async_issue_pending(host->dma_current); 558 559 datactrl |= MCI_DPSM_DMAENABLE; 560 561 /* Trigger the DMA transfer */ 562 writel(datactrl, host->base + MMCIDATACTRL); 563 564 /* 565 * Let the MMCI say when the data is ended and it's time 566 * to fire next DMA request. When that happens, MMCI will 567 * call mmci_data_end() 568 */ 569 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 570 host->base + MMCIMASK0); 571 return 0; 572 } 573 574 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 575 { 576 struct mmci_host_next *next = &host->next_data; 577 578 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 579 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 580 581 host->dma_desc_current = next->dma_desc; 582 host->dma_current = next->dma_chan; 583 next->dma_desc = NULL; 584 next->dma_chan = NULL; 585 } 586 587 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 588 bool is_first_req) 589 { 590 struct mmci_host *host = mmc_priv(mmc); 591 struct mmc_data *data = mrq->data; 592 struct mmci_host_next *nd = &host->next_data; 593 594 if (!data) 595 return; 596 597 BUG_ON(data->host_cookie); 598 599 if (mmci_validate_data(host, data)) 600 return; 601 602 if (!mmci_dma_prep_next(host, data)) 603 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 604 } 605 606 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 607 int err) 608 { 609 struct mmci_host *host = mmc_priv(mmc); 610 struct mmc_data *data = mrq->data; 611 612 if (!data || !data->host_cookie) 613 return; 614 615 mmci_dma_unmap(host, data); 616 617 if (err) { 618 struct mmci_host_next *next = &host->next_data; 619 struct dma_chan *chan; 620 if (data->flags & MMC_DATA_READ) 621 chan = host->dma_rx_channel; 622 else 623 chan = host->dma_tx_channel; 624 dmaengine_terminate_all(chan); 625 626 next->dma_desc = NULL; 627 next->dma_chan = NULL; 628 } 629 } 630 631 #else 632 /* Blank functions if the DMA engine is not available */ 633 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 634 { 635 } 636 static inline void mmci_dma_setup(struct mmci_host *host) 637 { 638 } 639 640 static inline void mmci_dma_release(struct mmci_host *host) 641 { 642 } 643 644 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 645 { 646 } 647 648 static inline void mmci_dma_finalize(struct mmci_host *host, 649 struct mmc_data *data) 650 { 651 } 652 653 static inline void mmci_dma_data_error(struct mmci_host *host) 654 { 655 } 656 657 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 658 { 659 return -ENOSYS; 660 } 661 662 #define mmci_pre_request NULL 663 #define mmci_post_request NULL 664 665 #endif 666 667 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 668 { 669 struct variant_data *variant = host->variant; 670 unsigned int datactrl, timeout, irqmask; 671 unsigned long long clks; 672 void __iomem *base; 673 int blksz_bits; 674 675 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 676 data->blksz, data->blocks, data->flags); 677 678 host->data = data; 679 host->size = data->blksz * data->blocks; 680 data->bytes_xfered = 0; 681 682 clks = (unsigned long long)data->timeout_ns * host->cclk; 683 do_div(clks, 1000000000UL); 684 685 timeout = data->timeout_clks + (unsigned int)clks; 686 687 base = host->base; 688 writel(timeout, base + MMCIDATATIMER); 689 writel(host->size, base + MMCIDATALENGTH); 690 691 blksz_bits = ffs(data->blksz) - 1; 692 BUG_ON(1 << blksz_bits != data->blksz); 693 694 if (variant->blksz_datactrl16) 695 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 696 else 697 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 698 699 if (data->flags & MMC_DATA_READ) 700 datactrl |= MCI_DPSM_DIRECTION; 701 702 /* The ST Micro variants has a special bit to enable SDIO */ 703 if (variant->sdio && host->mmc->card) 704 if (mmc_card_sdio(host->mmc->card)) { 705 /* 706 * The ST Micro variants has a special bit 707 * to enable SDIO. 708 */ 709 u32 clk; 710 711 datactrl |= MCI_ST_DPSM_SDIOEN; 712 713 /* 714 * The ST Micro variant for SDIO small write transfers 715 * needs to have clock H/W flow control disabled, 716 * otherwise the transfer will not start. The threshold 717 * depends on the rate of MCLK. 718 */ 719 if (data->flags & MMC_DATA_WRITE && 720 (host->size < 8 || 721 (host->size <= 8 && host->mclk > 50000000))) 722 clk = host->clk_reg & ~variant->clkreg_enable; 723 else 724 clk = host->clk_reg | variant->clkreg_enable; 725 726 mmci_write_clkreg(host, clk); 727 } 728 729 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 730 datactrl |= MCI_ST_DPSM_DDRMODE; 731 732 /* 733 * Attempt to use DMA operation mode, if this 734 * should fail, fall back to PIO mode 735 */ 736 if (!mmci_dma_start_data(host, datactrl)) 737 return; 738 739 /* IRQ mode, map the SG list for CPU reading/writing */ 740 mmci_init_sg(host, data); 741 742 if (data->flags & MMC_DATA_READ) { 743 irqmask = MCI_RXFIFOHALFFULLMASK; 744 745 /* 746 * If we have less than the fifo 'half-full' threshold to 747 * transfer, trigger a PIO interrupt as soon as any data 748 * is available. 749 */ 750 if (host->size < variant->fifohalfsize) 751 irqmask |= MCI_RXDATAAVLBLMASK; 752 } else { 753 /* 754 * We don't actually need to include "FIFO empty" here 755 * since its implicit in "FIFO half empty". 756 */ 757 irqmask = MCI_TXFIFOHALFEMPTYMASK; 758 } 759 760 writel(datactrl, base + MMCIDATACTRL); 761 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 762 mmci_set_mask1(host, irqmask); 763 } 764 765 static void 766 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 767 { 768 void __iomem *base = host->base; 769 770 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 771 cmd->opcode, cmd->arg, cmd->flags); 772 773 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 774 writel(0, base + MMCICOMMAND); 775 udelay(1); 776 } 777 778 c |= cmd->opcode | MCI_CPSM_ENABLE; 779 if (cmd->flags & MMC_RSP_PRESENT) { 780 if (cmd->flags & MMC_RSP_136) 781 c |= MCI_CPSM_LONGRSP; 782 c |= MCI_CPSM_RESPONSE; 783 } 784 if (/*interrupt*/0) 785 c |= MCI_CPSM_INTERRUPT; 786 787 host->cmd = cmd; 788 789 writel(cmd->arg, base + MMCIARGUMENT); 790 writel(c, base + MMCICOMMAND); 791 } 792 793 static void 794 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 795 unsigned int status) 796 { 797 /* First check for errors */ 798 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 799 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 800 u32 remain, success; 801 802 /* Terminate the DMA transfer */ 803 if (dma_inprogress(host)) { 804 mmci_dma_data_error(host); 805 mmci_dma_unmap(host, data); 806 } 807 808 /* 809 * Calculate how far we are into the transfer. Note that 810 * the data counter gives the number of bytes transferred 811 * on the MMC bus, not on the host side. On reads, this 812 * can be as much as a FIFO-worth of data ahead. This 813 * matters for FIFO overruns only. 814 */ 815 remain = readl(host->base + MMCIDATACNT); 816 success = data->blksz * data->blocks - remain; 817 818 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 819 status, success); 820 if (status & MCI_DATACRCFAIL) { 821 /* Last block was not successful */ 822 success -= 1; 823 data->error = -EILSEQ; 824 } else if (status & MCI_DATATIMEOUT) { 825 data->error = -ETIMEDOUT; 826 } else if (status & MCI_STARTBITERR) { 827 data->error = -ECOMM; 828 } else if (status & MCI_TXUNDERRUN) { 829 data->error = -EIO; 830 } else if (status & MCI_RXOVERRUN) { 831 if (success > host->variant->fifosize) 832 success -= host->variant->fifosize; 833 else 834 success = 0; 835 data->error = -EIO; 836 } 837 data->bytes_xfered = round_down(success, data->blksz); 838 } 839 840 if (status & MCI_DATABLOCKEND) 841 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 842 843 if (status & MCI_DATAEND || data->error) { 844 if (dma_inprogress(host)) 845 mmci_dma_finalize(host, data); 846 mmci_stop_data(host); 847 848 if (!data->error) 849 /* The error clause is handled above, success! */ 850 data->bytes_xfered = data->blksz * data->blocks; 851 852 if (!data->stop || host->mrq->sbc) { 853 mmci_request_end(host, data->mrq); 854 } else { 855 mmci_start_command(host, data->stop, 0); 856 } 857 } 858 } 859 860 static void 861 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 862 unsigned int status) 863 { 864 void __iomem *base = host->base; 865 bool sbc = (cmd == host->mrq->sbc); 866 867 host->cmd = NULL; 868 869 if (status & MCI_CMDTIMEOUT) { 870 cmd->error = -ETIMEDOUT; 871 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 872 cmd->error = -EILSEQ; 873 } else { 874 cmd->resp[0] = readl(base + MMCIRESPONSE0); 875 cmd->resp[1] = readl(base + MMCIRESPONSE1); 876 cmd->resp[2] = readl(base + MMCIRESPONSE2); 877 cmd->resp[3] = readl(base + MMCIRESPONSE3); 878 } 879 880 if ((!sbc && !cmd->data) || cmd->error) { 881 if (host->data) { 882 /* Terminate the DMA transfer */ 883 if (dma_inprogress(host)) { 884 mmci_dma_data_error(host); 885 mmci_dma_unmap(host, host->data); 886 } 887 mmci_stop_data(host); 888 } 889 mmci_request_end(host, host->mrq); 890 } else if (sbc) { 891 mmci_start_command(host, host->mrq->cmd, 0); 892 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 893 mmci_start_data(host, cmd->data); 894 } 895 } 896 897 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 898 { 899 void __iomem *base = host->base; 900 char *ptr = buffer; 901 u32 status; 902 int host_remain = host->size; 903 904 do { 905 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 906 907 if (count > remain) 908 count = remain; 909 910 if (count <= 0) 911 break; 912 913 /* 914 * SDIO especially may want to send something that is 915 * not divisible by 4 (as opposed to card sectors 916 * etc). Therefore make sure to always read the last bytes 917 * while only doing full 32-bit reads towards the FIFO. 918 */ 919 if (unlikely(count & 0x3)) { 920 if (count < 4) { 921 unsigned char buf[4]; 922 ioread32_rep(base + MMCIFIFO, buf, 1); 923 memcpy(ptr, buf, count); 924 } else { 925 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 926 count &= ~0x3; 927 } 928 } else { 929 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 930 } 931 932 ptr += count; 933 remain -= count; 934 host_remain -= count; 935 936 if (remain == 0) 937 break; 938 939 status = readl(base + MMCISTATUS); 940 } while (status & MCI_RXDATAAVLBL); 941 942 return ptr - buffer; 943 } 944 945 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 946 { 947 struct variant_data *variant = host->variant; 948 void __iomem *base = host->base; 949 char *ptr = buffer; 950 951 do { 952 unsigned int count, maxcnt; 953 954 maxcnt = status & MCI_TXFIFOEMPTY ? 955 variant->fifosize : variant->fifohalfsize; 956 count = min(remain, maxcnt); 957 958 /* 959 * SDIO especially may want to send something that is 960 * not divisible by 4 (as opposed to card sectors 961 * etc), and the FIFO only accept full 32-bit writes. 962 * So compensate by adding +3 on the count, a single 963 * byte become a 32bit write, 7 bytes will be two 964 * 32bit writes etc. 965 */ 966 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 967 968 ptr += count; 969 remain -= count; 970 971 if (remain == 0) 972 break; 973 974 status = readl(base + MMCISTATUS); 975 } while (status & MCI_TXFIFOHALFEMPTY); 976 977 return ptr - buffer; 978 } 979 980 /* 981 * PIO data transfer IRQ handler. 982 */ 983 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 984 { 985 struct mmci_host *host = dev_id; 986 struct sg_mapping_iter *sg_miter = &host->sg_miter; 987 struct variant_data *variant = host->variant; 988 void __iomem *base = host->base; 989 unsigned long flags; 990 u32 status; 991 992 status = readl(base + MMCISTATUS); 993 994 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 995 996 local_irq_save(flags); 997 998 do { 999 unsigned int remain, len; 1000 char *buffer; 1001 1002 /* 1003 * For write, we only need to test the half-empty flag 1004 * here - if the FIFO is completely empty, then by 1005 * definition it is more than half empty. 1006 * 1007 * For read, check for data available. 1008 */ 1009 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1010 break; 1011 1012 if (!sg_miter_next(sg_miter)) 1013 break; 1014 1015 buffer = sg_miter->addr; 1016 remain = sg_miter->length; 1017 1018 len = 0; 1019 if (status & MCI_RXACTIVE) 1020 len = mmci_pio_read(host, buffer, remain); 1021 if (status & MCI_TXACTIVE) 1022 len = mmci_pio_write(host, buffer, remain, status); 1023 1024 sg_miter->consumed = len; 1025 1026 host->size -= len; 1027 remain -= len; 1028 1029 if (remain) 1030 break; 1031 1032 status = readl(base + MMCISTATUS); 1033 } while (1); 1034 1035 sg_miter_stop(sg_miter); 1036 1037 local_irq_restore(flags); 1038 1039 /* 1040 * If we have less than the fifo 'half-full' threshold to transfer, 1041 * trigger a PIO interrupt as soon as any data is available. 1042 */ 1043 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1044 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1045 1046 /* 1047 * If we run out of data, disable the data IRQs; this 1048 * prevents a race where the FIFO becomes empty before 1049 * the chip itself has disabled the data path, and 1050 * stops us racing with our data end IRQ. 1051 */ 1052 if (host->size == 0) { 1053 mmci_set_mask1(host, 0); 1054 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1055 } 1056 1057 return IRQ_HANDLED; 1058 } 1059 1060 /* 1061 * Handle completion of command and data transfers. 1062 */ 1063 static irqreturn_t mmci_irq(int irq, void *dev_id) 1064 { 1065 struct mmci_host *host = dev_id; 1066 u32 status; 1067 int ret = 0; 1068 1069 spin_lock(&host->lock); 1070 1071 do { 1072 struct mmc_command *cmd; 1073 struct mmc_data *data; 1074 1075 status = readl(host->base + MMCISTATUS); 1076 1077 if (host->singleirq) { 1078 if (status & readl(host->base + MMCIMASK1)) 1079 mmci_pio_irq(irq, dev_id); 1080 1081 status &= ~MCI_IRQ1MASK; 1082 } 1083 1084 status &= readl(host->base + MMCIMASK0); 1085 writel(status, host->base + MMCICLEAR); 1086 1087 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1088 1089 data = host->data; 1090 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1091 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1092 MCI_DATABLOCKEND) && data) 1093 mmci_data_irq(host, data, status); 1094 1095 cmd = host->cmd; 1096 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1097 mmci_cmd_irq(host, cmd, status); 1098 1099 ret = 1; 1100 } while (status); 1101 1102 spin_unlock(&host->lock); 1103 1104 return IRQ_RETVAL(ret); 1105 } 1106 1107 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1108 { 1109 struct mmci_host *host = mmc_priv(mmc); 1110 unsigned long flags; 1111 1112 WARN_ON(host->mrq != NULL); 1113 1114 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1115 if (mrq->cmd->error) { 1116 mmc_request_done(mmc, mrq); 1117 return; 1118 } 1119 1120 pm_runtime_get_sync(mmc_dev(mmc)); 1121 1122 spin_lock_irqsave(&host->lock, flags); 1123 1124 host->mrq = mrq; 1125 1126 if (mrq->data) 1127 mmci_get_next_data(host, mrq->data); 1128 1129 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1130 mmci_start_data(host, mrq->data); 1131 1132 if (mrq->sbc) 1133 mmci_start_command(host, mrq->sbc, 0); 1134 else 1135 mmci_start_command(host, mrq->cmd, 0); 1136 1137 spin_unlock_irqrestore(&host->lock, flags); 1138 } 1139 1140 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1141 { 1142 struct mmci_host *host = mmc_priv(mmc); 1143 struct variant_data *variant = host->variant; 1144 u32 pwr = 0; 1145 unsigned long flags; 1146 int ret; 1147 1148 pm_runtime_get_sync(mmc_dev(mmc)); 1149 1150 if (host->plat->ios_handler && 1151 host->plat->ios_handler(mmc_dev(mmc), ios)) 1152 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1153 1154 switch (ios->power_mode) { 1155 case MMC_POWER_OFF: 1156 if (!IS_ERR(mmc->supply.vmmc)) 1157 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1158 1159 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1160 regulator_disable(mmc->supply.vqmmc); 1161 host->vqmmc_enabled = false; 1162 } 1163 1164 break; 1165 case MMC_POWER_UP: 1166 if (!IS_ERR(mmc->supply.vmmc)) 1167 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1168 1169 /* 1170 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1171 * and instead uses MCI_PWR_ON so apply whatever value is 1172 * configured in the variant data. 1173 */ 1174 pwr |= variant->pwrreg_powerup; 1175 1176 break; 1177 case MMC_POWER_ON: 1178 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1179 ret = regulator_enable(mmc->supply.vqmmc); 1180 if (ret < 0) 1181 dev_err(mmc_dev(mmc), 1182 "failed to enable vqmmc regulator\n"); 1183 else 1184 host->vqmmc_enabled = true; 1185 } 1186 1187 pwr |= MCI_PWR_ON; 1188 break; 1189 } 1190 1191 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1192 /* 1193 * The ST Micro variant has some additional bits 1194 * indicating signal direction for the signals in 1195 * the SD/MMC bus and feedback-clock usage. 1196 */ 1197 pwr |= host->plat->sigdir; 1198 1199 if (ios->bus_width == MMC_BUS_WIDTH_4) 1200 pwr &= ~MCI_ST_DATA74DIREN; 1201 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1202 pwr &= (~MCI_ST_DATA74DIREN & 1203 ~MCI_ST_DATA31DIREN & 1204 ~MCI_ST_DATA2DIREN); 1205 } 1206 1207 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1208 if (host->hw_designer != AMBA_VENDOR_ST) 1209 pwr |= MCI_ROD; 1210 else { 1211 /* 1212 * The ST Micro variant use the ROD bit for something 1213 * else and only has OD (Open Drain). 1214 */ 1215 pwr |= MCI_OD; 1216 } 1217 } 1218 1219 /* 1220 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1221 * gating the clock, the MCI_PWR_ON bit is cleared. 1222 */ 1223 if (!ios->clock && variant->pwrreg_clkgate) 1224 pwr &= ~MCI_PWR_ON; 1225 1226 spin_lock_irqsave(&host->lock, flags); 1227 1228 mmci_set_clkreg(host, ios->clock); 1229 mmci_write_pwrreg(host, pwr); 1230 1231 spin_unlock_irqrestore(&host->lock, flags); 1232 1233 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1234 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1235 } 1236 1237 static int mmci_get_ro(struct mmc_host *mmc) 1238 { 1239 struct mmci_host *host = mmc_priv(mmc); 1240 1241 if (host->gpio_wp == -ENOSYS) 1242 return -ENOSYS; 1243 1244 return gpio_get_value_cansleep(host->gpio_wp); 1245 } 1246 1247 static int mmci_get_cd(struct mmc_host *mmc) 1248 { 1249 struct mmci_host *host = mmc_priv(mmc); 1250 struct mmci_platform_data *plat = host->plat; 1251 unsigned int status; 1252 1253 if (host->gpio_cd == -ENOSYS) { 1254 if (!plat->status) 1255 return 1; /* Assume always present */ 1256 1257 status = plat->status(mmc_dev(host->mmc)); 1258 } else 1259 status = !!gpio_get_value_cansleep(host->gpio_cd) 1260 ^ plat->cd_invert; 1261 1262 /* 1263 * Use positive logic throughout - status is zero for no card, 1264 * non-zero for card inserted. 1265 */ 1266 return status; 1267 } 1268 1269 static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1270 { 1271 struct mmci_host *host = dev_id; 1272 1273 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1274 1275 return IRQ_HANDLED; 1276 } 1277 1278 static const struct mmc_host_ops mmci_ops = { 1279 .request = mmci_request, 1280 .pre_req = mmci_pre_request, 1281 .post_req = mmci_post_request, 1282 .set_ios = mmci_set_ios, 1283 .get_ro = mmci_get_ro, 1284 .get_cd = mmci_get_cd, 1285 }; 1286 1287 #ifdef CONFIG_OF 1288 static void mmci_dt_populate_generic_pdata(struct device_node *np, 1289 struct mmci_platform_data *pdata) 1290 { 1291 int bus_width = 0; 1292 1293 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1294 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1295 1296 if (of_get_property(np, "cd-inverted", NULL)) 1297 pdata->cd_invert = true; 1298 else 1299 pdata->cd_invert = false; 1300 1301 of_property_read_u32(np, "max-frequency", &pdata->f_max); 1302 if (!pdata->f_max) 1303 pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1304 1305 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1306 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1307 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1308 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1309 1310 of_property_read_u32(np, "bus-width", &bus_width); 1311 switch (bus_width) { 1312 case 0 : 1313 /* No bus-width supplied. */ 1314 break; 1315 case 4 : 1316 pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1317 break; 1318 case 8 : 1319 pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1320 break; 1321 default : 1322 pr_warn("%s: Unsupported bus width\n", np->full_name); 1323 } 1324 } 1325 #else 1326 static void mmci_dt_populate_generic_pdata(struct device_node *np, 1327 struct mmci_platform_data *pdata) 1328 { 1329 return; 1330 } 1331 #endif 1332 1333 static int mmci_probe(struct amba_device *dev, 1334 const struct amba_id *id) 1335 { 1336 struct mmci_platform_data *plat = dev->dev.platform_data; 1337 struct device_node *np = dev->dev.of_node; 1338 struct variant_data *variant = id->data; 1339 struct mmci_host *host; 1340 struct mmc_host *mmc; 1341 int ret; 1342 1343 /* Must have platform data or Device Tree. */ 1344 if (!plat && !np) { 1345 dev_err(&dev->dev, "No plat data or DT found\n"); 1346 return -EINVAL; 1347 } 1348 1349 if (!plat) { 1350 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1351 if (!plat) 1352 return -ENOMEM; 1353 } 1354 1355 if (np) 1356 mmci_dt_populate_generic_pdata(np, plat); 1357 1358 ret = amba_request_regions(dev, DRIVER_NAME); 1359 if (ret) 1360 goto out; 1361 1362 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1363 if (!mmc) { 1364 ret = -ENOMEM; 1365 goto rel_regions; 1366 } 1367 1368 host = mmc_priv(mmc); 1369 host->mmc = mmc; 1370 1371 host->gpio_wp = -ENOSYS; 1372 host->gpio_cd = -ENOSYS; 1373 host->gpio_cd_irq = -1; 1374 1375 host->hw_designer = amba_manf(dev); 1376 host->hw_revision = amba_rev(dev); 1377 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1378 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1379 1380 host->clk = devm_clk_get(&dev->dev, NULL); 1381 if (IS_ERR(host->clk)) { 1382 ret = PTR_ERR(host->clk); 1383 goto host_free; 1384 } 1385 1386 ret = clk_prepare_enable(host->clk); 1387 if (ret) 1388 goto host_free; 1389 1390 host->plat = plat; 1391 host->variant = variant; 1392 host->mclk = clk_get_rate(host->clk); 1393 /* 1394 * According to the spec, mclk is max 100 MHz, 1395 * so we try to adjust the clock down to this, 1396 * (if possible). 1397 */ 1398 if (host->mclk > 100000000) { 1399 ret = clk_set_rate(host->clk, 100000000); 1400 if (ret < 0) 1401 goto clk_disable; 1402 host->mclk = clk_get_rate(host->clk); 1403 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1404 host->mclk); 1405 } 1406 host->phybase = dev->res.start; 1407 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1408 if (!host->base) { 1409 ret = -ENOMEM; 1410 goto clk_disable; 1411 } 1412 1413 mmc->ops = &mmci_ops; 1414 /* 1415 * The ARM and ST versions of the block have slightly different 1416 * clock divider equations which means that the minimum divider 1417 * differs too. 1418 */ 1419 if (variant->st_clkdiv) 1420 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1421 else 1422 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1423 /* 1424 * If the platform data supplies a maximum operating 1425 * frequency, this takes precedence. Else, we fall back 1426 * to using the module parameter, which has a (low) 1427 * default value in case it is not specified. Either 1428 * value must not exceed the clock rate into the block, 1429 * of course. 1430 */ 1431 if (plat->f_max) 1432 mmc->f_max = min(host->mclk, plat->f_max); 1433 else 1434 mmc->f_max = min(host->mclk, fmax); 1435 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1436 1437 host->pinctrl = devm_pinctrl_get(&dev->dev); 1438 if (IS_ERR(host->pinctrl)) { 1439 ret = PTR_ERR(host->pinctrl); 1440 goto clk_disable; 1441 } 1442 1443 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1444 PINCTRL_STATE_DEFAULT); 1445 1446 /* enable pins to be muxed in and configured */ 1447 if (!IS_ERR(host->pins_default)) { 1448 ret = pinctrl_select_state(host->pinctrl, host->pins_default); 1449 if (ret) 1450 dev_warn(&dev->dev, "could not set default pins\n"); 1451 } else 1452 dev_warn(&dev->dev, "could not get default pinstate\n"); 1453 1454 /* Get regulators and the supported OCR mask */ 1455 mmc_regulator_get_supply(mmc); 1456 if (!mmc->ocr_avail) 1457 mmc->ocr_avail = plat->ocr_mask; 1458 else if (plat->ocr_mask) 1459 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1460 1461 mmc->caps = plat->capabilities; 1462 mmc->caps2 = plat->capabilities2; 1463 1464 /* We support these PM capabilities. */ 1465 mmc->pm_caps = MMC_PM_KEEP_POWER; 1466 1467 /* 1468 * We can do SGIO 1469 */ 1470 mmc->max_segs = NR_SG; 1471 1472 /* 1473 * Since only a certain number of bits are valid in the data length 1474 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1475 * single request. 1476 */ 1477 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1478 1479 /* 1480 * Set the maximum segment size. Since we aren't doing DMA 1481 * (yet) we are only limited by the data length register. 1482 */ 1483 mmc->max_seg_size = mmc->max_req_size; 1484 1485 /* 1486 * Block size can be up to 2048 bytes, but must be a power of two. 1487 */ 1488 mmc->max_blk_size = 1 << 11; 1489 1490 /* 1491 * Limit the number of blocks transferred so that we don't overflow 1492 * the maximum request size. 1493 */ 1494 mmc->max_blk_count = mmc->max_req_size >> 11; 1495 1496 spin_lock_init(&host->lock); 1497 1498 writel(0, host->base + MMCIMASK0); 1499 writel(0, host->base + MMCIMASK1); 1500 writel(0xfff, host->base + MMCICLEAR); 1501 1502 if (plat->gpio_cd == -EPROBE_DEFER) { 1503 ret = -EPROBE_DEFER; 1504 goto err_gpio_cd; 1505 } 1506 if (gpio_is_valid(plat->gpio_cd)) { 1507 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1508 if (ret == 0) 1509 ret = gpio_direction_input(plat->gpio_cd); 1510 if (ret == 0) 1511 host->gpio_cd = plat->gpio_cd; 1512 else if (ret != -ENOSYS) 1513 goto err_gpio_cd; 1514 1515 /* 1516 * A gpio pin that will detect cards when inserted and removed 1517 * will most likely want to trigger on the edges if it is 1518 * 0 when ejected and 1 when inserted (or mutatis mutandis 1519 * for the inverted case) so we request triggers on both 1520 * edges. 1521 */ 1522 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1523 mmci_cd_irq, 1524 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1525 DRIVER_NAME " (cd)", host); 1526 if (ret >= 0) 1527 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1528 } 1529 if (plat->gpio_wp == -EPROBE_DEFER) { 1530 ret = -EPROBE_DEFER; 1531 goto err_gpio_wp; 1532 } 1533 if (gpio_is_valid(plat->gpio_wp)) { 1534 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1535 if (ret == 0) 1536 ret = gpio_direction_input(plat->gpio_wp); 1537 if (ret == 0) 1538 host->gpio_wp = plat->gpio_wp; 1539 else if (ret != -ENOSYS) 1540 goto err_gpio_wp; 1541 } 1542 1543 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1544 && host->gpio_cd_irq < 0) 1545 mmc->caps |= MMC_CAP_NEEDS_POLL; 1546 1547 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1548 if (ret) 1549 goto unmap; 1550 1551 if (!dev->irq[1]) 1552 host->singleirq = true; 1553 else { 1554 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1555 DRIVER_NAME " (pio)", host); 1556 if (ret) 1557 goto irq0_free; 1558 } 1559 1560 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1561 1562 amba_set_drvdata(dev, mmc); 1563 1564 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1565 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1566 amba_rev(dev), (unsigned long long)dev->res.start, 1567 dev->irq[0], dev->irq[1]); 1568 1569 mmci_dma_setup(host); 1570 1571 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1572 pm_runtime_use_autosuspend(&dev->dev); 1573 pm_runtime_put(&dev->dev); 1574 1575 mmc_add_host(mmc); 1576 1577 return 0; 1578 1579 irq0_free: 1580 free_irq(dev->irq[0], host); 1581 unmap: 1582 if (host->gpio_wp != -ENOSYS) 1583 gpio_free(host->gpio_wp); 1584 err_gpio_wp: 1585 if (host->gpio_cd_irq >= 0) 1586 free_irq(host->gpio_cd_irq, host); 1587 if (host->gpio_cd != -ENOSYS) 1588 gpio_free(host->gpio_cd); 1589 err_gpio_cd: 1590 iounmap(host->base); 1591 clk_disable: 1592 clk_disable_unprepare(host->clk); 1593 host_free: 1594 mmc_free_host(mmc); 1595 rel_regions: 1596 amba_release_regions(dev); 1597 out: 1598 return ret; 1599 } 1600 1601 static int mmci_remove(struct amba_device *dev) 1602 { 1603 struct mmc_host *mmc = amba_get_drvdata(dev); 1604 1605 amba_set_drvdata(dev, NULL); 1606 1607 if (mmc) { 1608 struct mmci_host *host = mmc_priv(mmc); 1609 1610 /* 1611 * Undo pm_runtime_put() in probe. We use the _sync 1612 * version here so that we can access the primecell. 1613 */ 1614 pm_runtime_get_sync(&dev->dev); 1615 1616 mmc_remove_host(mmc); 1617 1618 writel(0, host->base + MMCIMASK0); 1619 writel(0, host->base + MMCIMASK1); 1620 1621 writel(0, host->base + MMCICOMMAND); 1622 writel(0, host->base + MMCIDATACTRL); 1623 1624 mmci_dma_release(host); 1625 free_irq(dev->irq[0], host); 1626 if (!host->singleirq) 1627 free_irq(dev->irq[1], host); 1628 1629 if (host->gpio_wp != -ENOSYS) 1630 gpio_free(host->gpio_wp); 1631 if (host->gpio_cd_irq >= 0) 1632 free_irq(host->gpio_cd_irq, host); 1633 if (host->gpio_cd != -ENOSYS) 1634 gpio_free(host->gpio_cd); 1635 1636 iounmap(host->base); 1637 clk_disable_unprepare(host->clk); 1638 1639 mmc_free_host(mmc); 1640 1641 amba_release_regions(dev); 1642 } 1643 1644 return 0; 1645 } 1646 1647 #ifdef CONFIG_SUSPEND 1648 static int mmci_suspend(struct device *dev) 1649 { 1650 struct amba_device *adev = to_amba_device(dev); 1651 struct mmc_host *mmc = amba_get_drvdata(adev); 1652 int ret = 0; 1653 1654 if (mmc) { 1655 struct mmci_host *host = mmc_priv(mmc); 1656 1657 ret = mmc_suspend_host(mmc); 1658 if (ret == 0) { 1659 pm_runtime_get_sync(dev); 1660 writel(0, host->base + MMCIMASK0); 1661 } 1662 } 1663 1664 return ret; 1665 } 1666 1667 static int mmci_resume(struct device *dev) 1668 { 1669 struct amba_device *adev = to_amba_device(dev); 1670 struct mmc_host *mmc = amba_get_drvdata(adev); 1671 int ret = 0; 1672 1673 if (mmc) { 1674 struct mmci_host *host = mmc_priv(mmc); 1675 1676 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1677 pm_runtime_put(dev); 1678 1679 ret = mmc_resume_host(mmc); 1680 } 1681 1682 return ret; 1683 } 1684 #endif 1685 1686 #ifdef CONFIG_PM_RUNTIME 1687 static int mmci_runtime_suspend(struct device *dev) 1688 { 1689 struct amba_device *adev = to_amba_device(dev); 1690 struct mmc_host *mmc = amba_get_drvdata(adev); 1691 1692 if (mmc) { 1693 struct mmci_host *host = mmc_priv(mmc); 1694 clk_disable_unprepare(host->clk); 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int mmci_runtime_resume(struct device *dev) 1701 { 1702 struct amba_device *adev = to_amba_device(dev); 1703 struct mmc_host *mmc = amba_get_drvdata(adev); 1704 1705 if (mmc) { 1706 struct mmci_host *host = mmc_priv(mmc); 1707 clk_prepare_enable(host->clk); 1708 } 1709 1710 return 0; 1711 } 1712 #endif 1713 1714 static const struct dev_pm_ops mmci_dev_pm_ops = { 1715 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1716 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1717 }; 1718 1719 static struct amba_id mmci_ids[] = { 1720 { 1721 .id = 0x00041180, 1722 .mask = 0xff0fffff, 1723 .data = &variant_arm, 1724 }, 1725 { 1726 .id = 0x01041180, 1727 .mask = 0xff0fffff, 1728 .data = &variant_arm_extended_fifo, 1729 }, 1730 { 1731 .id = 0x02041180, 1732 .mask = 0xff0fffff, 1733 .data = &variant_arm_extended_fifo_hwfc, 1734 }, 1735 { 1736 .id = 0x00041181, 1737 .mask = 0x000fffff, 1738 .data = &variant_arm, 1739 }, 1740 /* ST Micro variants */ 1741 { 1742 .id = 0x00180180, 1743 .mask = 0x00ffffff, 1744 .data = &variant_u300, 1745 }, 1746 { 1747 .id = 0x10180180, 1748 .mask = 0xf0ffffff, 1749 .data = &variant_nomadik, 1750 }, 1751 { 1752 .id = 0x00280180, 1753 .mask = 0x00ffffff, 1754 .data = &variant_u300, 1755 }, 1756 { 1757 .id = 0x00480180, 1758 .mask = 0xf0ffffff, 1759 .data = &variant_ux500, 1760 }, 1761 { 1762 .id = 0x10480180, 1763 .mask = 0xf0ffffff, 1764 .data = &variant_ux500v2, 1765 }, 1766 { 0, 0 }, 1767 }; 1768 1769 MODULE_DEVICE_TABLE(amba, mmci_ids); 1770 1771 static struct amba_driver mmci_driver = { 1772 .drv = { 1773 .name = DRIVER_NAME, 1774 .pm = &mmci_dev_pm_ops, 1775 }, 1776 .probe = mmci_probe, 1777 .remove = mmci_remove, 1778 .id_table = mmci_ids, 1779 }; 1780 1781 module_amba_driver(mmci_driver); 1782 1783 module_param(fmax, uint, 0444); 1784 1785 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1786 MODULE_LICENSE("GPL"); 1787