1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/of.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/gpio/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 static void mmci_variant_init(struct mmci_host *host); 49 static void ux500_variant_init(struct mmci_host *host); 50 static void ux500v2_variant_init(struct mmci_host *host); 51 52 static unsigned int fmax = 515633; 53 54 static struct variant_data variant_arm = { 55 .fifosize = 16 * 4, 56 .fifohalfsize = 8 * 4, 57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 60 .cmdreg_srsp = MCI_CPSM_RESPONSE, 61 .datalength_bits = 16, 62 .datactrl_blocksz = 11, 63 .pwrreg_powerup = MCI_PWR_UP, 64 .f_max = 100000000, 65 .reversed_irq_handling = true, 66 .mmcimask1 = true, 67 .irq_pio_mask = MCI_IRQ_PIO_MASK, 68 .start_err = MCI_STARTBITERR, 69 .opendrain = MCI_ROD, 70 .init = mmci_variant_init, 71 }; 72 73 static struct variant_data variant_arm_extended_fifo = { 74 .fifosize = 128 * 4, 75 .fifohalfsize = 64 * 4, 76 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 77 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 78 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 79 .cmdreg_srsp = MCI_CPSM_RESPONSE, 80 .datalength_bits = 16, 81 .datactrl_blocksz = 11, 82 .pwrreg_powerup = MCI_PWR_UP, 83 .f_max = 100000000, 84 .mmcimask1 = true, 85 .irq_pio_mask = MCI_IRQ_PIO_MASK, 86 .start_err = MCI_STARTBITERR, 87 .opendrain = MCI_ROD, 88 .init = mmci_variant_init, 89 }; 90 91 static struct variant_data variant_arm_extended_fifo_hwfc = { 92 .fifosize = 128 * 4, 93 .fifohalfsize = 64 * 4, 94 .clkreg_enable = MCI_ARM_HWFCEN, 95 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 96 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 97 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 98 .cmdreg_srsp = MCI_CPSM_RESPONSE, 99 .datalength_bits = 16, 100 .datactrl_blocksz = 11, 101 .pwrreg_powerup = MCI_PWR_UP, 102 .f_max = 100000000, 103 .mmcimask1 = true, 104 .irq_pio_mask = MCI_IRQ_PIO_MASK, 105 .start_err = MCI_STARTBITERR, 106 .opendrain = MCI_ROD, 107 .init = mmci_variant_init, 108 }; 109 110 static struct variant_data variant_u300 = { 111 .fifosize = 16 * 4, 112 .fifohalfsize = 8 * 4, 113 .clkreg_enable = MCI_ST_U300_HWFCEN, 114 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 115 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 116 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 117 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 118 .cmdreg_srsp = MCI_CPSM_RESPONSE, 119 .datalength_bits = 16, 120 .datactrl_blocksz = 11, 121 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 122 .st_sdio = true, 123 .pwrreg_powerup = MCI_PWR_ON, 124 .f_max = 100000000, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128 .mmcimask1 = true, 129 .irq_pio_mask = MCI_IRQ_PIO_MASK, 130 .start_err = MCI_STARTBITERR, 131 .opendrain = MCI_OD, 132 .init = mmci_variant_init, 133 }; 134 135 static struct variant_data variant_nomadik = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg = MCI_CLK_ENABLE, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 141 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 142 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 143 .cmdreg_srsp = MCI_CPSM_RESPONSE, 144 .datalength_bits = 24, 145 .datactrl_blocksz = 11, 146 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 147 .st_sdio = true, 148 .st_clkdiv = true, 149 .pwrreg_powerup = MCI_PWR_ON, 150 .f_max = 100000000, 151 .signal_direction = true, 152 .pwrreg_clkgate = true, 153 .pwrreg_nopower = true, 154 .mmcimask1 = true, 155 .irq_pio_mask = MCI_IRQ_PIO_MASK, 156 .start_err = MCI_STARTBITERR, 157 .opendrain = MCI_OD, 158 .init = mmci_variant_init, 159 }; 160 161 static struct variant_data variant_ux500 = { 162 .fifosize = 30 * 4, 163 .fifohalfsize = 8 * 4, 164 .clkreg = MCI_CLK_ENABLE, 165 .clkreg_enable = MCI_ST_UX500_HWFCEN, 166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 168 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 169 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 170 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 171 .cmdreg_srsp = MCI_CPSM_RESPONSE, 172 .datalength_bits = 24, 173 .datactrl_blocksz = 11, 174 .datactrl_any_blocksz = true, 175 .dma_power_of_2 = true, 176 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 177 .st_sdio = true, 178 .st_clkdiv = true, 179 .pwrreg_powerup = MCI_PWR_ON, 180 .f_max = 100000000, 181 .signal_direction = true, 182 .pwrreg_clkgate = true, 183 .busy_detect = true, 184 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 185 .busy_detect_flag = MCI_ST_CARDBUSY, 186 .busy_detect_mask = MCI_ST_BUSYENDMASK, 187 .pwrreg_nopower = true, 188 .mmcimask1 = true, 189 .irq_pio_mask = MCI_IRQ_PIO_MASK, 190 .start_err = MCI_STARTBITERR, 191 .opendrain = MCI_OD, 192 .init = ux500_variant_init, 193 }; 194 195 static struct variant_data variant_ux500v2 = { 196 .fifosize = 30 * 4, 197 .fifohalfsize = 8 * 4, 198 .clkreg = MCI_CLK_ENABLE, 199 .clkreg_enable = MCI_ST_UX500_HWFCEN, 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 202 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 203 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 204 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 205 .cmdreg_srsp = MCI_CPSM_RESPONSE, 206 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 207 .datalength_bits = 24, 208 .datactrl_blocksz = 11, 209 .datactrl_any_blocksz = true, 210 .dma_power_of_2 = true, 211 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 212 .st_sdio = true, 213 .st_clkdiv = true, 214 .pwrreg_powerup = MCI_PWR_ON, 215 .f_max = 100000000, 216 .signal_direction = true, 217 .pwrreg_clkgate = true, 218 .busy_detect = true, 219 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 220 .busy_detect_flag = MCI_ST_CARDBUSY, 221 .busy_detect_mask = MCI_ST_BUSYENDMASK, 222 .pwrreg_nopower = true, 223 .mmcimask1 = true, 224 .irq_pio_mask = MCI_IRQ_PIO_MASK, 225 .start_err = MCI_STARTBITERR, 226 .opendrain = MCI_OD, 227 .init = ux500v2_variant_init, 228 }; 229 230 static struct variant_data variant_stm32 = { 231 .fifosize = 32 * 4, 232 .fifohalfsize = 8 * 4, 233 .clkreg = MCI_CLK_ENABLE, 234 .clkreg_enable = MCI_ST_UX500_HWFCEN, 235 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 236 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 237 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 238 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 239 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 240 .cmdreg_srsp = MCI_CPSM_RESPONSE, 241 .irq_pio_mask = MCI_IRQ_PIO_MASK, 242 .datalength_bits = 24, 243 .datactrl_blocksz = 11, 244 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 245 .st_sdio = true, 246 .st_clkdiv = true, 247 .pwrreg_powerup = MCI_PWR_ON, 248 .f_max = 48000000, 249 .pwrreg_clkgate = true, 250 .pwrreg_nopower = true, 251 .init = mmci_variant_init, 252 }; 253 254 static struct variant_data variant_stm32_sdmmc = { 255 .fifosize = 16 * 4, 256 .fifohalfsize = 8 * 4, 257 .f_max = 208000000, 258 .stm32_clkdiv = true, 259 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 260 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 261 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 262 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 263 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 264 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 265 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 266 .datactrl_first = true, 267 .datacnt_useless = true, 268 .datalength_bits = 25, 269 .datactrl_blocksz = 14, 270 .datactrl_any_blocksz = true, 271 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 272 .stm32_idmabsize_mask = GENMASK(12, 5), 273 .busy_timeout = true, 274 .busy_detect = true, 275 .busy_detect_flag = MCI_STM32_BUSYD0, 276 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 277 .init = sdmmc_variant_init, 278 }; 279 280 static struct variant_data variant_stm32_sdmmcv2 = { 281 .fifosize = 16 * 4, 282 .fifohalfsize = 8 * 4, 283 .f_max = 267000000, 284 .stm32_clkdiv = true, 285 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 286 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 287 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 288 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 289 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 290 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 291 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 292 .datactrl_first = true, 293 .datacnt_useless = true, 294 .datalength_bits = 25, 295 .datactrl_blocksz = 14, 296 .datactrl_any_blocksz = true, 297 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 298 .stm32_idmabsize_mask = GENMASK(16, 5), 299 .dma_lli = true, 300 .busy_timeout = true, 301 .busy_detect = true, 302 .busy_detect_flag = MCI_STM32_BUSYD0, 303 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 304 .init = sdmmc_variant_init, 305 }; 306 307 static struct variant_data variant_qcom = { 308 .fifosize = 16 * 4, 309 .fifohalfsize = 8 * 4, 310 .clkreg = MCI_CLK_ENABLE, 311 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 312 MCI_QCOM_CLK_SELECT_IN_FBCLK, 313 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 314 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 315 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 316 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 317 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 318 .cmdreg_srsp = MCI_CPSM_RESPONSE, 319 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 320 .datalength_bits = 24, 321 .datactrl_blocksz = 11, 322 .datactrl_any_blocksz = true, 323 .pwrreg_powerup = MCI_PWR_UP, 324 .f_max = 208000000, 325 .explicit_mclk_control = true, 326 .qcom_fifo = true, 327 .qcom_dml = true, 328 .mmcimask1 = true, 329 .irq_pio_mask = MCI_IRQ_PIO_MASK, 330 .start_err = MCI_STARTBITERR, 331 .opendrain = MCI_ROD, 332 .init = qcom_variant_init, 333 }; 334 335 /* Busy detection for the ST Micro variant */ 336 static int mmci_card_busy(struct mmc_host *mmc) 337 { 338 struct mmci_host *host = mmc_priv(mmc); 339 unsigned long flags; 340 int busy = 0; 341 342 spin_lock_irqsave(&host->lock, flags); 343 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 344 busy = 1; 345 spin_unlock_irqrestore(&host->lock, flags); 346 347 return busy; 348 } 349 350 static void mmci_reg_delay(struct mmci_host *host) 351 { 352 /* 353 * According to the spec, at least three feedback clock cycles 354 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 355 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 356 * Worst delay time during card init is at 100 kHz => 30 us. 357 * Worst delay time when up and running is at 25 MHz => 120 ns. 358 */ 359 if (host->cclk < 25000000) 360 udelay(30); 361 else 362 ndelay(120); 363 } 364 365 /* 366 * This must be called with host->lock held 367 */ 368 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 369 { 370 if (host->clk_reg != clk) { 371 host->clk_reg = clk; 372 writel(clk, host->base + MMCICLOCK); 373 } 374 } 375 376 /* 377 * This must be called with host->lock held 378 */ 379 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 380 { 381 if (host->pwr_reg != pwr) { 382 host->pwr_reg = pwr; 383 writel(pwr, host->base + MMCIPOWER); 384 } 385 } 386 387 /* 388 * This must be called with host->lock held 389 */ 390 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 391 { 392 /* Keep busy mode in DPSM if enabled */ 393 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 394 395 if (host->datactrl_reg != datactrl) { 396 host->datactrl_reg = datactrl; 397 writel(datactrl, host->base + MMCIDATACTRL); 398 } 399 } 400 401 /* 402 * This must be called with host->lock held 403 */ 404 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 405 { 406 struct variant_data *variant = host->variant; 407 u32 clk = variant->clkreg; 408 409 /* Make sure cclk reflects the current calculated clock */ 410 host->cclk = 0; 411 412 if (desired) { 413 if (variant->explicit_mclk_control) { 414 host->cclk = host->mclk; 415 } else if (desired >= host->mclk) { 416 clk = MCI_CLK_BYPASS; 417 if (variant->st_clkdiv) 418 clk |= MCI_ST_UX500_NEG_EDGE; 419 host->cclk = host->mclk; 420 } else if (variant->st_clkdiv) { 421 /* 422 * DB8500 TRM says f = mclk / (clkdiv + 2) 423 * => clkdiv = (mclk / f) - 2 424 * Round the divider up so we don't exceed the max 425 * frequency 426 */ 427 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 428 if (clk >= 256) 429 clk = 255; 430 host->cclk = host->mclk / (clk + 2); 431 } else { 432 /* 433 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 434 * => clkdiv = mclk / (2 * f) - 1 435 */ 436 clk = host->mclk / (2 * desired) - 1; 437 if (clk >= 256) 438 clk = 255; 439 host->cclk = host->mclk / (2 * (clk + 1)); 440 } 441 442 clk |= variant->clkreg_enable; 443 clk |= MCI_CLK_ENABLE; 444 /* This hasn't proven to be worthwhile */ 445 /* clk |= MCI_CLK_PWRSAVE; */ 446 } 447 448 /* Set actual clock for debug */ 449 host->mmc->actual_clock = host->cclk; 450 451 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 452 clk |= MCI_4BIT_BUS; 453 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 454 clk |= variant->clkreg_8bit_bus_enable; 455 456 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 457 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 458 clk |= variant->clkreg_neg_edge_enable; 459 460 mmci_write_clkreg(host, clk); 461 } 462 463 static void mmci_dma_release(struct mmci_host *host) 464 { 465 if (host->ops && host->ops->dma_release) 466 host->ops->dma_release(host); 467 468 host->use_dma = false; 469 } 470 471 static void mmci_dma_setup(struct mmci_host *host) 472 { 473 if (!host->ops || !host->ops->dma_setup) 474 return; 475 476 if (host->ops->dma_setup(host)) 477 return; 478 479 /* initialize pre request cookie */ 480 host->next_cookie = 1; 481 482 host->use_dma = true; 483 } 484 485 /* 486 * Validate mmc prerequisites 487 */ 488 static int mmci_validate_data(struct mmci_host *host, 489 struct mmc_data *data) 490 { 491 struct variant_data *variant = host->variant; 492 493 if (!data) 494 return 0; 495 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { 496 dev_err(mmc_dev(host->mmc), 497 "unsupported block size (%d bytes)\n", data->blksz); 498 return -EINVAL; 499 } 500 501 if (host->ops && host->ops->validate_data) 502 return host->ops->validate_data(host, data); 503 504 return 0; 505 } 506 507 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 508 { 509 int err; 510 511 if (!host->ops || !host->ops->prep_data) 512 return 0; 513 514 err = host->ops->prep_data(host, data, next); 515 516 if (next && !err) 517 data->host_cookie = ++host->next_cookie < 0 ? 518 1 : host->next_cookie; 519 520 return err; 521 } 522 523 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 524 int err) 525 { 526 if (host->ops && host->ops->unprep_data) 527 host->ops->unprep_data(host, data, err); 528 529 data->host_cookie = 0; 530 } 531 532 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 533 { 534 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 535 536 if (host->ops && host->ops->get_next_data) 537 host->ops->get_next_data(host, data); 538 } 539 540 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 541 { 542 struct mmc_data *data = host->data; 543 int ret; 544 545 if (!host->use_dma) 546 return -EINVAL; 547 548 ret = mmci_prep_data(host, data, false); 549 if (ret) 550 return ret; 551 552 if (!host->ops || !host->ops->dma_start) 553 return -EINVAL; 554 555 /* Okay, go for it. */ 556 dev_vdbg(mmc_dev(host->mmc), 557 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 558 data->sg_len, data->blksz, data->blocks, data->flags); 559 560 ret = host->ops->dma_start(host, &datactrl); 561 if (ret) 562 return ret; 563 564 /* Trigger the DMA transfer */ 565 mmci_write_datactrlreg(host, datactrl); 566 567 /* 568 * Let the MMCI say when the data is ended and it's time 569 * to fire next DMA request. When that happens, MMCI will 570 * call mmci_data_end() 571 */ 572 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 573 host->base + MMCIMASK0); 574 return 0; 575 } 576 577 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 578 { 579 if (!host->use_dma) 580 return; 581 582 if (host->ops && host->ops->dma_finalize) 583 host->ops->dma_finalize(host, data); 584 } 585 586 static void mmci_dma_error(struct mmci_host *host) 587 { 588 if (!host->use_dma) 589 return; 590 591 if (host->ops && host->ops->dma_error) 592 host->ops->dma_error(host); 593 } 594 595 static void 596 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 597 { 598 writel(0, host->base + MMCICOMMAND); 599 600 BUG_ON(host->data); 601 602 host->mrq = NULL; 603 host->cmd = NULL; 604 605 mmc_request_done(host->mmc, mrq); 606 } 607 608 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 609 { 610 void __iomem *base = host->base; 611 struct variant_data *variant = host->variant; 612 613 if (host->singleirq) { 614 unsigned int mask0 = readl(base + MMCIMASK0); 615 616 mask0 &= ~variant->irq_pio_mask; 617 mask0 |= mask; 618 619 writel(mask0, base + MMCIMASK0); 620 } 621 622 if (variant->mmcimask1) 623 writel(mask, base + MMCIMASK1); 624 625 host->mask1_reg = mask; 626 } 627 628 static void mmci_stop_data(struct mmci_host *host) 629 { 630 mmci_write_datactrlreg(host, 0); 631 mmci_set_mask1(host, 0); 632 host->data = NULL; 633 } 634 635 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 636 { 637 unsigned int flags = SG_MITER_ATOMIC; 638 639 if (data->flags & MMC_DATA_READ) 640 flags |= SG_MITER_TO_SG; 641 else 642 flags |= SG_MITER_FROM_SG; 643 644 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 645 } 646 647 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 648 { 649 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 650 } 651 652 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 653 { 654 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 655 } 656 657 /* 658 * ux500_busy_complete() - this will wait until the busy status 659 * goes off, saving any status that occur in the meantime into 660 * host->busy_status until we know the card is not busy any more. 661 * The function returns true when the busy detection is ended 662 * and we should continue processing the command. 663 * 664 * The Ux500 typically fires two IRQs over a busy cycle like this: 665 * 666 * DAT0 busy +-----------------+ 667 * | | 668 * DAT0 not busy ----+ +-------- 669 * 670 * ^ ^ 671 * | | 672 * IRQ1 IRQ2 673 */ 674 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 675 { 676 void __iomem *base = host->base; 677 678 if (status & err_msk) { 679 /* Stop any ongoing busy detection if an error occurs */ 680 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 681 writel(readl(base + MMCIMASK0) & 682 ~host->variant->busy_detect_mask, base + MMCIMASK0); 683 host->busy_state = MMCI_BUSY_DONE; 684 host->busy_status = 0; 685 return true; 686 } 687 688 /* 689 * Before unmasking for the busy end IRQ, confirm that the 690 * command was sent successfully. To keep track of having a 691 * command in-progress, waiting for busy signaling to end, 692 * store the status in host->busy_status. 693 * 694 * Note that, the card may need a couple of clock cycles before 695 * it starts signaling busy on DAT0, hence re-read the 696 * MMCISTATUS register here, to allow the busy bit to be set. 697 * Potentially we may even need to poll the register for a 698 * while, to allow it to be set, but tests indicates that it 699 * isn't needed. 700 */ 701 if (host->busy_state == MMCI_BUSY_DONE) { 702 status = readl(base + MMCISTATUS); 703 if (status & host->variant->busy_detect_flag) { 704 writel(readl(base + MMCIMASK0) | 705 host->variant->busy_detect_mask, 706 base + MMCIMASK0); 707 708 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 709 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; 710 return false; 711 } 712 } 713 714 /* 715 * If there is a command in-progress that has been successfully 716 * sent, then bail out if busy status is set and wait for the 717 * busy end IRQ. 718 * 719 * Note that, the HW triggers an IRQ on both edges while 720 * monitoring DAT0 for busy completion, but there is only one 721 * status bit in MMCISTATUS for the busy state. Therefore 722 * both the start and the end interrupts needs to be cleared, 723 * one after the other. So, clear the busy start IRQ here. 724 */ 725 if (host->busy_state == MMCI_BUSY_WAITING_FOR_START_IRQ) { 726 if (status & host->variant->busy_detect_flag) { 727 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 728 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 729 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ; 730 return false; 731 } else { 732 dev_dbg(mmc_dev(host->mmc), 733 "lost busy status when waiting for busy start IRQ\n"); 734 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 735 writel(readl(base + MMCIMASK0) & 736 ~host->variant->busy_detect_mask, base + MMCIMASK0); 737 host->busy_state = MMCI_BUSY_DONE; 738 host->busy_status = 0; 739 return true; 740 } 741 } 742 743 if (host->busy_state == MMCI_BUSY_WAITING_FOR_END_IRQ) { 744 if (!(status & host->variant->busy_detect_flag)) { 745 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 746 host->busy_state = MMCI_BUSY_DONE; 747 return true; 748 } else { 749 dev_dbg(mmc_dev(host->mmc), 750 "busy status still asserted when handling busy end IRQ - will keep waiting\n"); 751 return false; 752 } 753 } 754 755 return true; 756 } 757 758 /* 759 * All the DMA operation mode stuff goes inside this ifdef. 760 * This assumes that you have a generic DMA device interface, 761 * no custom DMA interfaces are supported. 762 */ 763 #ifdef CONFIG_DMA_ENGINE 764 struct mmci_dmae_next { 765 struct dma_async_tx_descriptor *desc; 766 struct dma_chan *chan; 767 }; 768 769 struct mmci_dmae_priv { 770 struct dma_chan *cur; 771 struct dma_chan *rx_channel; 772 struct dma_chan *tx_channel; 773 struct dma_async_tx_descriptor *desc_current; 774 struct mmci_dmae_next next_data; 775 }; 776 777 int mmci_dmae_setup(struct mmci_host *host) 778 { 779 const char *rxname, *txname; 780 struct mmci_dmae_priv *dmae; 781 782 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 783 if (!dmae) 784 return -ENOMEM; 785 786 host->dma_priv = dmae; 787 788 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); 789 if (IS_ERR(dmae->rx_channel)) { 790 int ret = PTR_ERR(dmae->rx_channel); 791 dmae->rx_channel = NULL; 792 return ret; 793 } 794 795 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); 796 if (IS_ERR(dmae->tx_channel)) { 797 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) 798 dev_warn(mmc_dev(host->mmc), 799 "Deferred probe for TX channel ignored\n"); 800 dmae->tx_channel = NULL; 801 } 802 803 /* 804 * If only an RX channel is specified, the driver will 805 * attempt to use it bidirectionally, however if it 806 * is specified but cannot be located, DMA will be disabled. 807 */ 808 if (dmae->rx_channel && !dmae->tx_channel) 809 dmae->tx_channel = dmae->rx_channel; 810 811 if (dmae->rx_channel) 812 rxname = dma_chan_name(dmae->rx_channel); 813 else 814 rxname = "none"; 815 816 if (dmae->tx_channel) 817 txname = dma_chan_name(dmae->tx_channel); 818 else 819 txname = "none"; 820 821 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 822 rxname, txname); 823 824 /* 825 * Limit the maximum segment size in any SG entry according to 826 * the parameters of the DMA engine device. 827 */ 828 if (dmae->tx_channel) { 829 struct device *dev = dmae->tx_channel->device->dev; 830 unsigned int max_seg_size = dma_get_max_seg_size(dev); 831 832 if (max_seg_size < host->mmc->max_seg_size) 833 host->mmc->max_seg_size = max_seg_size; 834 } 835 if (dmae->rx_channel) { 836 struct device *dev = dmae->rx_channel->device->dev; 837 unsigned int max_seg_size = dma_get_max_seg_size(dev); 838 839 if (max_seg_size < host->mmc->max_seg_size) 840 host->mmc->max_seg_size = max_seg_size; 841 } 842 843 if (!dmae->tx_channel || !dmae->rx_channel) { 844 mmci_dmae_release(host); 845 return -EINVAL; 846 } 847 848 return 0; 849 } 850 851 /* 852 * This is used in or so inline it 853 * so it can be discarded. 854 */ 855 void mmci_dmae_release(struct mmci_host *host) 856 { 857 struct mmci_dmae_priv *dmae = host->dma_priv; 858 859 if (dmae->rx_channel) 860 dma_release_channel(dmae->rx_channel); 861 if (dmae->tx_channel) 862 dma_release_channel(dmae->tx_channel); 863 dmae->rx_channel = dmae->tx_channel = NULL; 864 } 865 866 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 867 { 868 struct mmci_dmae_priv *dmae = host->dma_priv; 869 struct dma_chan *chan; 870 871 if (data->flags & MMC_DATA_READ) 872 chan = dmae->rx_channel; 873 else 874 chan = dmae->tx_channel; 875 876 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 877 mmc_get_dma_dir(data)); 878 } 879 880 void mmci_dmae_error(struct mmci_host *host) 881 { 882 struct mmci_dmae_priv *dmae = host->dma_priv; 883 884 if (!dma_inprogress(host)) 885 return; 886 887 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 888 dmaengine_terminate_all(dmae->cur); 889 host->dma_in_progress = false; 890 dmae->cur = NULL; 891 dmae->desc_current = NULL; 892 host->data->host_cookie = 0; 893 894 mmci_dma_unmap(host, host->data); 895 } 896 897 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 898 { 899 struct mmci_dmae_priv *dmae = host->dma_priv; 900 u32 status; 901 int i; 902 903 if (!dma_inprogress(host)) 904 return; 905 906 /* Wait up to 1ms for the DMA to complete */ 907 for (i = 0; ; i++) { 908 status = readl(host->base + MMCISTATUS); 909 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 910 break; 911 udelay(10); 912 } 913 914 /* 915 * Check to see whether we still have some data left in the FIFO - 916 * this catches DMA controllers which are unable to monitor the 917 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 918 * contiguous buffers. On TX, we'll get a FIFO underrun error. 919 */ 920 if (status & MCI_RXDATAAVLBLMASK) { 921 mmci_dma_error(host); 922 if (!data->error) 923 data->error = -EIO; 924 } else if (!data->host_cookie) { 925 mmci_dma_unmap(host, data); 926 } 927 928 /* 929 * Use of DMA with scatter-gather is impossible. 930 * Give up with DMA and switch back to PIO mode. 931 */ 932 if (status & MCI_RXDATAAVLBLMASK) { 933 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 934 mmci_dma_release(host); 935 } 936 937 host->dma_in_progress = false; 938 dmae->cur = NULL; 939 dmae->desc_current = NULL; 940 } 941 942 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 943 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 944 struct dma_chan **dma_chan, 945 struct dma_async_tx_descriptor **dma_desc) 946 { 947 struct mmci_dmae_priv *dmae = host->dma_priv; 948 struct variant_data *variant = host->variant; 949 struct dma_slave_config conf = { 950 .src_addr = host->phybase + MMCIFIFO, 951 .dst_addr = host->phybase + MMCIFIFO, 952 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 953 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 954 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 955 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 956 .device_fc = false, 957 }; 958 struct dma_chan *chan; 959 struct dma_device *device; 960 struct dma_async_tx_descriptor *desc; 961 int nr_sg; 962 unsigned long flags = DMA_CTRL_ACK; 963 964 if (data->flags & MMC_DATA_READ) { 965 conf.direction = DMA_DEV_TO_MEM; 966 chan = dmae->rx_channel; 967 } else { 968 conf.direction = DMA_MEM_TO_DEV; 969 chan = dmae->tx_channel; 970 } 971 972 /* If there's no DMA channel, fall back to PIO */ 973 if (!chan) 974 return -EINVAL; 975 976 /* If less than or equal to the fifo size, don't bother with DMA */ 977 if (data->blksz * data->blocks <= variant->fifosize) 978 return -EINVAL; 979 980 /* 981 * This is necessary to get SDIO working on the Ux500. We do not yet 982 * know if this is a bug in: 983 * - The Ux500 DMA controller (DMA40) 984 * - The MMCI DMA interface on the Ux500 985 * some power of two blocks (such as 64 bytes) are sent regularly 986 * during SDIO traffic and those work fine so for these we enable DMA 987 * transfers. 988 */ 989 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) 990 return -EINVAL; 991 992 device = chan->device; 993 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 994 mmc_get_dma_dir(data)); 995 if (nr_sg == 0) 996 return -EINVAL; 997 998 if (host->variant->qcom_dml) 999 flags |= DMA_PREP_INTERRUPT; 1000 1001 dmaengine_slave_config(chan, &conf); 1002 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 1003 conf.direction, flags); 1004 if (!desc) 1005 goto unmap_exit; 1006 1007 *dma_chan = chan; 1008 *dma_desc = desc; 1009 1010 return 0; 1011 1012 unmap_exit: 1013 dma_unmap_sg(device->dev, data->sg, data->sg_len, 1014 mmc_get_dma_dir(data)); 1015 return -ENOMEM; 1016 } 1017 1018 int mmci_dmae_prep_data(struct mmci_host *host, 1019 struct mmc_data *data, 1020 bool next) 1021 { 1022 struct mmci_dmae_priv *dmae = host->dma_priv; 1023 struct mmci_dmae_next *nd = &dmae->next_data; 1024 1025 if (!host->use_dma) 1026 return -EINVAL; 1027 1028 if (next) 1029 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 1030 /* Check if next job is already prepared. */ 1031 if (dmae->cur && dmae->desc_current) 1032 return 0; 1033 1034 /* No job were prepared thus do it now. */ 1035 return _mmci_dmae_prep_data(host, data, &dmae->cur, 1036 &dmae->desc_current); 1037 } 1038 1039 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 1040 { 1041 struct mmci_dmae_priv *dmae = host->dma_priv; 1042 int ret; 1043 1044 host->dma_in_progress = true; 1045 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); 1046 if (ret < 0) { 1047 host->dma_in_progress = false; 1048 return ret; 1049 } 1050 dma_async_issue_pending(dmae->cur); 1051 1052 *datactrl |= MCI_DPSM_DMAENABLE; 1053 1054 return 0; 1055 } 1056 1057 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 1058 { 1059 struct mmci_dmae_priv *dmae = host->dma_priv; 1060 struct mmci_dmae_next *next = &dmae->next_data; 1061 1062 if (!host->use_dma) 1063 return; 1064 1065 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 1066 1067 dmae->desc_current = next->desc; 1068 dmae->cur = next->chan; 1069 next->desc = NULL; 1070 next->chan = NULL; 1071 } 1072 1073 void mmci_dmae_unprep_data(struct mmci_host *host, 1074 struct mmc_data *data, int err) 1075 1076 { 1077 struct mmci_dmae_priv *dmae = host->dma_priv; 1078 1079 if (!host->use_dma) 1080 return; 1081 1082 mmci_dma_unmap(host, data); 1083 1084 if (err) { 1085 struct mmci_dmae_next *next = &dmae->next_data; 1086 struct dma_chan *chan; 1087 if (data->flags & MMC_DATA_READ) 1088 chan = dmae->rx_channel; 1089 else 1090 chan = dmae->tx_channel; 1091 dmaengine_terminate_all(chan); 1092 1093 if (dmae->desc_current == next->desc) 1094 dmae->desc_current = NULL; 1095 1096 if (dmae->cur == next->chan) { 1097 host->dma_in_progress = false; 1098 dmae->cur = NULL; 1099 } 1100 1101 next->desc = NULL; 1102 next->chan = NULL; 1103 } 1104 } 1105 1106 static struct mmci_host_ops mmci_variant_ops = { 1107 .prep_data = mmci_dmae_prep_data, 1108 .unprep_data = mmci_dmae_unprep_data, 1109 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1110 .get_next_data = mmci_dmae_get_next_data, 1111 .dma_setup = mmci_dmae_setup, 1112 .dma_release = mmci_dmae_release, 1113 .dma_start = mmci_dmae_start, 1114 .dma_finalize = mmci_dmae_finalize, 1115 .dma_error = mmci_dmae_error, 1116 }; 1117 #else 1118 static struct mmci_host_ops mmci_variant_ops = { 1119 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1120 }; 1121 #endif 1122 1123 static void mmci_variant_init(struct mmci_host *host) 1124 { 1125 host->ops = &mmci_variant_ops; 1126 } 1127 1128 static void ux500_variant_init(struct mmci_host *host) 1129 { 1130 host->ops = &mmci_variant_ops; 1131 host->ops->busy_complete = ux500_busy_complete; 1132 } 1133 1134 static void ux500v2_variant_init(struct mmci_host *host) 1135 { 1136 host->ops = &mmci_variant_ops; 1137 host->ops->busy_complete = ux500_busy_complete; 1138 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1139 } 1140 1141 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1142 { 1143 struct mmci_host *host = mmc_priv(mmc); 1144 struct mmc_data *data = mrq->data; 1145 1146 if (!data) 1147 return; 1148 1149 WARN_ON(data->host_cookie); 1150 1151 if (mmci_validate_data(host, data)) 1152 return; 1153 1154 mmci_prep_data(host, data, true); 1155 } 1156 1157 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1158 int err) 1159 { 1160 struct mmci_host *host = mmc_priv(mmc); 1161 struct mmc_data *data = mrq->data; 1162 1163 if (!data || !data->host_cookie) 1164 return; 1165 1166 mmci_unprep_data(host, data, err); 1167 } 1168 1169 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1170 { 1171 struct variant_data *variant = host->variant; 1172 unsigned int datactrl, timeout, irqmask; 1173 unsigned long long clks; 1174 void __iomem *base; 1175 1176 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1177 data->blksz, data->blocks, data->flags); 1178 1179 host->data = data; 1180 host->size = data->blksz * data->blocks; 1181 data->bytes_xfered = 0; 1182 1183 clks = (unsigned long long)data->timeout_ns * host->cclk; 1184 do_div(clks, NSEC_PER_SEC); 1185 1186 timeout = data->timeout_clks + (unsigned int)clks; 1187 1188 base = host->base; 1189 writel(timeout, base + MMCIDATATIMER); 1190 writel(host->size, base + MMCIDATALENGTH); 1191 1192 datactrl = host->ops->get_datactrl_cfg(host); 1193 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1194 1195 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1196 u32 clk; 1197 1198 datactrl |= variant->datactrl_mask_sdio; 1199 1200 /* 1201 * The ST Micro variant for SDIO small write transfers 1202 * needs to have clock H/W flow control disabled, 1203 * otherwise the transfer will not start. The threshold 1204 * depends on the rate of MCLK. 1205 */ 1206 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1207 (host->size < 8 || 1208 (host->size <= 8 && host->mclk > 50000000))) 1209 clk = host->clk_reg & ~variant->clkreg_enable; 1210 else 1211 clk = host->clk_reg | variant->clkreg_enable; 1212 1213 mmci_write_clkreg(host, clk); 1214 } 1215 1216 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1217 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1218 datactrl |= variant->datactrl_mask_ddrmode; 1219 1220 /* 1221 * Attempt to use DMA operation mode, if this 1222 * should fail, fall back to PIO mode 1223 */ 1224 if (!mmci_dma_start(host, datactrl)) 1225 return; 1226 1227 /* IRQ mode, map the SG list for CPU reading/writing */ 1228 mmci_init_sg(host, data); 1229 1230 if (data->flags & MMC_DATA_READ) { 1231 irqmask = MCI_RXFIFOHALFFULLMASK; 1232 1233 /* 1234 * If we have less than the fifo 'half-full' threshold to 1235 * transfer, trigger a PIO interrupt as soon as any data 1236 * is available. 1237 */ 1238 if (host->size < variant->fifohalfsize) 1239 irqmask |= MCI_RXDATAAVLBLMASK; 1240 } else { 1241 /* 1242 * We don't actually need to include "FIFO empty" here 1243 * since its implicit in "FIFO half empty". 1244 */ 1245 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1246 } 1247 1248 mmci_write_datactrlreg(host, datactrl); 1249 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1250 mmci_set_mask1(host, irqmask); 1251 } 1252 1253 static void 1254 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1255 { 1256 void __iomem *base = host->base; 1257 unsigned long long clks; 1258 1259 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1260 cmd->opcode, cmd->arg, cmd->flags); 1261 1262 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1263 writel(0, base + MMCICOMMAND); 1264 mmci_reg_delay(host); 1265 } 1266 1267 if (host->variant->cmdreg_stop && 1268 cmd->opcode == MMC_STOP_TRANSMISSION) 1269 c |= host->variant->cmdreg_stop; 1270 1271 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1272 if (cmd->flags & MMC_RSP_PRESENT) { 1273 if (cmd->flags & MMC_RSP_136) 1274 c |= host->variant->cmdreg_lrsp_crc; 1275 else if (cmd->flags & MMC_RSP_CRC) 1276 c |= host->variant->cmdreg_srsp_crc; 1277 else 1278 c |= host->variant->cmdreg_srsp; 1279 } 1280 1281 host->busy_status = 0; 1282 host->busy_state = MMCI_BUSY_DONE; 1283 1284 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1285 if (!cmd->busy_timeout) 1286 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1287 1288 if (cmd->busy_timeout > host->mmc->max_busy_timeout) 1289 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; 1290 else 1291 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1292 1293 do_div(clks, MSEC_PER_SEC); 1294 writel_relaxed(clks, host->base + MMCIDATATIMER); 1295 } 1296 1297 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) 1298 host->ops->pre_sig_volt_switch(host); 1299 1300 if (/*interrupt*/0) 1301 c |= MCI_CPSM_INTERRUPT; 1302 1303 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1304 c |= host->variant->data_cmd_enable; 1305 1306 host->cmd = cmd; 1307 1308 writel(cmd->arg, base + MMCIARGUMENT); 1309 writel(c, base + MMCICOMMAND); 1310 } 1311 1312 static void mmci_stop_command(struct mmci_host *host) 1313 { 1314 host->stop_abort.error = 0; 1315 mmci_start_command(host, &host->stop_abort, 0); 1316 } 1317 1318 static void 1319 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1320 unsigned int status) 1321 { 1322 unsigned int status_err; 1323 1324 /* Make sure we have data to handle */ 1325 if (!data) 1326 return; 1327 1328 /* First check for errors */ 1329 status_err = status & (host->variant->start_err | 1330 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1331 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1332 1333 if (status_err) { 1334 u32 remain, success; 1335 1336 /* Terminate the DMA transfer */ 1337 mmci_dma_error(host); 1338 1339 /* 1340 * Calculate how far we are into the transfer. Note that 1341 * the data counter gives the number of bytes transferred 1342 * on the MMC bus, not on the host side. On reads, this 1343 * can be as much as a FIFO-worth of data ahead. This 1344 * matters for FIFO overruns only. 1345 */ 1346 if (!host->variant->datacnt_useless) { 1347 remain = readl(host->base + MMCIDATACNT); 1348 success = data->blksz * data->blocks - remain; 1349 } else { 1350 success = 0; 1351 } 1352 1353 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1354 status_err, success); 1355 if (status_err & MCI_DATACRCFAIL) { 1356 /* Last block was not successful */ 1357 success -= 1; 1358 data->error = -EILSEQ; 1359 } else if (status_err & MCI_DATATIMEOUT) { 1360 data->error = -ETIMEDOUT; 1361 } else if (status_err & MCI_STARTBITERR) { 1362 data->error = -ECOMM; 1363 } else if (status_err & MCI_TXUNDERRUN) { 1364 data->error = -EIO; 1365 } else if (status_err & MCI_RXOVERRUN) { 1366 if (success > host->variant->fifosize) 1367 success -= host->variant->fifosize; 1368 else 1369 success = 0; 1370 data->error = -EIO; 1371 } 1372 data->bytes_xfered = round_down(success, data->blksz); 1373 } 1374 1375 if (status & MCI_DATABLOCKEND) 1376 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1377 1378 if (status & MCI_DATAEND || data->error) { 1379 mmci_dma_finalize(host, data); 1380 1381 mmci_stop_data(host); 1382 1383 if (!data->error) 1384 /* The error clause is handled above, success! */ 1385 data->bytes_xfered = data->blksz * data->blocks; 1386 1387 if (!data->stop) { 1388 if (host->variant->cmdreg_stop && data->error) 1389 mmci_stop_command(host); 1390 else 1391 mmci_request_end(host, data->mrq); 1392 } else if (host->mrq->sbc && !data->error) { 1393 mmci_request_end(host, data->mrq); 1394 } else { 1395 mmci_start_command(host, data->stop, 0); 1396 } 1397 } 1398 } 1399 1400 static void 1401 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1402 unsigned int status) 1403 { 1404 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1405 void __iomem *base = host->base; 1406 bool sbc, busy_resp; 1407 1408 if (!cmd) 1409 return; 1410 1411 sbc = (cmd == host->mrq->sbc); 1412 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1413 1414 /* 1415 * We need to be one of these interrupts to be considered worth 1416 * handling. Note that we tag on any latent IRQs postponed 1417 * due to waiting for busy status. 1418 */ 1419 if (host->variant->busy_timeout && busy_resp) 1420 err_msk |= MCI_DATATIMEOUT; 1421 1422 if (!((status | host->busy_status) & 1423 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1424 return; 1425 1426 /* Handle busy detection on DAT0 if the variant supports it. */ 1427 if (busy_resp && host->variant->busy_detect) 1428 if (!host->ops->busy_complete(host, status, err_msk)) 1429 return; 1430 1431 host->cmd = NULL; 1432 1433 if (status & MCI_CMDTIMEOUT) { 1434 cmd->error = -ETIMEDOUT; 1435 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1436 cmd->error = -EILSEQ; 1437 } else if (host->variant->busy_timeout && busy_resp && 1438 status & MCI_DATATIMEOUT) { 1439 cmd->error = -ETIMEDOUT; 1440 /* 1441 * This will wake up mmci_irq_thread() which will issue 1442 * a hardware reset of the MMCI block. 1443 */ 1444 host->irq_action = IRQ_WAKE_THREAD; 1445 } else { 1446 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1447 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1448 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1449 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1450 } 1451 1452 if ((!sbc && !cmd->data) || cmd->error) { 1453 if (host->data) { 1454 /* Terminate the DMA transfer */ 1455 mmci_dma_error(host); 1456 1457 mmci_stop_data(host); 1458 if (host->variant->cmdreg_stop && cmd->error) { 1459 mmci_stop_command(host); 1460 return; 1461 } 1462 } 1463 1464 if (host->irq_action != IRQ_WAKE_THREAD) 1465 mmci_request_end(host, host->mrq); 1466 1467 } else if (sbc) { 1468 mmci_start_command(host, host->mrq->cmd, 0); 1469 } else if (!host->variant->datactrl_first && 1470 !(cmd->data->flags & MMC_DATA_READ)) { 1471 mmci_start_data(host, cmd->data); 1472 } 1473 } 1474 1475 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1476 { 1477 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1478 } 1479 1480 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1481 { 1482 /* 1483 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1484 * from the fifo range should be used 1485 */ 1486 if (status & MCI_RXFIFOHALFFULL) 1487 return host->variant->fifohalfsize; 1488 else if (status & MCI_RXDATAAVLBL) 1489 return 4; 1490 1491 return 0; 1492 } 1493 1494 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1495 { 1496 void __iomem *base = host->base; 1497 char *ptr = buffer; 1498 u32 status = readl(host->base + MMCISTATUS); 1499 int host_remain = host->size; 1500 1501 do { 1502 int count = host->get_rx_fifocnt(host, status, host_remain); 1503 1504 if (count > remain) 1505 count = remain; 1506 1507 if (count <= 0) 1508 break; 1509 1510 /* 1511 * SDIO especially may want to send something that is 1512 * not divisible by 4 (as opposed to card sectors 1513 * etc). Therefore make sure to always read the last bytes 1514 * while only doing full 32-bit reads towards the FIFO. 1515 */ 1516 if (unlikely(count & 0x3)) { 1517 if (count < 4) { 1518 unsigned char buf[4]; 1519 ioread32_rep(base + MMCIFIFO, buf, 1); 1520 memcpy(ptr, buf, count); 1521 } else { 1522 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1523 count &= ~0x3; 1524 } 1525 } else { 1526 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1527 } 1528 1529 ptr += count; 1530 remain -= count; 1531 host_remain -= count; 1532 1533 if (remain == 0) 1534 break; 1535 1536 status = readl(base + MMCISTATUS); 1537 } while (status & MCI_RXDATAAVLBL); 1538 1539 return ptr - buffer; 1540 } 1541 1542 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1543 { 1544 struct variant_data *variant = host->variant; 1545 void __iomem *base = host->base; 1546 char *ptr = buffer; 1547 1548 do { 1549 unsigned int count, maxcnt; 1550 1551 maxcnt = status & MCI_TXFIFOEMPTY ? 1552 variant->fifosize : variant->fifohalfsize; 1553 count = min(remain, maxcnt); 1554 1555 /* 1556 * SDIO especially may want to send something that is 1557 * not divisible by 4 (as opposed to card sectors 1558 * etc), and the FIFO only accept full 32-bit writes. 1559 * So compensate by adding +3 on the count, a single 1560 * byte become a 32bit write, 7 bytes will be two 1561 * 32bit writes etc. 1562 */ 1563 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1564 1565 ptr += count; 1566 remain -= count; 1567 1568 if (remain == 0) 1569 break; 1570 1571 status = readl(base + MMCISTATUS); 1572 } while (status & MCI_TXFIFOHALFEMPTY); 1573 1574 return ptr - buffer; 1575 } 1576 1577 /* 1578 * PIO data transfer IRQ handler. 1579 */ 1580 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1581 { 1582 struct mmci_host *host = dev_id; 1583 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1584 struct variant_data *variant = host->variant; 1585 void __iomem *base = host->base; 1586 u32 status; 1587 1588 status = readl(base + MMCISTATUS); 1589 1590 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1591 1592 do { 1593 unsigned int remain, len; 1594 char *buffer; 1595 1596 /* 1597 * For write, we only need to test the half-empty flag 1598 * here - if the FIFO is completely empty, then by 1599 * definition it is more than half empty. 1600 * 1601 * For read, check for data available. 1602 */ 1603 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1604 break; 1605 1606 if (!sg_miter_next(sg_miter)) 1607 break; 1608 1609 buffer = sg_miter->addr; 1610 remain = sg_miter->length; 1611 1612 len = 0; 1613 if (status & MCI_RXACTIVE) 1614 len = mmci_pio_read(host, buffer, remain); 1615 if (status & MCI_TXACTIVE) 1616 len = mmci_pio_write(host, buffer, remain, status); 1617 1618 sg_miter->consumed = len; 1619 1620 host->size -= len; 1621 remain -= len; 1622 1623 if (remain) 1624 break; 1625 1626 status = readl(base + MMCISTATUS); 1627 } while (1); 1628 1629 sg_miter_stop(sg_miter); 1630 1631 /* 1632 * If we have less than the fifo 'half-full' threshold to transfer, 1633 * trigger a PIO interrupt as soon as any data is available. 1634 */ 1635 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1636 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1637 1638 /* 1639 * If we run out of data, disable the data IRQs; this 1640 * prevents a race where the FIFO becomes empty before 1641 * the chip itself has disabled the data path, and 1642 * stops us racing with our data end IRQ. 1643 */ 1644 if (host->size == 0) { 1645 mmci_set_mask1(host, 0); 1646 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1647 } 1648 1649 return IRQ_HANDLED; 1650 } 1651 1652 /* 1653 * Handle completion of command and data transfers. 1654 */ 1655 static irqreturn_t mmci_irq(int irq, void *dev_id) 1656 { 1657 struct mmci_host *host = dev_id; 1658 u32 status; 1659 1660 spin_lock(&host->lock); 1661 host->irq_action = IRQ_HANDLED; 1662 1663 do { 1664 status = readl(host->base + MMCISTATUS); 1665 if (!status) 1666 break; 1667 1668 if (host->singleirq) { 1669 if (status & host->mask1_reg) 1670 mmci_pio_irq(irq, dev_id); 1671 1672 status &= ~host->variant->irq_pio_mask; 1673 } 1674 1675 /* 1676 * Busy detection is managed by mmci_cmd_irq(), including to 1677 * clear the corresponding IRQ. 1678 */ 1679 status &= readl(host->base + MMCIMASK0); 1680 if (host->variant->busy_detect) 1681 writel(status & ~host->variant->busy_detect_mask, 1682 host->base + MMCICLEAR); 1683 else 1684 writel(status, host->base + MMCICLEAR); 1685 1686 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1687 1688 if (host->variant->reversed_irq_handling) { 1689 mmci_data_irq(host, host->data, status); 1690 mmci_cmd_irq(host, host->cmd, status); 1691 } else { 1692 mmci_cmd_irq(host, host->cmd, status); 1693 mmci_data_irq(host, host->data, status); 1694 } 1695 1696 /* 1697 * Busy detection has been handled by mmci_cmd_irq() above. 1698 * Clear the status bit to prevent polling in IRQ context. 1699 */ 1700 if (host->variant->busy_detect_flag) 1701 status &= ~host->variant->busy_detect_flag; 1702 1703 } while (status); 1704 1705 spin_unlock(&host->lock); 1706 1707 return host->irq_action; 1708 } 1709 1710 /* 1711 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. 1712 * 1713 * A reset is needed for some variants, where a datatimeout for a R1B request 1714 * causes the DPSM to stay busy (non-functional). 1715 */ 1716 static irqreturn_t mmci_irq_thread(int irq, void *dev_id) 1717 { 1718 struct mmci_host *host = dev_id; 1719 unsigned long flags; 1720 1721 if (host->rst) { 1722 reset_control_assert(host->rst); 1723 udelay(2); 1724 reset_control_deassert(host->rst); 1725 } 1726 1727 spin_lock_irqsave(&host->lock, flags); 1728 writel(host->clk_reg, host->base + MMCICLOCK); 1729 writel(host->pwr_reg, host->base + MMCIPOWER); 1730 writel(MCI_IRQENABLE | host->variant->start_err, 1731 host->base + MMCIMASK0); 1732 1733 host->irq_action = IRQ_HANDLED; 1734 mmci_request_end(host, host->mrq); 1735 spin_unlock_irqrestore(&host->lock, flags); 1736 1737 return host->irq_action; 1738 } 1739 1740 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1741 { 1742 struct mmci_host *host = mmc_priv(mmc); 1743 unsigned long flags; 1744 1745 WARN_ON(host->mrq != NULL); 1746 1747 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1748 if (mrq->cmd->error) { 1749 mmc_request_done(mmc, mrq); 1750 return; 1751 } 1752 1753 spin_lock_irqsave(&host->lock, flags); 1754 1755 host->mrq = mrq; 1756 1757 if (mrq->data) 1758 mmci_get_next_data(host, mrq->data); 1759 1760 if (mrq->data && 1761 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1762 mmci_start_data(host, mrq->data); 1763 1764 if (mrq->sbc) 1765 mmci_start_command(host, mrq->sbc, 0); 1766 else 1767 mmci_start_command(host, mrq->cmd, 0); 1768 1769 spin_unlock_irqrestore(&host->lock, flags); 1770 } 1771 1772 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1773 { 1774 struct mmci_host *host = mmc_priv(mmc); 1775 u32 max_busy_timeout = 0; 1776 1777 if (!host->variant->busy_detect) 1778 return; 1779 1780 if (host->variant->busy_timeout && mmc->actual_clock) 1781 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, 1782 MSEC_PER_SEC); 1783 1784 mmc->max_busy_timeout = max_busy_timeout; 1785 } 1786 1787 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1788 { 1789 struct mmci_host *host = mmc_priv(mmc); 1790 struct variant_data *variant = host->variant; 1791 u32 pwr = 0; 1792 unsigned long flags; 1793 int ret; 1794 1795 switch (ios->power_mode) { 1796 case MMC_POWER_OFF: 1797 if (!IS_ERR(mmc->supply.vmmc)) 1798 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1799 1800 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1801 regulator_disable(mmc->supply.vqmmc); 1802 host->vqmmc_enabled = false; 1803 } 1804 1805 break; 1806 case MMC_POWER_UP: 1807 if (!IS_ERR(mmc->supply.vmmc)) 1808 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1809 1810 /* 1811 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1812 * and instead uses MCI_PWR_ON so apply whatever value is 1813 * configured in the variant data. 1814 */ 1815 pwr |= variant->pwrreg_powerup; 1816 1817 break; 1818 case MMC_POWER_ON: 1819 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1820 ret = regulator_enable(mmc->supply.vqmmc); 1821 if (ret < 0) 1822 dev_err(mmc_dev(mmc), 1823 "failed to enable vqmmc regulator\n"); 1824 else 1825 host->vqmmc_enabled = true; 1826 } 1827 1828 pwr |= MCI_PWR_ON; 1829 break; 1830 } 1831 1832 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1833 /* 1834 * The ST Micro variant has some additional bits 1835 * indicating signal direction for the signals in 1836 * the SD/MMC bus and feedback-clock usage. 1837 */ 1838 pwr |= host->pwr_reg_add; 1839 1840 if (ios->bus_width == MMC_BUS_WIDTH_4) 1841 pwr &= ~MCI_ST_DATA74DIREN; 1842 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1843 pwr &= (~MCI_ST_DATA74DIREN & 1844 ~MCI_ST_DATA31DIREN & 1845 ~MCI_ST_DATA2DIREN); 1846 } 1847 1848 if (variant->opendrain) { 1849 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1850 pwr |= variant->opendrain; 1851 } else { 1852 /* 1853 * If the variant cannot configure the pads by its own, then we 1854 * expect the pinctrl to be able to do that for us 1855 */ 1856 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1857 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1858 else 1859 pinctrl_select_default_state(mmc_dev(mmc)); 1860 } 1861 1862 /* 1863 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1864 * gating the clock, the MCI_PWR_ON bit is cleared. 1865 */ 1866 if (!ios->clock && variant->pwrreg_clkgate) 1867 pwr &= ~MCI_PWR_ON; 1868 1869 if (host->variant->explicit_mclk_control && 1870 ios->clock != host->clock_cache) { 1871 ret = clk_set_rate(host->clk, ios->clock); 1872 if (ret < 0) 1873 dev_err(mmc_dev(host->mmc), 1874 "Error setting clock rate (%d)\n", ret); 1875 else 1876 host->mclk = clk_get_rate(host->clk); 1877 } 1878 host->clock_cache = ios->clock; 1879 1880 spin_lock_irqsave(&host->lock, flags); 1881 1882 if (host->ops && host->ops->set_clkreg) 1883 host->ops->set_clkreg(host, ios->clock); 1884 else 1885 mmci_set_clkreg(host, ios->clock); 1886 1887 mmci_set_max_busy_timeout(mmc); 1888 1889 if (host->ops && host->ops->set_pwrreg) 1890 host->ops->set_pwrreg(host, pwr); 1891 else 1892 mmci_write_pwrreg(host, pwr); 1893 1894 mmci_reg_delay(host); 1895 1896 spin_unlock_irqrestore(&host->lock, flags); 1897 } 1898 1899 static int mmci_get_cd(struct mmc_host *mmc) 1900 { 1901 struct mmci_host *host = mmc_priv(mmc); 1902 struct mmci_platform_data *plat = host->plat; 1903 unsigned int status = mmc_gpio_get_cd(mmc); 1904 1905 if (status == -ENOSYS) { 1906 if (!plat->status) 1907 return 1; /* Assume always present */ 1908 1909 status = plat->status(mmc_dev(host->mmc)); 1910 } 1911 return status; 1912 } 1913 1914 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1915 { 1916 struct mmci_host *host = mmc_priv(mmc); 1917 int ret; 1918 1919 ret = mmc_regulator_set_vqmmc(mmc, ios); 1920 1921 if (!ret && host->ops && host->ops->post_sig_volt_switch) 1922 ret = host->ops->post_sig_volt_switch(host, ios); 1923 else if (ret) 1924 ret = 0; 1925 1926 if (ret < 0) 1927 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1928 1929 return ret; 1930 } 1931 1932 static struct mmc_host_ops mmci_ops = { 1933 .request = mmci_request, 1934 .pre_req = mmci_pre_request, 1935 .post_req = mmci_post_request, 1936 .set_ios = mmci_set_ios, 1937 .get_ro = mmc_gpio_get_ro, 1938 .get_cd = mmci_get_cd, 1939 .start_signal_voltage_switch = mmci_sig_volt_switch, 1940 }; 1941 1942 static void mmci_probe_level_translator(struct mmc_host *mmc) 1943 { 1944 struct device *dev = mmc_dev(mmc); 1945 struct mmci_host *host = mmc_priv(mmc); 1946 struct gpio_desc *cmd_gpio; 1947 struct gpio_desc *ck_gpio; 1948 struct gpio_desc *ckin_gpio; 1949 int clk_hi, clk_lo; 1950 1951 /* 1952 * Assume the level translator is present if st,use-ckin is set. 1953 * This is to cater for DTs which do not implement this test. 1954 */ 1955 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1956 1957 cmd_gpio = gpiod_get(dev, "st,cmd", GPIOD_OUT_HIGH); 1958 if (IS_ERR(cmd_gpio)) 1959 goto exit_cmd; 1960 1961 ck_gpio = gpiod_get(dev, "st,ck", GPIOD_OUT_HIGH); 1962 if (IS_ERR(ck_gpio)) 1963 goto exit_ck; 1964 1965 ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); 1966 if (IS_ERR(ckin_gpio)) 1967 goto exit_ckin; 1968 1969 /* All GPIOs are valid, test whether level translator works */ 1970 1971 /* Sample CKIN */ 1972 clk_hi = !!gpiod_get_value(ckin_gpio); 1973 1974 /* Set CK low */ 1975 gpiod_set_value(ck_gpio, 0); 1976 1977 /* Sample CKIN */ 1978 clk_lo = !!gpiod_get_value(ckin_gpio); 1979 1980 /* Tristate all */ 1981 gpiod_direction_input(cmd_gpio); 1982 gpiod_direction_input(ck_gpio); 1983 1984 /* Level translator is present if CK signal is propagated to CKIN */ 1985 if (!clk_hi || clk_lo) { 1986 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; 1987 dev_warn(dev, 1988 "Level translator inoperable, CK signal not detected on CKIN, disabling.\n"); 1989 } 1990 1991 gpiod_put(ckin_gpio); 1992 1993 exit_ckin: 1994 gpiod_put(ck_gpio); 1995 exit_ck: 1996 gpiod_put(cmd_gpio); 1997 exit_cmd: 1998 pinctrl_select_default_state(dev); 1999 } 2000 2001 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 2002 { 2003 struct mmci_host *host = mmc_priv(mmc); 2004 int ret = mmc_of_parse(mmc); 2005 2006 if (ret) 2007 return ret; 2008 2009 if (of_property_read_bool(np, "st,sig-dir-dat0")) 2010 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 2011 if (of_property_read_bool(np, "st,sig-dir-dat2")) 2012 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 2013 if (of_property_read_bool(np, "st,sig-dir-dat31")) 2014 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 2015 if (of_property_read_bool(np, "st,sig-dir-dat74")) 2016 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 2017 if (of_property_read_bool(np, "st,sig-dir-cmd")) 2018 host->pwr_reg_add |= MCI_ST_CMDDIREN; 2019 if (of_property_read_bool(np, "st,sig-pin-fbclk")) 2020 host->pwr_reg_add |= MCI_ST_FBCLKEN; 2021 if (of_property_read_bool(np, "st,sig-dir")) 2022 host->pwr_reg_add |= MCI_STM32_DIRPOL; 2023 if (of_property_read_bool(np, "st,neg-edge")) 2024 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 2025 if (of_property_read_bool(np, "st,use-ckin")) 2026 mmci_probe_level_translator(mmc); 2027 2028 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) 2029 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 2030 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) 2031 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2032 2033 return 0; 2034 } 2035 2036 static int mmci_probe(struct amba_device *dev, 2037 const struct amba_id *id) 2038 { 2039 struct mmci_platform_data *plat = dev->dev.platform_data; 2040 struct device_node *np = dev->dev.of_node; 2041 struct variant_data *variant = id->data; 2042 struct mmci_host *host; 2043 struct mmc_host *mmc; 2044 int ret; 2045 2046 /* Must have platform data or Device Tree. */ 2047 if (!plat && !np) { 2048 dev_err(&dev->dev, "No plat data or DT found\n"); 2049 return -EINVAL; 2050 } 2051 2052 if (!plat) { 2053 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 2054 if (!plat) 2055 return -ENOMEM; 2056 } 2057 2058 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 2059 if (!mmc) 2060 return -ENOMEM; 2061 2062 host = mmc_priv(mmc); 2063 host->mmc = mmc; 2064 host->mmc_ops = &mmci_ops; 2065 mmc->ops = &mmci_ops; 2066 2067 ret = mmci_of_parse(np, mmc); 2068 if (ret) 2069 goto host_free; 2070 2071 /* 2072 * Some variant (STM32) doesn't have opendrain bit, nevertheless 2073 * pins can be set accordingly using pinctrl 2074 */ 2075 if (!variant->opendrain) { 2076 host->pinctrl = devm_pinctrl_get(&dev->dev); 2077 if (IS_ERR(host->pinctrl)) { 2078 dev_err(&dev->dev, "failed to get pinctrl"); 2079 ret = PTR_ERR(host->pinctrl); 2080 goto host_free; 2081 } 2082 2083 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 2084 MMCI_PINCTRL_STATE_OPENDRAIN); 2085 if (IS_ERR(host->pins_opendrain)) { 2086 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 2087 ret = PTR_ERR(host->pins_opendrain); 2088 goto host_free; 2089 } 2090 } 2091 2092 host->hw_designer = amba_manf(dev); 2093 host->hw_revision = amba_rev(dev); 2094 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 2095 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 2096 2097 host->clk = devm_clk_get(&dev->dev, NULL); 2098 if (IS_ERR(host->clk)) { 2099 ret = PTR_ERR(host->clk); 2100 goto host_free; 2101 } 2102 2103 ret = clk_prepare_enable(host->clk); 2104 if (ret) 2105 goto host_free; 2106 2107 if (variant->qcom_fifo) 2108 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 2109 else 2110 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 2111 2112 host->plat = plat; 2113 host->variant = variant; 2114 host->mclk = clk_get_rate(host->clk); 2115 /* 2116 * According to the spec, mclk is max 100 MHz, 2117 * so we try to adjust the clock down to this, 2118 * (if possible). 2119 */ 2120 if (host->mclk > variant->f_max) { 2121 ret = clk_set_rate(host->clk, variant->f_max); 2122 if (ret < 0) 2123 goto clk_disable; 2124 host->mclk = clk_get_rate(host->clk); 2125 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 2126 host->mclk); 2127 } 2128 2129 host->phybase = dev->res.start; 2130 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 2131 if (IS_ERR(host->base)) { 2132 ret = PTR_ERR(host->base); 2133 goto clk_disable; 2134 } 2135 2136 if (variant->init) 2137 variant->init(host); 2138 2139 /* 2140 * The ARM and ST versions of the block have slightly different 2141 * clock divider equations which means that the minimum divider 2142 * differs too. 2143 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 2144 */ 2145 if (variant->st_clkdiv) 2146 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 2147 else if (variant->stm32_clkdiv) 2148 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 2149 else if (variant->explicit_mclk_control) 2150 mmc->f_min = clk_round_rate(host->clk, 100000); 2151 else 2152 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 2153 /* 2154 * If no maximum operating frequency is supplied, fall back to use 2155 * the module parameter, which has a (low) default value in case it 2156 * is not specified. Either value must not exceed the clock rate into 2157 * the block, of course. 2158 */ 2159 if (mmc->f_max) 2160 mmc->f_max = variant->explicit_mclk_control ? 2161 min(variant->f_max, mmc->f_max) : 2162 min(host->mclk, mmc->f_max); 2163 else 2164 mmc->f_max = variant->explicit_mclk_control ? 2165 fmax : min(host->mclk, fmax); 2166 2167 2168 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 2169 2170 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 2171 if (IS_ERR(host->rst)) { 2172 ret = PTR_ERR(host->rst); 2173 goto clk_disable; 2174 } 2175 ret = reset_control_deassert(host->rst); 2176 if (ret) 2177 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); 2178 2179 /* Get regulators and the supported OCR mask */ 2180 ret = mmc_regulator_get_supply(mmc); 2181 if (ret) 2182 goto clk_disable; 2183 2184 if (!mmc->ocr_avail) 2185 mmc->ocr_avail = plat->ocr_mask; 2186 else if (plat->ocr_mask) 2187 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 2188 2189 /* We support these capabilities. */ 2190 mmc->caps |= MMC_CAP_CMD23; 2191 2192 /* 2193 * Enable busy detection. 2194 */ 2195 if (variant->busy_detect) { 2196 mmci_ops.card_busy = mmci_card_busy; 2197 /* 2198 * Not all variants have a flag to enable busy detection 2199 * in the DPSM, but if they do, set it here. 2200 */ 2201 if (variant->busy_dpsm_flag) 2202 mmci_write_datactrlreg(host, 2203 host->variant->busy_dpsm_flag); 2204 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2205 } 2206 2207 /* Variants with mandatory busy timeout in HW needs R1B responses. */ 2208 if (variant->busy_timeout) 2209 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 2210 2211 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2212 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2213 host->stop_abort.arg = 0; 2214 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2215 2216 /* We support these PM capabilities. */ 2217 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2218 2219 /* 2220 * We can do SGIO 2221 */ 2222 mmc->max_segs = NR_SG; 2223 2224 /* 2225 * Since only a certain number of bits are valid in the data length 2226 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2227 * single request. 2228 */ 2229 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2230 2231 /* 2232 * Set the maximum segment size. Since we aren't doing DMA 2233 * (yet) we are only limited by the data length register. 2234 */ 2235 mmc->max_seg_size = mmc->max_req_size; 2236 2237 /* 2238 * Block size can be up to 2048 bytes, but must be a power of two. 2239 */ 2240 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2241 2242 /* 2243 * Limit the number of blocks transferred so that we don't overflow 2244 * the maximum request size. 2245 */ 2246 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2247 2248 spin_lock_init(&host->lock); 2249 2250 writel(0, host->base + MMCIMASK0); 2251 2252 if (variant->mmcimask1) 2253 writel(0, host->base + MMCIMASK1); 2254 2255 writel(0xfff, host->base + MMCICLEAR); 2256 2257 /* 2258 * If: 2259 * - not using DT but using a descriptor table, or 2260 * - using a table of descriptors ALONGSIDE DT, or 2261 * look up these descriptors named "cd" and "wp" right here, fail 2262 * silently of these do not exist 2263 */ 2264 if (!np) { 2265 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 2266 if (ret == -EPROBE_DEFER) 2267 goto clk_disable; 2268 2269 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 2270 if (ret == -EPROBE_DEFER) 2271 goto clk_disable; 2272 } 2273 2274 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, 2275 mmci_irq_thread, IRQF_SHARED, 2276 DRIVER_NAME " (cmd)", host); 2277 if (ret) 2278 goto clk_disable; 2279 2280 if (!dev->irq[1]) 2281 host->singleirq = true; 2282 else { 2283 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2284 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2285 if (ret) 2286 goto clk_disable; 2287 } 2288 2289 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2290 2291 amba_set_drvdata(dev, mmc); 2292 2293 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2294 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2295 amba_rev(dev), (unsigned long long)dev->res.start, 2296 dev->irq[0], dev->irq[1]); 2297 2298 mmci_dma_setup(host); 2299 2300 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2301 pm_runtime_use_autosuspend(&dev->dev); 2302 2303 ret = mmc_add_host(mmc); 2304 if (ret) 2305 goto clk_disable; 2306 2307 pm_runtime_put(&dev->dev); 2308 return 0; 2309 2310 clk_disable: 2311 clk_disable_unprepare(host->clk); 2312 host_free: 2313 mmc_free_host(mmc); 2314 return ret; 2315 } 2316 2317 static void mmci_remove(struct amba_device *dev) 2318 { 2319 struct mmc_host *mmc = amba_get_drvdata(dev); 2320 2321 if (mmc) { 2322 struct mmci_host *host = mmc_priv(mmc); 2323 struct variant_data *variant = host->variant; 2324 2325 /* 2326 * Undo pm_runtime_put() in probe. We use the _sync 2327 * version here so that we can access the primecell. 2328 */ 2329 pm_runtime_get_sync(&dev->dev); 2330 2331 mmc_remove_host(mmc); 2332 2333 writel(0, host->base + MMCIMASK0); 2334 2335 if (variant->mmcimask1) 2336 writel(0, host->base + MMCIMASK1); 2337 2338 writel(0, host->base + MMCICOMMAND); 2339 writel(0, host->base + MMCIDATACTRL); 2340 2341 mmci_dma_release(host); 2342 clk_disable_unprepare(host->clk); 2343 mmc_free_host(mmc); 2344 } 2345 } 2346 2347 #ifdef CONFIG_PM 2348 static void mmci_save(struct mmci_host *host) 2349 { 2350 unsigned long flags; 2351 2352 spin_lock_irqsave(&host->lock, flags); 2353 2354 writel(0, host->base + MMCIMASK0); 2355 if (host->variant->pwrreg_nopower) { 2356 writel(0, host->base + MMCIDATACTRL); 2357 writel(0, host->base + MMCIPOWER); 2358 writel(0, host->base + MMCICLOCK); 2359 } 2360 mmci_reg_delay(host); 2361 2362 spin_unlock_irqrestore(&host->lock, flags); 2363 } 2364 2365 static void mmci_restore(struct mmci_host *host) 2366 { 2367 unsigned long flags; 2368 2369 spin_lock_irqsave(&host->lock, flags); 2370 2371 if (host->variant->pwrreg_nopower) { 2372 writel(host->clk_reg, host->base + MMCICLOCK); 2373 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2374 writel(host->pwr_reg, host->base + MMCIPOWER); 2375 } 2376 writel(MCI_IRQENABLE | host->variant->start_err, 2377 host->base + MMCIMASK0); 2378 mmci_reg_delay(host); 2379 2380 spin_unlock_irqrestore(&host->lock, flags); 2381 } 2382 2383 static int mmci_runtime_suspend(struct device *dev) 2384 { 2385 struct amba_device *adev = to_amba_device(dev); 2386 struct mmc_host *mmc = amba_get_drvdata(adev); 2387 2388 if (mmc) { 2389 struct mmci_host *host = mmc_priv(mmc); 2390 pinctrl_pm_select_sleep_state(dev); 2391 mmci_save(host); 2392 clk_disable_unprepare(host->clk); 2393 } 2394 2395 return 0; 2396 } 2397 2398 static int mmci_runtime_resume(struct device *dev) 2399 { 2400 struct amba_device *adev = to_amba_device(dev); 2401 struct mmc_host *mmc = amba_get_drvdata(adev); 2402 2403 if (mmc) { 2404 struct mmci_host *host = mmc_priv(mmc); 2405 clk_prepare_enable(host->clk); 2406 mmci_restore(host); 2407 pinctrl_select_default_state(dev); 2408 } 2409 2410 return 0; 2411 } 2412 #endif 2413 2414 static const struct dev_pm_ops mmci_dev_pm_ops = { 2415 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2416 pm_runtime_force_resume) 2417 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2418 }; 2419 2420 static const struct amba_id mmci_ids[] = { 2421 { 2422 .id = 0x00041180, 2423 .mask = 0xff0fffff, 2424 .data = &variant_arm, 2425 }, 2426 { 2427 .id = 0x01041180, 2428 .mask = 0xff0fffff, 2429 .data = &variant_arm_extended_fifo, 2430 }, 2431 { 2432 .id = 0x02041180, 2433 .mask = 0xff0fffff, 2434 .data = &variant_arm_extended_fifo_hwfc, 2435 }, 2436 { 2437 .id = 0x00041181, 2438 .mask = 0x000fffff, 2439 .data = &variant_arm, 2440 }, 2441 /* ST Micro variants */ 2442 { 2443 .id = 0x00180180, 2444 .mask = 0x00ffffff, 2445 .data = &variant_u300, 2446 }, 2447 { 2448 .id = 0x10180180, 2449 .mask = 0xf0ffffff, 2450 .data = &variant_nomadik, 2451 }, 2452 { 2453 .id = 0x00280180, 2454 .mask = 0x00ffffff, 2455 .data = &variant_nomadik, 2456 }, 2457 { 2458 .id = 0x00480180, 2459 .mask = 0xf0ffffff, 2460 .data = &variant_ux500, 2461 }, 2462 { 2463 .id = 0x10480180, 2464 .mask = 0xf0ffffff, 2465 .data = &variant_ux500v2, 2466 }, 2467 { 2468 .id = 0x00880180, 2469 .mask = 0x00ffffff, 2470 .data = &variant_stm32, 2471 }, 2472 { 2473 .id = 0x10153180, 2474 .mask = 0xf0ffffff, 2475 .data = &variant_stm32_sdmmc, 2476 }, 2477 { 2478 .id = 0x00253180, 2479 .mask = 0xf0ffffff, 2480 .data = &variant_stm32_sdmmcv2, 2481 }, 2482 { 2483 .id = 0x20253180, 2484 .mask = 0xf0ffffff, 2485 .data = &variant_stm32_sdmmcv2, 2486 }, 2487 /* Qualcomm variants */ 2488 { 2489 .id = 0x00051180, 2490 .mask = 0x000fffff, 2491 .data = &variant_qcom, 2492 }, 2493 { 0, 0 }, 2494 }; 2495 2496 MODULE_DEVICE_TABLE(amba, mmci_ids); 2497 2498 static struct amba_driver mmci_driver = { 2499 .drv = { 2500 .name = DRIVER_NAME, 2501 .pm = &mmci_dev_pm_ops, 2502 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2503 }, 2504 .probe = mmci_probe, 2505 .remove = mmci_remove, 2506 .id_table = mmci_ids, 2507 }; 2508 2509 module_amba_driver(mmci_driver); 2510 2511 module_param(fmax, uint, 0444); 2512 2513 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2514 MODULE_LICENSE("GPL"); 2515