1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 4 * 5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 6 * Copyright (C) 2010 ST-Ericsson SA 7 */ 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/ioport.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/interrupt.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/highmem.h> 20 #include <linux/log2.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/pm.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/card.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/slot-gpio.h> 27 #include <linux/amba/bus.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/of.h> 31 #include <linux/regulator/consumer.h> 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/amba/mmci.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/types.h> 37 #include <linux/pinctrl/consumer.h> 38 #include <linux/reset.h> 39 #include <linux/gpio/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 46 #define DRIVER_NAME "mmci-pl18x" 47 48 static void mmci_variant_init(struct mmci_host *host); 49 static void ux500_variant_init(struct mmci_host *host); 50 static void ux500v2_variant_init(struct mmci_host *host); 51 52 static unsigned int fmax = 515633; 53 54 static struct variant_data variant_arm = { 55 .fifosize = 16 * 4, 56 .fifohalfsize = 8 * 4, 57 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 58 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 59 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 60 .cmdreg_srsp = MCI_CPSM_RESPONSE, 61 .datalength_bits = 16, 62 .datactrl_blocksz = 11, 63 .pwrreg_powerup = MCI_PWR_UP, 64 .f_max = 100000000, 65 .reversed_irq_handling = true, 66 .mmcimask1 = true, 67 .irq_pio_mask = MCI_IRQ_PIO_MASK, 68 .start_err = MCI_STARTBITERR, 69 .opendrain = MCI_ROD, 70 .init = mmci_variant_init, 71 }; 72 73 static struct variant_data variant_arm_extended_fifo = { 74 .fifosize = 128 * 4, 75 .fifohalfsize = 64 * 4, 76 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 77 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 78 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 79 .cmdreg_srsp = MCI_CPSM_RESPONSE, 80 .datalength_bits = 16, 81 .datactrl_blocksz = 11, 82 .pwrreg_powerup = MCI_PWR_UP, 83 .f_max = 100000000, 84 .mmcimask1 = true, 85 .irq_pio_mask = MCI_IRQ_PIO_MASK, 86 .start_err = MCI_STARTBITERR, 87 .opendrain = MCI_ROD, 88 .init = mmci_variant_init, 89 }; 90 91 static struct variant_data variant_arm_extended_fifo_hwfc = { 92 .fifosize = 128 * 4, 93 .fifohalfsize = 64 * 4, 94 .clkreg_enable = MCI_ARM_HWFCEN, 95 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 96 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 97 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 98 .cmdreg_srsp = MCI_CPSM_RESPONSE, 99 .datalength_bits = 16, 100 .datactrl_blocksz = 11, 101 .pwrreg_powerup = MCI_PWR_UP, 102 .f_max = 100000000, 103 .mmcimask1 = true, 104 .irq_pio_mask = MCI_IRQ_PIO_MASK, 105 .start_err = MCI_STARTBITERR, 106 .opendrain = MCI_ROD, 107 .init = mmci_variant_init, 108 }; 109 110 static struct variant_data variant_u300 = { 111 .fifosize = 16 * 4, 112 .fifohalfsize = 8 * 4, 113 .clkreg_enable = MCI_ST_U300_HWFCEN, 114 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 115 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 116 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 117 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 118 .cmdreg_srsp = MCI_CPSM_RESPONSE, 119 .datalength_bits = 16, 120 .datactrl_blocksz = 11, 121 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 122 .st_sdio = true, 123 .pwrreg_powerup = MCI_PWR_ON, 124 .f_max = 100000000, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128 .mmcimask1 = true, 129 .irq_pio_mask = MCI_IRQ_PIO_MASK, 130 .start_err = MCI_STARTBITERR, 131 .opendrain = MCI_OD, 132 .init = mmci_variant_init, 133 }; 134 135 static struct variant_data variant_nomadik = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg = MCI_CLK_ENABLE, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 141 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 142 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 143 .cmdreg_srsp = MCI_CPSM_RESPONSE, 144 .datalength_bits = 24, 145 .datactrl_blocksz = 11, 146 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 147 .st_sdio = true, 148 .st_clkdiv = true, 149 .pwrreg_powerup = MCI_PWR_ON, 150 .f_max = 100000000, 151 .signal_direction = true, 152 .pwrreg_clkgate = true, 153 .pwrreg_nopower = true, 154 .mmcimask1 = true, 155 .irq_pio_mask = MCI_IRQ_PIO_MASK, 156 .start_err = MCI_STARTBITERR, 157 .opendrain = MCI_OD, 158 .init = mmci_variant_init, 159 }; 160 161 static struct variant_data variant_ux500 = { 162 .fifosize = 30 * 4, 163 .fifohalfsize = 8 * 4, 164 .clkreg = MCI_CLK_ENABLE, 165 .clkreg_enable = MCI_ST_UX500_HWFCEN, 166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 168 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 169 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 170 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 171 .cmdreg_srsp = MCI_CPSM_RESPONSE, 172 .datalength_bits = 24, 173 .datactrl_blocksz = 11, 174 .datactrl_any_blocksz = true, 175 .dma_power_of_2 = true, 176 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 177 .st_sdio = true, 178 .st_clkdiv = true, 179 .pwrreg_powerup = MCI_PWR_ON, 180 .f_max = 100000000, 181 .signal_direction = true, 182 .pwrreg_clkgate = true, 183 .busy_detect = true, 184 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 185 .busy_detect_flag = MCI_ST_CARDBUSY, 186 .busy_detect_mask = MCI_ST_BUSYENDMASK, 187 .pwrreg_nopower = true, 188 .mmcimask1 = true, 189 .irq_pio_mask = MCI_IRQ_PIO_MASK, 190 .start_err = MCI_STARTBITERR, 191 .opendrain = MCI_OD, 192 .init = ux500_variant_init, 193 }; 194 195 static struct variant_data variant_ux500v2 = { 196 .fifosize = 30 * 4, 197 .fifohalfsize = 8 * 4, 198 .clkreg = MCI_CLK_ENABLE, 199 .clkreg_enable = MCI_ST_UX500_HWFCEN, 200 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 201 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 202 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 203 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 204 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 205 .cmdreg_srsp = MCI_CPSM_RESPONSE, 206 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 207 .datalength_bits = 24, 208 .datactrl_blocksz = 11, 209 .datactrl_any_blocksz = true, 210 .dma_power_of_2 = true, 211 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 212 .st_sdio = true, 213 .st_clkdiv = true, 214 .pwrreg_powerup = MCI_PWR_ON, 215 .f_max = 100000000, 216 .signal_direction = true, 217 .pwrreg_clkgate = true, 218 .busy_detect = true, 219 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 220 .busy_detect_flag = MCI_ST_CARDBUSY, 221 .busy_detect_mask = MCI_ST_BUSYENDMASK, 222 .pwrreg_nopower = true, 223 .mmcimask1 = true, 224 .irq_pio_mask = MCI_IRQ_PIO_MASK, 225 .start_err = MCI_STARTBITERR, 226 .opendrain = MCI_OD, 227 .init = ux500v2_variant_init, 228 }; 229 230 static struct variant_data variant_stm32 = { 231 .fifosize = 32 * 4, 232 .fifohalfsize = 8 * 4, 233 .clkreg = MCI_CLK_ENABLE, 234 .clkreg_enable = MCI_ST_UX500_HWFCEN, 235 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 236 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 237 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 238 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 239 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 240 .cmdreg_srsp = MCI_CPSM_RESPONSE, 241 .irq_pio_mask = MCI_IRQ_PIO_MASK, 242 .datalength_bits = 24, 243 .datactrl_blocksz = 11, 244 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 245 .st_sdio = true, 246 .st_clkdiv = true, 247 .pwrreg_powerup = MCI_PWR_ON, 248 .f_max = 48000000, 249 .pwrreg_clkgate = true, 250 .pwrreg_nopower = true, 251 .init = mmci_variant_init, 252 }; 253 254 static struct variant_data variant_stm32_sdmmc = { 255 .fifosize = 16 * 4, 256 .fifohalfsize = 8 * 4, 257 .f_max = 208000000, 258 .stm32_clkdiv = true, 259 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 260 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 261 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 262 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 263 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 264 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 265 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 266 .datactrl_first = true, 267 .datacnt_useless = true, 268 .datalength_bits = 25, 269 .datactrl_blocksz = 14, 270 .datactrl_any_blocksz = true, 271 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 272 .stm32_idmabsize_mask = GENMASK(12, 5), 273 .busy_timeout = true, 274 .busy_detect = true, 275 .busy_detect_flag = MCI_STM32_BUSYD0, 276 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 277 .init = sdmmc_variant_init, 278 }; 279 280 static struct variant_data variant_stm32_sdmmcv2 = { 281 .fifosize = 16 * 4, 282 .fifohalfsize = 8 * 4, 283 .f_max = 267000000, 284 .stm32_clkdiv = true, 285 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, 286 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, 287 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, 288 .cmdreg_srsp = MCI_CPSM_STM32_SRSP, 289 .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, 290 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, 291 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, 292 .datactrl_first = true, 293 .datacnt_useless = true, 294 .datalength_bits = 25, 295 .datactrl_blocksz = 14, 296 .datactrl_any_blocksz = true, 297 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 298 .stm32_idmabsize_mask = GENMASK(16, 5), 299 .dma_lli = true, 300 .busy_timeout = true, 301 .busy_detect = true, 302 .busy_detect_flag = MCI_STM32_BUSYD0, 303 .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK, 304 .init = sdmmc_variant_init, 305 }; 306 307 static struct variant_data variant_qcom = { 308 .fifosize = 16 * 4, 309 .fifohalfsize = 8 * 4, 310 .clkreg = MCI_CLK_ENABLE, 311 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 312 MCI_QCOM_CLK_SELECT_IN_FBCLK, 313 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 314 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 315 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 316 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 317 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 318 .cmdreg_srsp = MCI_CPSM_RESPONSE, 319 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 320 .datalength_bits = 24, 321 .datactrl_blocksz = 11, 322 .datactrl_any_blocksz = true, 323 .pwrreg_powerup = MCI_PWR_UP, 324 .f_max = 208000000, 325 .explicit_mclk_control = true, 326 .qcom_fifo = true, 327 .qcom_dml = true, 328 .mmcimask1 = true, 329 .irq_pio_mask = MCI_IRQ_PIO_MASK, 330 .start_err = MCI_STARTBITERR, 331 .opendrain = MCI_ROD, 332 .init = qcom_variant_init, 333 }; 334 335 /* Busy detection for the ST Micro variant */ 336 static int mmci_card_busy(struct mmc_host *mmc) 337 { 338 struct mmci_host *host = mmc_priv(mmc); 339 unsigned long flags; 340 int busy = 0; 341 342 spin_lock_irqsave(&host->lock, flags); 343 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 344 busy = 1; 345 spin_unlock_irqrestore(&host->lock, flags); 346 347 return busy; 348 } 349 350 static void mmci_reg_delay(struct mmci_host *host) 351 { 352 /* 353 * According to the spec, at least three feedback clock cycles 354 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 355 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 356 * Worst delay time during card init is at 100 kHz => 30 us. 357 * Worst delay time when up and running is at 25 MHz => 120 ns. 358 */ 359 if (host->cclk < 25000000) 360 udelay(30); 361 else 362 ndelay(120); 363 } 364 365 /* 366 * This must be called with host->lock held 367 */ 368 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 369 { 370 if (host->clk_reg != clk) { 371 host->clk_reg = clk; 372 writel(clk, host->base + MMCICLOCK); 373 } 374 } 375 376 /* 377 * This must be called with host->lock held 378 */ 379 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 380 { 381 if (host->pwr_reg != pwr) { 382 host->pwr_reg = pwr; 383 writel(pwr, host->base + MMCIPOWER); 384 } 385 } 386 387 /* 388 * This must be called with host->lock held 389 */ 390 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 391 { 392 /* Keep busy mode in DPSM if enabled */ 393 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 394 395 if (host->datactrl_reg != datactrl) { 396 host->datactrl_reg = datactrl; 397 writel(datactrl, host->base + MMCIDATACTRL); 398 } 399 } 400 401 /* 402 * This must be called with host->lock held 403 */ 404 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 405 { 406 struct variant_data *variant = host->variant; 407 u32 clk = variant->clkreg; 408 409 /* Make sure cclk reflects the current calculated clock */ 410 host->cclk = 0; 411 412 if (desired) { 413 if (variant->explicit_mclk_control) { 414 host->cclk = host->mclk; 415 } else if (desired >= host->mclk) { 416 clk = MCI_CLK_BYPASS; 417 if (variant->st_clkdiv) 418 clk |= MCI_ST_UX500_NEG_EDGE; 419 host->cclk = host->mclk; 420 } else if (variant->st_clkdiv) { 421 /* 422 * DB8500 TRM says f = mclk / (clkdiv + 2) 423 * => clkdiv = (mclk / f) - 2 424 * Round the divider up so we don't exceed the max 425 * frequency 426 */ 427 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 428 if (clk >= 256) 429 clk = 255; 430 host->cclk = host->mclk / (clk + 2); 431 } else { 432 /* 433 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 434 * => clkdiv = mclk / (2 * f) - 1 435 */ 436 clk = host->mclk / (2 * desired) - 1; 437 if (clk >= 256) 438 clk = 255; 439 host->cclk = host->mclk / (2 * (clk + 1)); 440 } 441 442 clk |= variant->clkreg_enable; 443 clk |= MCI_CLK_ENABLE; 444 /* This hasn't proven to be worthwhile */ 445 /* clk |= MCI_CLK_PWRSAVE; */ 446 } 447 448 /* Set actual clock for debug */ 449 host->mmc->actual_clock = host->cclk; 450 451 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 452 clk |= MCI_4BIT_BUS; 453 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 454 clk |= variant->clkreg_8bit_bus_enable; 455 456 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 457 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 458 clk |= variant->clkreg_neg_edge_enable; 459 460 mmci_write_clkreg(host, clk); 461 } 462 463 static void mmci_dma_release(struct mmci_host *host) 464 { 465 if (host->ops && host->ops->dma_release) 466 host->ops->dma_release(host); 467 468 host->use_dma = false; 469 } 470 471 static void mmci_dma_setup(struct mmci_host *host) 472 { 473 if (!host->ops || !host->ops->dma_setup) 474 return; 475 476 if (host->ops->dma_setup(host)) 477 return; 478 479 /* initialize pre request cookie */ 480 host->next_cookie = 1; 481 482 host->use_dma = true; 483 } 484 485 /* 486 * Validate mmc prerequisites 487 */ 488 static int mmci_validate_data(struct mmci_host *host, 489 struct mmc_data *data) 490 { 491 struct variant_data *variant = host->variant; 492 493 if (!data) 494 return 0; 495 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { 496 dev_err(mmc_dev(host->mmc), 497 "unsupported block size (%d bytes)\n", data->blksz); 498 return -EINVAL; 499 } 500 501 if (host->ops && host->ops->validate_data) 502 return host->ops->validate_data(host, data); 503 504 return 0; 505 } 506 507 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 508 { 509 int err; 510 511 if (!host->ops || !host->ops->prep_data) 512 return 0; 513 514 err = host->ops->prep_data(host, data, next); 515 516 if (next && !err) 517 data->host_cookie = ++host->next_cookie < 0 ? 518 1 : host->next_cookie; 519 520 return err; 521 } 522 523 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 524 int err) 525 { 526 if (host->ops && host->ops->unprep_data) 527 host->ops->unprep_data(host, data, err); 528 529 data->host_cookie = 0; 530 } 531 532 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 533 { 534 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 535 536 if (host->ops && host->ops->get_next_data) 537 host->ops->get_next_data(host, data); 538 } 539 540 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 541 { 542 struct mmc_data *data = host->data; 543 int ret; 544 545 if (!host->use_dma) 546 return -EINVAL; 547 548 ret = mmci_prep_data(host, data, false); 549 if (ret) 550 return ret; 551 552 if (!host->ops || !host->ops->dma_start) 553 return -EINVAL; 554 555 /* Okay, go for it. */ 556 dev_vdbg(mmc_dev(host->mmc), 557 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 558 data->sg_len, data->blksz, data->blocks, data->flags); 559 560 ret = host->ops->dma_start(host, &datactrl); 561 if (ret) 562 return ret; 563 564 /* Trigger the DMA transfer */ 565 mmci_write_datactrlreg(host, datactrl); 566 567 /* 568 * Let the MMCI say when the data is ended and it's time 569 * to fire next DMA request. When that happens, MMCI will 570 * call mmci_data_end() 571 */ 572 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 573 host->base + MMCIMASK0); 574 return 0; 575 } 576 577 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 578 { 579 if (!host->use_dma) 580 return; 581 582 if (host->ops && host->ops->dma_finalize) 583 host->ops->dma_finalize(host, data); 584 } 585 586 static void mmci_dma_error(struct mmci_host *host) 587 { 588 if (!host->use_dma) 589 return; 590 591 if (host->ops && host->ops->dma_error) 592 host->ops->dma_error(host); 593 } 594 595 static void 596 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 597 { 598 writel(0, host->base + MMCICOMMAND); 599 600 BUG_ON(host->data); 601 602 host->mrq = NULL; 603 host->cmd = NULL; 604 605 mmc_request_done(host->mmc, mrq); 606 } 607 608 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 609 { 610 void __iomem *base = host->base; 611 struct variant_data *variant = host->variant; 612 613 if (host->singleirq) { 614 unsigned int mask0 = readl(base + MMCIMASK0); 615 616 mask0 &= ~variant->irq_pio_mask; 617 mask0 |= mask; 618 619 writel(mask0, base + MMCIMASK0); 620 } 621 622 if (variant->mmcimask1) 623 writel(mask, base + MMCIMASK1); 624 625 host->mask1_reg = mask; 626 } 627 628 static void mmci_stop_data(struct mmci_host *host) 629 { 630 mmci_write_datactrlreg(host, 0); 631 mmci_set_mask1(host, 0); 632 host->data = NULL; 633 } 634 635 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 636 { 637 unsigned int flags = SG_MITER_ATOMIC; 638 639 if (data->flags & MMC_DATA_READ) 640 flags |= SG_MITER_TO_SG; 641 else 642 flags |= SG_MITER_FROM_SG; 643 644 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 645 } 646 647 static u32 mmci_get_dctrl_cfg(struct mmci_host *host) 648 { 649 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); 650 } 651 652 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) 653 { 654 return MCI_DPSM_ENABLE | (host->data->blksz << 16); 655 } 656 657 /* 658 * ux500_busy_complete() - this will wait until the busy status 659 * goes off, saving any status that occur in the meantime into 660 * host->busy_status until we know the card is not busy any more. 661 * The function returns true when the busy detection is ended 662 * and we should continue processing the command. 663 * 664 * The Ux500 typically fires two IRQs over a busy cycle like this: 665 * 666 * DAT0 busy +-----------------+ 667 * | | 668 * DAT0 not busy ----+ +-------- 669 * 670 * ^ ^ 671 * | | 672 * IRQ1 IRQ2 673 */ 674 static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk) 675 { 676 void __iomem *base = host->base; 677 int retries = 10; 678 679 if (status & err_msk) { 680 /* Stop any ongoing busy detection if an error occurs */ 681 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 682 writel(readl(base + MMCIMASK0) & 683 ~host->variant->busy_detect_mask, base + MMCIMASK0); 684 host->busy_state = MMCI_BUSY_DONE; 685 host->busy_status = 0; 686 return true; 687 } 688 689 /* 690 * Before unmasking for the busy end IRQ, confirm that the 691 * command was sent successfully. To keep track of having a 692 * command in-progress, waiting for busy signaling to end, 693 * store the status in host->busy_status. 694 * 695 * Note that, the card may need a couple of clock cycles before 696 * it starts signaling busy on DAT0, hence re-read the 697 * MMCISTATUS register here, to allow the busy bit to be set. 698 */ 699 if (host->busy_state == MMCI_BUSY_DONE) { 700 /* 701 * Save the first status register read to be sure to catch 702 * all bits that may be lost will retrying. If the command 703 * is still busy this will result in assigning 0 to 704 * host->busy_status, which is what it should be in IDLE. 705 */ 706 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); 707 while (retries) { 708 status = readl(base + MMCISTATUS); 709 /* Keep accumulating status bits */ 710 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 711 if (status & host->variant->busy_detect_flag) { 712 writel(readl(base + MMCIMASK0) | 713 host->variant->busy_detect_mask, 714 base + MMCIMASK0); 715 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; 716 return false; 717 } 718 retries--; 719 } 720 dev_dbg(mmc_dev(host->mmc), "no busy signalling in time\n"); 721 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 722 writel(readl(base + MMCIMASK0) & 723 ~host->variant->busy_detect_mask, base + MMCIMASK0); 724 host->busy_state = MMCI_BUSY_DONE; 725 host->busy_status = 0; 726 return true; 727 } 728 729 /* 730 * If there is a command in-progress that has been successfully 731 * sent, then bail out if busy status is set and wait for the 732 * busy end IRQ. 733 * 734 * Note that, the HW triggers an IRQ on both edges while 735 * monitoring DAT0 for busy completion, but there is only one 736 * status bit in MMCISTATUS for the busy state. Therefore 737 * both the start and the end interrupts needs to be cleared, 738 * one after the other. So, clear the busy start IRQ here. 739 */ 740 if (host->busy_state == MMCI_BUSY_WAITING_FOR_START_IRQ) { 741 if (status & host->variant->busy_detect_flag) { 742 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 743 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 744 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ; 745 return false; 746 } else { 747 dev_dbg(mmc_dev(host->mmc), 748 "lost busy status when waiting for busy start IRQ\n"); 749 writel(host->variant->busy_detect_mask, base + MMCICLEAR); 750 writel(readl(base + MMCIMASK0) & 751 ~host->variant->busy_detect_mask, base + MMCIMASK0); 752 host->busy_state = MMCI_BUSY_DONE; 753 host->busy_status = 0; 754 return true; 755 } 756 } 757 758 if (host->busy_state == MMCI_BUSY_WAITING_FOR_END_IRQ) { 759 if (!(status & host->variant->busy_detect_flag)) { 760 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); 761 host->busy_state = MMCI_BUSY_DONE; 762 return true; 763 } else { 764 dev_dbg(mmc_dev(host->mmc), 765 "busy status still asserted when handling busy end IRQ - will keep waiting\n"); 766 return false; 767 } 768 } 769 770 return true; 771 } 772 773 /* 774 * All the DMA operation mode stuff goes inside this ifdef. 775 * This assumes that you have a generic DMA device interface, 776 * no custom DMA interfaces are supported. 777 */ 778 #ifdef CONFIG_DMA_ENGINE 779 struct mmci_dmae_next { 780 struct dma_async_tx_descriptor *desc; 781 struct dma_chan *chan; 782 }; 783 784 struct mmci_dmae_priv { 785 struct dma_chan *cur; 786 struct dma_chan *rx_channel; 787 struct dma_chan *tx_channel; 788 struct dma_async_tx_descriptor *desc_current; 789 struct mmci_dmae_next next_data; 790 }; 791 792 int mmci_dmae_setup(struct mmci_host *host) 793 { 794 const char *rxname, *txname; 795 struct mmci_dmae_priv *dmae; 796 797 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 798 if (!dmae) 799 return -ENOMEM; 800 801 host->dma_priv = dmae; 802 803 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); 804 if (IS_ERR(dmae->rx_channel)) { 805 int ret = PTR_ERR(dmae->rx_channel); 806 dmae->rx_channel = NULL; 807 return ret; 808 } 809 810 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); 811 if (IS_ERR(dmae->tx_channel)) { 812 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) 813 dev_warn(mmc_dev(host->mmc), 814 "Deferred probe for TX channel ignored\n"); 815 dmae->tx_channel = NULL; 816 } 817 818 /* 819 * If only an RX channel is specified, the driver will 820 * attempt to use it bidirectionally, however if it 821 * is specified but cannot be located, DMA will be disabled. 822 */ 823 if (dmae->rx_channel && !dmae->tx_channel) 824 dmae->tx_channel = dmae->rx_channel; 825 826 if (dmae->rx_channel) 827 rxname = dma_chan_name(dmae->rx_channel); 828 else 829 rxname = "none"; 830 831 if (dmae->tx_channel) 832 txname = dma_chan_name(dmae->tx_channel); 833 else 834 txname = "none"; 835 836 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 837 rxname, txname); 838 839 /* 840 * Limit the maximum segment size in any SG entry according to 841 * the parameters of the DMA engine device. 842 */ 843 if (dmae->tx_channel) { 844 struct device *dev = dmae->tx_channel->device->dev; 845 unsigned int max_seg_size = dma_get_max_seg_size(dev); 846 847 if (max_seg_size < host->mmc->max_seg_size) 848 host->mmc->max_seg_size = max_seg_size; 849 } 850 if (dmae->rx_channel) { 851 struct device *dev = dmae->rx_channel->device->dev; 852 unsigned int max_seg_size = dma_get_max_seg_size(dev); 853 854 if (max_seg_size < host->mmc->max_seg_size) 855 host->mmc->max_seg_size = max_seg_size; 856 } 857 858 if (!dmae->tx_channel || !dmae->rx_channel) { 859 mmci_dmae_release(host); 860 return -EINVAL; 861 } 862 863 return 0; 864 } 865 866 /* 867 * This is used in or so inline it 868 * so it can be discarded. 869 */ 870 void mmci_dmae_release(struct mmci_host *host) 871 { 872 struct mmci_dmae_priv *dmae = host->dma_priv; 873 874 if (dmae->rx_channel) 875 dma_release_channel(dmae->rx_channel); 876 if (dmae->tx_channel) 877 dma_release_channel(dmae->tx_channel); 878 dmae->rx_channel = dmae->tx_channel = NULL; 879 } 880 881 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 882 { 883 struct mmci_dmae_priv *dmae = host->dma_priv; 884 struct dma_chan *chan; 885 886 if (data->flags & MMC_DATA_READ) 887 chan = dmae->rx_channel; 888 else 889 chan = dmae->tx_channel; 890 891 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 892 mmc_get_dma_dir(data)); 893 } 894 895 void mmci_dmae_error(struct mmci_host *host) 896 { 897 struct mmci_dmae_priv *dmae = host->dma_priv; 898 899 if (!dma_inprogress(host)) 900 return; 901 902 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 903 dmaengine_terminate_all(dmae->cur); 904 host->dma_in_progress = false; 905 dmae->cur = NULL; 906 dmae->desc_current = NULL; 907 host->data->host_cookie = 0; 908 909 mmci_dma_unmap(host, host->data); 910 } 911 912 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 913 { 914 struct mmci_dmae_priv *dmae = host->dma_priv; 915 u32 status; 916 int i; 917 918 if (!dma_inprogress(host)) 919 return; 920 921 /* Wait up to 1ms for the DMA to complete */ 922 for (i = 0; ; i++) { 923 status = readl(host->base + MMCISTATUS); 924 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 925 break; 926 udelay(10); 927 } 928 929 /* 930 * Check to see whether we still have some data left in the FIFO - 931 * this catches DMA controllers which are unable to monitor the 932 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 933 * contiguous buffers. On TX, we'll get a FIFO underrun error. 934 */ 935 if (status & MCI_RXDATAAVLBLMASK) { 936 mmci_dma_error(host); 937 if (!data->error) 938 data->error = -EIO; 939 } else if (!data->host_cookie) { 940 mmci_dma_unmap(host, data); 941 } 942 943 /* 944 * Use of DMA with scatter-gather is impossible. 945 * Give up with DMA and switch back to PIO mode. 946 */ 947 if (status & MCI_RXDATAAVLBLMASK) { 948 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 949 mmci_dma_release(host); 950 } 951 952 host->dma_in_progress = false; 953 dmae->cur = NULL; 954 dmae->desc_current = NULL; 955 } 956 957 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 958 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 959 struct dma_chan **dma_chan, 960 struct dma_async_tx_descriptor **dma_desc) 961 { 962 struct mmci_dmae_priv *dmae = host->dma_priv; 963 struct variant_data *variant = host->variant; 964 struct dma_slave_config conf = { 965 .src_addr = host->phybase + MMCIFIFO, 966 .dst_addr = host->phybase + MMCIFIFO, 967 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 968 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 969 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 970 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 971 .device_fc = false, 972 }; 973 struct dma_chan *chan; 974 struct dma_device *device; 975 struct dma_async_tx_descriptor *desc; 976 int nr_sg; 977 unsigned long flags = DMA_CTRL_ACK; 978 979 if (data->flags & MMC_DATA_READ) { 980 conf.direction = DMA_DEV_TO_MEM; 981 chan = dmae->rx_channel; 982 } else { 983 conf.direction = DMA_MEM_TO_DEV; 984 chan = dmae->tx_channel; 985 } 986 987 /* If there's no DMA channel, fall back to PIO */ 988 if (!chan) 989 return -EINVAL; 990 991 /* If less than or equal to the fifo size, don't bother with DMA */ 992 if (data->blksz * data->blocks <= variant->fifosize) 993 return -EINVAL; 994 995 /* 996 * This is necessary to get SDIO working on the Ux500. We do not yet 997 * know if this is a bug in: 998 * - The Ux500 DMA controller (DMA40) 999 * - The MMCI DMA interface on the Ux500 1000 * some power of two blocks (such as 64 bytes) are sent regularly 1001 * during SDIO traffic and those work fine so for these we enable DMA 1002 * transfers. 1003 */ 1004 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) 1005 return -EINVAL; 1006 1007 device = chan->device; 1008 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 1009 mmc_get_dma_dir(data)); 1010 if (nr_sg == 0) 1011 return -EINVAL; 1012 1013 if (host->variant->qcom_dml) 1014 flags |= DMA_PREP_INTERRUPT; 1015 1016 dmaengine_slave_config(chan, &conf); 1017 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 1018 conf.direction, flags); 1019 if (!desc) 1020 goto unmap_exit; 1021 1022 *dma_chan = chan; 1023 *dma_desc = desc; 1024 1025 return 0; 1026 1027 unmap_exit: 1028 dma_unmap_sg(device->dev, data->sg, data->sg_len, 1029 mmc_get_dma_dir(data)); 1030 return -ENOMEM; 1031 } 1032 1033 int mmci_dmae_prep_data(struct mmci_host *host, 1034 struct mmc_data *data, 1035 bool next) 1036 { 1037 struct mmci_dmae_priv *dmae = host->dma_priv; 1038 struct mmci_dmae_next *nd = &dmae->next_data; 1039 1040 if (!host->use_dma) 1041 return -EINVAL; 1042 1043 if (next) 1044 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 1045 /* Check if next job is already prepared. */ 1046 if (dmae->cur && dmae->desc_current) 1047 return 0; 1048 1049 /* No job were prepared thus do it now. */ 1050 return _mmci_dmae_prep_data(host, data, &dmae->cur, 1051 &dmae->desc_current); 1052 } 1053 1054 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 1055 { 1056 struct mmci_dmae_priv *dmae = host->dma_priv; 1057 int ret; 1058 1059 host->dma_in_progress = true; 1060 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); 1061 if (ret < 0) { 1062 host->dma_in_progress = false; 1063 return ret; 1064 } 1065 dma_async_issue_pending(dmae->cur); 1066 1067 *datactrl |= MCI_DPSM_DMAENABLE; 1068 1069 return 0; 1070 } 1071 1072 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 1073 { 1074 struct mmci_dmae_priv *dmae = host->dma_priv; 1075 struct mmci_dmae_next *next = &dmae->next_data; 1076 1077 if (!host->use_dma) 1078 return; 1079 1080 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 1081 1082 dmae->desc_current = next->desc; 1083 dmae->cur = next->chan; 1084 next->desc = NULL; 1085 next->chan = NULL; 1086 } 1087 1088 void mmci_dmae_unprep_data(struct mmci_host *host, 1089 struct mmc_data *data, int err) 1090 1091 { 1092 struct mmci_dmae_priv *dmae = host->dma_priv; 1093 1094 if (!host->use_dma) 1095 return; 1096 1097 mmci_dma_unmap(host, data); 1098 1099 if (err) { 1100 struct mmci_dmae_next *next = &dmae->next_data; 1101 struct dma_chan *chan; 1102 if (data->flags & MMC_DATA_READ) 1103 chan = dmae->rx_channel; 1104 else 1105 chan = dmae->tx_channel; 1106 dmaengine_terminate_all(chan); 1107 1108 if (dmae->desc_current == next->desc) 1109 dmae->desc_current = NULL; 1110 1111 if (dmae->cur == next->chan) { 1112 host->dma_in_progress = false; 1113 dmae->cur = NULL; 1114 } 1115 1116 next->desc = NULL; 1117 next->chan = NULL; 1118 } 1119 } 1120 1121 static struct mmci_host_ops mmci_variant_ops = { 1122 .prep_data = mmci_dmae_prep_data, 1123 .unprep_data = mmci_dmae_unprep_data, 1124 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1125 .get_next_data = mmci_dmae_get_next_data, 1126 .dma_setup = mmci_dmae_setup, 1127 .dma_release = mmci_dmae_release, 1128 .dma_start = mmci_dmae_start, 1129 .dma_finalize = mmci_dmae_finalize, 1130 .dma_error = mmci_dmae_error, 1131 }; 1132 #else 1133 static struct mmci_host_ops mmci_variant_ops = { 1134 .get_datactrl_cfg = mmci_get_dctrl_cfg, 1135 }; 1136 #endif 1137 1138 static void mmci_variant_init(struct mmci_host *host) 1139 { 1140 host->ops = &mmci_variant_ops; 1141 } 1142 1143 static void ux500_variant_init(struct mmci_host *host) 1144 { 1145 host->ops = &mmci_variant_ops; 1146 host->ops->busy_complete = ux500_busy_complete; 1147 } 1148 1149 static void ux500v2_variant_init(struct mmci_host *host) 1150 { 1151 host->ops = &mmci_variant_ops; 1152 host->ops->busy_complete = ux500_busy_complete; 1153 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; 1154 } 1155 1156 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 1157 { 1158 struct mmci_host *host = mmc_priv(mmc); 1159 struct mmc_data *data = mrq->data; 1160 1161 if (!data) 1162 return; 1163 1164 WARN_ON(data->host_cookie); 1165 1166 if (mmci_validate_data(host, data)) 1167 return; 1168 1169 mmci_prep_data(host, data, true); 1170 } 1171 1172 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 1173 int err) 1174 { 1175 struct mmci_host *host = mmc_priv(mmc); 1176 struct mmc_data *data = mrq->data; 1177 1178 if (!data || !data->host_cookie) 1179 return; 1180 1181 mmci_unprep_data(host, data, err); 1182 } 1183 1184 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 1185 { 1186 struct variant_data *variant = host->variant; 1187 unsigned int datactrl, timeout, irqmask; 1188 unsigned long long clks; 1189 void __iomem *base; 1190 1191 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 1192 data->blksz, data->blocks, data->flags); 1193 1194 host->data = data; 1195 host->size = data->blksz * data->blocks; 1196 data->bytes_xfered = 0; 1197 1198 clks = (unsigned long long)data->timeout_ns * host->cclk; 1199 do_div(clks, NSEC_PER_SEC); 1200 1201 timeout = data->timeout_clks + (unsigned int)clks; 1202 1203 base = host->base; 1204 writel(timeout, base + MMCIDATATIMER); 1205 writel(host->size, base + MMCIDATALENGTH); 1206 1207 datactrl = host->ops->get_datactrl_cfg(host); 1208 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; 1209 1210 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1211 u32 clk; 1212 1213 datactrl |= variant->datactrl_mask_sdio; 1214 1215 /* 1216 * The ST Micro variant for SDIO small write transfers 1217 * needs to have clock H/W flow control disabled, 1218 * otherwise the transfer will not start. The threshold 1219 * depends on the rate of MCLK. 1220 */ 1221 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1222 (host->size < 8 || 1223 (host->size <= 8 && host->mclk > 50000000))) 1224 clk = host->clk_reg & ~variant->clkreg_enable; 1225 else 1226 clk = host->clk_reg | variant->clkreg_enable; 1227 1228 mmci_write_clkreg(host, clk); 1229 } 1230 1231 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1232 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1233 datactrl |= variant->datactrl_mask_ddrmode; 1234 1235 /* 1236 * Attempt to use DMA operation mode, if this 1237 * should fail, fall back to PIO mode 1238 */ 1239 if (!mmci_dma_start(host, datactrl)) 1240 return; 1241 1242 /* IRQ mode, map the SG list for CPU reading/writing */ 1243 mmci_init_sg(host, data); 1244 1245 if (data->flags & MMC_DATA_READ) { 1246 irqmask = MCI_RXFIFOHALFFULLMASK; 1247 1248 /* 1249 * If we have less than the fifo 'half-full' threshold to 1250 * transfer, trigger a PIO interrupt as soon as any data 1251 * is available. 1252 */ 1253 if (host->size < variant->fifohalfsize) 1254 irqmask |= MCI_RXDATAAVLBLMASK; 1255 } else { 1256 /* 1257 * We don't actually need to include "FIFO empty" here 1258 * since its implicit in "FIFO half empty". 1259 */ 1260 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1261 } 1262 1263 mmci_write_datactrlreg(host, datactrl); 1264 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1265 mmci_set_mask1(host, irqmask); 1266 } 1267 1268 static void 1269 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1270 { 1271 void __iomem *base = host->base; 1272 unsigned long long clks; 1273 1274 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1275 cmd->opcode, cmd->arg, cmd->flags); 1276 1277 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1278 writel(0, base + MMCICOMMAND); 1279 mmci_reg_delay(host); 1280 } 1281 1282 if (host->variant->cmdreg_stop && 1283 cmd->opcode == MMC_STOP_TRANSMISSION) 1284 c |= host->variant->cmdreg_stop; 1285 1286 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1287 if (cmd->flags & MMC_RSP_PRESENT) { 1288 if (cmd->flags & MMC_RSP_136) 1289 c |= host->variant->cmdreg_lrsp_crc; 1290 else if (cmd->flags & MMC_RSP_CRC) 1291 c |= host->variant->cmdreg_srsp_crc; 1292 else 1293 c |= host->variant->cmdreg_srsp; 1294 } 1295 1296 host->busy_status = 0; 1297 host->busy_state = MMCI_BUSY_DONE; 1298 1299 if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) { 1300 if (!cmd->busy_timeout) 1301 cmd->busy_timeout = 10 * MSEC_PER_SEC; 1302 1303 if (cmd->busy_timeout > host->mmc->max_busy_timeout) 1304 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; 1305 else 1306 clks = (unsigned long long)cmd->busy_timeout * host->cclk; 1307 1308 do_div(clks, MSEC_PER_SEC); 1309 writel_relaxed(clks, host->base + MMCIDATATIMER); 1310 } 1311 1312 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) 1313 host->ops->pre_sig_volt_switch(host); 1314 1315 if (/*interrupt*/0) 1316 c |= MCI_CPSM_INTERRUPT; 1317 1318 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1319 c |= host->variant->data_cmd_enable; 1320 1321 host->cmd = cmd; 1322 1323 writel(cmd->arg, base + MMCIARGUMENT); 1324 writel(c, base + MMCICOMMAND); 1325 } 1326 1327 static void mmci_stop_command(struct mmci_host *host) 1328 { 1329 host->stop_abort.error = 0; 1330 mmci_start_command(host, &host->stop_abort, 0); 1331 } 1332 1333 static void 1334 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1335 unsigned int status) 1336 { 1337 unsigned int status_err; 1338 1339 /* Make sure we have data to handle */ 1340 if (!data) 1341 return; 1342 1343 /* First check for errors */ 1344 status_err = status & (host->variant->start_err | 1345 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1346 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1347 1348 if (status_err) { 1349 u32 remain, success; 1350 1351 /* Terminate the DMA transfer */ 1352 mmci_dma_error(host); 1353 1354 /* 1355 * Calculate how far we are into the transfer. Note that 1356 * the data counter gives the number of bytes transferred 1357 * on the MMC bus, not on the host side. On reads, this 1358 * can be as much as a FIFO-worth of data ahead. This 1359 * matters for FIFO overruns only. 1360 */ 1361 if (!host->variant->datacnt_useless) { 1362 remain = readl(host->base + MMCIDATACNT); 1363 success = data->blksz * data->blocks - remain; 1364 } else { 1365 success = 0; 1366 } 1367 1368 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1369 status_err, success); 1370 if (status_err & MCI_DATACRCFAIL) { 1371 /* Last block was not successful */ 1372 success -= 1; 1373 data->error = -EILSEQ; 1374 } else if (status_err & MCI_DATATIMEOUT) { 1375 data->error = -ETIMEDOUT; 1376 } else if (status_err & MCI_STARTBITERR) { 1377 data->error = -ECOMM; 1378 } else if (status_err & MCI_TXUNDERRUN) { 1379 data->error = -EIO; 1380 } else if (status_err & MCI_RXOVERRUN) { 1381 if (success > host->variant->fifosize) 1382 success -= host->variant->fifosize; 1383 else 1384 success = 0; 1385 data->error = -EIO; 1386 } 1387 data->bytes_xfered = round_down(success, data->blksz); 1388 } 1389 1390 if (status & MCI_DATABLOCKEND) 1391 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1392 1393 if (status & MCI_DATAEND || data->error) { 1394 mmci_dma_finalize(host, data); 1395 1396 mmci_stop_data(host); 1397 1398 if (!data->error) 1399 /* The error clause is handled above, success! */ 1400 data->bytes_xfered = data->blksz * data->blocks; 1401 1402 if (!data->stop) { 1403 if (host->variant->cmdreg_stop && data->error) 1404 mmci_stop_command(host); 1405 else 1406 mmci_request_end(host, data->mrq); 1407 } else if (host->mrq->sbc && !data->error) { 1408 mmci_request_end(host, data->mrq); 1409 } else { 1410 mmci_start_command(host, data->stop, 0); 1411 } 1412 } 1413 } 1414 1415 static void 1416 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1417 unsigned int status) 1418 { 1419 u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT; 1420 void __iomem *base = host->base; 1421 bool sbc, busy_resp; 1422 1423 if (!cmd) 1424 return; 1425 1426 sbc = (cmd == host->mrq->sbc); 1427 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1428 1429 /* 1430 * We need to be one of these interrupts to be considered worth 1431 * handling. Note that we tag on any latent IRQs postponed 1432 * due to waiting for busy status. 1433 */ 1434 if (host->variant->busy_timeout && busy_resp) 1435 err_msk |= MCI_DATATIMEOUT; 1436 1437 if (!((status | host->busy_status) & 1438 (err_msk | MCI_CMDSENT | MCI_CMDRESPEND))) 1439 return; 1440 1441 /* Handle busy detection on DAT0 if the variant supports it. */ 1442 if (busy_resp && host->variant->busy_detect) 1443 if (!host->ops->busy_complete(host, status, err_msk)) 1444 return; 1445 1446 host->cmd = NULL; 1447 1448 if (status & MCI_CMDTIMEOUT) { 1449 cmd->error = -ETIMEDOUT; 1450 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1451 cmd->error = -EILSEQ; 1452 } else if (host->variant->busy_timeout && busy_resp && 1453 status & MCI_DATATIMEOUT) { 1454 cmd->error = -ETIMEDOUT; 1455 /* 1456 * This will wake up mmci_irq_thread() which will issue 1457 * a hardware reset of the MMCI block. 1458 */ 1459 host->irq_action = IRQ_WAKE_THREAD; 1460 } else { 1461 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1462 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1463 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1464 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1465 } 1466 1467 if ((!sbc && !cmd->data) || cmd->error) { 1468 if (host->data) { 1469 /* Terminate the DMA transfer */ 1470 mmci_dma_error(host); 1471 1472 mmci_stop_data(host); 1473 if (host->variant->cmdreg_stop && cmd->error) { 1474 mmci_stop_command(host); 1475 return; 1476 } 1477 } 1478 1479 if (host->irq_action != IRQ_WAKE_THREAD) 1480 mmci_request_end(host, host->mrq); 1481 1482 } else if (sbc) { 1483 mmci_start_command(host, host->mrq->cmd, 0); 1484 } else if (!host->variant->datactrl_first && 1485 !(cmd->data->flags & MMC_DATA_READ)) { 1486 mmci_start_data(host, cmd->data); 1487 } 1488 } 1489 1490 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1491 { 1492 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1493 } 1494 1495 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1496 { 1497 /* 1498 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1499 * from the fifo range should be used 1500 */ 1501 if (status & MCI_RXFIFOHALFFULL) 1502 return host->variant->fifohalfsize; 1503 else if (status & MCI_RXDATAAVLBL) 1504 return 4; 1505 1506 return 0; 1507 } 1508 1509 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1510 { 1511 void __iomem *base = host->base; 1512 char *ptr = buffer; 1513 u32 status = readl(host->base + MMCISTATUS); 1514 int host_remain = host->size; 1515 1516 do { 1517 int count = host->get_rx_fifocnt(host, status, host_remain); 1518 1519 if (count > remain) 1520 count = remain; 1521 1522 if (count <= 0) 1523 break; 1524 1525 /* 1526 * SDIO especially may want to send something that is 1527 * not divisible by 4 (as opposed to card sectors 1528 * etc). Therefore make sure to always read the last bytes 1529 * while only doing full 32-bit reads towards the FIFO. 1530 */ 1531 if (unlikely(count & 0x3)) { 1532 if (count < 4) { 1533 unsigned char buf[4]; 1534 ioread32_rep(base + MMCIFIFO, buf, 1); 1535 memcpy(ptr, buf, count); 1536 } else { 1537 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1538 count &= ~0x3; 1539 } 1540 } else { 1541 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1542 } 1543 1544 ptr += count; 1545 remain -= count; 1546 host_remain -= count; 1547 1548 if (remain == 0) 1549 break; 1550 1551 status = readl(base + MMCISTATUS); 1552 } while (status & MCI_RXDATAAVLBL); 1553 1554 return ptr - buffer; 1555 } 1556 1557 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1558 { 1559 struct variant_data *variant = host->variant; 1560 void __iomem *base = host->base; 1561 char *ptr = buffer; 1562 1563 do { 1564 unsigned int count, maxcnt; 1565 1566 maxcnt = status & MCI_TXFIFOEMPTY ? 1567 variant->fifosize : variant->fifohalfsize; 1568 count = min(remain, maxcnt); 1569 1570 /* 1571 * SDIO especially may want to send something that is 1572 * not divisible by 4 (as opposed to card sectors 1573 * etc), and the FIFO only accept full 32-bit writes. 1574 * So compensate by adding +3 on the count, a single 1575 * byte become a 32bit write, 7 bytes will be two 1576 * 32bit writes etc. 1577 */ 1578 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1579 1580 ptr += count; 1581 remain -= count; 1582 1583 if (remain == 0) 1584 break; 1585 1586 status = readl(base + MMCISTATUS); 1587 } while (status & MCI_TXFIFOHALFEMPTY); 1588 1589 return ptr - buffer; 1590 } 1591 1592 /* 1593 * PIO data transfer IRQ handler. 1594 */ 1595 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1596 { 1597 struct mmci_host *host = dev_id; 1598 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1599 struct variant_data *variant = host->variant; 1600 void __iomem *base = host->base; 1601 u32 status; 1602 1603 status = readl(base + MMCISTATUS); 1604 1605 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1606 1607 do { 1608 unsigned int remain, len; 1609 char *buffer; 1610 1611 /* 1612 * For write, we only need to test the half-empty flag 1613 * here - if the FIFO is completely empty, then by 1614 * definition it is more than half empty. 1615 * 1616 * For read, check for data available. 1617 */ 1618 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1619 break; 1620 1621 if (!sg_miter_next(sg_miter)) 1622 break; 1623 1624 buffer = sg_miter->addr; 1625 remain = sg_miter->length; 1626 1627 len = 0; 1628 if (status & MCI_RXACTIVE) 1629 len = mmci_pio_read(host, buffer, remain); 1630 if (status & MCI_TXACTIVE) 1631 len = mmci_pio_write(host, buffer, remain, status); 1632 1633 sg_miter->consumed = len; 1634 1635 host->size -= len; 1636 remain -= len; 1637 1638 if (remain) 1639 break; 1640 1641 status = readl(base + MMCISTATUS); 1642 } while (1); 1643 1644 sg_miter_stop(sg_miter); 1645 1646 /* 1647 * If we have less than the fifo 'half-full' threshold to transfer, 1648 * trigger a PIO interrupt as soon as any data is available. 1649 */ 1650 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1651 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1652 1653 /* 1654 * If we run out of data, disable the data IRQs; this 1655 * prevents a race where the FIFO becomes empty before 1656 * the chip itself has disabled the data path, and 1657 * stops us racing with our data end IRQ. 1658 */ 1659 if (host->size == 0) { 1660 mmci_set_mask1(host, 0); 1661 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1662 } 1663 1664 return IRQ_HANDLED; 1665 } 1666 1667 /* 1668 * Handle completion of command and data transfers. 1669 */ 1670 static irqreturn_t mmci_irq(int irq, void *dev_id) 1671 { 1672 struct mmci_host *host = dev_id; 1673 u32 status; 1674 1675 spin_lock(&host->lock); 1676 host->irq_action = IRQ_HANDLED; 1677 1678 do { 1679 status = readl(host->base + MMCISTATUS); 1680 if (!status) 1681 break; 1682 1683 if (host->singleirq) { 1684 if (status & host->mask1_reg) 1685 mmci_pio_irq(irq, dev_id); 1686 1687 status &= ~host->variant->irq_pio_mask; 1688 } 1689 1690 /* 1691 * Busy detection is managed by mmci_cmd_irq(), including to 1692 * clear the corresponding IRQ. 1693 */ 1694 status &= readl(host->base + MMCIMASK0); 1695 if (host->variant->busy_detect) 1696 writel(status & ~host->variant->busy_detect_mask, 1697 host->base + MMCICLEAR); 1698 else 1699 writel(status, host->base + MMCICLEAR); 1700 1701 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1702 1703 if (host->variant->reversed_irq_handling) { 1704 mmci_data_irq(host, host->data, status); 1705 mmci_cmd_irq(host, host->cmd, status); 1706 } else { 1707 mmci_cmd_irq(host, host->cmd, status); 1708 mmci_data_irq(host, host->data, status); 1709 } 1710 1711 /* 1712 * Busy detection has been handled by mmci_cmd_irq() above. 1713 * Clear the status bit to prevent polling in IRQ context. 1714 */ 1715 if (host->variant->busy_detect_flag) 1716 status &= ~host->variant->busy_detect_flag; 1717 1718 } while (status); 1719 1720 spin_unlock(&host->lock); 1721 1722 return host->irq_action; 1723 } 1724 1725 /* 1726 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. 1727 * 1728 * A reset is needed for some variants, where a datatimeout for a R1B request 1729 * causes the DPSM to stay busy (non-functional). 1730 */ 1731 static irqreturn_t mmci_irq_thread(int irq, void *dev_id) 1732 { 1733 struct mmci_host *host = dev_id; 1734 unsigned long flags; 1735 1736 if (host->rst) { 1737 reset_control_assert(host->rst); 1738 udelay(2); 1739 reset_control_deassert(host->rst); 1740 } 1741 1742 spin_lock_irqsave(&host->lock, flags); 1743 writel(host->clk_reg, host->base + MMCICLOCK); 1744 writel(host->pwr_reg, host->base + MMCIPOWER); 1745 writel(MCI_IRQENABLE | host->variant->start_err, 1746 host->base + MMCIMASK0); 1747 1748 host->irq_action = IRQ_HANDLED; 1749 mmci_request_end(host, host->mrq); 1750 spin_unlock_irqrestore(&host->lock, flags); 1751 1752 return host->irq_action; 1753 } 1754 1755 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1756 { 1757 struct mmci_host *host = mmc_priv(mmc); 1758 unsigned long flags; 1759 1760 WARN_ON(host->mrq != NULL); 1761 1762 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1763 if (mrq->cmd->error) { 1764 mmc_request_done(mmc, mrq); 1765 return; 1766 } 1767 1768 spin_lock_irqsave(&host->lock, flags); 1769 1770 host->mrq = mrq; 1771 1772 if (mrq->data) 1773 mmci_get_next_data(host, mrq->data); 1774 1775 if (mrq->data && 1776 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1777 mmci_start_data(host, mrq->data); 1778 1779 if (mrq->sbc) 1780 mmci_start_command(host, mrq->sbc, 0); 1781 else 1782 mmci_start_command(host, mrq->cmd, 0); 1783 1784 spin_unlock_irqrestore(&host->lock, flags); 1785 } 1786 1787 static void mmci_set_max_busy_timeout(struct mmc_host *mmc) 1788 { 1789 struct mmci_host *host = mmc_priv(mmc); 1790 u32 max_busy_timeout = 0; 1791 1792 if (!host->variant->busy_detect) 1793 return; 1794 1795 if (host->variant->busy_timeout && mmc->actual_clock) 1796 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, 1797 MSEC_PER_SEC); 1798 1799 mmc->max_busy_timeout = max_busy_timeout; 1800 } 1801 1802 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1803 { 1804 struct mmci_host *host = mmc_priv(mmc); 1805 struct variant_data *variant = host->variant; 1806 u32 pwr = 0; 1807 unsigned long flags; 1808 int ret; 1809 1810 switch (ios->power_mode) { 1811 case MMC_POWER_OFF: 1812 if (!IS_ERR(mmc->supply.vmmc)) 1813 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1814 1815 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1816 regulator_disable(mmc->supply.vqmmc); 1817 host->vqmmc_enabled = false; 1818 } 1819 1820 break; 1821 case MMC_POWER_UP: 1822 if (!IS_ERR(mmc->supply.vmmc)) 1823 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1824 1825 /* 1826 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1827 * and instead uses MCI_PWR_ON so apply whatever value is 1828 * configured in the variant data. 1829 */ 1830 pwr |= variant->pwrreg_powerup; 1831 1832 break; 1833 case MMC_POWER_ON: 1834 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1835 ret = regulator_enable(mmc->supply.vqmmc); 1836 if (ret < 0) 1837 dev_err(mmc_dev(mmc), 1838 "failed to enable vqmmc regulator\n"); 1839 else 1840 host->vqmmc_enabled = true; 1841 } 1842 1843 pwr |= MCI_PWR_ON; 1844 break; 1845 } 1846 1847 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1848 /* 1849 * The ST Micro variant has some additional bits 1850 * indicating signal direction for the signals in 1851 * the SD/MMC bus and feedback-clock usage. 1852 */ 1853 pwr |= host->pwr_reg_add; 1854 1855 if (ios->bus_width == MMC_BUS_WIDTH_4) 1856 pwr &= ~MCI_ST_DATA74DIREN; 1857 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1858 pwr &= (~MCI_ST_DATA74DIREN & 1859 ~MCI_ST_DATA31DIREN & 1860 ~MCI_ST_DATA2DIREN); 1861 } 1862 1863 if (variant->opendrain) { 1864 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1865 pwr |= variant->opendrain; 1866 } else { 1867 /* 1868 * If the variant cannot configure the pads by its own, then we 1869 * expect the pinctrl to be able to do that for us 1870 */ 1871 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1872 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1873 else 1874 pinctrl_select_default_state(mmc_dev(mmc)); 1875 } 1876 1877 /* 1878 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1879 * gating the clock, the MCI_PWR_ON bit is cleared. 1880 */ 1881 if (!ios->clock && variant->pwrreg_clkgate) 1882 pwr &= ~MCI_PWR_ON; 1883 1884 if (host->variant->explicit_mclk_control && 1885 ios->clock != host->clock_cache) { 1886 ret = clk_set_rate(host->clk, ios->clock); 1887 if (ret < 0) 1888 dev_err(mmc_dev(host->mmc), 1889 "Error setting clock rate (%d)\n", ret); 1890 else 1891 host->mclk = clk_get_rate(host->clk); 1892 } 1893 host->clock_cache = ios->clock; 1894 1895 spin_lock_irqsave(&host->lock, flags); 1896 1897 if (host->ops && host->ops->set_clkreg) 1898 host->ops->set_clkreg(host, ios->clock); 1899 else 1900 mmci_set_clkreg(host, ios->clock); 1901 1902 mmci_set_max_busy_timeout(mmc); 1903 1904 if (host->ops && host->ops->set_pwrreg) 1905 host->ops->set_pwrreg(host, pwr); 1906 else 1907 mmci_write_pwrreg(host, pwr); 1908 1909 mmci_reg_delay(host); 1910 1911 spin_unlock_irqrestore(&host->lock, flags); 1912 } 1913 1914 static int mmci_get_cd(struct mmc_host *mmc) 1915 { 1916 struct mmci_host *host = mmc_priv(mmc); 1917 struct mmci_platform_data *plat = host->plat; 1918 unsigned int status = mmc_gpio_get_cd(mmc); 1919 1920 if (status == -ENOSYS) { 1921 if (!plat->status) 1922 return 1; /* Assume always present */ 1923 1924 status = plat->status(mmc_dev(host->mmc)); 1925 } 1926 return status; 1927 } 1928 1929 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1930 { 1931 struct mmci_host *host = mmc_priv(mmc); 1932 int ret; 1933 1934 ret = mmc_regulator_set_vqmmc(mmc, ios); 1935 1936 if (!ret && host->ops && host->ops->post_sig_volt_switch) 1937 ret = host->ops->post_sig_volt_switch(host, ios); 1938 else if (ret) 1939 ret = 0; 1940 1941 if (ret < 0) 1942 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1943 1944 return ret; 1945 } 1946 1947 static struct mmc_host_ops mmci_ops = { 1948 .request = mmci_request, 1949 .pre_req = mmci_pre_request, 1950 .post_req = mmci_post_request, 1951 .set_ios = mmci_set_ios, 1952 .get_ro = mmc_gpio_get_ro, 1953 .get_cd = mmci_get_cd, 1954 .start_signal_voltage_switch = mmci_sig_volt_switch, 1955 }; 1956 1957 static void mmci_probe_level_translator(struct mmc_host *mmc) 1958 { 1959 struct device *dev = mmc_dev(mmc); 1960 struct mmci_host *host = mmc_priv(mmc); 1961 struct gpio_desc *cmd_gpio; 1962 struct gpio_desc *ck_gpio; 1963 struct gpio_desc *ckin_gpio; 1964 int clk_hi, clk_lo; 1965 1966 /* 1967 * Assume the level translator is present if st,use-ckin is set. 1968 * This is to cater for DTs which do not implement this test. 1969 */ 1970 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; 1971 1972 cmd_gpio = gpiod_get(dev, "st,cmd", GPIOD_OUT_HIGH); 1973 if (IS_ERR(cmd_gpio)) 1974 goto exit_cmd; 1975 1976 ck_gpio = gpiod_get(dev, "st,ck", GPIOD_OUT_HIGH); 1977 if (IS_ERR(ck_gpio)) 1978 goto exit_ck; 1979 1980 ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); 1981 if (IS_ERR(ckin_gpio)) 1982 goto exit_ckin; 1983 1984 /* All GPIOs are valid, test whether level translator works */ 1985 1986 /* Sample CKIN */ 1987 clk_hi = !!gpiod_get_value(ckin_gpio); 1988 1989 /* Set CK low */ 1990 gpiod_set_value(ck_gpio, 0); 1991 1992 /* Sample CKIN */ 1993 clk_lo = !!gpiod_get_value(ckin_gpio); 1994 1995 /* Tristate all */ 1996 gpiod_direction_input(cmd_gpio); 1997 gpiod_direction_input(ck_gpio); 1998 1999 /* Level translator is present if CK signal is propagated to CKIN */ 2000 if (!clk_hi || clk_lo) { 2001 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; 2002 dev_warn(dev, 2003 "Level translator inoperable, CK signal not detected on CKIN, disabling.\n"); 2004 } 2005 2006 gpiod_put(ckin_gpio); 2007 2008 exit_ckin: 2009 gpiod_put(ck_gpio); 2010 exit_ck: 2011 gpiod_put(cmd_gpio); 2012 exit_cmd: 2013 pinctrl_select_default_state(dev); 2014 } 2015 2016 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 2017 { 2018 struct mmci_host *host = mmc_priv(mmc); 2019 int ret = mmc_of_parse(mmc); 2020 2021 if (ret) 2022 return ret; 2023 2024 if (of_property_read_bool(np, "st,sig-dir-dat0")) 2025 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 2026 if (of_property_read_bool(np, "st,sig-dir-dat2")) 2027 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 2028 if (of_property_read_bool(np, "st,sig-dir-dat31")) 2029 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 2030 if (of_property_read_bool(np, "st,sig-dir-dat74")) 2031 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 2032 if (of_property_read_bool(np, "st,sig-dir-cmd")) 2033 host->pwr_reg_add |= MCI_ST_CMDDIREN; 2034 if (of_property_read_bool(np, "st,sig-pin-fbclk")) 2035 host->pwr_reg_add |= MCI_ST_FBCLKEN; 2036 if (of_property_read_bool(np, "st,sig-dir")) 2037 host->pwr_reg_add |= MCI_STM32_DIRPOL; 2038 if (of_property_read_bool(np, "st,neg-edge")) 2039 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; 2040 if (of_property_read_bool(np, "st,use-ckin")) 2041 mmci_probe_level_translator(mmc); 2042 2043 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) 2044 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 2045 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) 2046 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 2047 2048 return 0; 2049 } 2050 2051 static int mmci_probe(struct amba_device *dev, 2052 const struct amba_id *id) 2053 { 2054 struct mmci_platform_data *plat = dev->dev.platform_data; 2055 struct device_node *np = dev->dev.of_node; 2056 struct variant_data *variant = id->data; 2057 struct mmci_host *host; 2058 struct mmc_host *mmc; 2059 int ret; 2060 2061 /* Must have platform data or Device Tree. */ 2062 if (!plat && !np) { 2063 dev_err(&dev->dev, "No plat data or DT found\n"); 2064 return -EINVAL; 2065 } 2066 2067 if (!plat) { 2068 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 2069 if (!plat) 2070 return -ENOMEM; 2071 } 2072 2073 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 2074 if (!mmc) 2075 return -ENOMEM; 2076 2077 host = mmc_priv(mmc); 2078 host->mmc = mmc; 2079 host->mmc_ops = &mmci_ops; 2080 mmc->ops = &mmci_ops; 2081 2082 ret = mmci_of_parse(np, mmc); 2083 if (ret) 2084 goto host_free; 2085 2086 /* 2087 * Some variant (STM32) doesn't have opendrain bit, nevertheless 2088 * pins can be set accordingly using pinctrl 2089 */ 2090 if (!variant->opendrain) { 2091 host->pinctrl = devm_pinctrl_get(&dev->dev); 2092 if (IS_ERR(host->pinctrl)) { 2093 dev_err(&dev->dev, "failed to get pinctrl"); 2094 ret = PTR_ERR(host->pinctrl); 2095 goto host_free; 2096 } 2097 2098 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 2099 MMCI_PINCTRL_STATE_OPENDRAIN); 2100 if (IS_ERR(host->pins_opendrain)) { 2101 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 2102 ret = PTR_ERR(host->pins_opendrain); 2103 goto host_free; 2104 } 2105 } 2106 2107 host->hw_designer = amba_manf(dev); 2108 host->hw_revision = amba_rev(dev); 2109 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 2110 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 2111 2112 host->clk = devm_clk_get(&dev->dev, NULL); 2113 if (IS_ERR(host->clk)) { 2114 ret = PTR_ERR(host->clk); 2115 goto host_free; 2116 } 2117 2118 ret = clk_prepare_enable(host->clk); 2119 if (ret) 2120 goto host_free; 2121 2122 if (variant->qcom_fifo) 2123 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 2124 else 2125 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 2126 2127 host->plat = plat; 2128 host->variant = variant; 2129 host->mclk = clk_get_rate(host->clk); 2130 /* 2131 * According to the spec, mclk is max 100 MHz, 2132 * so we try to adjust the clock down to this, 2133 * (if possible). 2134 */ 2135 if (host->mclk > variant->f_max) { 2136 ret = clk_set_rate(host->clk, variant->f_max); 2137 if (ret < 0) 2138 goto clk_disable; 2139 host->mclk = clk_get_rate(host->clk); 2140 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 2141 host->mclk); 2142 } 2143 2144 host->phybase = dev->res.start; 2145 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 2146 if (IS_ERR(host->base)) { 2147 ret = PTR_ERR(host->base); 2148 goto clk_disable; 2149 } 2150 2151 if (variant->init) 2152 variant->init(host); 2153 2154 /* 2155 * The ARM and ST versions of the block have slightly different 2156 * clock divider equations which means that the minimum divider 2157 * differs too. 2158 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 2159 */ 2160 if (variant->st_clkdiv) 2161 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 2162 else if (variant->stm32_clkdiv) 2163 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); 2164 else if (variant->explicit_mclk_control) 2165 mmc->f_min = clk_round_rate(host->clk, 100000); 2166 else 2167 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 2168 /* 2169 * If no maximum operating frequency is supplied, fall back to use 2170 * the module parameter, which has a (low) default value in case it 2171 * is not specified. Either value must not exceed the clock rate into 2172 * the block, of course. 2173 */ 2174 if (mmc->f_max) 2175 mmc->f_max = variant->explicit_mclk_control ? 2176 min(variant->f_max, mmc->f_max) : 2177 min(host->mclk, mmc->f_max); 2178 else 2179 mmc->f_max = variant->explicit_mclk_control ? 2180 fmax : min(host->mclk, fmax); 2181 2182 2183 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 2184 2185 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 2186 if (IS_ERR(host->rst)) { 2187 ret = PTR_ERR(host->rst); 2188 goto clk_disable; 2189 } 2190 ret = reset_control_deassert(host->rst); 2191 if (ret) 2192 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); 2193 2194 /* Get regulators and the supported OCR mask */ 2195 ret = mmc_regulator_get_supply(mmc); 2196 if (ret) 2197 goto clk_disable; 2198 2199 if (!mmc->ocr_avail) 2200 mmc->ocr_avail = plat->ocr_mask; 2201 else if (plat->ocr_mask) 2202 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 2203 2204 /* We support these capabilities. */ 2205 mmc->caps |= MMC_CAP_CMD23; 2206 2207 /* 2208 * Enable busy detection. 2209 */ 2210 if (variant->busy_detect) { 2211 mmci_ops.card_busy = mmci_card_busy; 2212 /* 2213 * Not all variants have a flag to enable busy detection 2214 * in the DPSM, but if they do, set it here. 2215 */ 2216 if (variant->busy_dpsm_flag) 2217 mmci_write_datactrlreg(host, 2218 host->variant->busy_dpsm_flag); 2219 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 2220 } 2221 2222 /* Variants with mandatory busy timeout in HW needs R1B responses. */ 2223 if (variant->busy_timeout) 2224 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; 2225 2226 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ 2227 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; 2228 host->stop_abort.arg = 0; 2229 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; 2230 2231 /* We support these PM capabilities. */ 2232 mmc->pm_caps |= MMC_PM_KEEP_POWER; 2233 2234 /* 2235 * We can do SGIO 2236 */ 2237 mmc->max_segs = NR_SG; 2238 2239 /* 2240 * Since only a certain number of bits are valid in the data length 2241 * register, we must ensure that we don't exceed 2^num-1 bytes in a 2242 * single request. 2243 */ 2244 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 2245 2246 /* 2247 * Set the maximum segment size. Since we aren't doing DMA 2248 * (yet) we are only limited by the data length register. 2249 */ 2250 mmc->max_seg_size = mmc->max_req_size; 2251 2252 /* 2253 * Block size can be up to 2048 bytes, but must be a power of two. 2254 */ 2255 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 2256 2257 /* 2258 * Limit the number of blocks transferred so that we don't overflow 2259 * the maximum request size. 2260 */ 2261 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 2262 2263 spin_lock_init(&host->lock); 2264 2265 writel(0, host->base + MMCIMASK0); 2266 2267 if (variant->mmcimask1) 2268 writel(0, host->base + MMCIMASK1); 2269 2270 writel(0xfff, host->base + MMCICLEAR); 2271 2272 /* 2273 * If: 2274 * - not using DT but using a descriptor table, or 2275 * - using a table of descriptors ALONGSIDE DT, or 2276 * look up these descriptors named "cd" and "wp" right here, fail 2277 * silently of these do not exist 2278 */ 2279 if (!np) { 2280 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); 2281 if (ret == -EPROBE_DEFER) 2282 goto clk_disable; 2283 2284 ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); 2285 if (ret == -EPROBE_DEFER) 2286 goto clk_disable; 2287 } 2288 2289 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, 2290 mmci_irq_thread, IRQF_SHARED, 2291 DRIVER_NAME " (cmd)", host); 2292 if (ret) 2293 goto clk_disable; 2294 2295 if (!dev->irq[1]) 2296 host->singleirq = true; 2297 else { 2298 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 2299 IRQF_SHARED, DRIVER_NAME " (pio)", host); 2300 if (ret) 2301 goto clk_disable; 2302 } 2303 2304 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 2305 2306 amba_set_drvdata(dev, mmc); 2307 2308 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2309 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2310 amba_rev(dev), (unsigned long long)dev->res.start, 2311 dev->irq[0], dev->irq[1]); 2312 2313 mmci_dma_setup(host); 2314 2315 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2316 pm_runtime_use_autosuspend(&dev->dev); 2317 2318 ret = mmc_add_host(mmc); 2319 if (ret) 2320 goto clk_disable; 2321 2322 pm_runtime_put(&dev->dev); 2323 return 0; 2324 2325 clk_disable: 2326 clk_disable_unprepare(host->clk); 2327 host_free: 2328 mmc_free_host(mmc); 2329 return ret; 2330 } 2331 2332 static void mmci_remove(struct amba_device *dev) 2333 { 2334 struct mmc_host *mmc = amba_get_drvdata(dev); 2335 2336 if (mmc) { 2337 struct mmci_host *host = mmc_priv(mmc); 2338 struct variant_data *variant = host->variant; 2339 2340 /* 2341 * Undo pm_runtime_put() in probe. We use the _sync 2342 * version here so that we can access the primecell. 2343 */ 2344 pm_runtime_get_sync(&dev->dev); 2345 2346 mmc_remove_host(mmc); 2347 2348 writel(0, host->base + MMCIMASK0); 2349 2350 if (variant->mmcimask1) 2351 writel(0, host->base + MMCIMASK1); 2352 2353 writel(0, host->base + MMCICOMMAND); 2354 writel(0, host->base + MMCIDATACTRL); 2355 2356 mmci_dma_release(host); 2357 clk_disable_unprepare(host->clk); 2358 mmc_free_host(mmc); 2359 } 2360 } 2361 2362 #ifdef CONFIG_PM 2363 static void mmci_save(struct mmci_host *host) 2364 { 2365 unsigned long flags; 2366 2367 spin_lock_irqsave(&host->lock, flags); 2368 2369 writel(0, host->base + MMCIMASK0); 2370 if (host->variant->pwrreg_nopower) { 2371 writel(0, host->base + MMCIDATACTRL); 2372 writel(0, host->base + MMCIPOWER); 2373 writel(0, host->base + MMCICLOCK); 2374 } 2375 mmci_reg_delay(host); 2376 2377 spin_unlock_irqrestore(&host->lock, flags); 2378 } 2379 2380 static void mmci_restore(struct mmci_host *host) 2381 { 2382 unsigned long flags; 2383 2384 spin_lock_irqsave(&host->lock, flags); 2385 2386 if (host->variant->pwrreg_nopower) { 2387 writel(host->clk_reg, host->base + MMCICLOCK); 2388 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2389 writel(host->pwr_reg, host->base + MMCIPOWER); 2390 } 2391 writel(MCI_IRQENABLE | host->variant->start_err, 2392 host->base + MMCIMASK0); 2393 mmci_reg_delay(host); 2394 2395 spin_unlock_irqrestore(&host->lock, flags); 2396 } 2397 2398 static int mmci_runtime_suspend(struct device *dev) 2399 { 2400 struct amba_device *adev = to_amba_device(dev); 2401 struct mmc_host *mmc = amba_get_drvdata(adev); 2402 2403 if (mmc) { 2404 struct mmci_host *host = mmc_priv(mmc); 2405 pinctrl_pm_select_sleep_state(dev); 2406 mmci_save(host); 2407 clk_disable_unprepare(host->clk); 2408 } 2409 2410 return 0; 2411 } 2412 2413 static int mmci_runtime_resume(struct device *dev) 2414 { 2415 struct amba_device *adev = to_amba_device(dev); 2416 struct mmc_host *mmc = amba_get_drvdata(adev); 2417 2418 if (mmc) { 2419 struct mmci_host *host = mmc_priv(mmc); 2420 clk_prepare_enable(host->clk); 2421 mmci_restore(host); 2422 pinctrl_select_default_state(dev); 2423 } 2424 2425 return 0; 2426 } 2427 #endif 2428 2429 static const struct dev_pm_ops mmci_dev_pm_ops = { 2430 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2431 pm_runtime_force_resume) 2432 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2433 }; 2434 2435 static const struct amba_id mmci_ids[] = { 2436 { 2437 .id = 0x00041180, 2438 .mask = 0xff0fffff, 2439 .data = &variant_arm, 2440 }, 2441 { 2442 .id = 0x01041180, 2443 .mask = 0xff0fffff, 2444 .data = &variant_arm_extended_fifo, 2445 }, 2446 { 2447 .id = 0x02041180, 2448 .mask = 0xff0fffff, 2449 .data = &variant_arm_extended_fifo_hwfc, 2450 }, 2451 { 2452 .id = 0x00041181, 2453 .mask = 0x000fffff, 2454 .data = &variant_arm, 2455 }, 2456 /* ST Micro variants */ 2457 { 2458 .id = 0x00180180, 2459 .mask = 0x00ffffff, 2460 .data = &variant_u300, 2461 }, 2462 { 2463 .id = 0x10180180, 2464 .mask = 0xf0ffffff, 2465 .data = &variant_nomadik, 2466 }, 2467 { 2468 .id = 0x00280180, 2469 .mask = 0x00ffffff, 2470 .data = &variant_nomadik, 2471 }, 2472 { 2473 .id = 0x00480180, 2474 .mask = 0xf0ffffff, 2475 .data = &variant_ux500, 2476 }, 2477 { 2478 .id = 0x10480180, 2479 .mask = 0xf0ffffff, 2480 .data = &variant_ux500v2, 2481 }, 2482 { 2483 .id = 0x00880180, 2484 .mask = 0x00ffffff, 2485 .data = &variant_stm32, 2486 }, 2487 { 2488 .id = 0x10153180, 2489 .mask = 0xf0ffffff, 2490 .data = &variant_stm32_sdmmc, 2491 }, 2492 { 2493 .id = 0x00253180, 2494 .mask = 0xf0ffffff, 2495 .data = &variant_stm32_sdmmcv2, 2496 }, 2497 { 2498 .id = 0x20253180, 2499 .mask = 0xf0ffffff, 2500 .data = &variant_stm32_sdmmcv2, 2501 }, 2502 /* Qualcomm variants */ 2503 { 2504 .id = 0x00051180, 2505 .mask = 0x000fffff, 2506 .data = &variant_qcom, 2507 }, 2508 { 0, 0 }, 2509 }; 2510 2511 MODULE_DEVICE_TABLE(amba, mmci_ids); 2512 2513 static struct amba_driver mmci_driver = { 2514 .drv = { 2515 .name = DRIVER_NAME, 2516 .pm = &mmci_dev_pm_ops, 2517 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2518 }, 2519 .probe = mmci_probe, 2520 .remove = mmci_remove, 2521 .id_table = mmci_ids, 2522 }; 2523 2524 module_amba_driver(mmci_driver); 2525 2526 module_param(fmax, uint, 0444); 2527 2528 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2529 MODULE_LICENSE("GPL"); 2530