1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/highmem.h> 21 #include <linux/log2.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/card.h> 24 #include <linux/amba/bus.h> 25 #include <linux/clk.h> 26 #include <linux/scatterlist.h> 27 #include <linux/gpio.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/dmaengine.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/amba/mmci.h> 32 #include <linux/pm_runtime.h> 33 34 #include <asm/div64.h> 35 #include <asm/io.h> 36 #include <asm/sizes.h> 37 38 #include "mmci.h" 39 40 #define DRIVER_NAME "mmci-pl18x" 41 42 static unsigned int fmax = 515633; 43 44 /** 45 * struct variant_data - MMCI variant-specific quirks 46 * @clkreg: default value for MCICLOCK register 47 * @clkreg_enable: enable value for MMCICLOCK register 48 * @datalength_bits: number of bits in the MMCIDATALENGTH register 49 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 50 * is asserted (likewise for RX) 51 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 52 * is asserted (likewise for RX) 53 * @sdio: variant supports SDIO 54 * @st_clkdiv: true if using a ST-specific clock divider algorithm 55 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 56 * @pwrreg_powerup: power up value for MMCIPOWER register 57 * @signal_direction: input/out direction of bus signals can be indicated 58 */ 59 struct variant_data { 60 unsigned int clkreg; 61 unsigned int clkreg_enable; 62 unsigned int datalength_bits; 63 unsigned int fifosize; 64 unsigned int fifohalfsize; 65 bool sdio; 66 bool st_clkdiv; 67 bool blksz_datactrl16; 68 u32 pwrreg_powerup; 69 bool signal_direction; 70 }; 71 72 static struct variant_data variant_arm = { 73 .fifosize = 16 * 4, 74 .fifohalfsize = 8 * 4, 75 .datalength_bits = 16, 76 .pwrreg_powerup = MCI_PWR_UP, 77 }; 78 79 static struct variant_data variant_arm_extended_fifo = { 80 .fifosize = 128 * 4, 81 .fifohalfsize = 64 * 4, 82 .datalength_bits = 16, 83 .pwrreg_powerup = MCI_PWR_UP, 84 }; 85 86 static struct variant_data variant_u300 = { 87 .fifosize = 16 * 4, 88 .fifohalfsize = 8 * 4, 89 .clkreg_enable = MCI_ST_U300_HWFCEN, 90 .datalength_bits = 16, 91 .sdio = true, 92 .pwrreg_powerup = MCI_PWR_ON, 93 .signal_direction = true, 94 }; 95 96 static struct variant_data variant_ux500 = { 97 .fifosize = 30 * 4, 98 .fifohalfsize = 8 * 4, 99 .clkreg = MCI_CLK_ENABLE, 100 .clkreg_enable = MCI_ST_UX500_HWFCEN, 101 .datalength_bits = 24, 102 .sdio = true, 103 .st_clkdiv = true, 104 .pwrreg_powerup = MCI_PWR_ON, 105 .signal_direction = true, 106 }; 107 108 static struct variant_data variant_ux500v2 = { 109 .fifosize = 30 * 4, 110 .fifohalfsize = 8 * 4, 111 .clkreg = MCI_CLK_ENABLE, 112 .clkreg_enable = MCI_ST_UX500_HWFCEN, 113 .datalength_bits = 24, 114 .sdio = true, 115 .st_clkdiv = true, 116 .blksz_datactrl16 = true, 117 .pwrreg_powerup = MCI_PWR_ON, 118 .signal_direction = true, 119 }; 120 121 /* 122 * This must be called with host->lock held 123 */ 124 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 125 { 126 struct variant_data *variant = host->variant; 127 u32 clk = variant->clkreg; 128 129 if (desired) { 130 if (desired >= host->mclk) { 131 clk = MCI_CLK_BYPASS; 132 if (variant->st_clkdiv) 133 clk |= MCI_ST_UX500_NEG_EDGE; 134 host->cclk = host->mclk; 135 } else if (variant->st_clkdiv) { 136 /* 137 * DB8500 TRM says f = mclk / (clkdiv + 2) 138 * => clkdiv = (mclk / f) - 2 139 * Round the divider up so we don't exceed the max 140 * frequency 141 */ 142 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 143 if (clk >= 256) 144 clk = 255; 145 host->cclk = host->mclk / (clk + 2); 146 } else { 147 /* 148 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 149 * => clkdiv = mclk / (2 * f) - 1 150 */ 151 clk = host->mclk / (2 * desired) - 1; 152 if (clk >= 256) 153 clk = 255; 154 host->cclk = host->mclk / (2 * (clk + 1)); 155 } 156 157 clk |= variant->clkreg_enable; 158 clk |= MCI_CLK_ENABLE; 159 /* This hasn't proven to be worthwhile */ 160 /* clk |= MCI_CLK_PWRSAVE; */ 161 } 162 163 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 164 clk |= MCI_4BIT_BUS; 165 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 166 clk |= MCI_ST_8BIT_BUS; 167 168 writel(clk, host->base + MMCICLOCK); 169 } 170 171 static void 172 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 173 { 174 writel(0, host->base + MMCICOMMAND); 175 176 BUG_ON(host->data); 177 178 host->mrq = NULL; 179 host->cmd = NULL; 180 181 mmc_request_done(host->mmc, mrq); 182 183 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 184 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 185 } 186 187 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 188 { 189 void __iomem *base = host->base; 190 191 if (host->singleirq) { 192 unsigned int mask0 = readl(base + MMCIMASK0); 193 194 mask0 &= ~MCI_IRQ1MASK; 195 mask0 |= mask; 196 197 writel(mask0, base + MMCIMASK0); 198 } 199 200 writel(mask, base + MMCIMASK1); 201 } 202 203 static void mmci_stop_data(struct mmci_host *host) 204 { 205 writel(0, host->base + MMCIDATACTRL); 206 mmci_set_mask1(host, 0); 207 host->data = NULL; 208 } 209 210 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 211 { 212 unsigned int flags = SG_MITER_ATOMIC; 213 214 if (data->flags & MMC_DATA_READ) 215 flags |= SG_MITER_TO_SG; 216 else 217 flags |= SG_MITER_FROM_SG; 218 219 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 220 } 221 222 /* 223 * All the DMA operation mode stuff goes inside this ifdef. 224 * This assumes that you have a generic DMA device interface, 225 * no custom DMA interfaces are supported. 226 */ 227 #ifdef CONFIG_DMA_ENGINE 228 static void __devinit mmci_dma_setup(struct mmci_host *host) 229 { 230 struct mmci_platform_data *plat = host->plat; 231 const char *rxname, *txname; 232 dma_cap_mask_t mask; 233 234 if (!plat || !plat->dma_filter) { 235 dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 236 return; 237 } 238 239 /* initialize pre request cookie */ 240 host->next_data.cookie = 1; 241 242 /* Try to acquire a generic DMA engine slave channel */ 243 dma_cap_zero(mask); 244 dma_cap_set(DMA_SLAVE, mask); 245 246 /* 247 * If only an RX channel is specified, the driver will 248 * attempt to use it bidirectionally, however if it is 249 * is specified but cannot be located, DMA will be disabled. 250 */ 251 if (plat->dma_rx_param) { 252 host->dma_rx_channel = dma_request_channel(mask, 253 plat->dma_filter, 254 plat->dma_rx_param); 255 /* E.g if no DMA hardware is present */ 256 if (!host->dma_rx_channel) 257 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 258 } 259 260 if (plat->dma_tx_param) { 261 host->dma_tx_channel = dma_request_channel(mask, 262 plat->dma_filter, 263 plat->dma_tx_param); 264 if (!host->dma_tx_channel) 265 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 266 } else { 267 host->dma_tx_channel = host->dma_rx_channel; 268 } 269 270 if (host->dma_rx_channel) 271 rxname = dma_chan_name(host->dma_rx_channel); 272 else 273 rxname = "none"; 274 275 if (host->dma_tx_channel) 276 txname = dma_chan_name(host->dma_tx_channel); 277 else 278 txname = "none"; 279 280 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 281 rxname, txname); 282 283 /* 284 * Limit the maximum segment size in any SG entry according to 285 * the parameters of the DMA engine device. 286 */ 287 if (host->dma_tx_channel) { 288 struct device *dev = host->dma_tx_channel->device->dev; 289 unsigned int max_seg_size = dma_get_max_seg_size(dev); 290 291 if (max_seg_size < host->mmc->max_seg_size) 292 host->mmc->max_seg_size = max_seg_size; 293 } 294 if (host->dma_rx_channel) { 295 struct device *dev = host->dma_rx_channel->device->dev; 296 unsigned int max_seg_size = dma_get_max_seg_size(dev); 297 298 if (max_seg_size < host->mmc->max_seg_size) 299 host->mmc->max_seg_size = max_seg_size; 300 } 301 } 302 303 /* 304 * This is used in __devinit or __devexit so inline it 305 * so it can be discarded. 306 */ 307 static inline void mmci_dma_release(struct mmci_host *host) 308 { 309 struct mmci_platform_data *plat = host->plat; 310 311 if (host->dma_rx_channel) 312 dma_release_channel(host->dma_rx_channel); 313 if (host->dma_tx_channel && plat->dma_tx_param) 314 dma_release_channel(host->dma_tx_channel); 315 host->dma_rx_channel = host->dma_tx_channel = NULL; 316 } 317 318 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 319 { 320 struct dma_chan *chan = host->dma_current; 321 enum dma_data_direction dir; 322 u32 status; 323 int i; 324 325 /* Wait up to 1ms for the DMA to complete */ 326 for (i = 0; ; i++) { 327 status = readl(host->base + MMCISTATUS); 328 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 329 break; 330 udelay(10); 331 } 332 333 /* 334 * Check to see whether we still have some data left in the FIFO - 335 * this catches DMA controllers which are unable to monitor the 336 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 337 * contiguous buffers. On TX, we'll get a FIFO underrun error. 338 */ 339 if (status & MCI_RXDATAAVLBLMASK) { 340 dmaengine_terminate_all(chan); 341 if (!data->error) 342 data->error = -EIO; 343 } 344 345 if (data->flags & MMC_DATA_WRITE) { 346 dir = DMA_TO_DEVICE; 347 } else { 348 dir = DMA_FROM_DEVICE; 349 } 350 351 if (!data->host_cookie) 352 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 353 354 /* 355 * Use of DMA with scatter-gather is impossible. 356 * Give up with DMA and switch back to PIO mode. 357 */ 358 if (status & MCI_RXDATAAVLBLMASK) { 359 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 360 mmci_dma_release(host); 361 } 362 } 363 364 static void mmci_dma_data_error(struct mmci_host *host) 365 { 366 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 367 dmaengine_terminate_all(host->dma_current); 368 } 369 370 static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 371 struct mmci_host_next *next) 372 { 373 struct variant_data *variant = host->variant; 374 struct dma_slave_config conf = { 375 .src_addr = host->phybase + MMCIFIFO, 376 .dst_addr = host->phybase + MMCIFIFO, 377 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 378 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 379 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 380 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 381 }; 382 struct dma_chan *chan; 383 struct dma_device *device; 384 struct dma_async_tx_descriptor *desc; 385 enum dma_data_direction buffer_dirn; 386 int nr_sg; 387 388 /* Check if next job is already prepared */ 389 if (data->host_cookie && !next && 390 host->dma_current && host->dma_desc_current) 391 return 0; 392 393 if (!next) { 394 host->dma_current = NULL; 395 host->dma_desc_current = NULL; 396 } 397 398 if (data->flags & MMC_DATA_READ) { 399 conf.direction = DMA_DEV_TO_MEM; 400 buffer_dirn = DMA_FROM_DEVICE; 401 chan = host->dma_rx_channel; 402 } else { 403 conf.direction = DMA_MEM_TO_DEV; 404 buffer_dirn = DMA_TO_DEVICE; 405 chan = host->dma_tx_channel; 406 } 407 408 /* If there's no DMA channel, fall back to PIO */ 409 if (!chan) 410 return -EINVAL; 411 412 /* If less than or equal to the fifo size, don't bother with DMA */ 413 if (data->blksz * data->blocks <= variant->fifosize) 414 return -EINVAL; 415 416 device = chan->device; 417 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 418 if (nr_sg == 0) 419 return -EINVAL; 420 421 dmaengine_slave_config(chan, &conf); 422 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, 423 conf.direction, DMA_CTRL_ACK); 424 if (!desc) 425 goto unmap_exit; 426 427 if (next) { 428 next->dma_chan = chan; 429 next->dma_desc = desc; 430 } else { 431 host->dma_current = chan; 432 host->dma_desc_current = desc; 433 } 434 435 return 0; 436 437 unmap_exit: 438 if (!next) 439 dmaengine_terminate_all(chan); 440 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 441 return -ENOMEM; 442 } 443 444 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 445 { 446 int ret; 447 struct mmc_data *data = host->data; 448 449 ret = mmci_dma_prep_data(host, host->data, NULL); 450 if (ret) 451 return ret; 452 453 /* Okay, go for it. */ 454 dev_vdbg(mmc_dev(host->mmc), 455 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 456 data->sg_len, data->blksz, data->blocks, data->flags); 457 dmaengine_submit(host->dma_desc_current); 458 dma_async_issue_pending(host->dma_current); 459 460 datactrl |= MCI_DPSM_DMAENABLE; 461 462 /* Trigger the DMA transfer */ 463 writel(datactrl, host->base + MMCIDATACTRL); 464 465 /* 466 * Let the MMCI say when the data is ended and it's time 467 * to fire next DMA request. When that happens, MMCI will 468 * call mmci_data_end() 469 */ 470 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 471 host->base + MMCIMASK0); 472 return 0; 473 } 474 475 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 476 { 477 struct mmci_host_next *next = &host->next_data; 478 479 if (data->host_cookie && data->host_cookie != next->cookie) { 480 pr_warning("[%s] invalid cookie: data->host_cookie %d" 481 " host->next_data.cookie %d\n", 482 __func__, data->host_cookie, host->next_data.cookie); 483 data->host_cookie = 0; 484 } 485 486 if (!data->host_cookie) 487 return; 488 489 host->dma_desc_current = next->dma_desc; 490 host->dma_current = next->dma_chan; 491 492 next->dma_desc = NULL; 493 next->dma_chan = NULL; 494 } 495 496 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 497 bool is_first_req) 498 { 499 struct mmci_host *host = mmc_priv(mmc); 500 struct mmc_data *data = mrq->data; 501 struct mmci_host_next *nd = &host->next_data; 502 503 if (!data) 504 return; 505 506 if (data->host_cookie) { 507 data->host_cookie = 0; 508 return; 509 } 510 511 /* if config for dma */ 512 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 513 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 514 if (mmci_dma_prep_data(host, data, nd)) 515 data->host_cookie = 0; 516 else 517 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 518 } 519 } 520 521 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 522 int err) 523 { 524 struct mmci_host *host = mmc_priv(mmc); 525 struct mmc_data *data = mrq->data; 526 struct dma_chan *chan; 527 enum dma_data_direction dir; 528 529 if (!data) 530 return; 531 532 if (data->flags & MMC_DATA_READ) { 533 dir = DMA_FROM_DEVICE; 534 chan = host->dma_rx_channel; 535 } else { 536 dir = DMA_TO_DEVICE; 537 chan = host->dma_tx_channel; 538 } 539 540 541 /* if config for dma */ 542 if (chan) { 543 if (err) 544 dmaengine_terminate_all(chan); 545 if (data->host_cookie) 546 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 547 data->sg_len, dir); 548 mrq->data->host_cookie = 0; 549 } 550 } 551 552 #else 553 /* Blank functions if the DMA engine is not available */ 554 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 555 { 556 } 557 static inline void mmci_dma_setup(struct mmci_host *host) 558 { 559 } 560 561 static inline void mmci_dma_release(struct mmci_host *host) 562 { 563 } 564 565 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 566 { 567 } 568 569 static inline void mmci_dma_data_error(struct mmci_host *host) 570 { 571 } 572 573 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 574 { 575 return -ENOSYS; 576 } 577 578 #define mmci_pre_request NULL 579 #define mmci_post_request NULL 580 581 #endif 582 583 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 584 { 585 struct variant_data *variant = host->variant; 586 unsigned int datactrl, timeout, irqmask; 587 unsigned long long clks; 588 void __iomem *base; 589 int blksz_bits; 590 591 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 592 data->blksz, data->blocks, data->flags); 593 594 host->data = data; 595 host->size = data->blksz * data->blocks; 596 data->bytes_xfered = 0; 597 598 clks = (unsigned long long)data->timeout_ns * host->cclk; 599 do_div(clks, 1000000000UL); 600 601 timeout = data->timeout_clks + (unsigned int)clks; 602 603 base = host->base; 604 writel(timeout, base + MMCIDATATIMER); 605 writel(host->size, base + MMCIDATALENGTH); 606 607 blksz_bits = ffs(data->blksz) - 1; 608 BUG_ON(1 << blksz_bits != data->blksz); 609 610 if (variant->blksz_datactrl16) 611 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 612 else 613 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 614 615 if (data->flags & MMC_DATA_READ) 616 datactrl |= MCI_DPSM_DIRECTION; 617 618 /* The ST Micro variants has a special bit to enable SDIO */ 619 if (variant->sdio && host->mmc->card) 620 if (mmc_card_sdio(host->mmc->card)) 621 datactrl |= MCI_ST_DPSM_SDIOEN; 622 623 /* 624 * Attempt to use DMA operation mode, if this 625 * should fail, fall back to PIO mode 626 */ 627 if (!mmci_dma_start_data(host, datactrl)) 628 return; 629 630 /* IRQ mode, map the SG list for CPU reading/writing */ 631 mmci_init_sg(host, data); 632 633 if (data->flags & MMC_DATA_READ) { 634 irqmask = MCI_RXFIFOHALFFULLMASK; 635 636 /* 637 * If we have less than the fifo 'half-full' threshold to 638 * transfer, trigger a PIO interrupt as soon as any data 639 * is available. 640 */ 641 if (host->size < variant->fifohalfsize) 642 irqmask |= MCI_RXDATAAVLBLMASK; 643 } else { 644 /* 645 * We don't actually need to include "FIFO empty" here 646 * since its implicit in "FIFO half empty". 647 */ 648 irqmask = MCI_TXFIFOHALFEMPTYMASK; 649 } 650 651 writel(datactrl, base + MMCIDATACTRL); 652 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 653 mmci_set_mask1(host, irqmask); 654 } 655 656 static void 657 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 658 { 659 void __iomem *base = host->base; 660 661 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 662 cmd->opcode, cmd->arg, cmd->flags); 663 664 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 665 writel(0, base + MMCICOMMAND); 666 udelay(1); 667 } 668 669 c |= cmd->opcode | MCI_CPSM_ENABLE; 670 if (cmd->flags & MMC_RSP_PRESENT) { 671 if (cmd->flags & MMC_RSP_136) 672 c |= MCI_CPSM_LONGRSP; 673 c |= MCI_CPSM_RESPONSE; 674 } 675 if (/*interrupt*/0) 676 c |= MCI_CPSM_INTERRUPT; 677 678 host->cmd = cmd; 679 680 writel(cmd->arg, base + MMCIARGUMENT); 681 writel(c, base + MMCICOMMAND); 682 } 683 684 static void 685 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 686 unsigned int status) 687 { 688 /* First check for errors */ 689 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 690 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 691 u32 remain, success; 692 693 /* Terminate the DMA transfer */ 694 if (dma_inprogress(host)) 695 mmci_dma_data_error(host); 696 697 /* 698 * Calculate how far we are into the transfer. Note that 699 * the data counter gives the number of bytes transferred 700 * on the MMC bus, not on the host side. On reads, this 701 * can be as much as a FIFO-worth of data ahead. This 702 * matters for FIFO overruns only. 703 */ 704 remain = readl(host->base + MMCIDATACNT); 705 success = data->blksz * data->blocks - remain; 706 707 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 708 status, success); 709 if (status & MCI_DATACRCFAIL) { 710 /* Last block was not successful */ 711 success -= 1; 712 data->error = -EILSEQ; 713 } else if (status & MCI_DATATIMEOUT) { 714 data->error = -ETIMEDOUT; 715 } else if (status & MCI_STARTBITERR) { 716 data->error = -ECOMM; 717 } else if (status & MCI_TXUNDERRUN) { 718 data->error = -EIO; 719 } else if (status & MCI_RXOVERRUN) { 720 if (success > host->variant->fifosize) 721 success -= host->variant->fifosize; 722 else 723 success = 0; 724 data->error = -EIO; 725 } 726 data->bytes_xfered = round_down(success, data->blksz); 727 } 728 729 if (status & MCI_DATABLOCKEND) 730 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 731 732 if (status & MCI_DATAEND || data->error) { 733 if (dma_inprogress(host)) 734 mmci_dma_unmap(host, data); 735 mmci_stop_data(host); 736 737 if (!data->error) 738 /* The error clause is handled above, success! */ 739 data->bytes_xfered = data->blksz * data->blocks; 740 741 if (!data->stop) { 742 mmci_request_end(host, data->mrq); 743 } else { 744 mmci_start_command(host, data->stop, 0); 745 } 746 } 747 } 748 749 static void 750 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 751 unsigned int status) 752 { 753 void __iomem *base = host->base; 754 755 host->cmd = NULL; 756 757 if (status & MCI_CMDTIMEOUT) { 758 cmd->error = -ETIMEDOUT; 759 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 760 cmd->error = -EILSEQ; 761 } else { 762 cmd->resp[0] = readl(base + MMCIRESPONSE0); 763 cmd->resp[1] = readl(base + MMCIRESPONSE1); 764 cmd->resp[2] = readl(base + MMCIRESPONSE2); 765 cmd->resp[3] = readl(base + MMCIRESPONSE3); 766 } 767 768 if (!cmd->data || cmd->error) { 769 if (host->data) { 770 /* Terminate the DMA transfer */ 771 if (dma_inprogress(host)) 772 mmci_dma_data_error(host); 773 mmci_stop_data(host); 774 } 775 mmci_request_end(host, cmd->mrq); 776 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 777 mmci_start_data(host, cmd->data); 778 } 779 } 780 781 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 782 { 783 void __iomem *base = host->base; 784 char *ptr = buffer; 785 u32 status; 786 int host_remain = host->size; 787 788 do { 789 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 790 791 if (count > remain) 792 count = remain; 793 794 if (count <= 0) 795 break; 796 797 readsl(base + MMCIFIFO, ptr, count >> 2); 798 799 ptr += count; 800 remain -= count; 801 host_remain -= count; 802 803 if (remain == 0) 804 break; 805 806 status = readl(base + MMCISTATUS); 807 } while (status & MCI_RXDATAAVLBL); 808 809 return ptr - buffer; 810 } 811 812 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 813 { 814 struct variant_data *variant = host->variant; 815 void __iomem *base = host->base; 816 char *ptr = buffer; 817 818 do { 819 unsigned int count, maxcnt; 820 821 maxcnt = status & MCI_TXFIFOEMPTY ? 822 variant->fifosize : variant->fifohalfsize; 823 count = min(remain, maxcnt); 824 825 /* 826 * The ST Micro variant for SDIO transfer sizes 827 * less then 8 bytes should have clock H/W flow 828 * control disabled. 829 */ 830 if (variant->sdio && 831 mmc_card_sdio(host->mmc->card)) { 832 if (count < 8) 833 writel(readl(host->base + MMCICLOCK) & 834 ~variant->clkreg_enable, 835 host->base + MMCICLOCK); 836 else 837 writel(readl(host->base + MMCICLOCK) | 838 variant->clkreg_enable, 839 host->base + MMCICLOCK); 840 } 841 842 /* 843 * SDIO especially may want to send something that is 844 * not divisible by 4 (as opposed to card sectors 845 * etc), and the FIFO only accept full 32-bit writes. 846 * So compensate by adding +3 on the count, a single 847 * byte become a 32bit write, 7 bytes will be two 848 * 32bit writes etc. 849 */ 850 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 851 852 ptr += count; 853 remain -= count; 854 855 if (remain == 0) 856 break; 857 858 status = readl(base + MMCISTATUS); 859 } while (status & MCI_TXFIFOHALFEMPTY); 860 861 return ptr - buffer; 862 } 863 864 /* 865 * PIO data transfer IRQ handler. 866 */ 867 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 868 { 869 struct mmci_host *host = dev_id; 870 struct sg_mapping_iter *sg_miter = &host->sg_miter; 871 struct variant_data *variant = host->variant; 872 void __iomem *base = host->base; 873 unsigned long flags; 874 u32 status; 875 876 status = readl(base + MMCISTATUS); 877 878 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 879 880 local_irq_save(flags); 881 882 do { 883 unsigned int remain, len; 884 char *buffer; 885 886 /* 887 * For write, we only need to test the half-empty flag 888 * here - if the FIFO is completely empty, then by 889 * definition it is more than half empty. 890 * 891 * For read, check for data available. 892 */ 893 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 894 break; 895 896 if (!sg_miter_next(sg_miter)) 897 break; 898 899 buffer = sg_miter->addr; 900 remain = sg_miter->length; 901 902 len = 0; 903 if (status & MCI_RXACTIVE) 904 len = mmci_pio_read(host, buffer, remain); 905 if (status & MCI_TXACTIVE) 906 len = mmci_pio_write(host, buffer, remain, status); 907 908 sg_miter->consumed = len; 909 910 host->size -= len; 911 remain -= len; 912 913 if (remain) 914 break; 915 916 status = readl(base + MMCISTATUS); 917 } while (1); 918 919 sg_miter_stop(sg_miter); 920 921 local_irq_restore(flags); 922 923 /* 924 * If we have less than the fifo 'half-full' threshold to transfer, 925 * trigger a PIO interrupt as soon as any data is available. 926 */ 927 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 928 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 929 930 /* 931 * If we run out of data, disable the data IRQs; this 932 * prevents a race where the FIFO becomes empty before 933 * the chip itself has disabled the data path, and 934 * stops us racing with our data end IRQ. 935 */ 936 if (host->size == 0) { 937 mmci_set_mask1(host, 0); 938 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 939 } 940 941 return IRQ_HANDLED; 942 } 943 944 /* 945 * Handle completion of command and data transfers. 946 */ 947 static irqreturn_t mmci_irq(int irq, void *dev_id) 948 { 949 struct mmci_host *host = dev_id; 950 u32 status; 951 int ret = 0; 952 953 spin_lock(&host->lock); 954 955 do { 956 struct mmc_command *cmd; 957 struct mmc_data *data; 958 959 status = readl(host->base + MMCISTATUS); 960 961 if (host->singleirq) { 962 if (status & readl(host->base + MMCIMASK1)) 963 mmci_pio_irq(irq, dev_id); 964 965 status &= ~MCI_IRQ1MASK; 966 } 967 968 status &= readl(host->base + MMCIMASK0); 969 writel(status, host->base + MMCICLEAR); 970 971 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 972 973 data = host->data; 974 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 975 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 976 MCI_DATABLOCKEND) && data) 977 mmci_data_irq(host, data, status); 978 979 cmd = host->cmd; 980 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 981 mmci_cmd_irq(host, cmd, status); 982 983 ret = 1; 984 } while (status); 985 986 spin_unlock(&host->lock); 987 988 return IRQ_RETVAL(ret); 989 } 990 991 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 992 { 993 struct mmci_host *host = mmc_priv(mmc); 994 unsigned long flags; 995 996 WARN_ON(host->mrq != NULL); 997 998 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 999 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 1000 mrq->data->blksz); 1001 mrq->cmd->error = -EINVAL; 1002 mmc_request_done(mmc, mrq); 1003 return; 1004 } 1005 1006 pm_runtime_get_sync(mmc_dev(mmc)); 1007 1008 spin_lock_irqsave(&host->lock, flags); 1009 1010 host->mrq = mrq; 1011 1012 if (mrq->data) 1013 mmci_get_next_data(host, mrq->data); 1014 1015 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1016 mmci_start_data(host, mrq->data); 1017 1018 mmci_start_command(host, mrq->cmd, 0); 1019 1020 spin_unlock_irqrestore(&host->lock, flags); 1021 } 1022 1023 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1024 { 1025 struct mmci_host *host = mmc_priv(mmc); 1026 struct variant_data *variant = host->variant; 1027 u32 pwr = 0; 1028 unsigned long flags; 1029 int ret; 1030 1031 pm_runtime_get_sync(mmc_dev(mmc)); 1032 1033 if (host->plat->ios_handler && 1034 host->plat->ios_handler(mmc_dev(mmc), ios)) 1035 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1036 1037 switch (ios->power_mode) { 1038 case MMC_POWER_OFF: 1039 if (host->vcc) 1040 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 1041 break; 1042 case MMC_POWER_UP: 1043 if (host->vcc) { 1044 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 1045 if (ret) { 1046 dev_err(mmc_dev(mmc), "unable to set OCR\n"); 1047 /* 1048 * The .set_ios() function in the mmc_host_ops 1049 * struct return void, and failing to set the 1050 * power should be rare so we print an error 1051 * and return here. 1052 */ 1053 goto out; 1054 } 1055 } 1056 /* 1057 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1058 * and instead uses MCI_PWR_ON so apply whatever value is 1059 * configured in the variant data. 1060 */ 1061 pwr |= variant->pwrreg_powerup; 1062 1063 break; 1064 case MMC_POWER_ON: 1065 pwr |= MCI_PWR_ON; 1066 break; 1067 } 1068 1069 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1070 /* 1071 * The ST Micro variant has some additional bits 1072 * indicating signal direction for the signals in 1073 * the SD/MMC bus and feedback-clock usage. 1074 */ 1075 pwr |= host->plat->sigdir; 1076 1077 if (ios->bus_width == MMC_BUS_WIDTH_4) 1078 pwr &= ~MCI_ST_DATA74DIREN; 1079 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1080 pwr &= (~MCI_ST_DATA74DIREN & 1081 ~MCI_ST_DATA31DIREN & 1082 ~MCI_ST_DATA2DIREN); 1083 } 1084 1085 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1086 if (host->hw_designer != AMBA_VENDOR_ST) 1087 pwr |= MCI_ROD; 1088 else { 1089 /* 1090 * The ST Micro variant use the ROD bit for something 1091 * else and only has OD (Open Drain). 1092 */ 1093 pwr |= MCI_OD; 1094 } 1095 } 1096 1097 spin_lock_irqsave(&host->lock, flags); 1098 1099 mmci_set_clkreg(host, ios->clock); 1100 1101 if (host->pwr != pwr) { 1102 host->pwr = pwr; 1103 writel(pwr, host->base + MMCIPOWER); 1104 } 1105 1106 spin_unlock_irqrestore(&host->lock, flags); 1107 1108 out: 1109 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1110 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1111 } 1112 1113 static int mmci_get_ro(struct mmc_host *mmc) 1114 { 1115 struct mmci_host *host = mmc_priv(mmc); 1116 1117 if (host->gpio_wp == -ENOSYS) 1118 return -ENOSYS; 1119 1120 return gpio_get_value_cansleep(host->gpio_wp); 1121 } 1122 1123 static int mmci_get_cd(struct mmc_host *mmc) 1124 { 1125 struct mmci_host *host = mmc_priv(mmc); 1126 struct mmci_platform_data *plat = host->plat; 1127 unsigned int status; 1128 1129 if (host->gpio_cd == -ENOSYS) { 1130 if (!plat->status) 1131 return 1; /* Assume always present */ 1132 1133 status = plat->status(mmc_dev(host->mmc)); 1134 } else 1135 status = !!gpio_get_value_cansleep(host->gpio_cd) 1136 ^ plat->cd_invert; 1137 1138 /* 1139 * Use positive logic throughout - status is zero for no card, 1140 * non-zero for card inserted. 1141 */ 1142 return status; 1143 } 1144 1145 static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1146 { 1147 struct mmci_host *host = dev_id; 1148 1149 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1150 1151 return IRQ_HANDLED; 1152 } 1153 1154 static const struct mmc_host_ops mmci_ops = { 1155 .request = mmci_request, 1156 .pre_req = mmci_pre_request, 1157 .post_req = mmci_post_request, 1158 .set_ios = mmci_set_ios, 1159 .get_ro = mmci_get_ro, 1160 .get_cd = mmci_get_cd, 1161 }; 1162 1163 static int __devinit mmci_probe(struct amba_device *dev, 1164 const struct amba_id *id) 1165 { 1166 struct mmci_platform_data *plat = dev->dev.platform_data; 1167 struct variant_data *variant = id->data; 1168 struct mmci_host *host; 1169 struct mmc_host *mmc; 1170 int ret; 1171 1172 /* must have platform data */ 1173 if (!plat) { 1174 ret = -EINVAL; 1175 goto out; 1176 } 1177 1178 ret = amba_request_regions(dev, DRIVER_NAME); 1179 if (ret) 1180 goto out; 1181 1182 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1183 if (!mmc) { 1184 ret = -ENOMEM; 1185 goto rel_regions; 1186 } 1187 1188 host = mmc_priv(mmc); 1189 host->mmc = mmc; 1190 1191 host->gpio_wp = -ENOSYS; 1192 host->gpio_cd = -ENOSYS; 1193 host->gpio_cd_irq = -1; 1194 1195 host->hw_designer = amba_manf(dev); 1196 host->hw_revision = amba_rev(dev); 1197 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1198 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1199 1200 host->clk = clk_get(&dev->dev, NULL); 1201 if (IS_ERR(host->clk)) { 1202 ret = PTR_ERR(host->clk); 1203 host->clk = NULL; 1204 goto host_free; 1205 } 1206 1207 ret = clk_prepare(host->clk); 1208 if (ret) 1209 goto clk_free; 1210 1211 ret = clk_enable(host->clk); 1212 if (ret) 1213 goto clk_unprep; 1214 1215 host->plat = plat; 1216 host->variant = variant; 1217 host->mclk = clk_get_rate(host->clk); 1218 /* 1219 * According to the spec, mclk is max 100 MHz, 1220 * so we try to adjust the clock down to this, 1221 * (if possible). 1222 */ 1223 if (host->mclk > 100000000) { 1224 ret = clk_set_rate(host->clk, 100000000); 1225 if (ret < 0) 1226 goto clk_disable; 1227 host->mclk = clk_get_rate(host->clk); 1228 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1229 host->mclk); 1230 } 1231 host->phybase = dev->res.start; 1232 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1233 if (!host->base) { 1234 ret = -ENOMEM; 1235 goto clk_disable; 1236 } 1237 1238 mmc->ops = &mmci_ops; 1239 /* 1240 * The ARM and ST versions of the block have slightly different 1241 * clock divider equations which means that the minimum divider 1242 * differs too. 1243 */ 1244 if (variant->st_clkdiv) 1245 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1246 else 1247 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1248 /* 1249 * If the platform data supplies a maximum operating 1250 * frequency, this takes precedence. Else, we fall back 1251 * to using the module parameter, which has a (low) 1252 * default value in case it is not specified. Either 1253 * value must not exceed the clock rate into the block, 1254 * of course. 1255 */ 1256 if (plat->f_max) 1257 mmc->f_max = min(host->mclk, plat->f_max); 1258 else 1259 mmc->f_max = min(host->mclk, fmax); 1260 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1261 1262 #ifdef CONFIG_REGULATOR 1263 /* If we're using the regulator framework, try to fetch a regulator */ 1264 host->vcc = regulator_get(&dev->dev, "vmmc"); 1265 if (IS_ERR(host->vcc)) 1266 host->vcc = NULL; 1267 else { 1268 int mask = mmc_regulator_get_ocrmask(host->vcc); 1269 1270 if (mask < 0) 1271 dev_err(&dev->dev, "error getting OCR mask (%d)\n", 1272 mask); 1273 else { 1274 host->mmc->ocr_avail = (u32) mask; 1275 if (plat->ocr_mask) 1276 dev_warn(&dev->dev, 1277 "Provided ocr_mask/setpower will not be used " 1278 "(using regulator instead)\n"); 1279 } 1280 } 1281 #endif 1282 /* Fall back to platform data if no regulator is found */ 1283 if (host->vcc == NULL) 1284 mmc->ocr_avail = plat->ocr_mask; 1285 mmc->caps = plat->capabilities; 1286 mmc->caps2 = plat->capabilities2; 1287 1288 /* 1289 * We can do SGIO 1290 */ 1291 mmc->max_segs = NR_SG; 1292 1293 /* 1294 * Since only a certain number of bits are valid in the data length 1295 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1296 * single request. 1297 */ 1298 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1299 1300 /* 1301 * Set the maximum segment size. Since we aren't doing DMA 1302 * (yet) we are only limited by the data length register. 1303 */ 1304 mmc->max_seg_size = mmc->max_req_size; 1305 1306 /* 1307 * Block size can be up to 2048 bytes, but must be a power of two. 1308 */ 1309 mmc->max_blk_size = 2048; 1310 1311 /* 1312 * No limit on the number of blocks transferred. 1313 */ 1314 mmc->max_blk_count = mmc->max_req_size; 1315 1316 spin_lock_init(&host->lock); 1317 1318 writel(0, host->base + MMCIMASK0); 1319 writel(0, host->base + MMCIMASK1); 1320 writel(0xfff, host->base + MMCICLEAR); 1321 1322 if (gpio_is_valid(plat->gpio_cd)) { 1323 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1324 if (ret == 0) 1325 ret = gpio_direction_input(plat->gpio_cd); 1326 if (ret == 0) 1327 host->gpio_cd = plat->gpio_cd; 1328 else if (ret != -ENOSYS) 1329 goto err_gpio_cd; 1330 1331 /* 1332 * A gpio pin that will detect cards when inserted and removed 1333 * will most likely want to trigger on the edges if it is 1334 * 0 when ejected and 1 when inserted (or mutatis mutandis 1335 * for the inverted case) so we request triggers on both 1336 * edges. 1337 */ 1338 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1339 mmci_cd_irq, 1340 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1341 DRIVER_NAME " (cd)", host); 1342 if (ret >= 0) 1343 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1344 } 1345 if (gpio_is_valid(plat->gpio_wp)) { 1346 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1347 if (ret == 0) 1348 ret = gpio_direction_input(plat->gpio_wp); 1349 if (ret == 0) 1350 host->gpio_wp = plat->gpio_wp; 1351 else if (ret != -ENOSYS) 1352 goto err_gpio_wp; 1353 } 1354 1355 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1356 && host->gpio_cd_irq < 0) 1357 mmc->caps |= MMC_CAP_NEEDS_POLL; 1358 1359 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1360 if (ret) 1361 goto unmap; 1362 1363 if (dev->irq[1] == NO_IRQ) 1364 host->singleirq = true; 1365 else { 1366 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1367 DRIVER_NAME " (pio)", host); 1368 if (ret) 1369 goto irq0_free; 1370 } 1371 1372 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1373 1374 amba_set_drvdata(dev, mmc); 1375 1376 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1377 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1378 amba_rev(dev), (unsigned long long)dev->res.start, 1379 dev->irq[0], dev->irq[1]); 1380 1381 mmci_dma_setup(host); 1382 1383 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1384 pm_runtime_use_autosuspend(&dev->dev); 1385 pm_runtime_put(&dev->dev); 1386 1387 mmc_add_host(mmc); 1388 1389 return 0; 1390 1391 irq0_free: 1392 free_irq(dev->irq[0], host); 1393 unmap: 1394 if (host->gpio_wp != -ENOSYS) 1395 gpio_free(host->gpio_wp); 1396 err_gpio_wp: 1397 if (host->gpio_cd_irq >= 0) 1398 free_irq(host->gpio_cd_irq, host); 1399 if (host->gpio_cd != -ENOSYS) 1400 gpio_free(host->gpio_cd); 1401 err_gpio_cd: 1402 iounmap(host->base); 1403 clk_disable: 1404 clk_disable(host->clk); 1405 clk_unprep: 1406 clk_unprepare(host->clk); 1407 clk_free: 1408 clk_put(host->clk); 1409 host_free: 1410 mmc_free_host(mmc); 1411 rel_regions: 1412 amba_release_regions(dev); 1413 out: 1414 return ret; 1415 } 1416 1417 static int __devexit mmci_remove(struct amba_device *dev) 1418 { 1419 struct mmc_host *mmc = amba_get_drvdata(dev); 1420 1421 amba_set_drvdata(dev, NULL); 1422 1423 if (mmc) { 1424 struct mmci_host *host = mmc_priv(mmc); 1425 1426 /* 1427 * Undo pm_runtime_put() in probe. We use the _sync 1428 * version here so that we can access the primecell. 1429 */ 1430 pm_runtime_get_sync(&dev->dev); 1431 1432 mmc_remove_host(mmc); 1433 1434 writel(0, host->base + MMCIMASK0); 1435 writel(0, host->base + MMCIMASK1); 1436 1437 writel(0, host->base + MMCICOMMAND); 1438 writel(0, host->base + MMCIDATACTRL); 1439 1440 mmci_dma_release(host); 1441 free_irq(dev->irq[0], host); 1442 if (!host->singleirq) 1443 free_irq(dev->irq[1], host); 1444 1445 if (host->gpio_wp != -ENOSYS) 1446 gpio_free(host->gpio_wp); 1447 if (host->gpio_cd_irq >= 0) 1448 free_irq(host->gpio_cd_irq, host); 1449 if (host->gpio_cd != -ENOSYS) 1450 gpio_free(host->gpio_cd); 1451 1452 iounmap(host->base); 1453 clk_disable(host->clk); 1454 clk_unprepare(host->clk); 1455 clk_put(host->clk); 1456 1457 if (host->vcc) 1458 mmc_regulator_set_ocr(mmc, host->vcc, 0); 1459 regulator_put(host->vcc); 1460 1461 mmc_free_host(mmc); 1462 1463 amba_release_regions(dev); 1464 } 1465 1466 return 0; 1467 } 1468 1469 #ifdef CONFIG_SUSPEND 1470 static int mmci_suspend(struct device *dev) 1471 { 1472 struct amba_device *adev = to_amba_device(dev); 1473 struct mmc_host *mmc = amba_get_drvdata(adev); 1474 int ret = 0; 1475 1476 if (mmc) { 1477 struct mmci_host *host = mmc_priv(mmc); 1478 1479 ret = mmc_suspend_host(mmc); 1480 if (ret == 0) { 1481 pm_runtime_get_sync(dev); 1482 writel(0, host->base + MMCIMASK0); 1483 } 1484 } 1485 1486 return ret; 1487 } 1488 1489 static int mmci_resume(struct device *dev) 1490 { 1491 struct amba_device *adev = to_amba_device(dev); 1492 struct mmc_host *mmc = amba_get_drvdata(adev); 1493 int ret = 0; 1494 1495 if (mmc) { 1496 struct mmci_host *host = mmc_priv(mmc); 1497 1498 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1499 pm_runtime_put(dev); 1500 1501 ret = mmc_resume_host(mmc); 1502 } 1503 1504 return ret; 1505 } 1506 #endif 1507 1508 static const struct dev_pm_ops mmci_dev_pm_ops = { 1509 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1510 }; 1511 1512 static struct amba_id mmci_ids[] = { 1513 { 1514 .id = 0x00041180, 1515 .mask = 0xff0fffff, 1516 .data = &variant_arm, 1517 }, 1518 { 1519 .id = 0x01041180, 1520 .mask = 0xff0fffff, 1521 .data = &variant_arm_extended_fifo, 1522 }, 1523 { 1524 .id = 0x00041181, 1525 .mask = 0x000fffff, 1526 .data = &variant_arm, 1527 }, 1528 /* ST Micro variants */ 1529 { 1530 .id = 0x00180180, 1531 .mask = 0x00ffffff, 1532 .data = &variant_u300, 1533 }, 1534 { 1535 .id = 0x00280180, 1536 .mask = 0x00ffffff, 1537 .data = &variant_u300, 1538 }, 1539 { 1540 .id = 0x00480180, 1541 .mask = 0xf0ffffff, 1542 .data = &variant_ux500, 1543 }, 1544 { 1545 .id = 0x10480180, 1546 .mask = 0xf0ffffff, 1547 .data = &variant_ux500v2, 1548 }, 1549 { 0, 0 }, 1550 }; 1551 1552 MODULE_DEVICE_TABLE(amba, mmci_ids); 1553 1554 static struct amba_driver mmci_driver = { 1555 .drv = { 1556 .name = DRIVER_NAME, 1557 .pm = &mmci_dev_pm_ops, 1558 }, 1559 .probe = mmci_probe, 1560 .remove = __devexit_p(mmci_remove), 1561 .id_table = mmci_ids, 1562 }; 1563 1564 static int __init mmci_init(void) 1565 { 1566 return amba_driver_register(&mmci_driver); 1567 } 1568 1569 static void __exit mmci_exit(void) 1570 { 1571 amba_driver_unregister(&mmci_driver); 1572 } 1573 1574 module_init(mmci_init); 1575 module_exit(mmci_exit); 1576 module_param(fmax, uint, 0444); 1577 1578 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1579 MODULE_LICENSE("GPL"); 1580