1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/amba/mmci.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/types.h> 39 #include <linux/pinctrl/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 #include <asm/sizes.h> 44 45 #include "mmci.h" 46 #include "mmci_qcom_dml.h" 47 48 #define DRIVER_NAME "mmci-pl18x" 49 50 static unsigned int fmax = 515633; 51 52 /** 53 * struct variant_data - MMCI variant-specific quirks 54 * @clkreg: default value for MCICLOCK register 55 * @clkreg_enable: enable value for MMCICLOCK register 56 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 57 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 58 * @datalength_bits: number of bits in the MMCIDATALENGTH register 59 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 60 * is asserted (likewise for RX) 61 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 62 * is asserted (likewise for RX) 63 * @data_cmd_enable: enable value for data commands. 64 * @st_sdio: enable ST specific SDIO logic 65 * @st_clkdiv: true if using a ST-specific clock divider algorithm 66 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 67 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 68 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 69 * register 70 * @datactrl_mask_sdio: SDIO enable mask in datactrl register 71 * @pwrreg_powerup: power up value for MMCIPOWER register 72 * @f_max: maximum clk frequency supported by the controller. 73 * @signal_direction: input/out direction of bus signals can be indicated 74 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 75 * @busy_detect: true if busy detection on dat0 is supported 76 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 77 * @explicit_mclk_control: enable explicit mclk control in driver. 78 * @qcom_fifo: enables qcom specific fifo pio read logic. 79 * @qcom_dml: enables qcom specific dma glue for dma transfers. 80 * @reversed_irq_handling: handle data irq before cmd irq. 81 */ 82 struct variant_data { 83 unsigned int clkreg; 84 unsigned int clkreg_enable; 85 unsigned int clkreg_8bit_bus_enable; 86 unsigned int clkreg_neg_edge_enable; 87 unsigned int datalength_bits; 88 unsigned int fifosize; 89 unsigned int fifohalfsize; 90 unsigned int data_cmd_enable; 91 unsigned int datactrl_mask_ddrmode; 92 unsigned int datactrl_mask_sdio; 93 bool st_sdio; 94 bool st_clkdiv; 95 bool blksz_datactrl16; 96 bool blksz_datactrl4; 97 u32 pwrreg_powerup; 98 u32 f_max; 99 bool signal_direction; 100 bool pwrreg_clkgate; 101 bool busy_detect; 102 bool pwrreg_nopower; 103 bool explicit_mclk_control; 104 bool qcom_fifo; 105 bool qcom_dml; 106 bool reversed_irq_handling; 107 }; 108 109 static struct variant_data variant_arm = { 110 .fifosize = 16 * 4, 111 .fifohalfsize = 8 * 4, 112 .datalength_bits = 16, 113 .pwrreg_powerup = MCI_PWR_UP, 114 .f_max = 100000000, 115 .reversed_irq_handling = true, 116 }; 117 118 static struct variant_data variant_arm_extended_fifo = { 119 .fifosize = 128 * 4, 120 .fifohalfsize = 64 * 4, 121 .datalength_bits = 16, 122 .pwrreg_powerup = MCI_PWR_UP, 123 .f_max = 100000000, 124 }; 125 126 static struct variant_data variant_arm_extended_fifo_hwfc = { 127 .fifosize = 128 * 4, 128 .fifohalfsize = 64 * 4, 129 .clkreg_enable = MCI_ARM_HWFCEN, 130 .datalength_bits = 16, 131 .pwrreg_powerup = MCI_PWR_UP, 132 .f_max = 100000000, 133 }; 134 135 static struct variant_data variant_u300 = { 136 .fifosize = 16 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg_enable = MCI_ST_U300_HWFCEN, 139 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 140 .datalength_bits = 16, 141 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 142 .st_sdio = true, 143 .pwrreg_powerup = MCI_PWR_ON, 144 .f_max = 100000000, 145 .signal_direction = true, 146 .pwrreg_clkgate = true, 147 .pwrreg_nopower = true, 148 }; 149 150 static struct variant_data variant_nomadik = { 151 .fifosize = 16 * 4, 152 .fifohalfsize = 8 * 4, 153 .clkreg = MCI_CLK_ENABLE, 154 .datalength_bits = 24, 155 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 156 .st_sdio = true, 157 .st_clkdiv = true, 158 .pwrreg_powerup = MCI_PWR_ON, 159 .f_max = 100000000, 160 .signal_direction = true, 161 .pwrreg_clkgate = true, 162 .pwrreg_nopower = true, 163 }; 164 165 static struct variant_data variant_ux500 = { 166 .fifosize = 30 * 4, 167 .fifohalfsize = 8 * 4, 168 .clkreg = MCI_CLK_ENABLE, 169 .clkreg_enable = MCI_ST_UX500_HWFCEN, 170 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 171 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 172 .datalength_bits = 24, 173 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 174 .st_sdio = true, 175 .st_clkdiv = true, 176 .pwrreg_powerup = MCI_PWR_ON, 177 .f_max = 100000000, 178 .signal_direction = true, 179 .pwrreg_clkgate = true, 180 .busy_detect = true, 181 .pwrreg_nopower = true, 182 }; 183 184 static struct variant_data variant_ux500v2 = { 185 .fifosize = 30 * 4, 186 .fifohalfsize = 8 * 4, 187 .clkreg = MCI_CLK_ENABLE, 188 .clkreg_enable = MCI_ST_UX500_HWFCEN, 189 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 190 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 191 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, 192 .datalength_bits = 24, 193 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 194 .st_sdio = true, 195 .st_clkdiv = true, 196 .blksz_datactrl16 = true, 197 .pwrreg_powerup = MCI_PWR_ON, 198 .f_max = 100000000, 199 .signal_direction = true, 200 .pwrreg_clkgate = true, 201 .busy_detect = true, 202 .pwrreg_nopower = true, 203 }; 204 205 static struct variant_data variant_qcom = { 206 .fifosize = 16 * 4, 207 .fifohalfsize = 8 * 4, 208 .clkreg = MCI_CLK_ENABLE, 209 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 210 MCI_QCOM_CLK_SELECT_IN_FBCLK, 211 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 212 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 213 .data_cmd_enable = MCI_QCOM_CSPM_DATCMD, 214 .blksz_datactrl4 = true, 215 .datalength_bits = 24, 216 .pwrreg_powerup = MCI_PWR_UP, 217 .f_max = 208000000, 218 .explicit_mclk_control = true, 219 .qcom_fifo = true, 220 .qcom_dml = true, 221 }; 222 223 static int mmci_card_busy(struct mmc_host *mmc) 224 { 225 struct mmci_host *host = mmc_priv(mmc); 226 unsigned long flags; 227 int busy = 0; 228 229 pm_runtime_get_sync(mmc_dev(mmc)); 230 231 spin_lock_irqsave(&host->lock, flags); 232 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 233 busy = 1; 234 spin_unlock_irqrestore(&host->lock, flags); 235 236 pm_runtime_mark_last_busy(mmc_dev(mmc)); 237 pm_runtime_put_autosuspend(mmc_dev(mmc)); 238 239 return busy; 240 } 241 242 /* 243 * Validate mmc prerequisites 244 */ 245 static int mmci_validate_data(struct mmci_host *host, 246 struct mmc_data *data) 247 { 248 if (!data) 249 return 0; 250 251 if (!is_power_of_2(data->blksz)) { 252 dev_err(mmc_dev(host->mmc), 253 "unsupported block size (%d bytes)\n", data->blksz); 254 return -EINVAL; 255 } 256 257 return 0; 258 } 259 260 static void mmci_reg_delay(struct mmci_host *host) 261 { 262 /* 263 * According to the spec, at least three feedback clock cycles 264 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 265 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 266 * Worst delay time during card init is at 100 kHz => 30 us. 267 * Worst delay time when up and running is at 25 MHz => 120 ns. 268 */ 269 if (host->cclk < 25000000) 270 udelay(30); 271 else 272 ndelay(120); 273 } 274 275 /* 276 * This must be called with host->lock held 277 */ 278 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 279 { 280 if (host->clk_reg != clk) { 281 host->clk_reg = clk; 282 writel(clk, host->base + MMCICLOCK); 283 } 284 } 285 286 /* 287 * This must be called with host->lock held 288 */ 289 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 290 { 291 if (host->pwr_reg != pwr) { 292 host->pwr_reg = pwr; 293 writel(pwr, host->base + MMCIPOWER); 294 } 295 } 296 297 /* 298 * This must be called with host->lock held 299 */ 300 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 301 { 302 /* Keep ST Micro busy mode if enabled */ 303 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 304 305 if (host->datactrl_reg != datactrl) { 306 host->datactrl_reg = datactrl; 307 writel(datactrl, host->base + MMCIDATACTRL); 308 } 309 } 310 311 /* 312 * This must be called with host->lock held 313 */ 314 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 315 { 316 struct variant_data *variant = host->variant; 317 u32 clk = variant->clkreg; 318 319 /* Make sure cclk reflects the current calculated clock */ 320 host->cclk = 0; 321 322 if (desired) { 323 if (variant->explicit_mclk_control) { 324 host->cclk = host->mclk; 325 } else if (desired >= host->mclk) { 326 clk = MCI_CLK_BYPASS; 327 if (variant->st_clkdiv) 328 clk |= MCI_ST_UX500_NEG_EDGE; 329 host->cclk = host->mclk; 330 } else if (variant->st_clkdiv) { 331 /* 332 * DB8500 TRM says f = mclk / (clkdiv + 2) 333 * => clkdiv = (mclk / f) - 2 334 * Round the divider up so we don't exceed the max 335 * frequency 336 */ 337 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 338 if (clk >= 256) 339 clk = 255; 340 host->cclk = host->mclk / (clk + 2); 341 } else { 342 /* 343 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 344 * => clkdiv = mclk / (2 * f) - 1 345 */ 346 clk = host->mclk / (2 * desired) - 1; 347 if (clk >= 256) 348 clk = 255; 349 host->cclk = host->mclk / (2 * (clk + 1)); 350 } 351 352 clk |= variant->clkreg_enable; 353 clk |= MCI_CLK_ENABLE; 354 /* This hasn't proven to be worthwhile */ 355 /* clk |= MCI_CLK_PWRSAVE; */ 356 } 357 358 /* Set actual clock for debug */ 359 host->mmc->actual_clock = host->cclk; 360 361 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 362 clk |= MCI_4BIT_BUS; 363 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 364 clk |= variant->clkreg_8bit_bus_enable; 365 366 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 367 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 368 clk |= variant->clkreg_neg_edge_enable; 369 370 mmci_write_clkreg(host, clk); 371 } 372 373 static void 374 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 375 { 376 writel(0, host->base + MMCICOMMAND); 377 378 BUG_ON(host->data); 379 380 host->mrq = NULL; 381 host->cmd = NULL; 382 383 mmc_request_done(host->mmc, mrq); 384 385 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 386 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 387 } 388 389 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 390 { 391 void __iomem *base = host->base; 392 393 if (host->singleirq) { 394 unsigned int mask0 = readl(base + MMCIMASK0); 395 396 mask0 &= ~MCI_IRQ1MASK; 397 mask0 |= mask; 398 399 writel(mask0, base + MMCIMASK0); 400 } 401 402 writel(mask, base + MMCIMASK1); 403 } 404 405 static void mmci_stop_data(struct mmci_host *host) 406 { 407 mmci_write_datactrlreg(host, 0); 408 mmci_set_mask1(host, 0); 409 host->data = NULL; 410 } 411 412 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 413 { 414 unsigned int flags = SG_MITER_ATOMIC; 415 416 if (data->flags & MMC_DATA_READ) 417 flags |= SG_MITER_TO_SG; 418 else 419 flags |= SG_MITER_FROM_SG; 420 421 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 422 } 423 424 /* 425 * All the DMA operation mode stuff goes inside this ifdef. 426 * This assumes that you have a generic DMA device interface, 427 * no custom DMA interfaces are supported. 428 */ 429 #ifdef CONFIG_DMA_ENGINE 430 static void mmci_dma_setup(struct mmci_host *host) 431 { 432 const char *rxname, *txname; 433 dma_cap_mask_t mask; 434 struct variant_data *variant = host->variant; 435 436 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 437 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 438 439 /* initialize pre request cookie */ 440 host->next_data.cookie = 1; 441 442 /* Try to acquire a generic DMA engine slave channel */ 443 dma_cap_zero(mask); 444 dma_cap_set(DMA_SLAVE, mask); 445 446 /* 447 * If only an RX channel is specified, the driver will 448 * attempt to use it bidirectionally, however if it is 449 * is specified but cannot be located, DMA will be disabled. 450 */ 451 if (host->dma_rx_channel && !host->dma_tx_channel) 452 host->dma_tx_channel = host->dma_rx_channel; 453 454 if (host->dma_rx_channel) 455 rxname = dma_chan_name(host->dma_rx_channel); 456 else 457 rxname = "none"; 458 459 if (host->dma_tx_channel) 460 txname = dma_chan_name(host->dma_tx_channel); 461 else 462 txname = "none"; 463 464 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 465 rxname, txname); 466 467 /* 468 * Limit the maximum segment size in any SG entry according to 469 * the parameters of the DMA engine device. 470 */ 471 if (host->dma_tx_channel) { 472 struct device *dev = host->dma_tx_channel->device->dev; 473 unsigned int max_seg_size = dma_get_max_seg_size(dev); 474 475 if (max_seg_size < host->mmc->max_seg_size) 476 host->mmc->max_seg_size = max_seg_size; 477 } 478 if (host->dma_rx_channel) { 479 struct device *dev = host->dma_rx_channel->device->dev; 480 unsigned int max_seg_size = dma_get_max_seg_size(dev); 481 482 if (max_seg_size < host->mmc->max_seg_size) 483 host->mmc->max_seg_size = max_seg_size; 484 } 485 486 if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) 487 if (dml_hw_init(host, host->mmc->parent->of_node)) 488 variant->qcom_dml = false; 489 } 490 491 /* 492 * This is used in or so inline it 493 * so it can be discarded. 494 */ 495 static inline void mmci_dma_release(struct mmci_host *host) 496 { 497 if (host->dma_rx_channel) 498 dma_release_channel(host->dma_rx_channel); 499 if (host->dma_tx_channel) 500 dma_release_channel(host->dma_tx_channel); 501 host->dma_rx_channel = host->dma_tx_channel = NULL; 502 } 503 504 static void mmci_dma_data_error(struct mmci_host *host) 505 { 506 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 507 dmaengine_terminate_all(host->dma_current); 508 host->dma_current = NULL; 509 host->dma_desc_current = NULL; 510 host->data->host_cookie = 0; 511 } 512 513 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 514 { 515 struct dma_chan *chan; 516 enum dma_data_direction dir; 517 518 if (data->flags & MMC_DATA_READ) { 519 dir = DMA_FROM_DEVICE; 520 chan = host->dma_rx_channel; 521 } else { 522 dir = DMA_TO_DEVICE; 523 chan = host->dma_tx_channel; 524 } 525 526 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 527 } 528 529 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 530 { 531 u32 status; 532 int i; 533 534 /* Wait up to 1ms for the DMA to complete */ 535 for (i = 0; ; i++) { 536 status = readl(host->base + MMCISTATUS); 537 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 538 break; 539 udelay(10); 540 } 541 542 /* 543 * Check to see whether we still have some data left in the FIFO - 544 * this catches DMA controllers which are unable to monitor the 545 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 546 * contiguous buffers. On TX, we'll get a FIFO underrun error. 547 */ 548 if (status & MCI_RXDATAAVLBLMASK) { 549 mmci_dma_data_error(host); 550 if (!data->error) 551 data->error = -EIO; 552 } 553 554 if (!data->host_cookie) 555 mmci_dma_unmap(host, data); 556 557 /* 558 * Use of DMA with scatter-gather is impossible. 559 * Give up with DMA and switch back to PIO mode. 560 */ 561 if (status & MCI_RXDATAAVLBLMASK) { 562 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 563 mmci_dma_release(host); 564 } 565 566 host->dma_current = NULL; 567 host->dma_desc_current = NULL; 568 } 569 570 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 571 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 572 struct dma_chan **dma_chan, 573 struct dma_async_tx_descriptor **dma_desc) 574 { 575 struct variant_data *variant = host->variant; 576 struct dma_slave_config conf = { 577 .src_addr = host->phybase + MMCIFIFO, 578 .dst_addr = host->phybase + MMCIFIFO, 579 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 580 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 581 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 582 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 583 .device_fc = false, 584 }; 585 struct dma_chan *chan; 586 struct dma_device *device; 587 struct dma_async_tx_descriptor *desc; 588 enum dma_data_direction buffer_dirn; 589 int nr_sg; 590 unsigned long flags = DMA_CTRL_ACK; 591 592 if (data->flags & MMC_DATA_READ) { 593 conf.direction = DMA_DEV_TO_MEM; 594 buffer_dirn = DMA_FROM_DEVICE; 595 chan = host->dma_rx_channel; 596 } else { 597 conf.direction = DMA_MEM_TO_DEV; 598 buffer_dirn = DMA_TO_DEVICE; 599 chan = host->dma_tx_channel; 600 } 601 602 /* If there's no DMA channel, fall back to PIO */ 603 if (!chan) 604 return -EINVAL; 605 606 /* If less than or equal to the fifo size, don't bother with DMA */ 607 if (data->blksz * data->blocks <= variant->fifosize) 608 return -EINVAL; 609 610 device = chan->device; 611 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 612 if (nr_sg == 0) 613 return -EINVAL; 614 615 if (host->variant->qcom_dml) 616 flags |= DMA_PREP_INTERRUPT; 617 618 dmaengine_slave_config(chan, &conf); 619 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 620 conf.direction, flags); 621 if (!desc) 622 goto unmap_exit; 623 624 *dma_chan = chan; 625 *dma_desc = desc; 626 627 return 0; 628 629 unmap_exit: 630 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 631 return -ENOMEM; 632 } 633 634 static inline int mmci_dma_prep_data(struct mmci_host *host, 635 struct mmc_data *data) 636 { 637 /* Check if next job is already prepared. */ 638 if (host->dma_current && host->dma_desc_current) 639 return 0; 640 641 /* No job were prepared thus do it now. */ 642 return __mmci_dma_prep_data(host, data, &host->dma_current, 643 &host->dma_desc_current); 644 } 645 646 static inline int mmci_dma_prep_next(struct mmci_host *host, 647 struct mmc_data *data) 648 { 649 struct mmci_host_next *nd = &host->next_data; 650 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 651 } 652 653 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 654 { 655 int ret; 656 struct mmc_data *data = host->data; 657 658 ret = mmci_dma_prep_data(host, host->data); 659 if (ret) 660 return ret; 661 662 /* Okay, go for it. */ 663 dev_vdbg(mmc_dev(host->mmc), 664 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 665 data->sg_len, data->blksz, data->blocks, data->flags); 666 dmaengine_submit(host->dma_desc_current); 667 dma_async_issue_pending(host->dma_current); 668 669 if (host->variant->qcom_dml) 670 dml_start_xfer(host, data); 671 672 datactrl |= MCI_DPSM_DMAENABLE; 673 674 /* Trigger the DMA transfer */ 675 mmci_write_datactrlreg(host, datactrl); 676 677 /* 678 * Let the MMCI say when the data is ended and it's time 679 * to fire next DMA request. When that happens, MMCI will 680 * call mmci_data_end() 681 */ 682 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 683 host->base + MMCIMASK0); 684 return 0; 685 } 686 687 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 688 { 689 struct mmci_host_next *next = &host->next_data; 690 691 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 692 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 693 694 host->dma_desc_current = next->dma_desc; 695 host->dma_current = next->dma_chan; 696 next->dma_desc = NULL; 697 next->dma_chan = NULL; 698 } 699 700 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 701 bool is_first_req) 702 { 703 struct mmci_host *host = mmc_priv(mmc); 704 struct mmc_data *data = mrq->data; 705 struct mmci_host_next *nd = &host->next_data; 706 707 if (!data) 708 return; 709 710 BUG_ON(data->host_cookie); 711 712 if (mmci_validate_data(host, data)) 713 return; 714 715 if (!mmci_dma_prep_next(host, data)) 716 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 717 } 718 719 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 720 int err) 721 { 722 struct mmci_host *host = mmc_priv(mmc); 723 struct mmc_data *data = mrq->data; 724 725 if (!data || !data->host_cookie) 726 return; 727 728 mmci_dma_unmap(host, data); 729 730 if (err) { 731 struct mmci_host_next *next = &host->next_data; 732 struct dma_chan *chan; 733 if (data->flags & MMC_DATA_READ) 734 chan = host->dma_rx_channel; 735 else 736 chan = host->dma_tx_channel; 737 dmaengine_terminate_all(chan); 738 739 next->dma_desc = NULL; 740 next->dma_chan = NULL; 741 } 742 } 743 744 #else 745 /* Blank functions if the DMA engine is not available */ 746 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 747 { 748 } 749 static inline void mmci_dma_setup(struct mmci_host *host) 750 { 751 } 752 753 static inline void mmci_dma_release(struct mmci_host *host) 754 { 755 } 756 757 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 758 { 759 } 760 761 static inline void mmci_dma_finalize(struct mmci_host *host, 762 struct mmc_data *data) 763 { 764 } 765 766 static inline void mmci_dma_data_error(struct mmci_host *host) 767 { 768 } 769 770 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 771 { 772 return -ENOSYS; 773 } 774 775 #define mmci_pre_request NULL 776 #define mmci_post_request NULL 777 778 #endif 779 780 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 781 { 782 struct variant_data *variant = host->variant; 783 unsigned int datactrl, timeout, irqmask; 784 unsigned long long clks; 785 void __iomem *base; 786 int blksz_bits; 787 788 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 789 data->blksz, data->blocks, data->flags); 790 791 host->data = data; 792 host->size = data->blksz * data->blocks; 793 data->bytes_xfered = 0; 794 795 clks = (unsigned long long)data->timeout_ns * host->cclk; 796 do_div(clks, NSEC_PER_SEC); 797 798 timeout = data->timeout_clks + (unsigned int)clks; 799 800 base = host->base; 801 writel(timeout, base + MMCIDATATIMER); 802 writel(host->size, base + MMCIDATALENGTH); 803 804 blksz_bits = ffs(data->blksz) - 1; 805 BUG_ON(1 << blksz_bits != data->blksz); 806 807 if (variant->blksz_datactrl16) 808 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 809 else if (variant->blksz_datactrl4) 810 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 811 else 812 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 813 814 if (data->flags & MMC_DATA_READ) 815 datactrl |= MCI_DPSM_DIRECTION; 816 817 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 818 u32 clk; 819 820 datactrl |= variant->datactrl_mask_sdio; 821 822 /* 823 * The ST Micro variant for SDIO small write transfers 824 * needs to have clock H/W flow control disabled, 825 * otherwise the transfer will not start. The threshold 826 * depends on the rate of MCLK. 827 */ 828 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 829 (host->size < 8 || 830 (host->size <= 8 && host->mclk > 50000000))) 831 clk = host->clk_reg & ~variant->clkreg_enable; 832 else 833 clk = host->clk_reg | variant->clkreg_enable; 834 835 mmci_write_clkreg(host, clk); 836 } 837 838 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 839 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 840 datactrl |= variant->datactrl_mask_ddrmode; 841 842 /* 843 * Attempt to use DMA operation mode, if this 844 * should fail, fall back to PIO mode 845 */ 846 if (!mmci_dma_start_data(host, datactrl)) 847 return; 848 849 /* IRQ mode, map the SG list for CPU reading/writing */ 850 mmci_init_sg(host, data); 851 852 if (data->flags & MMC_DATA_READ) { 853 irqmask = MCI_RXFIFOHALFFULLMASK; 854 855 /* 856 * If we have less than the fifo 'half-full' threshold to 857 * transfer, trigger a PIO interrupt as soon as any data 858 * is available. 859 */ 860 if (host->size < variant->fifohalfsize) 861 irqmask |= MCI_RXDATAAVLBLMASK; 862 } else { 863 /* 864 * We don't actually need to include "FIFO empty" here 865 * since its implicit in "FIFO half empty". 866 */ 867 irqmask = MCI_TXFIFOHALFEMPTYMASK; 868 } 869 870 mmci_write_datactrlreg(host, datactrl); 871 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 872 mmci_set_mask1(host, irqmask); 873 } 874 875 static void 876 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 877 { 878 void __iomem *base = host->base; 879 880 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 881 cmd->opcode, cmd->arg, cmd->flags); 882 883 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 884 writel(0, base + MMCICOMMAND); 885 mmci_reg_delay(host); 886 } 887 888 c |= cmd->opcode | MCI_CPSM_ENABLE; 889 if (cmd->flags & MMC_RSP_PRESENT) { 890 if (cmd->flags & MMC_RSP_136) 891 c |= MCI_CPSM_LONGRSP; 892 c |= MCI_CPSM_RESPONSE; 893 } 894 if (/*interrupt*/0) 895 c |= MCI_CPSM_INTERRUPT; 896 897 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 898 c |= host->variant->data_cmd_enable; 899 900 host->cmd = cmd; 901 902 writel(cmd->arg, base + MMCIARGUMENT); 903 writel(c, base + MMCICOMMAND); 904 } 905 906 static void 907 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 908 unsigned int status) 909 { 910 /* Make sure we have data to handle */ 911 if (!data) 912 return; 913 914 /* First check for errors */ 915 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 916 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 917 u32 remain, success; 918 919 /* Terminate the DMA transfer */ 920 if (dma_inprogress(host)) { 921 mmci_dma_data_error(host); 922 mmci_dma_unmap(host, data); 923 } 924 925 /* 926 * Calculate how far we are into the transfer. Note that 927 * the data counter gives the number of bytes transferred 928 * on the MMC bus, not on the host side. On reads, this 929 * can be as much as a FIFO-worth of data ahead. This 930 * matters for FIFO overruns only. 931 */ 932 remain = readl(host->base + MMCIDATACNT); 933 success = data->blksz * data->blocks - remain; 934 935 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 936 status, success); 937 if (status & MCI_DATACRCFAIL) { 938 /* Last block was not successful */ 939 success -= 1; 940 data->error = -EILSEQ; 941 } else if (status & MCI_DATATIMEOUT) { 942 data->error = -ETIMEDOUT; 943 } else if (status & MCI_STARTBITERR) { 944 data->error = -ECOMM; 945 } else if (status & MCI_TXUNDERRUN) { 946 data->error = -EIO; 947 } else if (status & MCI_RXOVERRUN) { 948 if (success > host->variant->fifosize) 949 success -= host->variant->fifosize; 950 else 951 success = 0; 952 data->error = -EIO; 953 } 954 data->bytes_xfered = round_down(success, data->blksz); 955 } 956 957 if (status & MCI_DATABLOCKEND) 958 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 959 960 if (status & MCI_DATAEND || data->error) { 961 if (dma_inprogress(host)) 962 mmci_dma_finalize(host, data); 963 mmci_stop_data(host); 964 965 if (!data->error) 966 /* The error clause is handled above, success! */ 967 data->bytes_xfered = data->blksz * data->blocks; 968 969 if (!data->stop || host->mrq->sbc) { 970 mmci_request_end(host, data->mrq); 971 } else { 972 mmci_start_command(host, data->stop, 0); 973 } 974 } 975 } 976 977 static void 978 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 979 unsigned int status) 980 { 981 void __iomem *base = host->base; 982 bool sbc, busy_resp; 983 984 if (!cmd) 985 return; 986 987 sbc = (cmd == host->mrq->sbc); 988 busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY); 989 990 if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 991 MCI_CMDSENT|MCI_CMDRESPEND))) 992 return; 993 994 /* Check if we need to wait for busy completion. */ 995 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 996 return; 997 998 /* Enable busy completion if needed and supported. */ 999 if (!host->busy_status && busy_resp && 1000 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1001 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 1002 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 1003 base + MMCIMASK0); 1004 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 1005 return; 1006 } 1007 1008 /* At busy completion, mask the IRQ and complete the request. */ 1009 if (host->busy_status) { 1010 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 1011 base + MMCIMASK0); 1012 host->busy_status = 0; 1013 } 1014 1015 host->cmd = NULL; 1016 1017 if (status & MCI_CMDTIMEOUT) { 1018 cmd->error = -ETIMEDOUT; 1019 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1020 cmd->error = -EILSEQ; 1021 } else { 1022 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1023 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1024 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1025 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1026 } 1027 1028 if ((!sbc && !cmd->data) || cmd->error) { 1029 if (host->data) { 1030 /* Terminate the DMA transfer */ 1031 if (dma_inprogress(host)) { 1032 mmci_dma_data_error(host); 1033 mmci_dma_unmap(host, host->data); 1034 } 1035 mmci_stop_data(host); 1036 } 1037 mmci_request_end(host, host->mrq); 1038 } else if (sbc) { 1039 mmci_start_command(host, host->mrq->cmd, 0); 1040 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 1041 mmci_start_data(host, cmd->data); 1042 } 1043 } 1044 1045 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1046 { 1047 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1048 } 1049 1050 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1051 { 1052 /* 1053 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1054 * from the fifo range should be used 1055 */ 1056 if (status & MCI_RXFIFOHALFFULL) 1057 return host->variant->fifohalfsize; 1058 else if (status & MCI_RXDATAAVLBL) 1059 return 4; 1060 1061 return 0; 1062 } 1063 1064 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1065 { 1066 void __iomem *base = host->base; 1067 char *ptr = buffer; 1068 u32 status = readl(host->base + MMCISTATUS); 1069 int host_remain = host->size; 1070 1071 do { 1072 int count = host->get_rx_fifocnt(host, status, host_remain); 1073 1074 if (count > remain) 1075 count = remain; 1076 1077 if (count <= 0) 1078 break; 1079 1080 /* 1081 * SDIO especially may want to send something that is 1082 * not divisible by 4 (as opposed to card sectors 1083 * etc). Therefore make sure to always read the last bytes 1084 * while only doing full 32-bit reads towards the FIFO. 1085 */ 1086 if (unlikely(count & 0x3)) { 1087 if (count < 4) { 1088 unsigned char buf[4]; 1089 ioread32_rep(base + MMCIFIFO, buf, 1); 1090 memcpy(ptr, buf, count); 1091 } else { 1092 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1093 count &= ~0x3; 1094 } 1095 } else { 1096 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1097 } 1098 1099 ptr += count; 1100 remain -= count; 1101 host_remain -= count; 1102 1103 if (remain == 0) 1104 break; 1105 1106 status = readl(base + MMCISTATUS); 1107 } while (status & MCI_RXDATAAVLBL); 1108 1109 return ptr - buffer; 1110 } 1111 1112 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1113 { 1114 struct variant_data *variant = host->variant; 1115 void __iomem *base = host->base; 1116 char *ptr = buffer; 1117 1118 do { 1119 unsigned int count, maxcnt; 1120 1121 maxcnt = status & MCI_TXFIFOEMPTY ? 1122 variant->fifosize : variant->fifohalfsize; 1123 count = min(remain, maxcnt); 1124 1125 /* 1126 * SDIO especially may want to send something that is 1127 * not divisible by 4 (as opposed to card sectors 1128 * etc), and the FIFO only accept full 32-bit writes. 1129 * So compensate by adding +3 on the count, a single 1130 * byte become a 32bit write, 7 bytes will be two 1131 * 32bit writes etc. 1132 */ 1133 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1134 1135 ptr += count; 1136 remain -= count; 1137 1138 if (remain == 0) 1139 break; 1140 1141 status = readl(base + MMCISTATUS); 1142 } while (status & MCI_TXFIFOHALFEMPTY); 1143 1144 return ptr - buffer; 1145 } 1146 1147 /* 1148 * PIO data transfer IRQ handler. 1149 */ 1150 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1151 { 1152 struct mmci_host *host = dev_id; 1153 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1154 struct variant_data *variant = host->variant; 1155 void __iomem *base = host->base; 1156 unsigned long flags; 1157 u32 status; 1158 1159 status = readl(base + MMCISTATUS); 1160 1161 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1162 1163 local_irq_save(flags); 1164 1165 do { 1166 unsigned int remain, len; 1167 char *buffer; 1168 1169 /* 1170 * For write, we only need to test the half-empty flag 1171 * here - if the FIFO is completely empty, then by 1172 * definition it is more than half empty. 1173 * 1174 * For read, check for data available. 1175 */ 1176 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1177 break; 1178 1179 if (!sg_miter_next(sg_miter)) 1180 break; 1181 1182 buffer = sg_miter->addr; 1183 remain = sg_miter->length; 1184 1185 len = 0; 1186 if (status & MCI_RXACTIVE) 1187 len = mmci_pio_read(host, buffer, remain); 1188 if (status & MCI_TXACTIVE) 1189 len = mmci_pio_write(host, buffer, remain, status); 1190 1191 sg_miter->consumed = len; 1192 1193 host->size -= len; 1194 remain -= len; 1195 1196 if (remain) 1197 break; 1198 1199 status = readl(base + MMCISTATUS); 1200 } while (1); 1201 1202 sg_miter_stop(sg_miter); 1203 1204 local_irq_restore(flags); 1205 1206 /* 1207 * If we have less than the fifo 'half-full' threshold to transfer, 1208 * trigger a PIO interrupt as soon as any data is available. 1209 */ 1210 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1211 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1212 1213 /* 1214 * If we run out of data, disable the data IRQs; this 1215 * prevents a race where the FIFO becomes empty before 1216 * the chip itself has disabled the data path, and 1217 * stops us racing with our data end IRQ. 1218 */ 1219 if (host->size == 0) { 1220 mmci_set_mask1(host, 0); 1221 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1222 } 1223 1224 return IRQ_HANDLED; 1225 } 1226 1227 /* 1228 * Handle completion of command and data transfers. 1229 */ 1230 static irqreturn_t mmci_irq(int irq, void *dev_id) 1231 { 1232 struct mmci_host *host = dev_id; 1233 u32 status; 1234 int ret = 0; 1235 1236 spin_lock(&host->lock); 1237 1238 do { 1239 status = readl(host->base + MMCISTATUS); 1240 1241 if (host->singleirq) { 1242 if (status & readl(host->base + MMCIMASK1)) 1243 mmci_pio_irq(irq, dev_id); 1244 1245 status &= ~MCI_IRQ1MASK; 1246 } 1247 1248 /* 1249 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1250 * enabled) since the HW seems to be triggering the IRQ on both 1251 * edges while monitoring DAT0 for busy completion. 1252 */ 1253 status &= readl(host->base + MMCIMASK0); 1254 writel(status, host->base + MMCICLEAR); 1255 1256 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1257 1258 if (host->variant->reversed_irq_handling) { 1259 mmci_data_irq(host, host->data, status); 1260 mmci_cmd_irq(host, host->cmd, status); 1261 } else { 1262 mmci_cmd_irq(host, host->cmd, status); 1263 mmci_data_irq(host, host->data, status); 1264 } 1265 1266 /* Don't poll for busy completion in irq context. */ 1267 if (host->busy_status) 1268 status &= ~MCI_ST_CARDBUSY; 1269 1270 ret = 1; 1271 } while (status); 1272 1273 spin_unlock(&host->lock); 1274 1275 return IRQ_RETVAL(ret); 1276 } 1277 1278 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1279 { 1280 struct mmci_host *host = mmc_priv(mmc); 1281 unsigned long flags; 1282 1283 WARN_ON(host->mrq != NULL); 1284 1285 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1286 if (mrq->cmd->error) { 1287 mmc_request_done(mmc, mrq); 1288 return; 1289 } 1290 1291 pm_runtime_get_sync(mmc_dev(mmc)); 1292 1293 spin_lock_irqsave(&host->lock, flags); 1294 1295 host->mrq = mrq; 1296 1297 if (mrq->data) 1298 mmci_get_next_data(host, mrq->data); 1299 1300 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1301 mmci_start_data(host, mrq->data); 1302 1303 if (mrq->sbc) 1304 mmci_start_command(host, mrq->sbc, 0); 1305 else 1306 mmci_start_command(host, mrq->cmd, 0); 1307 1308 spin_unlock_irqrestore(&host->lock, flags); 1309 } 1310 1311 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1312 { 1313 struct mmci_host *host = mmc_priv(mmc); 1314 struct variant_data *variant = host->variant; 1315 u32 pwr = 0; 1316 unsigned long flags; 1317 int ret; 1318 1319 pm_runtime_get_sync(mmc_dev(mmc)); 1320 1321 if (host->plat->ios_handler && 1322 host->plat->ios_handler(mmc_dev(mmc), ios)) 1323 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1324 1325 switch (ios->power_mode) { 1326 case MMC_POWER_OFF: 1327 if (!IS_ERR(mmc->supply.vmmc)) 1328 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1329 1330 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1331 regulator_disable(mmc->supply.vqmmc); 1332 host->vqmmc_enabled = false; 1333 } 1334 1335 break; 1336 case MMC_POWER_UP: 1337 if (!IS_ERR(mmc->supply.vmmc)) 1338 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1339 1340 /* 1341 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1342 * and instead uses MCI_PWR_ON so apply whatever value is 1343 * configured in the variant data. 1344 */ 1345 pwr |= variant->pwrreg_powerup; 1346 1347 break; 1348 case MMC_POWER_ON: 1349 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1350 ret = regulator_enable(mmc->supply.vqmmc); 1351 if (ret < 0) 1352 dev_err(mmc_dev(mmc), 1353 "failed to enable vqmmc regulator\n"); 1354 else 1355 host->vqmmc_enabled = true; 1356 } 1357 1358 pwr |= MCI_PWR_ON; 1359 break; 1360 } 1361 1362 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1363 /* 1364 * The ST Micro variant has some additional bits 1365 * indicating signal direction for the signals in 1366 * the SD/MMC bus and feedback-clock usage. 1367 */ 1368 pwr |= host->pwr_reg_add; 1369 1370 if (ios->bus_width == MMC_BUS_WIDTH_4) 1371 pwr &= ~MCI_ST_DATA74DIREN; 1372 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1373 pwr &= (~MCI_ST_DATA74DIREN & 1374 ~MCI_ST_DATA31DIREN & 1375 ~MCI_ST_DATA2DIREN); 1376 } 1377 1378 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1379 if (host->hw_designer != AMBA_VENDOR_ST) 1380 pwr |= MCI_ROD; 1381 else { 1382 /* 1383 * The ST Micro variant use the ROD bit for something 1384 * else and only has OD (Open Drain). 1385 */ 1386 pwr |= MCI_OD; 1387 } 1388 } 1389 1390 /* 1391 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1392 * gating the clock, the MCI_PWR_ON bit is cleared. 1393 */ 1394 if (!ios->clock && variant->pwrreg_clkgate) 1395 pwr &= ~MCI_PWR_ON; 1396 1397 if (host->variant->explicit_mclk_control && 1398 ios->clock != host->clock_cache) { 1399 ret = clk_set_rate(host->clk, ios->clock); 1400 if (ret < 0) 1401 dev_err(mmc_dev(host->mmc), 1402 "Error setting clock rate (%d)\n", ret); 1403 else 1404 host->mclk = clk_get_rate(host->clk); 1405 } 1406 host->clock_cache = ios->clock; 1407 1408 spin_lock_irqsave(&host->lock, flags); 1409 1410 mmci_set_clkreg(host, ios->clock); 1411 mmci_write_pwrreg(host, pwr); 1412 mmci_reg_delay(host); 1413 1414 spin_unlock_irqrestore(&host->lock, flags); 1415 1416 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1417 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1418 } 1419 1420 static int mmci_get_cd(struct mmc_host *mmc) 1421 { 1422 struct mmci_host *host = mmc_priv(mmc); 1423 struct mmci_platform_data *plat = host->plat; 1424 unsigned int status = mmc_gpio_get_cd(mmc); 1425 1426 if (status == -ENOSYS) { 1427 if (!plat->status) 1428 return 1; /* Assume always present */ 1429 1430 status = plat->status(mmc_dev(host->mmc)); 1431 } 1432 return status; 1433 } 1434 1435 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1436 { 1437 int ret = 0; 1438 1439 if (!IS_ERR(mmc->supply.vqmmc)) { 1440 1441 pm_runtime_get_sync(mmc_dev(mmc)); 1442 1443 switch (ios->signal_voltage) { 1444 case MMC_SIGNAL_VOLTAGE_330: 1445 ret = regulator_set_voltage(mmc->supply.vqmmc, 1446 2700000, 3600000); 1447 break; 1448 case MMC_SIGNAL_VOLTAGE_180: 1449 ret = regulator_set_voltage(mmc->supply.vqmmc, 1450 1700000, 1950000); 1451 break; 1452 case MMC_SIGNAL_VOLTAGE_120: 1453 ret = regulator_set_voltage(mmc->supply.vqmmc, 1454 1100000, 1300000); 1455 break; 1456 } 1457 1458 if (ret) 1459 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1460 1461 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1462 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1463 } 1464 1465 return ret; 1466 } 1467 1468 static struct mmc_host_ops mmci_ops = { 1469 .request = mmci_request, 1470 .pre_req = mmci_pre_request, 1471 .post_req = mmci_post_request, 1472 .set_ios = mmci_set_ios, 1473 .get_ro = mmc_gpio_get_ro, 1474 .get_cd = mmci_get_cd, 1475 .start_signal_voltage_switch = mmci_sig_volt_switch, 1476 }; 1477 1478 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1479 { 1480 struct mmci_host *host = mmc_priv(mmc); 1481 int ret = mmc_of_parse(mmc); 1482 1483 if (ret) 1484 return ret; 1485 1486 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1487 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1488 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1489 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1490 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1491 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1492 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1493 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1494 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1495 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1496 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1497 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1498 1499 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1500 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1501 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1502 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1503 1504 return 0; 1505 } 1506 1507 static int mmci_probe(struct amba_device *dev, 1508 const struct amba_id *id) 1509 { 1510 struct mmci_platform_data *plat = dev->dev.platform_data; 1511 struct device_node *np = dev->dev.of_node; 1512 struct variant_data *variant = id->data; 1513 struct mmci_host *host; 1514 struct mmc_host *mmc; 1515 int ret; 1516 1517 /* Must have platform data or Device Tree. */ 1518 if (!plat && !np) { 1519 dev_err(&dev->dev, "No plat data or DT found\n"); 1520 return -EINVAL; 1521 } 1522 1523 if (!plat) { 1524 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1525 if (!plat) 1526 return -ENOMEM; 1527 } 1528 1529 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1530 if (!mmc) 1531 return -ENOMEM; 1532 1533 ret = mmci_of_parse(np, mmc); 1534 if (ret) 1535 goto host_free; 1536 1537 host = mmc_priv(mmc); 1538 host->mmc = mmc; 1539 1540 host->hw_designer = amba_manf(dev); 1541 host->hw_revision = amba_rev(dev); 1542 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1543 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1544 1545 host->clk = devm_clk_get(&dev->dev, NULL); 1546 if (IS_ERR(host->clk)) { 1547 ret = PTR_ERR(host->clk); 1548 goto host_free; 1549 } 1550 1551 ret = clk_prepare_enable(host->clk); 1552 if (ret) 1553 goto host_free; 1554 1555 if (variant->qcom_fifo) 1556 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1557 else 1558 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1559 1560 host->plat = plat; 1561 host->variant = variant; 1562 host->mclk = clk_get_rate(host->clk); 1563 /* 1564 * According to the spec, mclk is max 100 MHz, 1565 * so we try to adjust the clock down to this, 1566 * (if possible). 1567 */ 1568 if (host->mclk > variant->f_max) { 1569 ret = clk_set_rate(host->clk, variant->f_max); 1570 if (ret < 0) 1571 goto clk_disable; 1572 host->mclk = clk_get_rate(host->clk); 1573 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1574 host->mclk); 1575 } 1576 1577 host->phybase = dev->res.start; 1578 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1579 if (IS_ERR(host->base)) { 1580 ret = PTR_ERR(host->base); 1581 goto clk_disable; 1582 } 1583 1584 /* 1585 * The ARM and ST versions of the block have slightly different 1586 * clock divider equations which means that the minimum divider 1587 * differs too. 1588 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1589 */ 1590 if (variant->st_clkdiv) 1591 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1592 else if (variant->explicit_mclk_control) 1593 mmc->f_min = clk_round_rate(host->clk, 100000); 1594 else 1595 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1596 /* 1597 * If no maximum operating frequency is supplied, fall back to use 1598 * the module parameter, which has a (low) default value in case it 1599 * is not specified. Either value must not exceed the clock rate into 1600 * the block, of course. 1601 */ 1602 if (mmc->f_max) 1603 mmc->f_max = variant->explicit_mclk_control ? 1604 min(variant->f_max, mmc->f_max) : 1605 min(host->mclk, mmc->f_max); 1606 else 1607 mmc->f_max = variant->explicit_mclk_control ? 1608 fmax : min(host->mclk, fmax); 1609 1610 1611 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1612 1613 /* Get regulators and the supported OCR mask */ 1614 mmc_regulator_get_supply(mmc); 1615 if (!mmc->ocr_avail) 1616 mmc->ocr_avail = plat->ocr_mask; 1617 else if (plat->ocr_mask) 1618 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1619 1620 /* DT takes precedence over platform data. */ 1621 if (!np) { 1622 if (!plat->cd_invert) 1623 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1624 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1625 } 1626 1627 /* We support these capabilities. */ 1628 mmc->caps |= MMC_CAP_CMD23; 1629 1630 if (variant->busy_detect) { 1631 mmci_ops.card_busy = mmci_card_busy; 1632 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1633 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1634 mmc->max_busy_timeout = 0; 1635 } 1636 1637 mmc->ops = &mmci_ops; 1638 1639 /* We support these PM capabilities. */ 1640 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1641 1642 /* 1643 * We can do SGIO 1644 */ 1645 mmc->max_segs = NR_SG; 1646 1647 /* 1648 * Since only a certain number of bits are valid in the data length 1649 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1650 * single request. 1651 */ 1652 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1653 1654 /* 1655 * Set the maximum segment size. Since we aren't doing DMA 1656 * (yet) we are only limited by the data length register. 1657 */ 1658 mmc->max_seg_size = mmc->max_req_size; 1659 1660 /* 1661 * Block size can be up to 2048 bytes, but must be a power of two. 1662 */ 1663 mmc->max_blk_size = 1 << 11; 1664 1665 /* 1666 * Limit the number of blocks transferred so that we don't overflow 1667 * the maximum request size. 1668 */ 1669 mmc->max_blk_count = mmc->max_req_size >> 11; 1670 1671 spin_lock_init(&host->lock); 1672 1673 writel(0, host->base + MMCIMASK0); 1674 writel(0, host->base + MMCIMASK1); 1675 writel(0xfff, host->base + MMCICLEAR); 1676 1677 /* 1678 * If: 1679 * - not using DT but using a descriptor table, or 1680 * - using a table of descriptors ALONGSIDE DT, or 1681 * look up these descriptors named "cd" and "wp" right here, fail 1682 * silently of these do not exist and proceed to try platform data 1683 */ 1684 if (!np) { 1685 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1686 if (ret < 0) { 1687 if (ret == -EPROBE_DEFER) 1688 goto clk_disable; 1689 else if (gpio_is_valid(plat->gpio_cd)) { 1690 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1691 if (ret) 1692 goto clk_disable; 1693 } 1694 } 1695 1696 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1697 if (ret < 0) { 1698 if (ret == -EPROBE_DEFER) 1699 goto clk_disable; 1700 else if (gpio_is_valid(plat->gpio_wp)) { 1701 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1702 if (ret) 1703 goto clk_disable; 1704 } 1705 } 1706 } 1707 1708 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1709 DRIVER_NAME " (cmd)", host); 1710 if (ret) 1711 goto clk_disable; 1712 1713 if (!dev->irq[1]) 1714 host->singleirq = true; 1715 else { 1716 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1717 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1718 if (ret) 1719 goto clk_disable; 1720 } 1721 1722 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1723 1724 amba_set_drvdata(dev, mmc); 1725 1726 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1727 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1728 amba_rev(dev), (unsigned long long)dev->res.start, 1729 dev->irq[0], dev->irq[1]); 1730 1731 mmci_dma_setup(host); 1732 1733 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1734 pm_runtime_use_autosuspend(&dev->dev); 1735 pm_runtime_put(&dev->dev); 1736 1737 mmc_add_host(mmc); 1738 1739 return 0; 1740 1741 clk_disable: 1742 clk_disable_unprepare(host->clk); 1743 host_free: 1744 mmc_free_host(mmc); 1745 return ret; 1746 } 1747 1748 static int mmci_remove(struct amba_device *dev) 1749 { 1750 struct mmc_host *mmc = amba_get_drvdata(dev); 1751 1752 if (mmc) { 1753 struct mmci_host *host = mmc_priv(mmc); 1754 1755 /* 1756 * Undo pm_runtime_put() in probe. We use the _sync 1757 * version here so that we can access the primecell. 1758 */ 1759 pm_runtime_get_sync(&dev->dev); 1760 1761 mmc_remove_host(mmc); 1762 1763 writel(0, host->base + MMCIMASK0); 1764 writel(0, host->base + MMCIMASK1); 1765 1766 writel(0, host->base + MMCICOMMAND); 1767 writel(0, host->base + MMCIDATACTRL); 1768 1769 mmci_dma_release(host); 1770 clk_disable_unprepare(host->clk); 1771 mmc_free_host(mmc); 1772 } 1773 1774 return 0; 1775 } 1776 1777 #ifdef CONFIG_PM 1778 static void mmci_save(struct mmci_host *host) 1779 { 1780 unsigned long flags; 1781 1782 spin_lock_irqsave(&host->lock, flags); 1783 1784 writel(0, host->base + MMCIMASK0); 1785 if (host->variant->pwrreg_nopower) { 1786 writel(0, host->base + MMCIDATACTRL); 1787 writel(0, host->base + MMCIPOWER); 1788 writel(0, host->base + MMCICLOCK); 1789 } 1790 mmci_reg_delay(host); 1791 1792 spin_unlock_irqrestore(&host->lock, flags); 1793 } 1794 1795 static void mmci_restore(struct mmci_host *host) 1796 { 1797 unsigned long flags; 1798 1799 spin_lock_irqsave(&host->lock, flags); 1800 1801 if (host->variant->pwrreg_nopower) { 1802 writel(host->clk_reg, host->base + MMCICLOCK); 1803 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1804 writel(host->pwr_reg, host->base + MMCIPOWER); 1805 } 1806 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1807 mmci_reg_delay(host); 1808 1809 spin_unlock_irqrestore(&host->lock, flags); 1810 } 1811 1812 static int mmci_runtime_suspend(struct device *dev) 1813 { 1814 struct amba_device *adev = to_amba_device(dev); 1815 struct mmc_host *mmc = amba_get_drvdata(adev); 1816 1817 if (mmc) { 1818 struct mmci_host *host = mmc_priv(mmc); 1819 pinctrl_pm_select_sleep_state(dev); 1820 mmci_save(host); 1821 clk_disable_unprepare(host->clk); 1822 } 1823 1824 return 0; 1825 } 1826 1827 static int mmci_runtime_resume(struct device *dev) 1828 { 1829 struct amba_device *adev = to_amba_device(dev); 1830 struct mmc_host *mmc = amba_get_drvdata(adev); 1831 1832 if (mmc) { 1833 struct mmci_host *host = mmc_priv(mmc); 1834 clk_prepare_enable(host->clk); 1835 mmci_restore(host); 1836 pinctrl_pm_select_default_state(dev); 1837 } 1838 1839 return 0; 1840 } 1841 #endif 1842 1843 static const struct dev_pm_ops mmci_dev_pm_ops = { 1844 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1845 pm_runtime_force_resume) 1846 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1847 }; 1848 1849 static struct amba_id mmci_ids[] = { 1850 { 1851 .id = 0x00041180, 1852 .mask = 0xff0fffff, 1853 .data = &variant_arm, 1854 }, 1855 { 1856 .id = 0x01041180, 1857 .mask = 0xff0fffff, 1858 .data = &variant_arm_extended_fifo, 1859 }, 1860 { 1861 .id = 0x02041180, 1862 .mask = 0xff0fffff, 1863 .data = &variant_arm_extended_fifo_hwfc, 1864 }, 1865 { 1866 .id = 0x00041181, 1867 .mask = 0x000fffff, 1868 .data = &variant_arm, 1869 }, 1870 /* ST Micro variants */ 1871 { 1872 .id = 0x00180180, 1873 .mask = 0x00ffffff, 1874 .data = &variant_u300, 1875 }, 1876 { 1877 .id = 0x10180180, 1878 .mask = 0xf0ffffff, 1879 .data = &variant_nomadik, 1880 }, 1881 { 1882 .id = 0x00280180, 1883 .mask = 0x00ffffff, 1884 .data = &variant_u300, 1885 }, 1886 { 1887 .id = 0x00480180, 1888 .mask = 0xf0ffffff, 1889 .data = &variant_ux500, 1890 }, 1891 { 1892 .id = 0x10480180, 1893 .mask = 0xf0ffffff, 1894 .data = &variant_ux500v2, 1895 }, 1896 /* Qualcomm variants */ 1897 { 1898 .id = 0x00051180, 1899 .mask = 0x000fffff, 1900 .data = &variant_qcom, 1901 }, 1902 { 0, 0 }, 1903 }; 1904 1905 MODULE_DEVICE_TABLE(amba, mmci_ids); 1906 1907 static struct amba_driver mmci_driver = { 1908 .drv = { 1909 .name = DRIVER_NAME, 1910 .pm = &mmci_dev_pm_ops, 1911 }, 1912 .probe = mmci_probe, 1913 .remove = mmci_remove, 1914 .id_table = mmci_ids, 1915 }; 1916 1917 module_amba_driver(mmci_driver); 1918 1919 module_param(fmax, uint, 0444); 1920 1921 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1922 MODULE_LICENSE("GPL"); 1923