1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/dmaengine.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/amba/mmci.h> 37 #include <linux/pm_runtime.h> 38 #include <linux/types.h> 39 #include <linux/pinctrl/consumer.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 #include "mmci_qcom_dml.h" 46 47 #define DRIVER_NAME "mmci-pl18x" 48 49 static unsigned int fmax = 515633; 50 51 /** 52 * struct variant_data - MMCI variant-specific quirks 53 * @clkreg: default value for MCICLOCK register 54 * @clkreg_enable: enable value for MMCICLOCK register 55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 57 * @datalength_bits: number of bits in the MMCIDATALENGTH register 58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 59 * is asserted (likewise for RX) 60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 61 * is asserted (likewise for RX) 62 * @data_cmd_enable: enable value for data commands. 63 * @st_sdio: enable ST specific SDIO logic 64 * @st_clkdiv: true if using a ST-specific clock divider algorithm 65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 68 * register 69 * @datactrl_mask_sdio: SDIO enable mask in datactrl register 70 * @pwrreg_powerup: power up value for MMCIPOWER register 71 * @f_max: maximum clk frequency supported by the controller. 72 * @signal_direction: input/out direction of bus signals can be indicated 73 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 74 * @busy_detect: true if busy detection on dat0 is supported 75 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 76 * @explicit_mclk_control: enable explicit mclk control in driver. 77 * @qcom_fifo: enables qcom specific fifo pio read logic. 78 * @qcom_dml: enables qcom specific dma glue for dma transfers. 79 * @reversed_irq_handling: handle data irq before cmd irq. 80 */ 81 struct variant_data { 82 unsigned int clkreg; 83 unsigned int clkreg_enable; 84 unsigned int clkreg_8bit_bus_enable; 85 unsigned int clkreg_neg_edge_enable; 86 unsigned int datalength_bits; 87 unsigned int fifosize; 88 unsigned int fifohalfsize; 89 unsigned int data_cmd_enable; 90 unsigned int datactrl_mask_ddrmode; 91 unsigned int datactrl_mask_sdio; 92 bool st_sdio; 93 bool st_clkdiv; 94 bool blksz_datactrl16; 95 bool blksz_datactrl4; 96 u32 pwrreg_powerup; 97 u32 f_max; 98 bool signal_direction; 99 bool pwrreg_clkgate; 100 bool busy_detect; 101 bool pwrreg_nopower; 102 bool explicit_mclk_control; 103 bool qcom_fifo; 104 bool qcom_dml; 105 bool reversed_irq_handling; 106 }; 107 108 static struct variant_data variant_arm = { 109 .fifosize = 16 * 4, 110 .fifohalfsize = 8 * 4, 111 .datalength_bits = 16, 112 .pwrreg_powerup = MCI_PWR_UP, 113 .f_max = 100000000, 114 .reversed_irq_handling = true, 115 }; 116 117 static struct variant_data variant_arm_extended_fifo = { 118 .fifosize = 128 * 4, 119 .fifohalfsize = 64 * 4, 120 .datalength_bits = 16, 121 .pwrreg_powerup = MCI_PWR_UP, 122 .f_max = 100000000, 123 }; 124 125 static struct variant_data variant_arm_extended_fifo_hwfc = { 126 .fifosize = 128 * 4, 127 .fifohalfsize = 64 * 4, 128 .clkreg_enable = MCI_ARM_HWFCEN, 129 .datalength_bits = 16, 130 .pwrreg_powerup = MCI_PWR_UP, 131 .f_max = 100000000, 132 }; 133 134 static struct variant_data variant_u300 = { 135 .fifosize = 16 * 4, 136 .fifohalfsize = 8 * 4, 137 .clkreg_enable = MCI_ST_U300_HWFCEN, 138 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 139 .datalength_bits = 16, 140 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 141 .st_sdio = true, 142 .pwrreg_powerup = MCI_PWR_ON, 143 .f_max = 100000000, 144 .signal_direction = true, 145 .pwrreg_clkgate = true, 146 .pwrreg_nopower = true, 147 }; 148 149 static struct variant_data variant_nomadik = { 150 .fifosize = 16 * 4, 151 .fifohalfsize = 8 * 4, 152 .clkreg = MCI_CLK_ENABLE, 153 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 154 .datalength_bits = 24, 155 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 156 .st_sdio = true, 157 .st_clkdiv = true, 158 .pwrreg_powerup = MCI_PWR_ON, 159 .f_max = 100000000, 160 .signal_direction = true, 161 .pwrreg_clkgate = true, 162 .pwrreg_nopower = true, 163 }; 164 165 static struct variant_data variant_ux500 = { 166 .fifosize = 30 * 4, 167 .fifohalfsize = 8 * 4, 168 .clkreg = MCI_CLK_ENABLE, 169 .clkreg_enable = MCI_ST_UX500_HWFCEN, 170 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 171 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 172 .datalength_bits = 24, 173 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 174 .st_sdio = true, 175 .st_clkdiv = true, 176 .pwrreg_powerup = MCI_PWR_ON, 177 .f_max = 100000000, 178 .signal_direction = true, 179 .pwrreg_clkgate = true, 180 .busy_detect = true, 181 .pwrreg_nopower = true, 182 }; 183 184 static struct variant_data variant_ux500v2 = { 185 .fifosize = 30 * 4, 186 .fifohalfsize = 8 * 4, 187 .clkreg = MCI_CLK_ENABLE, 188 .clkreg_enable = MCI_ST_UX500_HWFCEN, 189 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 190 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 191 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, 192 .datalength_bits = 24, 193 .datactrl_mask_sdio = MCI_ST_DPSM_SDIOEN, 194 .st_sdio = true, 195 .st_clkdiv = true, 196 .blksz_datactrl16 = true, 197 .pwrreg_powerup = MCI_PWR_ON, 198 .f_max = 100000000, 199 .signal_direction = true, 200 .pwrreg_clkgate = true, 201 .busy_detect = true, 202 .pwrreg_nopower = true, 203 }; 204 205 static struct variant_data variant_qcom = { 206 .fifosize = 16 * 4, 207 .fifohalfsize = 8 * 4, 208 .clkreg = MCI_CLK_ENABLE, 209 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 210 MCI_QCOM_CLK_SELECT_IN_FBCLK, 211 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 212 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 213 .data_cmd_enable = MCI_QCOM_CSPM_DATCMD, 214 .blksz_datactrl4 = true, 215 .datalength_bits = 24, 216 .pwrreg_powerup = MCI_PWR_UP, 217 .f_max = 208000000, 218 .explicit_mclk_control = true, 219 .qcom_fifo = true, 220 .qcom_dml = true, 221 }; 222 223 static int mmci_card_busy(struct mmc_host *mmc) 224 { 225 struct mmci_host *host = mmc_priv(mmc); 226 unsigned long flags; 227 int busy = 0; 228 229 spin_lock_irqsave(&host->lock, flags); 230 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 231 busy = 1; 232 spin_unlock_irqrestore(&host->lock, flags); 233 234 return busy; 235 } 236 237 /* 238 * Validate mmc prerequisites 239 */ 240 static int mmci_validate_data(struct mmci_host *host, 241 struct mmc_data *data) 242 { 243 if (!data) 244 return 0; 245 246 if (!is_power_of_2(data->blksz)) { 247 dev_err(mmc_dev(host->mmc), 248 "unsupported block size (%d bytes)\n", data->blksz); 249 return -EINVAL; 250 } 251 252 return 0; 253 } 254 255 static void mmci_reg_delay(struct mmci_host *host) 256 { 257 /* 258 * According to the spec, at least three feedback clock cycles 259 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 260 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 261 * Worst delay time during card init is at 100 kHz => 30 us. 262 * Worst delay time when up and running is at 25 MHz => 120 ns. 263 */ 264 if (host->cclk < 25000000) 265 udelay(30); 266 else 267 ndelay(120); 268 } 269 270 /* 271 * This must be called with host->lock held 272 */ 273 static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 274 { 275 if (host->clk_reg != clk) { 276 host->clk_reg = clk; 277 writel(clk, host->base + MMCICLOCK); 278 } 279 } 280 281 /* 282 * This must be called with host->lock held 283 */ 284 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 285 { 286 if (host->pwr_reg != pwr) { 287 host->pwr_reg = pwr; 288 writel(pwr, host->base + MMCIPOWER); 289 } 290 } 291 292 /* 293 * This must be called with host->lock held 294 */ 295 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 296 { 297 /* Keep ST Micro busy mode if enabled */ 298 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 299 300 if (host->datactrl_reg != datactrl) { 301 host->datactrl_reg = datactrl; 302 writel(datactrl, host->base + MMCIDATACTRL); 303 } 304 } 305 306 /* 307 * This must be called with host->lock held 308 */ 309 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 310 { 311 struct variant_data *variant = host->variant; 312 u32 clk = variant->clkreg; 313 314 /* Make sure cclk reflects the current calculated clock */ 315 host->cclk = 0; 316 317 if (desired) { 318 if (variant->explicit_mclk_control) { 319 host->cclk = host->mclk; 320 } else if (desired >= host->mclk) { 321 clk = MCI_CLK_BYPASS; 322 if (variant->st_clkdiv) 323 clk |= MCI_ST_UX500_NEG_EDGE; 324 host->cclk = host->mclk; 325 } else if (variant->st_clkdiv) { 326 /* 327 * DB8500 TRM says f = mclk / (clkdiv + 2) 328 * => clkdiv = (mclk / f) - 2 329 * Round the divider up so we don't exceed the max 330 * frequency 331 */ 332 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 333 if (clk >= 256) 334 clk = 255; 335 host->cclk = host->mclk / (clk + 2); 336 } else { 337 /* 338 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 339 * => clkdiv = mclk / (2 * f) - 1 340 */ 341 clk = host->mclk / (2 * desired) - 1; 342 if (clk >= 256) 343 clk = 255; 344 host->cclk = host->mclk / (2 * (clk + 1)); 345 } 346 347 clk |= variant->clkreg_enable; 348 clk |= MCI_CLK_ENABLE; 349 /* This hasn't proven to be worthwhile */ 350 /* clk |= MCI_CLK_PWRSAVE; */ 351 } 352 353 /* Set actual clock for debug */ 354 host->mmc->actual_clock = host->cclk; 355 356 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 357 clk |= MCI_4BIT_BUS; 358 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 359 clk |= variant->clkreg_8bit_bus_enable; 360 361 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 362 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 363 clk |= variant->clkreg_neg_edge_enable; 364 365 mmci_write_clkreg(host, clk); 366 } 367 368 static void 369 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 370 { 371 writel(0, host->base + MMCICOMMAND); 372 373 BUG_ON(host->data); 374 375 host->mrq = NULL; 376 host->cmd = NULL; 377 378 mmc_request_done(host->mmc, mrq); 379 } 380 381 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 382 { 383 void __iomem *base = host->base; 384 385 if (host->singleirq) { 386 unsigned int mask0 = readl(base + MMCIMASK0); 387 388 mask0 &= ~MCI_IRQ1MASK; 389 mask0 |= mask; 390 391 writel(mask0, base + MMCIMASK0); 392 } 393 394 writel(mask, base + MMCIMASK1); 395 } 396 397 static void mmci_stop_data(struct mmci_host *host) 398 { 399 mmci_write_datactrlreg(host, 0); 400 mmci_set_mask1(host, 0); 401 host->data = NULL; 402 } 403 404 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 405 { 406 unsigned int flags = SG_MITER_ATOMIC; 407 408 if (data->flags & MMC_DATA_READ) 409 flags |= SG_MITER_TO_SG; 410 else 411 flags |= SG_MITER_FROM_SG; 412 413 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 414 } 415 416 /* 417 * All the DMA operation mode stuff goes inside this ifdef. 418 * This assumes that you have a generic DMA device interface, 419 * no custom DMA interfaces are supported. 420 */ 421 #ifdef CONFIG_DMA_ENGINE 422 static void mmci_dma_setup(struct mmci_host *host) 423 { 424 const char *rxname, *txname; 425 struct variant_data *variant = host->variant; 426 427 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 428 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 429 430 /* initialize pre request cookie */ 431 host->next_data.cookie = 1; 432 433 /* 434 * If only an RX channel is specified, the driver will 435 * attempt to use it bidirectionally, however if it is 436 * is specified but cannot be located, DMA will be disabled. 437 */ 438 if (host->dma_rx_channel && !host->dma_tx_channel) 439 host->dma_tx_channel = host->dma_rx_channel; 440 441 if (host->dma_rx_channel) 442 rxname = dma_chan_name(host->dma_rx_channel); 443 else 444 rxname = "none"; 445 446 if (host->dma_tx_channel) 447 txname = dma_chan_name(host->dma_tx_channel); 448 else 449 txname = "none"; 450 451 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 452 rxname, txname); 453 454 /* 455 * Limit the maximum segment size in any SG entry according to 456 * the parameters of the DMA engine device. 457 */ 458 if (host->dma_tx_channel) { 459 struct device *dev = host->dma_tx_channel->device->dev; 460 unsigned int max_seg_size = dma_get_max_seg_size(dev); 461 462 if (max_seg_size < host->mmc->max_seg_size) 463 host->mmc->max_seg_size = max_seg_size; 464 } 465 if (host->dma_rx_channel) { 466 struct device *dev = host->dma_rx_channel->device->dev; 467 unsigned int max_seg_size = dma_get_max_seg_size(dev); 468 469 if (max_seg_size < host->mmc->max_seg_size) 470 host->mmc->max_seg_size = max_seg_size; 471 } 472 473 if (variant->qcom_dml && host->dma_rx_channel && host->dma_tx_channel) 474 if (dml_hw_init(host, host->mmc->parent->of_node)) 475 variant->qcom_dml = false; 476 } 477 478 /* 479 * This is used in or so inline it 480 * so it can be discarded. 481 */ 482 static inline void mmci_dma_release(struct mmci_host *host) 483 { 484 if (host->dma_rx_channel) 485 dma_release_channel(host->dma_rx_channel); 486 if (host->dma_tx_channel) 487 dma_release_channel(host->dma_tx_channel); 488 host->dma_rx_channel = host->dma_tx_channel = NULL; 489 } 490 491 static void mmci_dma_data_error(struct mmci_host *host) 492 { 493 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 494 dmaengine_terminate_all(host->dma_current); 495 host->dma_current = NULL; 496 host->dma_desc_current = NULL; 497 host->data->host_cookie = 0; 498 } 499 500 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 501 { 502 struct dma_chan *chan; 503 enum dma_data_direction dir; 504 505 if (data->flags & MMC_DATA_READ) { 506 dir = DMA_FROM_DEVICE; 507 chan = host->dma_rx_channel; 508 } else { 509 dir = DMA_TO_DEVICE; 510 chan = host->dma_tx_channel; 511 } 512 513 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 514 } 515 516 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 517 { 518 u32 status; 519 int i; 520 521 /* Wait up to 1ms for the DMA to complete */ 522 for (i = 0; ; i++) { 523 status = readl(host->base + MMCISTATUS); 524 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 525 break; 526 udelay(10); 527 } 528 529 /* 530 * Check to see whether we still have some data left in the FIFO - 531 * this catches DMA controllers which are unable to monitor the 532 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 533 * contiguous buffers. On TX, we'll get a FIFO underrun error. 534 */ 535 if (status & MCI_RXDATAAVLBLMASK) { 536 mmci_dma_data_error(host); 537 if (!data->error) 538 data->error = -EIO; 539 } 540 541 if (!data->host_cookie) 542 mmci_dma_unmap(host, data); 543 544 /* 545 * Use of DMA with scatter-gather is impossible. 546 * Give up with DMA and switch back to PIO mode. 547 */ 548 if (status & MCI_RXDATAAVLBLMASK) { 549 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 550 mmci_dma_release(host); 551 } 552 553 host->dma_current = NULL; 554 host->dma_desc_current = NULL; 555 } 556 557 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 558 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 559 struct dma_chan **dma_chan, 560 struct dma_async_tx_descriptor **dma_desc) 561 { 562 struct variant_data *variant = host->variant; 563 struct dma_slave_config conf = { 564 .src_addr = host->phybase + MMCIFIFO, 565 .dst_addr = host->phybase + MMCIFIFO, 566 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 567 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 568 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 569 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 570 .device_fc = false, 571 }; 572 struct dma_chan *chan; 573 struct dma_device *device; 574 struct dma_async_tx_descriptor *desc; 575 enum dma_data_direction buffer_dirn; 576 int nr_sg; 577 unsigned long flags = DMA_CTRL_ACK; 578 579 if (data->flags & MMC_DATA_READ) { 580 conf.direction = DMA_DEV_TO_MEM; 581 buffer_dirn = DMA_FROM_DEVICE; 582 chan = host->dma_rx_channel; 583 } else { 584 conf.direction = DMA_MEM_TO_DEV; 585 buffer_dirn = DMA_TO_DEVICE; 586 chan = host->dma_tx_channel; 587 } 588 589 /* If there's no DMA channel, fall back to PIO */ 590 if (!chan) 591 return -EINVAL; 592 593 /* If less than or equal to the fifo size, don't bother with DMA */ 594 if (data->blksz * data->blocks <= variant->fifosize) 595 return -EINVAL; 596 597 device = chan->device; 598 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 599 if (nr_sg == 0) 600 return -EINVAL; 601 602 if (host->variant->qcom_dml) 603 flags |= DMA_PREP_INTERRUPT; 604 605 dmaengine_slave_config(chan, &conf); 606 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 607 conf.direction, flags); 608 if (!desc) 609 goto unmap_exit; 610 611 *dma_chan = chan; 612 *dma_desc = desc; 613 614 return 0; 615 616 unmap_exit: 617 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 618 return -ENOMEM; 619 } 620 621 static inline int mmci_dma_prep_data(struct mmci_host *host, 622 struct mmc_data *data) 623 { 624 /* Check if next job is already prepared. */ 625 if (host->dma_current && host->dma_desc_current) 626 return 0; 627 628 /* No job were prepared thus do it now. */ 629 return __mmci_dma_prep_data(host, data, &host->dma_current, 630 &host->dma_desc_current); 631 } 632 633 static inline int mmci_dma_prep_next(struct mmci_host *host, 634 struct mmc_data *data) 635 { 636 struct mmci_host_next *nd = &host->next_data; 637 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 638 } 639 640 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 641 { 642 int ret; 643 struct mmc_data *data = host->data; 644 645 ret = mmci_dma_prep_data(host, host->data); 646 if (ret) 647 return ret; 648 649 /* Okay, go for it. */ 650 dev_vdbg(mmc_dev(host->mmc), 651 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 652 data->sg_len, data->blksz, data->blocks, data->flags); 653 dmaengine_submit(host->dma_desc_current); 654 dma_async_issue_pending(host->dma_current); 655 656 if (host->variant->qcom_dml) 657 dml_start_xfer(host, data); 658 659 datactrl |= MCI_DPSM_DMAENABLE; 660 661 /* Trigger the DMA transfer */ 662 mmci_write_datactrlreg(host, datactrl); 663 664 /* 665 * Let the MMCI say when the data is ended and it's time 666 * to fire next DMA request. When that happens, MMCI will 667 * call mmci_data_end() 668 */ 669 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 670 host->base + MMCIMASK0); 671 return 0; 672 } 673 674 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 675 { 676 struct mmci_host_next *next = &host->next_data; 677 678 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 679 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 680 681 host->dma_desc_current = next->dma_desc; 682 host->dma_current = next->dma_chan; 683 next->dma_desc = NULL; 684 next->dma_chan = NULL; 685 } 686 687 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 688 bool is_first_req) 689 { 690 struct mmci_host *host = mmc_priv(mmc); 691 struct mmc_data *data = mrq->data; 692 struct mmci_host_next *nd = &host->next_data; 693 694 if (!data) 695 return; 696 697 BUG_ON(data->host_cookie); 698 699 if (mmci_validate_data(host, data)) 700 return; 701 702 if (!mmci_dma_prep_next(host, data)) 703 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 704 } 705 706 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 707 int err) 708 { 709 struct mmci_host *host = mmc_priv(mmc); 710 struct mmc_data *data = mrq->data; 711 712 if (!data || !data->host_cookie) 713 return; 714 715 mmci_dma_unmap(host, data); 716 717 if (err) { 718 struct mmci_host_next *next = &host->next_data; 719 struct dma_chan *chan; 720 if (data->flags & MMC_DATA_READ) 721 chan = host->dma_rx_channel; 722 else 723 chan = host->dma_tx_channel; 724 dmaengine_terminate_all(chan); 725 726 if (host->dma_desc_current == next->dma_desc) 727 host->dma_desc_current = NULL; 728 729 if (host->dma_current == next->dma_chan) 730 host->dma_current = NULL; 731 732 next->dma_desc = NULL; 733 next->dma_chan = NULL; 734 data->host_cookie = 0; 735 } 736 } 737 738 #else 739 /* Blank functions if the DMA engine is not available */ 740 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 741 { 742 } 743 static inline void mmci_dma_setup(struct mmci_host *host) 744 { 745 } 746 747 static inline void mmci_dma_release(struct mmci_host *host) 748 { 749 } 750 751 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 752 { 753 } 754 755 static inline void mmci_dma_finalize(struct mmci_host *host, 756 struct mmc_data *data) 757 { 758 } 759 760 static inline void mmci_dma_data_error(struct mmci_host *host) 761 { 762 } 763 764 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 765 { 766 return -ENOSYS; 767 } 768 769 #define mmci_pre_request NULL 770 #define mmci_post_request NULL 771 772 #endif 773 774 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 775 { 776 struct variant_data *variant = host->variant; 777 unsigned int datactrl, timeout, irqmask; 778 unsigned long long clks; 779 void __iomem *base; 780 int blksz_bits; 781 782 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 783 data->blksz, data->blocks, data->flags); 784 785 host->data = data; 786 host->size = data->blksz * data->blocks; 787 data->bytes_xfered = 0; 788 789 clks = (unsigned long long)data->timeout_ns * host->cclk; 790 do_div(clks, NSEC_PER_SEC); 791 792 timeout = data->timeout_clks + (unsigned int)clks; 793 794 base = host->base; 795 writel(timeout, base + MMCIDATATIMER); 796 writel(host->size, base + MMCIDATALENGTH); 797 798 blksz_bits = ffs(data->blksz) - 1; 799 BUG_ON(1 << blksz_bits != data->blksz); 800 801 if (variant->blksz_datactrl16) 802 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 803 else if (variant->blksz_datactrl4) 804 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 805 else 806 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 807 808 if (data->flags & MMC_DATA_READ) 809 datactrl |= MCI_DPSM_DIRECTION; 810 811 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 812 u32 clk; 813 814 datactrl |= variant->datactrl_mask_sdio; 815 816 /* 817 * The ST Micro variant for SDIO small write transfers 818 * needs to have clock H/W flow control disabled, 819 * otherwise the transfer will not start. The threshold 820 * depends on the rate of MCLK. 821 */ 822 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 823 (host->size < 8 || 824 (host->size <= 8 && host->mclk > 50000000))) 825 clk = host->clk_reg & ~variant->clkreg_enable; 826 else 827 clk = host->clk_reg | variant->clkreg_enable; 828 829 mmci_write_clkreg(host, clk); 830 } 831 832 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 833 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 834 datactrl |= variant->datactrl_mask_ddrmode; 835 836 /* 837 * Attempt to use DMA operation mode, if this 838 * should fail, fall back to PIO mode 839 */ 840 if (!mmci_dma_start_data(host, datactrl)) 841 return; 842 843 /* IRQ mode, map the SG list for CPU reading/writing */ 844 mmci_init_sg(host, data); 845 846 if (data->flags & MMC_DATA_READ) { 847 irqmask = MCI_RXFIFOHALFFULLMASK; 848 849 /* 850 * If we have less than the fifo 'half-full' threshold to 851 * transfer, trigger a PIO interrupt as soon as any data 852 * is available. 853 */ 854 if (host->size < variant->fifohalfsize) 855 irqmask |= MCI_RXDATAAVLBLMASK; 856 } else { 857 /* 858 * We don't actually need to include "FIFO empty" here 859 * since its implicit in "FIFO half empty". 860 */ 861 irqmask = MCI_TXFIFOHALFEMPTYMASK; 862 } 863 864 mmci_write_datactrlreg(host, datactrl); 865 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 866 mmci_set_mask1(host, irqmask); 867 } 868 869 static void 870 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 871 { 872 void __iomem *base = host->base; 873 874 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 875 cmd->opcode, cmd->arg, cmd->flags); 876 877 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 878 writel(0, base + MMCICOMMAND); 879 mmci_reg_delay(host); 880 } 881 882 c |= cmd->opcode | MCI_CPSM_ENABLE; 883 if (cmd->flags & MMC_RSP_PRESENT) { 884 if (cmd->flags & MMC_RSP_136) 885 c |= MCI_CPSM_LONGRSP; 886 c |= MCI_CPSM_RESPONSE; 887 } 888 if (/*interrupt*/0) 889 c |= MCI_CPSM_INTERRUPT; 890 891 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 892 c |= host->variant->data_cmd_enable; 893 894 host->cmd = cmd; 895 896 writel(cmd->arg, base + MMCIARGUMENT); 897 writel(c, base + MMCICOMMAND); 898 } 899 900 static void 901 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 902 unsigned int status) 903 { 904 /* Make sure we have data to handle */ 905 if (!data) 906 return; 907 908 /* First check for errors */ 909 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 910 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 911 u32 remain, success; 912 913 /* Terminate the DMA transfer */ 914 if (dma_inprogress(host)) { 915 mmci_dma_data_error(host); 916 mmci_dma_unmap(host, data); 917 } 918 919 /* 920 * Calculate how far we are into the transfer. Note that 921 * the data counter gives the number of bytes transferred 922 * on the MMC bus, not on the host side. On reads, this 923 * can be as much as a FIFO-worth of data ahead. This 924 * matters for FIFO overruns only. 925 */ 926 remain = readl(host->base + MMCIDATACNT); 927 success = data->blksz * data->blocks - remain; 928 929 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 930 status, success); 931 if (status & MCI_DATACRCFAIL) { 932 /* Last block was not successful */ 933 success -= 1; 934 data->error = -EILSEQ; 935 } else if (status & MCI_DATATIMEOUT) { 936 data->error = -ETIMEDOUT; 937 } else if (status & MCI_STARTBITERR) { 938 data->error = -ECOMM; 939 } else if (status & MCI_TXUNDERRUN) { 940 data->error = -EIO; 941 } else if (status & MCI_RXOVERRUN) { 942 if (success > host->variant->fifosize) 943 success -= host->variant->fifosize; 944 else 945 success = 0; 946 data->error = -EIO; 947 } 948 data->bytes_xfered = round_down(success, data->blksz); 949 } 950 951 if (status & MCI_DATABLOCKEND) 952 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 953 954 if (status & MCI_DATAEND || data->error) { 955 if (dma_inprogress(host)) 956 mmci_dma_finalize(host, data); 957 mmci_stop_data(host); 958 959 if (!data->error) 960 /* The error clause is handled above, success! */ 961 data->bytes_xfered = data->blksz * data->blocks; 962 963 if (!data->stop || host->mrq->sbc) { 964 mmci_request_end(host, data->mrq); 965 } else { 966 mmci_start_command(host, data->stop, 0); 967 } 968 } 969 } 970 971 static void 972 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 973 unsigned int status) 974 { 975 void __iomem *base = host->base; 976 bool sbc, busy_resp; 977 978 if (!cmd) 979 return; 980 981 sbc = (cmd == host->mrq->sbc); 982 busy_resp = host->variant->busy_detect && (cmd->flags & MMC_RSP_BUSY); 983 984 if (!((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 985 MCI_CMDSENT|MCI_CMDRESPEND))) 986 return; 987 988 /* Check if we need to wait for busy completion. */ 989 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 990 return; 991 992 /* Enable busy completion if needed and supported. */ 993 if (!host->busy_status && busy_resp && 994 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 995 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 996 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 997 base + MMCIMASK0); 998 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 999 return; 1000 } 1001 1002 /* At busy completion, mask the IRQ and complete the request. */ 1003 if (host->busy_status) { 1004 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 1005 base + MMCIMASK0); 1006 host->busy_status = 0; 1007 } 1008 1009 host->cmd = NULL; 1010 1011 if (status & MCI_CMDTIMEOUT) { 1012 cmd->error = -ETIMEDOUT; 1013 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1014 cmd->error = -EILSEQ; 1015 } else { 1016 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1017 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1018 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1019 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1020 } 1021 1022 if ((!sbc && !cmd->data) || cmd->error) { 1023 if (host->data) { 1024 /* Terminate the DMA transfer */ 1025 if (dma_inprogress(host)) { 1026 mmci_dma_data_error(host); 1027 mmci_dma_unmap(host, host->data); 1028 } 1029 mmci_stop_data(host); 1030 } 1031 mmci_request_end(host, host->mrq); 1032 } else if (sbc) { 1033 mmci_start_command(host, host->mrq->cmd, 0); 1034 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 1035 mmci_start_data(host, cmd->data); 1036 } 1037 } 1038 1039 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1040 { 1041 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1042 } 1043 1044 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1045 { 1046 /* 1047 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1048 * from the fifo range should be used 1049 */ 1050 if (status & MCI_RXFIFOHALFFULL) 1051 return host->variant->fifohalfsize; 1052 else if (status & MCI_RXDATAAVLBL) 1053 return 4; 1054 1055 return 0; 1056 } 1057 1058 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1059 { 1060 void __iomem *base = host->base; 1061 char *ptr = buffer; 1062 u32 status = readl(host->base + MMCISTATUS); 1063 int host_remain = host->size; 1064 1065 do { 1066 int count = host->get_rx_fifocnt(host, status, host_remain); 1067 1068 if (count > remain) 1069 count = remain; 1070 1071 if (count <= 0) 1072 break; 1073 1074 /* 1075 * SDIO especially may want to send something that is 1076 * not divisible by 4 (as opposed to card sectors 1077 * etc). Therefore make sure to always read the last bytes 1078 * while only doing full 32-bit reads towards the FIFO. 1079 */ 1080 if (unlikely(count & 0x3)) { 1081 if (count < 4) { 1082 unsigned char buf[4]; 1083 ioread32_rep(base + MMCIFIFO, buf, 1); 1084 memcpy(ptr, buf, count); 1085 } else { 1086 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1087 count &= ~0x3; 1088 } 1089 } else { 1090 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1091 } 1092 1093 ptr += count; 1094 remain -= count; 1095 host_remain -= count; 1096 1097 if (remain == 0) 1098 break; 1099 1100 status = readl(base + MMCISTATUS); 1101 } while (status & MCI_RXDATAAVLBL); 1102 1103 return ptr - buffer; 1104 } 1105 1106 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1107 { 1108 struct variant_data *variant = host->variant; 1109 void __iomem *base = host->base; 1110 char *ptr = buffer; 1111 1112 do { 1113 unsigned int count, maxcnt; 1114 1115 maxcnt = status & MCI_TXFIFOEMPTY ? 1116 variant->fifosize : variant->fifohalfsize; 1117 count = min(remain, maxcnt); 1118 1119 /* 1120 * SDIO especially may want to send something that is 1121 * not divisible by 4 (as opposed to card sectors 1122 * etc), and the FIFO only accept full 32-bit writes. 1123 * So compensate by adding +3 on the count, a single 1124 * byte become a 32bit write, 7 bytes will be two 1125 * 32bit writes etc. 1126 */ 1127 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1128 1129 ptr += count; 1130 remain -= count; 1131 1132 if (remain == 0) 1133 break; 1134 1135 status = readl(base + MMCISTATUS); 1136 } while (status & MCI_TXFIFOHALFEMPTY); 1137 1138 return ptr - buffer; 1139 } 1140 1141 /* 1142 * PIO data transfer IRQ handler. 1143 */ 1144 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1145 { 1146 struct mmci_host *host = dev_id; 1147 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1148 struct variant_data *variant = host->variant; 1149 void __iomem *base = host->base; 1150 unsigned long flags; 1151 u32 status; 1152 1153 status = readl(base + MMCISTATUS); 1154 1155 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1156 1157 local_irq_save(flags); 1158 1159 do { 1160 unsigned int remain, len; 1161 char *buffer; 1162 1163 /* 1164 * For write, we only need to test the half-empty flag 1165 * here - if the FIFO is completely empty, then by 1166 * definition it is more than half empty. 1167 * 1168 * For read, check for data available. 1169 */ 1170 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1171 break; 1172 1173 if (!sg_miter_next(sg_miter)) 1174 break; 1175 1176 buffer = sg_miter->addr; 1177 remain = sg_miter->length; 1178 1179 len = 0; 1180 if (status & MCI_RXACTIVE) 1181 len = mmci_pio_read(host, buffer, remain); 1182 if (status & MCI_TXACTIVE) 1183 len = mmci_pio_write(host, buffer, remain, status); 1184 1185 sg_miter->consumed = len; 1186 1187 host->size -= len; 1188 remain -= len; 1189 1190 if (remain) 1191 break; 1192 1193 status = readl(base + MMCISTATUS); 1194 } while (1); 1195 1196 sg_miter_stop(sg_miter); 1197 1198 local_irq_restore(flags); 1199 1200 /* 1201 * If we have less than the fifo 'half-full' threshold to transfer, 1202 * trigger a PIO interrupt as soon as any data is available. 1203 */ 1204 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1205 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1206 1207 /* 1208 * If we run out of data, disable the data IRQs; this 1209 * prevents a race where the FIFO becomes empty before 1210 * the chip itself has disabled the data path, and 1211 * stops us racing with our data end IRQ. 1212 */ 1213 if (host->size == 0) { 1214 mmci_set_mask1(host, 0); 1215 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1216 } 1217 1218 return IRQ_HANDLED; 1219 } 1220 1221 /* 1222 * Handle completion of command and data transfers. 1223 */ 1224 static irqreturn_t mmci_irq(int irq, void *dev_id) 1225 { 1226 struct mmci_host *host = dev_id; 1227 u32 status; 1228 int ret = 0; 1229 1230 spin_lock(&host->lock); 1231 1232 do { 1233 status = readl(host->base + MMCISTATUS); 1234 1235 if (host->singleirq) { 1236 if (status & readl(host->base + MMCIMASK1)) 1237 mmci_pio_irq(irq, dev_id); 1238 1239 status &= ~MCI_IRQ1MASK; 1240 } 1241 1242 /* 1243 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1244 * enabled) since the HW seems to be triggering the IRQ on both 1245 * edges while monitoring DAT0 for busy completion. 1246 */ 1247 status &= readl(host->base + MMCIMASK0); 1248 writel(status, host->base + MMCICLEAR); 1249 1250 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1251 1252 if (host->variant->reversed_irq_handling) { 1253 mmci_data_irq(host, host->data, status); 1254 mmci_cmd_irq(host, host->cmd, status); 1255 } else { 1256 mmci_cmd_irq(host, host->cmd, status); 1257 mmci_data_irq(host, host->data, status); 1258 } 1259 1260 /* Don't poll for busy completion in irq context. */ 1261 if (host->busy_status) 1262 status &= ~MCI_ST_CARDBUSY; 1263 1264 ret = 1; 1265 } while (status); 1266 1267 spin_unlock(&host->lock); 1268 1269 return IRQ_RETVAL(ret); 1270 } 1271 1272 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1273 { 1274 struct mmci_host *host = mmc_priv(mmc); 1275 unsigned long flags; 1276 1277 WARN_ON(host->mrq != NULL); 1278 1279 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1280 if (mrq->cmd->error) { 1281 mmc_request_done(mmc, mrq); 1282 return; 1283 } 1284 1285 spin_lock_irqsave(&host->lock, flags); 1286 1287 host->mrq = mrq; 1288 1289 if (mrq->data) 1290 mmci_get_next_data(host, mrq->data); 1291 1292 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1293 mmci_start_data(host, mrq->data); 1294 1295 if (mrq->sbc) 1296 mmci_start_command(host, mrq->sbc, 0); 1297 else 1298 mmci_start_command(host, mrq->cmd, 0); 1299 1300 spin_unlock_irqrestore(&host->lock, flags); 1301 } 1302 1303 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1304 { 1305 struct mmci_host *host = mmc_priv(mmc); 1306 struct variant_data *variant = host->variant; 1307 u32 pwr = 0; 1308 unsigned long flags; 1309 int ret; 1310 1311 if (host->plat->ios_handler && 1312 host->plat->ios_handler(mmc_dev(mmc), ios)) 1313 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1314 1315 switch (ios->power_mode) { 1316 case MMC_POWER_OFF: 1317 if (!IS_ERR(mmc->supply.vmmc)) 1318 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1319 1320 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1321 regulator_disable(mmc->supply.vqmmc); 1322 host->vqmmc_enabled = false; 1323 } 1324 1325 break; 1326 case MMC_POWER_UP: 1327 if (!IS_ERR(mmc->supply.vmmc)) 1328 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1329 1330 /* 1331 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1332 * and instead uses MCI_PWR_ON so apply whatever value is 1333 * configured in the variant data. 1334 */ 1335 pwr |= variant->pwrreg_powerup; 1336 1337 break; 1338 case MMC_POWER_ON: 1339 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1340 ret = regulator_enable(mmc->supply.vqmmc); 1341 if (ret < 0) 1342 dev_err(mmc_dev(mmc), 1343 "failed to enable vqmmc regulator\n"); 1344 else 1345 host->vqmmc_enabled = true; 1346 } 1347 1348 pwr |= MCI_PWR_ON; 1349 break; 1350 } 1351 1352 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1353 /* 1354 * The ST Micro variant has some additional bits 1355 * indicating signal direction for the signals in 1356 * the SD/MMC bus and feedback-clock usage. 1357 */ 1358 pwr |= host->pwr_reg_add; 1359 1360 if (ios->bus_width == MMC_BUS_WIDTH_4) 1361 pwr &= ~MCI_ST_DATA74DIREN; 1362 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1363 pwr &= (~MCI_ST_DATA74DIREN & 1364 ~MCI_ST_DATA31DIREN & 1365 ~MCI_ST_DATA2DIREN); 1366 } 1367 1368 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1369 if (host->hw_designer != AMBA_VENDOR_ST) 1370 pwr |= MCI_ROD; 1371 else { 1372 /* 1373 * The ST Micro variant use the ROD bit for something 1374 * else and only has OD (Open Drain). 1375 */ 1376 pwr |= MCI_OD; 1377 } 1378 } 1379 1380 /* 1381 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1382 * gating the clock, the MCI_PWR_ON bit is cleared. 1383 */ 1384 if (!ios->clock && variant->pwrreg_clkgate) 1385 pwr &= ~MCI_PWR_ON; 1386 1387 if (host->variant->explicit_mclk_control && 1388 ios->clock != host->clock_cache) { 1389 ret = clk_set_rate(host->clk, ios->clock); 1390 if (ret < 0) 1391 dev_err(mmc_dev(host->mmc), 1392 "Error setting clock rate (%d)\n", ret); 1393 else 1394 host->mclk = clk_get_rate(host->clk); 1395 } 1396 host->clock_cache = ios->clock; 1397 1398 spin_lock_irqsave(&host->lock, flags); 1399 1400 mmci_set_clkreg(host, ios->clock); 1401 mmci_write_pwrreg(host, pwr); 1402 mmci_reg_delay(host); 1403 1404 spin_unlock_irqrestore(&host->lock, flags); 1405 } 1406 1407 static int mmci_get_cd(struct mmc_host *mmc) 1408 { 1409 struct mmci_host *host = mmc_priv(mmc); 1410 struct mmci_platform_data *plat = host->plat; 1411 unsigned int status = mmc_gpio_get_cd(mmc); 1412 1413 if (status == -ENOSYS) { 1414 if (!plat->status) 1415 return 1; /* Assume always present */ 1416 1417 status = plat->status(mmc_dev(host->mmc)); 1418 } 1419 return status; 1420 } 1421 1422 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1423 { 1424 int ret = 0; 1425 1426 if (!IS_ERR(mmc->supply.vqmmc)) { 1427 1428 switch (ios->signal_voltage) { 1429 case MMC_SIGNAL_VOLTAGE_330: 1430 ret = regulator_set_voltage(mmc->supply.vqmmc, 1431 2700000, 3600000); 1432 break; 1433 case MMC_SIGNAL_VOLTAGE_180: 1434 ret = regulator_set_voltage(mmc->supply.vqmmc, 1435 1700000, 1950000); 1436 break; 1437 case MMC_SIGNAL_VOLTAGE_120: 1438 ret = regulator_set_voltage(mmc->supply.vqmmc, 1439 1100000, 1300000); 1440 break; 1441 } 1442 1443 if (ret) 1444 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1445 } 1446 1447 return ret; 1448 } 1449 1450 static struct mmc_host_ops mmci_ops = { 1451 .request = mmci_request, 1452 .pre_req = mmci_pre_request, 1453 .post_req = mmci_post_request, 1454 .set_ios = mmci_set_ios, 1455 .get_ro = mmc_gpio_get_ro, 1456 .get_cd = mmci_get_cd, 1457 .start_signal_voltage_switch = mmci_sig_volt_switch, 1458 }; 1459 1460 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1461 { 1462 struct mmci_host *host = mmc_priv(mmc); 1463 int ret = mmc_of_parse(mmc); 1464 1465 if (ret) 1466 return ret; 1467 1468 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1469 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1470 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1471 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1472 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1473 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1474 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1475 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1476 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1477 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1478 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1479 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1480 1481 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1482 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1483 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1484 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1485 1486 return 0; 1487 } 1488 1489 static int mmci_probe(struct amba_device *dev, 1490 const struct amba_id *id) 1491 { 1492 struct mmci_platform_data *plat = dev->dev.platform_data; 1493 struct device_node *np = dev->dev.of_node; 1494 struct variant_data *variant = id->data; 1495 struct mmci_host *host; 1496 struct mmc_host *mmc; 1497 int ret; 1498 1499 /* Must have platform data or Device Tree. */ 1500 if (!plat && !np) { 1501 dev_err(&dev->dev, "No plat data or DT found\n"); 1502 return -EINVAL; 1503 } 1504 1505 if (!plat) { 1506 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1507 if (!plat) 1508 return -ENOMEM; 1509 } 1510 1511 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1512 if (!mmc) 1513 return -ENOMEM; 1514 1515 ret = mmci_of_parse(np, mmc); 1516 if (ret) 1517 goto host_free; 1518 1519 host = mmc_priv(mmc); 1520 host->mmc = mmc; 1521 1522 host->hw_designer = amba_manf(dev); 1523 host->hw_revision = amba_rev(dev); 1524 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1525 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1526 1527 host->clk = devm_clk_get(&dev->dev, NULL); 1528 if (IS_ERR(host->clk)) { 1529 ret = PTR_ERR(host->clk); 1530 goto host_free; 1531 } 1532 1533 ret = clk_prepare_enable(host->clk); 1534 if (ret) 1535 goto host_free; 1536 1537 if (variant->qcom_fifo) 1538 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1539 else 1540 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1541 1542 host->plat = plat; 1543 host->variant = variant; 1544 host->mclk = clk_get_rate(host->clk); 1545 /* 1546 * According to the spec, mclk is max 100 MHz, 1547 * so we try to adjust the clock down to this, 1548 * (if possible). 1549 */ 1550 if (host->mclk > variant->f_max) { 1551 ret = clk_set_rate(host->clk, variant->f_max); 1552 if (ret < 0) 1553 goto clk_disable; 1554 host->mclk = clk_get_rate(host->clk); 1555 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1556 host->mclk); 1557 } 1558 1559 host->phybase = dev->res.start; 1560 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1561 if (IS_ERR(host->base)) { 1562 ret = PTR_ERR(host->base); 1563 goto clk_disable; 1564 } 1565 1566 /* 1567 * The ARM and ST versions of the block have slightly different 1568 * clock divider equations which means that the minimum divider 1569 * differs too. 1570 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1571 */ 1572 if (variant->st_clkdiv) 1573 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1574 else if (variant->explicit_mclk_control) 1575 mmc->f_min = clk_round_rate(host->clk, 100000); 1576 else 1577 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1578 /* 1579 * If no maximum operating frequency is supplied, fall back to use 1580 * the module parameter, which has a (low) default value in case it 1581 * is not specified. Either value must not exceed the clock rate into 1582 * the block, of course. 1583 */ 1584 if (mmc->f_max) 1585 mmc->f_max = variant->explicit_mclk_control ? 1586 min(variant->f_max, mmc->f_max) : 1587 min(host->mclk, mmc->f_max); 1588 else 1589 mmc->f_max = variant->explicit_mclk_control ? 1590 fmax : min(host->mclk, fmax); 1591 1592 1593 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1594 1595 /* Get regulators and the supported OCR mask */ 1596 ret = mmc_regulator_get_supply(mmc); 1597 if (ret == -EPROBE_DEFER) 1598 goto clk_disable; 1599 1600 if (!mmc->ocr_avail) 1601 mmc->ocr_avail = plat->ocr_mask; 1602 else if (plat->ocr_mask) 1603 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1604 1605 /* DT takes precedence over platform data. */ 1606 if (!np) { 1607 if (!plat->cd_invert) 1608 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1609 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1610 } 1611 1612 /* We support these capabilities. */ 1613 mmc->caps |= MMC_CAP_CMD23; 1614 1615 if (variant->busy_detect) { 1616 mmci_ops.card_busy = mmci_card_busy; 1617 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1618 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1619 mmc->max_busy_timeout = 0; 1620 } 1621 1622 mmc->ops = &mmci_ops; 1623 1624 /* We support these PM capabilities. */ 1625 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1626 1627 /* 1628 * We can do SGIO 1629 */ 1630 mmc->max_segs = NR_SG; 1631 1632 /* 1633 * Since only a certain number of bits are valid in the data length 1634 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1635 * single request. 1636 */ 1637 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1638 1639 /* 1640 * Set the maximum segment size. Since we aren't doing DMA 1641 * (yet) we are only limited by the data length register. 1642 */ 1643 mmc->max_seg_size = mmc->max_req_size; 1644 1645 /* 1646 * Block size can be up to 2048 bytes, but must be a power of two. 1647 */ 1648 mmc->max_blk_size = 1 << 11; 1649 1650 /* 1651 * Limit the number of blocks transferred so that we don't overflow 1652 * the maximum request size. 1653 */ 1654 mmc->max_blk_count = mmc->max_req_size >> 11; 1655 1656 spin_lock_init(&host->lock); 1657 1658 writel(0, host->base + MMCIMASK0); 1659 writel(0, host->base + MMCIMASK1); 1660 writel(0xfff, host->base + MMCICLEAR); 1661 1662 /* 1663 * If: 1664 * - not using DT but using a descriptor table, or 1665 * - using a table of descriptors ALONGSIDE DT, or 1666 * look up these descriptors named "cd" and "wp" right here, fail 1667 * silently of these do not exist and proceed to try platform data 1668 */ 1669 if (!np) { 1670 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1671 if (ret < 0) { 1672 if (ret == -EPROBE_DEFER) 1673 goto clk_disable; 1674 else if (gpio_is_valid(plat->gpio_cd)) { 1675 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1676 if (ret) 1677 goto clk_disable; 1678 } 1679 } 1680 1681 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1682 if (ret < 0) { 1683 if (ret == -EPROBE_DEFER) 1684 goto clk_disable; 1685 else if (gpio_is_valid(plat->gpio_wp)) { 1686 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1687 if (ret) 1688 goto clk_disable; 1689 } 1690 } 1691 } 1692 1693 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1694 DRIVER_NAME " (cmd)", host); 1695 if (ret) 1696 goto clk_disable; 1697 1698 if (!dev->irq[1]) 1699 host->singleirq = true; 1700 else { 1701 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1702 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1703 if (ret) 1704 goto clk_disable; 1705 } 1706 1707 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1708 1709 amba_set_drvdata(dev, mmc); 1710 1711 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1712 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1713 amba_rev(dev), (unsigned long long)dev->res.start, 1714 dev->irq[0], dev->irq[1]); 1715 1716 mmci_dma_setup(host); 1717 1718 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1719 pm_runtime_use_autosuspend(&dev->dev); 1720 1721 mmc_add_host(mmc); 1722 1723 pm_runtime_put(&dev->dev); 1724 return 0; 1725 1726 clk_disable: 1727 clk_disable_unprepare(host->clk); 1728 host_free: 1729 mmc_free_host(mmc); 1730 return ret; 1731 } 1732 1733 static int mmci_remove(struct amba_device *dev) 1734 { 1735 struct mmc_host *mmc = amba_get_drvdata(dev); 1736 1737 if (mmc) { 1738 struct mmci_host *host = mmc_priv(mmc); 1739 1740 /* 1741 * Undo pm_runtime_put() in probe. We use the _sync 1742 * version here so that we can access the primecell. 1743 */ 1744 pm_runtime_get_sync(&dev->dev); 1745 1746 mmc_remove_host(mmc); 1747 1748 writel(0, host->base + MMCIMASK0); 1749 writel(0, host->base + MMCIMASK1); 1750 1751 writel(0, host->base + MMCICOMMAND); 1752 writel(0, host->base + MMCIDATACTRL); 1753 1754 mmci_dma_release(host); 1755 clk_disable_unprepare(host->clk); 1756 mmc_free_host(mmc); 1757 } 1758 1759 return 0; 1760 } 1761 1762 #ifdef CONFIG_PM 1763 static void mmci_save(struct mmci_host *host) 1764 { 1765 unsigned long flags; 1766 1767 spin_lock_irqsave(&host->lock, flags); 1768 1769 writel(0, host->base + MMCIMASK0); 1770 if (host->variant->pwrreg_nopower) { 1771 writel(0, host->base + MMCIDATACTRL); 1772 writel(0, host->base + MMCIPOWER); 1773 writel(0, host->base + MMCICLOCK); 1774 } 1775 mmci_reg_delay(host); 1776 1777 spin_unlock_irqrestore(&host->lock, flags); 1778 } 1779 1780 static void mmci_restore(struct mmci_host *host) 1781 { 1782 unsigned long flags; 1783 1784 spin_lock_irqsave(&host->lock, flags); 1785 1786 if (host->variant->pwrreg_nopower) { 1787 writel(host->clk_reg, host->base + MMCICLOCK); 1788 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1789 writel(host->pwr_reg, host->base + MMCIPOWER); 1790 } 1791 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1792 mmci_reg_delay(host); 1793 1794 spin_unlock_irqrestore(&host->lock, flags); 1795 } 1796 1797 static int mmci_runtime_suspend(struct device *dev) 1798 { 1799 struct amba_device *adev = to_amba_device(dev); 1800 struct mmc_host *mmc = amba_get_drvdata(adev); 1801 1802 if (mmc) { 1803 struct mmci_host *host = mmc_priv(mmc); 1804 pinctrl_pm_select_sleep_state(dev); 1805 mmci_save(host); 1806 clk_disable_unprepare(host->clk); 1807 } 1808 1809 return 0; 1810 } 1811 1812 static int mmci_runtime_resume(struct device *dev) 1813 { 1814 struct amba_device *adev = to_amba_device(dev); 1815 struct mmc_host *mmc = amba_get_drvdata(adev); 1816 1817 if (mmc) { 1818 struct mmci_host *host = mmc_priv(mmc); 1819 clk_prepare_enable(host->clk); 1820 mmci_restore(host); 1821 pinctrl_pm_select_default_state(dev); 1822 } 1823 1824 return 0; 1825 } 1826 #endif 1827 1828 static const struct dev_pm_ops mmci_dev_pm_ops = { 1829 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1830 pm_runtime_force_resume) 1831 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1832 }; 1833 1834 static struct amba_id mmci_ids[] = { 1835 { 1836 .id = 0x00041180, 1837 .mask = 0xff0fffff, 1838 .data = &variant_arm, 1839 }, 1840 { 1841 .id = 0x01041180, 1842 .mask = 0xff0fffff, 1843 .data = &variant_arm_extended_fifo, 1844 }, 1845 { 1846 .id = 0x02041180, 1847 .mask = 0xff0fffff, 1848 .data = &variant_arm_extended_fifo_hwfc, 1849 }, 1850 { 1851 .id = 0x00041181, 1852 .mask = 0x000fffff, 1853 .data = &variant_arm, 1854 }, 1855 /* ST Micro variants */ 1856 { 1857 .id = 0x00180180, 1858 .mask = 0x00ffffff, 1859 .data = &variant_u300, 1860 }, 1861 { 1862 .id = 0x10180180, 1863 .mask = 0xf0ffffff, 1864 .data = &variant_nomadik, 1865 }, 1866 { 1867 .id = 0x00280180, 1868 .mask = 0x00ffffff, 1869 .data = &variant_nomadik, 1870 }, 1871 { 1872 .id = 0x00480180, 1873 .mask = 0xf0ffffff, 1874 .data = &variant_ux500, 1875 }, 1876 { 1877 .id = 0x10480180, 1878 .mask = 0xf0ffffff, 1879 .data = &variant_ux500v2, 1880 }, 1881 /* Qualcomm variants */ 1882 { 1883 .id = 0x00051180, 1884 .mask = 0x000fffff, 1885 .data = &variant_qcom, 1886 }, 1887 { 0, 0 }, 1888 }; 1889 1890 MODULE_DEVICE_TABLE(amba, mmci_ids); 1891 1892 static struct amba_driver mmci_driver = { 1893 .drv = { 1894 .name = DRIVER_NAME, 1895 .pm = &mmci_dev_pm_ops, 1896 }, 1897 .probe = mmci_probe, 1898 .remove = mmci_remove, 1899 .id_table = mmci_ids, 1900 }; 1901 1902 module_amba_driver(mmci_driver); 1903 1904 module_param(fmax, uint, 0444); 1905 1906 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1907 MODULE_LICENSE("GPL"); 1908