1 /* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/ioport.h> 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/highmem.h> 23 #include <linux/log2.h> 24 #include <linux/mmc/pm.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/amba/bus.h> 29 #include <linux/clk.h> 30 #include <linux/scatterlist.h> 31 #include <linux/of.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/amba/mmci.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/types.h> 38 #include <linux/pinctrl/consumer.h> 39 #include <linux/reset.h> 40 41 #include <asm/div64.h> 42 #include <asm/io.h> 43 44 #include "mmci.h" 45 #include "mmci_qcom_dml.h" 46 47 #define DRIVER_NAME "mmci-pl18x" 48 49 #ifdef CONFIG_DMA_ENGINE 50 void mmci_variant_init(struct mmci_host *host); 51 #else 52 static inline void mmci_variant_init(struct mmci_host *host) {} 53 #endif 54 55 static unsigned int fmax = 515633; 56 57 static struct variant_data variant_arm = { 58 .fifosize = 16 * 4, 59 .fifohalfsize = 8 * 4, 60 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 61 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 62 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 63 .cmdreg_srsp = MCI_CPSM_RESPONSE, 64 .datalength_bits = 16, 65 .datactrl_blocksz = 11, 66 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 67 .pwrreg_powerup = MCI_PWR_UP, 68 .f_max = 100000000, 69 .reversed_irq_handling = true, 70 .mmcimask1 = true, 71 .irq_pio_mask = MCI_IRQ_PIO_MASK, 72 .start_err = MCI_STARTBITERR, 73 .opendrain = MCI_ROD, 74 .init = mmci_variant_init, 75 }; 76 77 static struct variant_data variant_arm_extended_fifo = { 78 .fifosize = 128 * 4, 79 .fifohalfsize = 64 * 4, 80 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 81 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 82 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 83 .cmdreg_srsp = MCI_CPSM_RESPONSE, 84 .datalength_bits = 16, 85 .datactrl_blocksz = 11, 86 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 87 .pwrreg_powerup = MCI_PWR_UP, 88 .f_max = 100000000, 89 .mmcimask1 = true, 90 .irq_pio_mask = MCI_IRQ_PIO_MASK, 91 .start_err = MCI_STARTBITERR, 92 .opendrain = MCI_ROD, 93 .init = mmci_variant_init, 94 }; 95 96 static struct variant_data variant_arm_extended_fifo_hwfc = { 97 .fifosize = 128 * 4, 98 .fifohalfsize = 64 * 4, 99 .clkreg_enable = MCI_ARM_HWFCEN, 100 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 101 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 102 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 103 .cmdreg_srsp = MCI_CPSM_RESPONSE, 104 .datalength_bits = 16, 105 .datactrl_blocksz = 11, 106 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 107 .pwrreg_powerup = MCI_PWR_UP, 108 .f_max = 100000000, 109 .mmcimask1 = true, 110 .irq_pio_mask = MCI_IRQ_PIO_MASK, 111 .start_err = MCI_STARTBITERR, 112 .opendrain = MCI_ROD, 113 .init = mmci_variant_init, 114 }; 115 116 static struct variant_data variant_u300 = { 117 .fifosize = 16 * 4, 118 .fifohalfsize = 8 * 4, 119 .clkreg_enable = MCI_ST_U300_HWFCEN, 120 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 121 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 122 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 123 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 124 .cmdreg_srsp = MCI_CPSM_RESPONSE, 125 .datalength_bits = 16, 126 .datactrl_blocksz = 11, 127 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 128 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 129 .st_sdio = true, 130 .pwrreg_powerup = MCI_PWR_ON, 131 .f_max = 100000000, 132 .signal_direction = true, 133 .pwrreg_clkgate = true, 134 .pwrreg_nopower = true, 135 .mmcimask1 = true, 136 .irq_pio_mask = MCI_IRQ_PIO_MASK, 137 .start_err = MCI_STARTBITERR, 138 .opendrain = MCI_OD, 139 .init = mmci_variant_init, 140 }; 141 142 static struct variant_data variant_nomadik = { 143 .fifosize = 16 * 4, 144 .fifohalfsize = 8 * 4, 145 .clkreg = MCI_CLK_ENABLE, 146 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 147 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 148 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 149 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 150 .cmdreg_srsp = MCI_CPSM_RESPONSE, 151 .datalength_bits = 24, 152 .datactrl_blocksz = 11, 153 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 154 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 155 .st_sdio = true, 156 .st_clkdiv = true, 157 .pwrreg_powerup = MCI_PWR_ON, 158 .f_max = 100000000, 159 .signal_direction = true, 160 .pwrreg_clkgate = true, 161 .pwrreg_nopower = true, 162 .mmcimask1 = true, 163 .irq_pio_mask = MCI_IRQ_PIO_MASK, 164 .start_err = MCI_STARTBITERR, 165 .opendrain = MCI_OD, 166 .init = mmci_variant_init, 167 }; 168 169 static struct variant_data variant_ux500 = { 170 .fifosize = 30 * 4, 171 .fifohalfsize = 8 * 4, 172 .clkreg = MCI_CLK_ENABLE, 173 .clkreg_enable = MCI_ST_UX500_HWFCEN, 174 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 175 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 176 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 177 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 178 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 179 .cmdreg_srsp = MCI_CPSM_RESPONSE, 180 .datalength_bits = 24, 181 .datactrl_blocksz = 11, 182 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 183 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 184 .st_sdio = true, 185 .st_clkdiv = true, 186 .pwrreg_powerup = MCI_PWR_ON, 187 .f_max = 100000000, 188 .signal_direction = true, 189 .pwrreg_clkgate = true, 190 .busy_detect = true, 191 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 192 .busy_detect_flag = MCI_ST_CARDBUSY, 193 .busy_detect_mask = MCI_ST_BUSYENDMASK, 194 .pwrreg_nopower = true, 195 .mmcimask1 = true, 196 .irq_pio_mask = MCI_IRQ_PIO_MASK, 197 .start_err = MCI_STARTBITERR, 198 .opendrain = MCI_OD, 199 .init = mmci_variant_init, 200 }; 201 202 static struct variant_data variant_ux500v2 = { 203 .fifosize = 30 * 4, 204 .fifohalfsize = 8 * 4, 205 .clkreg = MCI_CLK_ENABLE, 206 .clkreg_enable = MCI_ST_UX500_HWFCEN, 207 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 208 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 209 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 210 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 211 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 212 .cmdreg_srsp = MCI_CPSM_RESPONSE, 213 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, 214 .datalength_bits = 24, 215 .datactrl_blocksz = 11, 216 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 217 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 218 .st_sdio = true, 219 .st_clkdiv = true, 220 .blksz_datactrl16 = true, 221 .pwrreg_powerup = MCI_PWR_ON, 222 .f_max = 100000000, 223 .signal_direction = true, 224 .pwrreg_clkgate = true, 225 .busy_detect = true, 226 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, 227 .busy_detect_flag = MCI_ST_CARDBUSY, 228 .busy_detect_mask = MCI_ST_BUSYENDMASK, 229 .pwrreg_nopower = true, 230 .mmcimask1 = true, 231 .irq_pio_mask = MCI_IRQ_PIO_MASK, 232 .start_err = MCI_STARTBITERR, 233 .opendrain = MCI_OD, 234 .init = mmci_variant_init, 235 }; 236 237 static struct variant_data variant_stm32 = { 238 .fifosize = 32 * 4, 239 .fifohalfsize = 8 * 4, 240 .clkreg = MCI_CLK_ENABLE, 241 .clkreg_enable = MCI_ST_UX500_HWFCEN, 242 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 243 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 244 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 245 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 246 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 247 .cmdreg_srsp = MCI_CPSM_RESPONSE, 248 .irq_pio_mask = MCI_IRQ_PIO_MASK, 249 .datalength_bits = 24, 250 .datactrl_blocksz = 11, 251 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 252 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, 253 .st_sdio = true, 254 .st_clkdiv = true, 255 .pwrreg_powerup = MCI_PWR_ON, 256 .f_max = 48000000, 257 .pwrreg_clkgate = true, 258 .pwrreg_nopower = true, 259 .init = mmci_variant_init, 260 }; 261 262 static struct variant_data variant_qcom = { 263 .fifosize = 16 * 4, 264 .fifohalfsize = 8 * 4, 265 .clkreg = MCI_CLK_ENABLE, 266 .clkreg_enable = MCI_QCOM_CLK_FLOWENA | 267 MCI_QCOM_CLK_SELECT_IN_FBCLK, 268 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, 269 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, 270 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, 271 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, 272 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, 273 .cmdreg_srsp = MCI_CPSM_RESPONSE, 274 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, 275 .blksz_datactrl4 = true, 276 .datalength_bits = 24, 277 .datactrl_blocksz = 11, 278 .datactrl_dpsm_enable = MCI_DPSM_ENABLE, 279 .pwrreg_powerup = MCI_PWR_UP, 280 .f_max = 208000000, 281 .explicit_mclk_control = true, 282 .qcom_fifo = true, 283 .qcom_dml = true, 284 .mmcimask1 = true, 285 .irq_pio_mask = MCI_IRQ_PIO_MASK, 286 .start_err = MCI_STARTBITERR, 287 .opendrain = MCI_ROD, 288 .init = qcom_variant_init, 289 }; 290 291 /* Busy detection for the ST Micro variant */ 292 static int mmci_card_busy(struct mmc_host *mmc) 293 { 294 struct mmci_host *host = mmc_priv(mmc); 295 unsigned long flags; 296 int busy = 0; 297 298 spin_lock_irqsave(&host->lock, flags); 299 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) 300 busy = 1; 301 spin_unlock_irqrestore(&host->lock, flags); 302 303 return busy; 304 } 305 306 static void mmci_reg_delay(struct mmci_host *host) 307 { 308 /* 309 * According to the spec, at least three feedback clock cycles 310 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 311 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 312 * Worst delay time during card init is at 100 kHz => 30 us. 313 * Worst delay time when up and running is at 25 MHz => 120 ns. 314 */ 315 if (host->cclk < 25000000) 316 udelay(30); 317 else 318 ndelay(120); 319 } 320 321 /* 322 * This must be called with host->lock held 323 */ 324 void mmci_write_clkreg(struct mmci_host *host, u32 clk) 325 { 326 if (host->clk_reg != clk) { 327 host->clk_reg = clk; 328 writel(clk, host->base + MMCICLOCK); 329 } 330 } 331 332 /* 333 * This must be called with host->lock held 334 */ 335 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 336 { 337 if (host->pwr_reg != pwr) { 338 host->pwr_reg = pwr; 339 writel(pwr, host->base + MMCIPOWER); 340 } 341 } 342 343 /* 344 * This must be called with host->lock held 345 */ 346 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 347 { 348 /* Keep busy mode in DPSM if enabled */ 349 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; 350 351 if (host->datactrl_reg != datactrl) { 352 host->datactrl_reg = datactrl; 353 writel(datactrl, host->base + MMCIDATACTRL); 354 } 355 } 356 357 /* 358 * This must be called with host->lock held 359 */ 360 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 361 { 362 struct variant_data *variant = host->variant; 363 u32 clk = variant->clkreg; 364 365 /* Make sure cclk reflects the current calculated clock */ 366 host->cclk = 0; 367 368 if (desired) { 369 if (variant->explicit_mclk_control) { 370 host->cclk = host->mclk; 371 } else if (desired >= host->mclk) { 372 clk = MCI_CLK_BYPASS; 373 if (variant->st_clkdiv) 374 clk |= MCI_ST_UX500_NEG_EDGE; 375 host->cclk = host->mclk; 376 } else if (variant->st_clkdiv) { 377 /* 378 * DB8500 TRM says f = mclk / (clkdiv + 2) 379 * => clkdiv = (mclk / f) - 2 380 * Round the divider up so we don't exceed the max 381 * frequency 382 */ 383 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 384 if (clk >= 256) 385 clk = 255; 386 host->cclk = host->mclk / (clk + 2); 387 } else { 388 /* 389 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 390 * => clkdiv = mclk / (2 * f) - 1 391 */ 392 clk = host->mclk / (2 * desired) - 1; 393 if (clk >= 256) 394 clk = 255; 395 host->cclk = host->mclk / (2 * (clk + 1)); 396 } 397 398 clk |= variant->clkreg_enable; 399 clk |= MCI_CLK_ENABLE; 400 /* This hasn't proven to be worthwhile */ 401 /* clk |= MCI_CLK_PWRSAVE; */ 402 } 403 404 /* Set actual clock for debug */ 405 host->mmc->actual_clock = host->cclk; 406 407 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 408 clk |= MCI_4BIT_BUS; 409 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 410 clk |= variant->clkreg_8bit_bus_enable; 411 412 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 413 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 414 clk |= variant->clkreg_neg_edge_enable; 415 416 mmci_write_clkreg(host, clk); 417 } 418 419 void mmci_dma_release(struct mmci_host *host) 420 { 421 if (host->ops && host->ops->dma_release) 422 host->ops->dma_release(host); 423 424 host->use_dma = false; 425 } 426 427 void mmci_dma_setup(struct mmci_host *host) 428 { 429 if (!host->ops || !host->ops->dma_setup) 430 return; 431 432 if (host->ops->dma_setup(host)) 433 return; 434 435 /* initialize pre request cookie */ 436 host->next_cookie = 1; 437 438 host->use_dma = true; 439 } 440 441 /* 442 * Validate mmc prerequisites 443 */ 444 static int mmci_validate_data(struct mmci_host *host, 445 struct mmc_data *data) 446 { 447 if (!data) 448 return 0; 449 450 if (!is_power_of_2(data->blksz)) { 451 dev_err(mmc_dev(host->mmc), 452 "unsupported block size (%d bytes)\n", data->blksz); 453 return -EINVAL; 454 } 455 456 if (host->ops && host->ops->validate_data) 457 return host->ops->validate_data(host, data); 458 459 return 0; 460 } 461 462 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) 463 { 464 int err; 465 466 if (!host->ops || !host->ops->prep_data) 467 return 0; 468 469 err = host->ops->prep_data(host, data, next); 470 471 if (next && !err) 472 data->host_cookie = ++host->next_cookie < 0 ? 473 1 : host->next_cookie; 474 475 return err; 476 } 477 478 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, 479 int err) 480 { 481 if (host->ops && host->ops->unprep_data) 482 host->ops->unprep_data(host, data, err); 483 484 data->host_cookie = 0; 485 } 486 487 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 488 { 489 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); 490 491 if (host->ops && host->ops->get_next_data) 492 host->ops->get_next_data(host, data); 493 } 494 495 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) 496 { 497 struct mmc_data *data = host->data; 498 int ret; 499 500 if (!host->use_dma) 501 return -EINVAL; 502 503 ret = mmci_prep_data(host, data, false); 504 if (ret) 505 return ret; 506 507 if (!host->ops || !host->ops->dma_start) 508 return -EINVAL; 509 510 /* Okay, go for it. */ 511 dev_vdbg(mmc_dev(host->mmc), 512 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 513 data->sg_len, data->blksz, data->blocks, data->flags); 514 515 host->ops->dma_start(host, &datactrl); 516 517 /* Trigger the DMA transfer */ 518 mmci_write_datactrlreg(host, datactrl); 519 520 /* 521 * Let the MMCI say when the data is ended and it's time 522 * to fire next DMA request. When that happens, MMCI will 523 * call mmci_data_end() 524 */ 525 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 526 host->base + MMCIMASK0); 527 return 0; 528 } 529 530 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 531 { 532 if (!host->use_dma) 533 return; 534 535 if (host->ops && host->ops->dma_finalize) 536 host->ops->dma_finalize(host, data); 537 } 538 539 void mmci_dma_error(struct mmci_host *host) 540 { 541 if (!host->use_dma) 542 return; 543 544 if (host->ops && host->ops->dma_error) 545 host->ops->dma_error(host); 546 } 547 548 static void 549 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 550 { 551 writel(0, host->base + MMCICOMMAND); 552 553 BUG_ON(host->data); 554 555 host->mrq = NULL; 556 host->cmd = NULL; 557 558 mmc_request_done(host->mmc, mrq); 559 } 560 561 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 562 { 563 void __iomem *base = host->base; 564 struct variant_data *variant = host->variant; 565 566 if (host->singleirq) { 567 unsigned int mask0 = readl(base + MMCIMASK0); 568 569 mask0 &= ~variant->irq_pio_mask; 570 mask0 |= mask; 571 572 writel(mask0, base + MMCIMASK0); 573 } 574 575 if (variant->mmcimask1) 576 writel(mask, base + MMCIMASK1); 577 578 host->mask1_reg = mask; 579 } 580 581 static void mmci_stop_data(struct mmci_host *host) 582 { 583 mmci_write_datactrlreg(host, 0); 584 mmci_set_mask1(host, 0); 585 host->data = NULL; 586 } 587 588 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 589 { 590 unsigned int flags = SG_MITER_ATOMIC; 591 592 if (data->flags & MMC_DATA_READ) 593 flags |= SG_MITER_TO_SG; 594 else 595 flags |= SG_MITER_FROM_SG; 596 597 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 598 } 599 600 /* 601 * All the DMA operation mode stuff goes inside this ifdef. 602 * This assumes that you have a generic DMA device interface, 603 * no custom DMA interfaces are supported. 604 */ 605 #ifdef CONFIG_DMA_ENGINE 606 struct mmci_dmae_next { 607 struct dma_async_tx_descriptor *desc; 608 struct dma_chan *chan; 609 }; 610 611 struct mmci_dmae_priv { 612 struct dma_chan *cur; 613 struct dma_chan *rx_channel; 614 struct dma_chan *tx_channel; 615 struct dma_async_tx_descriptor *desc_current; 616 struct mmci_dmae_next next_data; 617 }; 618 619 int mmci_dmae_setup(struct mmci_host *host) 620 { 621 const char *rxname, *txname; 622 struct mmci_dmae_priv *dmae; 623 624 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); 625 if (!dmae) 626 return -ENOMEM; 627 628 host->dma_priv = dmae; 629 630 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 631 "rx"); 632 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), 633 "tx"); 634 635 /* 636 * If only an RX channel is specified, the driver will 637 * attempt to use it bidirectionally, however if it is 638 * is specified but cannot be located, DMA will be disabled. 639 */ 640 if (dmae->rx_channel && !dmae->tx_channel) 641 dmae->tx_channel = dmae->rx_channel; 642 643 if (dmae->rx_channel) 644 rxname = dma_chan_name(dmae->rx_channel); 645 else 646 rxname = "none"; 647 648 if (dmae->tx_channel) 649 txname = dma_chan_name(dmae->tx_channel); 650 else 651 txname = "none"; 652 653 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 654 rxname, txname); 655 656 /* 657 * Limit the maximum segment size in any SG entry according to 658 * the parameters of the DMA engine device. 659 */ 660 if (dmae->tx_channel) { 661 struct device *dev = dmae->tx_channel->device->dev; 662 unsigned int max_seg_size = dma_get_max_seg_size(dev); 663 664 if (max_seg_size < host->mmc->max_seg_size) 665 host->mmc->max_seg_size = max_seg_size; 666 } 667 if (dmae->rx_channel) { 668 struct device *dev = dmae->rx_channel->device->dev; 669 unsigned int max_seg_size = dma_get_max_seg_size(dev); 670 671 if (max_seg_size < host->mmc->max_seg_size) 672 host->mmc->max_seg_size = max_seg_size; 673 } 674 675 if (!dmae->tx_channel || !dmae->rx_channel) { 676 mmci_dmae_release(host); 677 return -EINVAL; 678 } 679 680 return 0; 681 } 682 683 /* 684 * This is used in or so inline it 685 * so it can be discarded. 686 */ 687 void mmci_dmae_release(struct mmci_host *host) 688 { 689 struct mmci_dmae_priv *dmae = host->dma_priv; 690 691 if (dmae->rx_channel) 692 dma_release_channel(dmae->rx_channel); 693 if (dmae->tx_channel) 694 dma_release_channel(dmae->tx_channel); 695 dmae->rx_channel = dmae->tx_channel = NULL; 696 } 697 698 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 699 { 700 struct mmci_dmae_priv *dmae = host->dma_priv; 701 struct dma_chan *chan; 702 703 if (data->flags & MMC_DATA_READ) 704 chan = dmae->rx_channel; 705 else 706 chan = dmae->tx_channel; 707 708 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, 709 mmc_get_dma_dir(data)); 710 } 711 712 void mmci_dmae_error(struct mmci_host *host) 713 { 714 struct mmci_dmae_priv *dmae = host->dma_priv; 715 716 if (!dma_inprogress(host)) 717 return; 718 719 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 720 dmaengine_terminate_all(dmae->cur); 721 host->dma_in_progress = false; 722 dmae->cur = NULL; 723 dmae->desc_current = NULL; 724 host->data->host_cookie = 0; 725 726 mmci_dma_unmap(host, host->data); 727 } 728 729 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) 730 { 731 struct mmci_dmae_priv *dmae = host->dma_priv; 732 u32 status; 733 int i; 734 735 if (!dma_inprogress(host)) 736 return; 737 738 /* Wait up to 1ms for the DMA to complete */ 739 for (i = 0; ; i++) { 740 status = readl(host->base + MMCISTATUS); 741 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 742 break; 743 udelay(10); 744 } 745 746 /* 747 * Check to see whether we still have some data left in the FIFO - 748 * this catches DMA controllers which are unable to monitor the 749 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 750 * contiguous buffers. On TX, we'll get a FIFO underrun error. 751 */ 752 if (status & MCI_RXDATAAVLBLMASK) { 753 mmci_dma_error(host); 754 if (!data->error) 755 data->error = -EIO; 756 } else if (!data->host_cookie) { 757 mmci_dma_unmap(host, data); 758 } 759 760 /* 761 * Use of DMA with scatter-gather is impossible. 762 * Give up with DMA and switch back to PIO mode. 763 */ 764 if (status & MCI_RXDATAAVLBLMASK) { 765 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 766 mmci_dma_release(host); 767 } 768 769 host->dma_in_progress = false; 770 dmae->cur = NULL; 771 dmae->desc_current = NULL; 772 } 773 774 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 775 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, 776 struct dma_chan **dma_chan, 777 struct dma_async_tx_descriptor **dma_desc) 778 { 779 struct mmci_dmae_priv *dmae = host->dma_priv; 780 struct variant_data *variant = host->variant; 781 struct dma_slave_config conf = { 782 .src_addr = host->phybase + MMCIFIFO, 783 .dst_addr = host->phybase + MMCIFIFO, 784 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 785 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 786 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 787 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 788 .device_fc = false, 789 }; 790 struct dma_chan *chan; 791 struct dma_device *device; 792 struct dma_async_tx_descriptor *desc; 793 int nr_sg; 794 unsigned long flags = DMA_CTRL_ACK; 795 796 if (data->flags & MMC_DATA_READ) { 797 conf.direction = DMA_DEV_TO_MEM; 798 chan = dmae->rx_channel; 799 } else { 800 conf.direction = DMA_MEM_TO_DEV; 801 chan = dmae->tx_channel; 802 } 803 804 /* If there's no DMA channel, fall back to PIO */ 805 if (!chan) 806 return -EINVAL; 807 808 /* If less than or equal to the fifo size, don't bother with DMA */ 809 if (data->blksz * data->blocks <= variant->fifosize) 810 return -EINVAL; 811 812 device = chan->device; 813 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, 814 mmc_get_dma_dir(data)); 815 if (nr_sg == 0) 816 return -EINVAL; 817 818 if (host->variant->qcom_dml) 819 flags |= DMA_PREP_INTERRUPT; 820 821 dmaengine_slave_config(chan, &conf); 822 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 823 conf.direction, flags); 824 if (!desc) 825 goto unmap_exit; 826 827 *dma_chan = chan; 828 *dma_desc = desc; 829 830 return 0; 831 832 unmap_exit: 833 dma_unmap_sg(device->dev, data->sg, data->sg_len, 834 mmc_get_dma_dir(data)); 835 return -ENOMEM; 836 } 837 838 int mmci_dmae_prep_data(struct mmci_host *host, 839 struct mmc_data *data, 840 bool next) 841 { 842 struct mmci_dmae_priv *dmae = host->dma_priv; 843 struct mmci_dmae_next *nd = &dmae->next_data; 844 845 if (!host->use_dma) 846 return -EINVAL; 847 848 if (next) 849 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); 850 /* Check if next job is already prepared. */ 851 if (dmae->cur && dmae->desc_current) 852 return 0; 853 854 /* No job were prepared thus do it now. */ 855 return _mmci_dmae_prep_data(host, data, &dmae->cur, 856 &dmae->desc_current); 857 } 858 859 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) 860 { 861 struct mmci_dmae_priv *dmae = host->dma_priv; 862 struct mmc_data *data = host->data; 863 864 host->dma_in_progress = true; 865 dmaengine_submit(dmae->desc_current); 866 dma_async_issue_pending(dmae->cur); 867 868 if (host->variant->qcom_dml) 869 dml_start_xfer(host, data); 870 871 *datactrl |= MCI_DPSM_DMAENABLE; 872 873 return 0; 874 } 875 876 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) 877 { 878 struct mmci_dmae_priv *dmae = host->dma_priv; 879 struct mmci_dmae_next *next = &dmae->next_data; 880 881 if (!host->use_dma) 882 return; 883 884 WARN_ON(!data->host_cookie && (next->desc || next->chan)); 885 886 dmae->desc_current = next->desc; 887 dmae->cur = next->chan; 888 next->desc = NULL; 889 next->chan = NULL; 890 } 891 892 void mmci_dmae_unprep_data(struct mmci_host *host, 893 struct mmc_data *data, int err) 894 895 { 896 struct mmci_dmae_priv *dmae = host->dma_priv; 897 898 if (!host->use_dma) 899 return; 900 901 mmci_dma_unmap(host, data); 902 903 if (err) { 904 struct mmci_dmae_next *next = &dmae->next_data; 905 struct dma_chan *chan; 906 if (data->flags & MMC_DATA_READ) 907 chan = dmae->rx_channel; 908 else 909 chan = dmae->tx_channel; 910 dmaengine_terminate_all(chan); 911 912 if (dmae->desc_current == next->desc) 913 dmae->desc_current = NULL; 914 915 if (dmae->cur == next->chan) { 916 host->dma_in_progress = false; 917 dmae->cur = NULL; 918 } 919 920 next->desc = NULL; 921 next->chan = NULL; 922 } 923 } 924 925 static struct mmci_host_ops mmci_variant_ops = { 926 .prep_data = mmci_dmae_prep_data, 927 .unprep_data = mmci_dmae_unprep_data, 928 .get_next_data = mmci_dmae_get_next_data, 929 .dma_setup = mmci_dmae_setup, 930 .dma_release = mmci_dmae_release, 931 .dma_start = mmci_dmae_start, 932 .dma_finalize = mmci_dmae_finalize, 933 .dma_error = mmci_dmae_error, 934 }; 935 936 void mmci_variant_init(struct mmci_host *host) 937 { 938 host->ops = &mmci_variant_ops; 939 } 940 #endif 941 942 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) 943 { 944 struct mmci_host *host = mmc_priv(mmc); 945 struct mmc_data *data = mrq->data; 946 947 if (!data) 948 return; 949 950 WARN_ON(data->host_cookie); 951 952 if (mmci_validate_data(host, data)) 953 return; 954 955 mmci_prep_data(host, data, true); 956 } 957 958 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 959 int err) 960 { 961 struct mmci_host *host = mmc_priv(mmc); 962 struct mmc_data *data = mrq->data; 963 964 if (!data || !data->host_cookie) 965 return; 966 967 mmci_unprep_data(host, data, err); 968 } 969 970 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 971 { 972 struct variant_data *variant = host->variant; 973 unsigned int datactrl, timeout, irqmask; 974 unsigned long long clks; 975 void __iomem *base; 976 int blksz_bits; 977 978 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 979 data->blksz, data->blocks, data->flags); 980 981 host->data = data; 982 host->size = data->blksz * data->blocks; 983 data->bytes_xfered = 0; 984 985 clks = (unsigned long long)data->timeout_ns * host->cclk; 986 do_div(clks, NSEC_PER_SEC); 987 988 timeout = data->timeout_clks + (unsigned int)clks; 989 990 base = host->base; 991 writel(timeout, base + MMCIDATATIMER); 992 writel(host->size, base + MMCIDATALENGTH); 993 994 blksz_bits = ffs(data->blksz) - 1; 995 BUG_ON(1 << blksz_bits != data->blksz); 996 997 if (variant->blksz_datactrl16) 998 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16); 999 else if (variant->blksz_datactrl4) 1000 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4); 1001 else 1002 datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; 1003 1004 if (data->flags & MMC_DATA_READ) 1005 datactrl |= MCI_DPSM_DIRECTION; 1006 1007 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { 1008 u32 clk; 1009 1010 datactrl |= variant->datactrl_mask_sdio; 1011 1012 /* 1013 * The ST Micro variant for SDIO small write transfers 1014 * needs to have clock H/W flow control disabled, 1015 * otherwise the transfer will not start. The threshold 1016 * depends on the rate of MCLK. 1017 */ 1018 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && 1019 (host->size < 8 || 1020 (host->size <= 8 && host->mclk > 50000000))) 1021 clk = host->clk_reg & ~variant->clkreg_enable; 1022 else 1023 clk = host->clk_reg | variant->clkreg_enable; 1024 1025 mmci_write_clkreg(host, clk); 1026 } 1027 1028 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 1029 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 1030 datactrl |= variant->datactrl_mask_ddrmode; 1031 1032 /* 1033 * Attempt to use DMA operation mode, if this 1034 * should fail, fall back to PIO mode 1035 */ 1036 if (!mmci_dma_start(host, datactrl)) 1037 return; 1038 1039 /* IRQ mode, map the SG list for CPU reading/writing */ 1040 mmci_init_sg(host, data); 1041 1042 if (data->flags & MMC_DATA_READ) { 1043 irqmask = MCI_RXFIFOHALFFULLMASK; 1044 1045 /* 1046 * If we have less than the fifo 'half-full' threshold to 1047 * transfer, trigger a PIO interrupt as soon as any data 1048 * is available. 1049 */ 1050 if (host->size < variant->fifohalfsize) 1051 irqmask |= MCI_RXDATAAVLBLMASK; 1052 } else { 1053 /* 1054 * We don't actually need to include "FIFO empty" here 1055 * since its implicit in "FIFO half empty". 1056 */ 1057 irqmask = MCI_TXFIFOHALFEMPTYMASK; 1058 } 1059 1060 mmci_write_datactrlreg(host, datactrl); 1061 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 1062 mmci_set_mask1(host, irqmask); 1063 } 1064 1065 static void 1066 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 1067 { 1068 void __iomem *base = host->base; 1069 1070 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 1071 cmd->opcode, cmd->arg, cmd->flags); 1072 1073 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { 1074 writel(0, base + MMCICOMMAND); 1075 mmci_reg_delay(host); 1076 } 1077 1078 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; 1079 if (cmd->flags & MMC_RSP_PRESENT) { 1080 if (cmd->flags & MMC_RSP_136) 1081 c |= host->variant->cmdreg_lrsp_crc; 1082 else if (cmd->flags & MMC_RSP_CRC) 1083 c |= host->variant->cmdreg_srsp_crc; 1084 else 1085 c |= host->variant->cmdreg_srsp; 1086 } 1087 if (/*interrupt*/0) 1088 c |= MCI_CPSM_INTERRUPT; 1089 1090 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 1091 c |= host->variant->data_cmd_enable; 1092 1093 host->cmd = cmd; 1094 1095 writel(cmd->arg, base + MMCIARGUMENT); 1096 writel(c, base + MMCICOMMAND); 1097 } 1098 1099 static void 1100 mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 1101 unsigned int status) 1102 { 1103 unsigned int status_err; 1104 1105 /* Make sure we have data to handle */ 1106 if (!data) 1107 return; 1108 1109 /* First check for errors */ 1110 status_err = status & (host->variant->start_err | 1111 MCI_DATACRCFAIL | MCI_DATATIMEOUT | 1112 MCI_TXUNDERRUN | MCI_RXOVERRUN); 1113 1114 if (status_err) { 1115 u32 remain, success; 1116 1117 /* Terminate the DMA transfer */ 1118 mmci_dma_error(host); 1119 1120 /* 1121 * Calculate how far we are into the transfer. Note that 1122 * the data counter gives the number of bytes transferred 1123 * on the MMC bus, not on the host side. On reads, this 1124 * can be as much as a FIFO-worth of data ahead. This 1125 * matters for FIFO overruns only. 1126 */ 1127 if (!host->variant->datacnt_useless) { 1128 remain = readl(host->base + MMCIDATACNT); 1129 success = data->blksz * data->blocks - remain; 1130 } else { 1131 success = 0; 1132 } 1133 1134 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 1135 status_err, success); 1136 if (status_err & MCI_DATACRCFAIL) { 1137 /* Last block was not successful */ 1138 success -= 1; 1139 data->error = -EILSEQ; 1140 } else if (status_err & MCI_DATATIMEOUT) { 1141 data->error = -ETIMEDOUT; 1142 } else if (status_err & MCI_STARTBITERR) { 1143 data->error = -ECOMM; 1144 } else if (status_err & MCI_TXUNDERRUN) { 1145 data->error = -EIO; 1146 } else if (status_err & MCI_RXOVERRUN) { 1147 if (success > host->variant->fifosize) 1148 success -= host->variant->fifosize; 1149 else 1150 success = 0; 1151 data->error = -EIO; 1152 } 1153 data->bytes_xfered = round_down(success, data->blksz); 1154 } 1155 1156 if (status & MCI_DATABLOCKEND) 1157 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 1158 1159 if (status & MCI_DATAEND || data->error) { 1160 mmci_dma_finalize(host, data); 1161 1162 mmci_stop_data(host); 1163 1164 if (!data->error) 1165 /* The error clause is handled above, success! */ 1166 data->bytes_xfered = data->blksz * data->blocks; 1167 1168 if (!data->stop || host->mrq->sbc) { 1169 mmci_request_end(host, data->mrq); 1170 } else { 1171 mmci_start_command(host, data->stop, 0); 1172 } 1173 } 1174 } 1175 1176 static void 1177 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 1178 unsigned int status) 1179 { 1180 void __iomem *base = host->base; 1181 bool sbc; 1182 1183 if (!cmd) 1184 return; 1185 1186 sbc = (cmd == host->mrq->sbc); 1187 1188 /* 1189 * We need to be one of these interrupts to be considered worth 1190 * handling. Note that we tag on any latent IRQs postponed 1191 * due to waiting for busy status. 1192 */ 1193 if (!((status|host->busy_status) & 1194 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) 1195 return; 1196 1197 /* 1198 * ST Micro variant: handle busy detection. 1199 */ 1200 if (host->variant->busy_detect) { 1201 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); 1202 1203 /* We are busy with a command, return */ 1204 if (host->busy_status && 1205 (status & host->variant->busy_detect_flag)) 1206 return; 1207 1208 /* 1209 * We were not busy, but we now got a busy response on 1210 * something that was not an error, and we double-check 1211 * that the special busy status bit is still set before 1212 * proceeding. 1213 */ 1214 if (!host->busy_status && busy_resp && 1215 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 1216 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { 1217 1218 /* Clear the busy start IRQ */ 1219 writel(host->variant->busy_detect_mask, 1220 host->base + MMCICLEAR); 1221 1222 /* Unmask the busy end IRQ */ 1223 writel(readl(base + MMCIMASK0) | 1224 host->variant->busy_detect_mask, 1225 base + MMCIMASK0); 1226 /* 1227 * Now cache the last response status code (until 1228 * the busy bit goes low), and return. 1229 */ 1230 host->busy_status = 1231 status & (MCI_CMDSENT|MCI_CMDRESPEND); 1232 return; 1233 } 1234 1235 /* 1236 * At this point we are not busy with a command, we have 1237 * not received a new busy request, clear and mask the busy 1238 * end IRQ and fall through to process the IRQ. 1239 */ 1240 if (host->busy_status) { 1241 1242 writel(host->variant->busy_detect_mask, 1243 host->base + MMCICLEAR); 1244 1245 writel(readl(base + MMCIMASK0) & 1246 ~host->variant->busy_detect_mask, 1247 base + MMCIMASK0); 1248 host->busy_status = 0; 1249 } 1250 } 1251 1252 host->cmd = NULL; 1253 1254 if (status & MCI_CMDTIMEOUT) { 1255 cmd->error = -ETIMEDOUT; 1256 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 1257 cmd->error = -EILSEQ; 1258 } else { 1259 cmd->resp[0] = readl(base + MMCIRESPONSE0); 1260 cmd->resp[1] = readl(base + MMCIRESPONSE1); 1261 cmd->resp[2] = readl(base + MMCIRESPONSE2); 1262 cmd->resp[3] = readl(base + MMCIRESPONSE3); 1263 } 1264 1265 if ((!sbc && !cmd->data) || cmd->error) { 1266 if (host->data) { 1267 /* Terminate the DMA transfer */ 1268 mmci_dma_error(host); 1269 1270 mmci_stop_data(host); 1271 } 1272 mmci_request_end(host, host->mrq); 1273 } else if (sbc) { 1274 mmci_start_command(host, host->mrq->cmd, 0); 1275 } else if (!host->variant->datactrl_first && 1276 !(cmd->data->flags & MMC_DATA_READ)) { 1277 mmci_start_data(host, cmd->data); 1278 } 1279 } 1280 1281 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 1282 { 1283 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1284 } 1285 1286 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1287 { 1288 /* 1289 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1290 * from the fifo range should be used 1291 */ 1292 if (status & MCI_RXFIFOHALFFULL) 1293 return host->variant->fifohalfsize; 1294 else if (status & MCI_RXDATAAVLBL) 1295 return 4; 1296 1297 return 0; 1298 } 1299 1300 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1301 { 1302 void __iomem *base = host->base; 1303 char *ptr = buffer; 1304 u32 status = readl(host->base + MMCISTATUS); 1305 int host_remain = host->size; 1306 1307 do { 1308 int count = host->get_rx_fifocnt(host, status, host_remain); 1309 1310 if (count > remain) 1311 count = remain; 1312 1313 if (count <= 0) 1314 break; 1315 1316 /* 1317 * SDIO especially may want to send something that is 1318 * not divisible by 4 (as opposed to card sectors 1319 * etc). Therefore make sure to always read the last bytes 1320 * while only doing full 32-bit reads towards the FIFO. 1321 */ 1322 if (unlikely(count & 0x3)) { 1323 if (count < 4) { 1324 unsigned char buf[4]; 1325 ioread32_rep(base + MMCIFIFO, buf, 1); 1326 memcpy(ptr, buf, count); 1327 } else { 1328 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1329 count &= ~0x3; 1330 } 1331 } else { 1332 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1333 } 1334 1335 ptr += count; 1336 remain -= count; 1337 host_remain -= count; 1338 1339 if (remain == 0) 1340 break; 1341 1342 status = readl(base + MMCISTATUS); 1343 } while (status & MCI_RXDATAAVLBL); 1344 1345 return ptr - buffer; 1346 } 1347 1348 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1349 { 1350 struct variant_data *variant = host->variant; 1351 void __iomem *base = host->base; 1352 char *ptr = buffer; 1353 1354 do { 1355 unsigned int count, maxcnt; 1356 1357 maxcnt = status & MCI_TXFIFOEMPTY ? 1358 variant->fifosize : variant->fifohalfsize; 1359 count = min(remain, maxcnt); 1360 1361 /* 1362 * SDIO especially may want to send something that is 1363 * not divisible by 4 (as opposed to card sectors 1364 * etc), and the FIFO only accept full 32-bit writes. 1365 * So compensate by adding +3 on the count, a single 1366 * byte become a 32bit write, 7 bytes will be two 1367 * 32bit writes etc. 1368 */ 1369 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1370 1371 ptr += count; 1372 remain -= count; 1373 1374 if (remain == 0) 1375 break; 1376 1377 status = readl(base + MMCISTATUS); 1378 } while (status & MCI_TXFIFOHALFEMPTY); 1379 1380 return ptr - buffer; 1381 } 1382 1383 /* 1384 * PIO data transfer IRQ handler. 1385 */ 1386 static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1387 { 1388 struct mmci_host *host = dev_id; 1389 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1390 struct variant_data *variant = host->variant; 1391 void __iomem *base = host->base; 1392 u32 status; 1393 1394 status = readl(base + MMCISTATUS); 1395 1396 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1397 1398 do { 1399 unsigned int remain, len; 1400 char *buffer; 1401 1402 /* 1403 * For write, we only need to test the half-empty flag 1404 * here - if the FIFO is completely empty, then by 1405 * definition it is more than half empty. 1406 * 1407 * For read, check for data available. 1408 */ 1409 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1410 break; 1411 1412 if (!sg_miter_next(sg_miter)) 1413 break; 1414 1415 buffer = sg_miter->addr; 1416 remain = sg_miter->length; 1417 1418 len = 0; 1419 if (status & MCI_RXACTIVE) 1420 len = mmci_pio_read(host, buffer, remain); 1421 if (status & MCI_TXACTIVE) 1422 len = mmci_pio_write(host, buffer, remain, status); 1423 1424 sg_miter->consumed = len; 1425 1426 host->size -= len; 1427 remain -= len; 1428 1429 if (remain) 1430 break; 1431 1432 status = readl(base + MMCISTATUS); 1433 } while (1); 1434 1435 sg_miter_stop(sg_miter); 1436 1437 /* 1438 * If we have less than the fifo 'half-full' threshold to transfer, 1439 * trigger a PIO interrupt as soon as any data is available. 1440 */ 1441 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1442 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1443 1444 /* 1445 * If we run out of data, disable the data IRQs; this 1446 * prevents a race where the FIFO becomes empty before 1447 * the chip itself has disabled the data path, and 1448 * stops us racing with our data end IRQ. 1449 */ 1450 if (host->size == 0) { 1451 mmci_set_mask1(host, 0); 1452 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1453 } 1454 1455 return IRQ_HANDLED; 1456 } 1457 1458 /* 1459 * Handle completion of command and data transfers. 1460 */ 1461 static irqreturn_t mmci_irq(int irq, void *dev_id) 1462 { 1463 struct mmci_host *host = dev_id; 1464 u32 status; 1465 int ret = 0; 1466 1467 spin_lock(&host->lock); 1468 1469 do { 1470 status = readl(host->base + MMCISTATUS); 1471 1472 if (host->singleirq) { 1473 if (status & host->mask1_reg) 1474 mmci_pio_irq(irq, dev_id); 1475 1476 status &= ~host->variant->irq_pio_mask; 1477 } 1478 1479 /* 1480 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's 1481 * enabled) in mmci_cmd_irq() function where ST Micro busy 1482 * detection variant is handled. Considering the HW seems to be 1483 * triggering the IRQ on both edges while monitoring DAT0 for 1484 * busy completion and that same status bit is used to monitor 1485 * start and end of busy detection, special care must be taken 1486 * to make sure that both start and end interrupts are always 1487 * cleared one after the other. 1488 */ 1489 status &= readl(host->base + MMCIMASK0); 1490 if (host->variant->busy_detect) 1491 writel(status & ~host->variant->busy_detect_mask, 1492 host->base + MMCICLEAR); 1493 else 1494 writel(status, host->base + MMCICLEAR); 1495 1496 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1497 1498 if (host->variant->reversed_irq_handling) { 1499 mmci_data_irq(host, host->data, status); 1500 mmci_cmd_irq(host, host->cmd, status); 1501 } else { 1502 mmci_cmd_irq(host, host->cmd, status); 1503 mmci_data_irq(host, host->data, status); 1504 } 1505 1506 /* 1507 * Don't poll for busy completion in irq context. 1508 */ 1509 if (host->variant->busy_detect && host->busy_status) 1510 status &= ~host->variant->busy_detect_flag; 1511 1512 ret = 1; 1513 } while (status); 1514 1515 spin_unlock(&host->lock); 1516 1517 return IRQ_RETVAL(ret); 1518 } 1519 1520 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1521 { 1522 struct mmci_host *host = mmc_priv(mmc); 1523 unsigned long flags; 1524 1525 WARN_ON(host->mrq != NULL); 1526 1527 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1528 if (mrq->cmd->error) { 1529 mmc_request_done(mmc, mrq); 1530 return; 1531 } 1532 1533 spin_lock_irqsave(&host->lock, flags); 1534 1535 host->mrq = mrq; 1536 1537 if (mrq->data) 1538 mmci_get_next_data(host, mrq->data); 1539 1540 if (mrq->data && 1541 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) 1542 mmci_start_data(host, mrq->data); 1543 1544 if (mrq->sbc) 1545 mmci_start_command(host, mrq->sbc, 0); 1546 else 1547 mmci_start_command(host, mrq->cmd, 0); 1548 1549 spin_unlock_irqrestore(&host->lock, flags); 1550 } 1551 1552 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1553 { 1554 struct mmci_host *host = mmc_priv(mmc); 1555 struct variant_data *variant = host->variant; 1556 u32 pwr = 0; 1557 unsigned long flags; 1558 int ret; 1559 1560 if (host->plat->ios_handler && 1561 host->plat->ios_handler(mmc_dev(mmc), ios)) 1562 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1563 1564 switch (ios->power_mode) { 1565 case MMC_POWER_OFF: 1566 if (!IS_ERR(mmc->supply.vmmc)) 1567 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1568 1569 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1570 regulator_disable(mmc->supply.vqmmc); 1571 host->vqmmc_enabled = false; 1572 } 1573 1574 break; 1575 case MMC_POWER_UP: 1576 if (!IS_ERR(mmc->supply.vmmc)) 1577 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1578 1579 /* 1580 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1581 * and instead uses MCI_PWR_ON so apply whatever value is 1582 * configured in the variant data. 1583 */ 1584 pwr |= variant->pwrreg_powerup; 1585 1586 break; 1587 case MMC_POWER_ON: 1588 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1589 ret = regulator_enable(mmc->supply.vqmmc); 1590 if (ret < 0) 1591 dev_err(mmc_dev(mmc), 1592 "failed to enable vqmmc regulator\n"); 1593 else 1594 host->vqmmc_enabled = true; 1595 } 1596 1597 pwr |= MCI_PWR_ON; 1598 break; 1599 } 1600 1601 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1602 /* 1603 * The ST Micro variant has some additional bits 1604 * indicating signal direction for the signals in 1605 * the SD/MMC bus and feedback-clock usage. 1606 */ 1607 pwr |= host->pwr_reg_add; 1608 1609 if (ios->bus_width == MMC_BUS_WIDTH_4) 1610 pwr &= ~MCI_ST_DATA74DIREN; 1611 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1612 pwr &= (~MCI_ST_DATA74DIREN & 1613 ~MCI_ST_DATA31DIREN & 1614 ~MCI_ST_DATA2DIREN); 1615 } 1616 1617 if (variant->opendrain) { 1618 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1619 pwr |= variant->opendrain; 1620 } else { 1621 /* 1622 * If the variant cannot configure the pads by its own, then we 1623 * expect the pinctrl to be able to do that for us 1624 */ 1625 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1626 pinctrl_select_state(host->pinctrl, host->pins_opendrain); 1627 else 1628 pinctrl_select_state(host->pinctrl, host->pins_default); 1629 } 1630 1631 /* 1632 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1633 * gating the clock, the MCI_PWR_ON bit is cleared. 1634 */ 1635 if (!ios->clock && variant->pwrreg_clkgate) 1636 pwr &= ~MCI_PWR_ON; 1637 1638 if (host->variant->explicit_mclk_control && 1639 ios->clock != host->clock_cache) { 1640 ret = clk_set_rate(host->clk, ios->clock); 1641 if (ret < 0) 1642 dev_err(mmc_dev(host->mmc), 1643 "Error setting clock rate (%d)\n", ret); 1644 else 1645 host->mclk = clk_get_rate(host->clk); 1646 } 1647 host->clock_cache = ios->clock; 1648 1649 spin_lock_irqsave(&host->lock, flags); 1650 1651 if (host->ops && host->ops->set_clkreg) 1652 host->ops->set_clkreg(host, ios->clock); 1653 else 1654 mmci_set_clkreg(host, ios->clock); 1655 1656 if (host->ops && host->ops->set_pwrreg) 1657 host->ops->set_pwrreg(host, pwr); 1658 else 1659 mmci_write_pwrreg(host, pwr); 1660 1661 mmci_reg_delay(host); 1662 1663 spin_unlock_irqrestore(&host->lock, flags); 1664 } 1665 1666 static int mmci_get_cd(struct mmc_host *mmc) 1667 { 1668 struct mmci_host *host = mmc_priv(mmc); 1669 struct mmci_platform_data *plat = host->plat; 1670 unsigned int status = mmc_gpio_get_cd(mmc); 1671 1672 if (status == -ENOSYS) { 1673 if (!plat->status) 1674 return 1; /* Assume always present */ 1675 1676 status = plat->status(mmc_dev(host->mmc)); 1677 } 1678 return status; 1679 } 1680 1681 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1682 { 1683 int ret = 0; 1684 1685 if (!IS_ERR(mmc->supply.vqmmc)) { 1686 1687 switch (ios->signal_voltage) { 1688 case MMC_SIGNAL_VOLTAGE_330: 1689 ret = regulator_set_voltage(mmc->supply.vqmmc, 1690 2700000, 3600000); 1691 break; 1692 case MMC_SIGNAL_VOLTAGE_180: 1693 ret = regulator_set_voltage(mmc->supply.vqmmc, 1694 1700000, 1950000); 1695 break; 1696 case MMC_SIGNAL_VOLTAGE_120: 1697 ret = regulator_set_voltage(mmc->supply.vqmmc, 1698 1100000, 1300000); 1699 break; 1700 } 1701 1702 if (ret) 1703 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1704 } 1705 1706 return ret; 1707 } 1708 1709 static struct mmc_host_ops mmci_ops = { 1710 .request = mmci_request, 1711 .pre_req = mmci_pre_request, 1712 .post_req = mmci_post_request, 1713 .set_ios = mmci_set_ios, 1714 .get_ro = mmc_gpio_get_ro, 1715 .get_cd = mmci_get_cd, 1716 .start_signal_voltage_switch = mmci_sig_volt_switch, 1717 }; 1718 1719 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1720 { 1721 struct mmci_host *host = mmc_priv(mmc); 1722 int ret = mmc_of_parse(mmc); 1723 1724 if (ret) 1725 return ret; 1726 1727 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1728 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1729 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1730 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1731 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1732 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1733 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1734 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1735 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1736 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1737 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1738 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1739 1740 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1741 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1742 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1743 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1744 1745 return 0; 1746 } 1747 1748 static int mmci_probe(struct amba_device *dev, 1749 const struct amba_id *id) 1750 { 1751 struct mmci_platform_data *plat = dev->dev.platform_data; 1752 struct device_node *np = dev->dev.of_node; 1753 struct variant_data *variant = id->data; 1754 struct mmci_host *host; 1755 struct mmc_host *mmc; 1756 int ret; 1757 1758 /* Must have platform data or Device Tree. */ 1759 if (!plat && !np) { 1760 dev_err(&dev->dev, "No plat data or DT found\n"); 1761 return -EINVAL; 1762 } 1763 1764 if (!plat) { 1765 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1766 if (!plat) 1767 return -ENOMEM; 1768 } 1769 1770 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1771 if (!mmc) 1772 return -ENOMEM; 1773 1774 ret = mmci_of_parse(np, mmc); 1775 if (ret) 1776 goto host_free; 1777 1778 host = mmc_priv(mmc); 1779 host->mmc = mmc; 1780 1781 /* 1782 * Some variant (STM32) doesn't have opendrain bit, nevertheless 1783 * pins can be set accordingly using pinctrl 1784 */ 1785 if (!variant->opendrain) { 1786 host->pinctrl = devm_pinctrl_get(&dev->dev); 1787 if (IS_ERR(host->pinctrl)) { 1788 dev_err(&dev->dev, "failed to get pinctrl"); 1789 ret = PTR_ERR(host->pinctrl); 1790 goto host_free; 1791 } 1792 1793 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1794 PINCTRL_STATE_DEFAULT); 1795 if (IS_ERR(host->pins_default)) { 1796 dev_err(mmc_dev(mmc), "Can't select default pins\n"); 1797 ret = PTR_ERR(host->pins_default); 1798 goto host_free; 1799 } 1800 1801 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, 1802 MMCI_PINCTRL_STATE_OPENDRAIN); 1803 if (IS_ERR(host->pins_opendrain)) { 1804 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); 1805 ret = PTR_ERR(host->pins_opendrain); 1806 goto host_free; 1807 } 1808 } 1809 1810 host->hw_designer = amba_manf(dev); 1811 host->hw_revision = amba_rev(dev); 1812 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1813 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1814 1815 host->clk = devm_clk_get(&dev->dev, NULL); 1816 if (IS_ERR(host->clk)) { 1817 ret = PTR_ERR(host->clk); 1818 goto host_free; 1819 } 1820 1821 ret = clk_prepare_enable(host->clk); 1822 if (ret) 1823 goto host_free; 1824 1825 if (variant->qcom_fifo) 1826 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1827 else 1828 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1829 1830 host->plat = plat; 1831 host->variant = variant; 1832 host->mclk = clk_get_rate(host->clk); 1833 /* 1834 * According to the spec, mclk is max 100 MHz, 1835 * so we try to adjust the clock down to this, 1836 * (if possible). 1837 */ 1838 if (host->mclk > variant->f_max) { 1839 ret = clk_set_rate(host->clk, variant->f_max); 1840 if (ret < 0) 1841 goto clk_disable; 1842 host->mclk = clk_get_rate(host->clk); 1843 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1844 host->mclk); 1845 } 1846 1847 host->phybase = dev->res.start; 1848 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1849 if (IS_ERR(host->base)) { 1850 ret = PTR_ERR(host->base); 1851 goto clk_disable; 1852 } 1853 1854 if (variant->init) 1855 variant->init(host); 1856 1857 /* 1858 * The ARM and ST versions of the block have slightly different 1859 * clock divider equations which means that the minimum divider 1860 * differs too. 1861 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1862 */ 1863 if (variant->st_clkdiv) 1864 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1865 else if (variant->explicit_mclk_control) 1866 mmc->f_min = clk_round_rate(host->clk, 100000); 1867 else 1868 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1869 /* 1870 * If no maximum operating frequency is supplied, fall back to use 1871 * the module parameter, which has a (low) default value in case it 1872 * is not specified. Either value must not exceed the clock rate into 1873 * the block, of course. 1874 */ 1875 if (mmc->f_max) 1876 mmc->f_max = variant->explicit_mclk_control ? 1877 min(variant->f_max, mmc->f_max) : 1878 min(host->mclk, mmc->f_max); 1879 else 1880 mmc->f_max = variant->explicit_mclk_control ? 1881 fmax : min(host->mclk, fmax); 1882 1883 1884 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1885 1886 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); 1887 if (IS_ERR(host->rst)) { 1888 ret = PTR_ERR(host->rst); 1889 goto clk_disable; 1890 } 1891 1892 /* Get regulators and the supported OCR mask */ 1893 ret = mmc_regulator_get_supply(mmc); 1894 if (ret) 1895 goto clk_disable; 1896 1897 if (!mmc->ocr_avail) 1898 mmc->ocr_avail = plat->ocr_mask; 1899 else if (plat->ocr_mask) 1900 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1901 1902 /* We support these capabilities. */ 1903 mmc->caps |= MMC_CAP_CMD23; 1904 1905 /* 1906 * Enable busy detection. 1907 */ 1908 if (variant->busy_detect) { 1909 mmci_ops.card_busy = mmci_card_busy; 1910 /* 1911 * Not all variants have a flag to enable busy detection 1912 * in the DPSM, but if they do, set it here. 1913 */ 1914 if (variant->busy_dpsm_flag) 1915 mmci_write_datactrlreg(host, 1916 host->variant->busy_dpsm_flag); 1917 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1918 mmc->max_busy_timeout = 0; 1919 } 1920 1921 mmc->ops = &mmci_ops; 1922 1923 /* We support these PM capabilities. */ 1924 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1925 1926 /* 1927 * We can do SGIO 1928 */ 1929 mmc->max_segs = NR_SG; 1930 1931 /* 1932 * Since only a certain number of bits are valid in the data length 1933 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1934 * single request. 1935 */ 1936 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1937 1938 /* 1939 * Set the maximum segment size. Since we aren't doing DMA 1940 * (yet) we are only limited by the data length register. 1941 */ 1942 mmc->max_seg_size = mmc->max_req_size; 1943 1944 /* 1945 * Block size can be up to 2048 bytes, but must be a power of two. 1946 */ 1947 mmc->max_blk_size = 1 << variant->datactrl_blocksz; 1948 1949 /* 1950 * Limit the number of blocks transferred so that we don't overflow 1951 * the maximum request size. 1952 */ 1953 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; 1954 1955 spin_lock_init(&host->lock); 1956 1957 writel(0, host->base + MMCIMASK0); 1958 1959 if (variant->mmcimask1) 1960 writel(0, host->base + MMCIMASK1); 1961 1962 writel(0xfff, host->base + MMCICLEAR); 1963 1964 /* 1965 * If: 1966 * - not using DT but using a descriptor table, or 1967 * - using a table of descriptors ALONGSIDE DT, or 1968 * look up these descriptors named "cd" and "wp" right here, fail 1969 * silently of these do not exist 1970 */ 1971 if (!np) { 1972 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); 1973 if (ret == -EPROBE_DEFER) 1974 goto clk_disable; 1975 1976 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL); 1977 if (ret == -EPROBE_DEFER) 1978 goto clk_disable; 1979 } 1980 1981 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1982 DRIVER_NAME " (cmd)", host); 1983 if (ret) 1984 goto clk_disable; 1985 1986 if (!dev->irq[1]) 1987 host->singleirq = true; 1988 else { 1989 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1990 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1991 if (ret) 1992 goto clk_disable; 1993 } 1994 1995 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); 1996 1997 amba_set_drvdata(dev, mmc); 1998 1999 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 2000 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 2001 amba_rev(dev), (unsigned long long)dev->res.start, 2002 dev->irq[0], dev->irq[1]); 2003 2004 mmci_dma_setup(host); 2005 2006 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 2007 pm_runtime_use_autosuspend(&dev->dev); 2008 2009 mmc_add_host(mmc); 2010 2011 pm_runtime_put(&dev->dev); 2012 return 0; 2013 2014 clk_disable: 2015 clk_disable_unprepare(host->clk); 2016 host_free: 2017 mmc_free_host(mmc); 2018 return ret; 2019 } 2020 2021 static int mmci_remove(struct amba_device *dev) 2022 { 2023 struct mmc_host *mmc = amba_get_drvdata(dev); 2024 2025 if (mmc) { 2026 struct mmci_host *host = mmc_priv(mmc); 2027 struct variant_data *variant = host->variant; 2028 2029 /* 2030 * Undo pm_runtime_put() in probe. We use the _sync 2031 * version here so that we can access the primecell. 2032 */ 2033 pm_runtime_get_sync(&dev->dev); 2034 2035 mmc_remove_host(mmc); 2036 2037 writel(0, host->base + MMCIMASK0); 2038 2039 if (variant->mmcimask1) 2040 writel(0, host->base + MMCIMASK1); 2041 2042 writel(0, host->base + MMCICOMMAND); 2043 writel(0, host->base + MMCIDATACTRL); 2044 2045 mmci_dma_release(host); 2046 clk_disable_unprepare(host->clk); 2047 mmc_free_host(mmc); 2048 } 2049 2050 return 0; 2051 } 2052 2053 #ifdef CONFIG_PM 2054 static void mmci_save(struct mmci_host *host) 2055 { 2056 unsigned long flags; 2057 2058 spin_lock_irqsave(&host->lock, flags); 2059 2060 writel(0, host->base + MMCIMASK0); 2061 if (host->variant->pwrreg_nopower) { 2062 writel(0, host->base + MMCIDATACTRL); 2063 writel(0, host->base + MMCIPOWER); 2064 writel(0, host->base + MMCICLOCK); 2065 } 2066 mmci_reg_delay(host); 2067 2068 spin_unlock_irqrestore(&host->lock, flags); 2069 } 2070 2071 static void mmci_restore(struct mmci_host *host) 2072 { 2073 unsigned long flags; 2074 2075 spin_lock_irqsave(&host->lock, flags); 2076 2077 if (host->variant->pwrreg_nopower) { 2078 writel(host->clk_reg, host->base + MMCICLOCK); 2079 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 2080 writel(host->pwr_reg, host->base + MMCIPOWER); 2081 } 2082 writel(MCI_IRQENABLE | host->variant->start_err, 2083 host->base + MMCIMASK0); 2084 mmci_reg_delay(host); 2085 2086 spin_unlock_irqrestore(&host->lock, flags); 2087 } 2088 2089 static int mmci_runtime_suspend(struct device *dev) 2090 { 2091 struct amba_device *adev = to_amba_device(dev); 2092 struct mmc_host *mmc = amba_get_drvdata(adev); 2093 2094 if (mmc) { 2095 struct mmci_host *host = mmc_priv(mmc); 2096 pinctrl_pm_select_sleep_state(dev); 2097 mmci_save(host); 2098 clk_disable_unprepare(host->clk); 2099 } 2100 2101 return 0; 2102 } 2103 2104 static int mmci_runtime_resume(struct device *dev) 2105 { 2106 struct amba_device *adev = to_amba_device(dev); 2107 struct mmc_host *mmc = amba_get_drvdata(adev); 2108 2109 if (mmc) { 2110 struct mmci_host *host = mmc_priv(mmc); 2111 clk_prepare_enable(host->clk); 2112 mmci_restore(host); 2113 pinctrl_pm_select_default_state(dev); 2114 } 2115 2116 return 0; 2117 } 2118 #endif 2119 2120 static const struct dev_pm_ops mmci_dev_pm_ops = { 2121 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2122 pm_runtime_force_resume) 2123 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 2124 }; 2125 2126 static const struct amba_id mmci_ids[] = { 2127 { 2128 .id = 0x00041180, 2129 .mask = 0xff0fffff, 2130 .data = &variant_arm, 2131 }, 2132 { 2133 .id = 0x01041180, 2134 .mask = 0xff0fffff, 2135 .data = &variant_arm_extended_fifo, 2136 }, 2137 { 2138 .id = 0x02041180, 2139 .mask = 0xff0fffff, 2140 .data = &variant_arm_extended_fifo_hwfc, 2141 }, 2142 { 2143 .id = 0x00041181, 2144 .mask = 0x000fffff, 2145 .data = &variant_arm, 2146 }, 2147 /* ST Micro variants */ 2148 { 2149 .id = 0x00180180, 2150 .mask = 0x00ffffff, 2151 .data = &variant_u300, 2152 }, 2153 { 2154 .id = 0x10180180, 2155 .mask = 0xf0ffffff, 2156 .data = &variant_nomadik, 2157 }, 2158 { 2159 .id = 0x00280180, 2160 .mask = 0x00ffffff, 2161 .data = &variant_nomadik, 2162 }, 2163 { 2164 .id = 0x00480180, 2165 .mask = 0xf0ffffff, 2166 .data = &variant_ux500, 2167 }, 2168 { 2169 .id = 0x10480180, 2170 .mask = 0xf0ffffff, 2171 .data = &variant_ux500v2, 2172 }, 2173 { 2174 .id = 0x00880180, 2175 .mask = 0x00ffffff, 2176 .data = &variant_stm32, 2177 }, 2178 /* Qualcomm variants */ 2179 { 2180 .id = 0x00051180, 2181 .mask = 0x000fffff, 2182 .data = &variant_qcom, 2183 }, 2184 { 0, 0 }, 2185 }; 2186 2187 MODULE_DEVICE_TABLE(amba, mmci_ids); 2188 2189 static struct amba_driver mmci_driver = { 2190 .drv = { 2191 .name = DRIVER_NAME, 2192 .pm = &mmci_dev_pm_ops, 2193 }, 2194 .probe = mmci_probe, 2195 .remove = mmci_remove, 2196 .id_table = mmci_ids, 2197 }; 2198 2199 module_amba_driver(mmci_driver); 2200 2201 module_param(fmax, uint, 0444); 2202 2203 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 2204 MODULE_LICENSE("GPL"); 2205