11c6a0718SPierre Ossman /* 270f10482SPierre Ossman * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 31c6a0718SPierre Ossman * 41c6a0718SPierre Ossman * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5c8ebae37SRussell King * Copyright (C) 2010 ST-Ericsson SA 61c6a0718SPierre Ossman * 71c6a0718SPierre Ossman * This program is free software; you can redistribute it and/or modify 81c6a0718SPierre Ossman * it under the terms of the GNU General Public License version 2 as 91c6a0718SPierre Ossman * published by the Free Software Foundation. 101c6a0718SPierre Ossman */ 111c6a0718SPierre Ossman #include <linux/module.h> 121c6a0718SPierre Ossman #include <linux/moduleparam.h> 131c6a0718SPierre Ossman #include <linux/init.h> 141c6a0718SPierre Ossman #include <linux/ioport.h> 151c6a0718SPierre Ossman #include <linux/device.h> 161c6a0718SPierre Ossman #include <linux/interrupt.h> 17613b152cSRussell King #include <linux/kernel.h> 181c6a0718SPierre Ossman #include <linux/delay.h> 191c6a0718SPierre Ossman #include <linux/err.h> 201c6a0718SPierre Ossman #include <linux/highmem.h> 21019a5f56SNicolas Pitre #include <linux/log2.h> 221c6a0718SPierre Ossman #include <linux/mmc/host.h> 2334177802SLinus Walleij #include <linux/mmc/card.h> 241c6a0718SPierre Ossman #include <linux/amba/bus.h> 251c6a0718SPierre Ossman #include <linux/clk.h> 26bd6dee6fSJens Axboe #include <linux/scatterlist.h> 2789001446SRussell King #include <linux/gpio.h> 2834e84f39SLinus Walleij #include <linux/regulator/consumer.h> 29c8ebae37SRussell King #include <linux/dmaengine.h> 30c8ebae37SRussell King #include <linux/dma-mapping.h> 31c8ebae37SRussell King #include <linux/amba/mmci.h> 321c3be369SRussell King #include <linux/pm_runtime.h> 331c6a0718SPierre Ossman 341c6a0718SPierre Ossman #include <asm/div64.h> 351c6a0718SPierre Ossman #include <asm/io.h> 361c6a0718SPierre Ossman #include <asm/sizes.h> 371c6a0718SPierre Ossman 381c6a0718SPierre Ossman #include "mmci.h" 391c6a0718SPierre Ossman 401c6a0718SPierre Ossman #define DRIVER_NAME "mmci-pl18x" 411c6a0718SPierre Ossman 421c6a0718SPierre Ossman static unsigned int fmax = 515633; 431c6a0718SPierre Ossman 444956e109SRabin Vincent /** 454956e109SRabin Vincent * struct variant_data - MMCI variant-specific quirks 464956e109SRabin Vincent * @clkreg: default value for MCICLOCK register 474380c14fSRabin Vincent * @clkreg_enable: enable value for MMCICLOCK register 4808458ef6SRabin Vincent * @datalength_bits: number of bits in the MMCIDATALENGTH register 498301bb68SRabin Vincent * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 508301bb68SRabin Vincent * is asserted (likewise for RX) 518301bb68SRabin Vincent * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 528301bb68SRabin Vincent * is asserted (likewise for RX) 5334177802SLinus Walleij * @sdio: variant supports SDIO 54b70a67f9SLinus Walleij * @st_clkdiv: true if using a ST-specific clock divider algorithm 551784b157SPhilippe Langlais * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 567d72a1d4SUlf Hansson * @pwrreg_powerup: power up value for MMCIPOWER register 574d1a3a0dSUlf Hansson * @signal_direction: input/out direction of bus signals can be indicated 584956e109SRabin Vincent */ 594956e109SRabin Vincent struct variant_data { 604956e109SRabin Vincent unsigned int clkreg; 614380c14fSRabin Vincent unsigned int clkreg_enable; 6208458ef6SRabin Vincent unsigned int datalength_bits; 638301bb68SRabin Vincent unsigned int fifosize; 648301bb68SRabin Vincent unsigned int fifohalfsize; 6534177802SLinus Walleij bool sdio; 66b70a67f9SLinus Walleij bool st_clkdiv; 671784b157SPhilippe Langlais bool blksz_datactrl16; 687d72a1d4SUlf Hansson u32 pwrreg_powerup; 694d1a3a0dSUlf Hansson bool signal_direction; 704956e109SRabin Vincent }; 714956e109SRabin Vincent 724956e109SRabin Vincent static struct variant_data variant_arm = { 738301bb68SRabin Vincent .fifosize = 16 * 4, 748301bb68SRabin Vincent .fifohalfsize = 8 * 4, 7508458ef6SRabin Vincent .datalength_bits = 16, 767d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 774956e109SRabin Vincent }; 784956e109SRabin Vincent 79768fbc18SPawel Moll static struct variant_data variant_arm_extended_fifo = { 80768fbc18SPawel Moll .fifosize = 128 * 4, 81768fbc18SPawel Moll .fifohalfsize = 64 * 4, 82768fbc18SPawel Moll .datalength_bits = 16, 837d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_UP, 84768fbc18SPawel Moll }; 85768fbc18SPawel Moll 864956e109SRabin Vincent static struct variant_data variant_u300 = { 878301bb68SRabin Vincent .fifosize = 16 * 4, 888301bb68SRabin Vincent .fifohalfsize = 8 * 4, 8949ac215eSLinus Walleij .clkreg_enable = MCI_ST_U300_HWFCEN, 9008458ef6SRabin Vincent .datalength_bits = 16, 9134177802SLinus Walleij .sdio = true, 927d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 934d1a3a0dSUlf Hansson .signal_direction = true, 944956e109SRabin Vincent }; 954956e109SRabin Vincent 964956e109SRabin Vincent static struct variant_data variant_ux500 = { 978301bb68SRabin Vincent .fifosize = 30 * 4, 988301bb68SRabin Vincent .fifohalfsize = 8 * 4, 994956e109SRabin Vincent .clkreg = MCI_CLK_ENABLE, 10049ac215eSLinus Walleij .clkreg_enable = MCI_ST_UX500_HWFCEN, 10108458ef6SRabin Vincent .datalength_bits = 24, 10234177802SLinus Walleij .sdio = true, 103b70a67f9SLinus Walleij .st_clkdiv = true, 1047d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1054d1a3a0dSUlf Hansson .signal_direction = true, 1064956e109SRabin Vincent }; 107b70a67f9SLinus Walleij 1081784b157SPhilippe Langlais static struct variant_data variant_ux500v2 = { 1091784b157SPhilippe Langlais .fifosize = 30 * 4, 1101784b157SPhilippe Langlais .fifohalfsize = 8 * 4, 1111784b157SPhilippe Langlais .clkreg = MCI_CLK_ENABLE, 1121784b157SPhilippe Langlais .clkreg_enable = MCI_ST_UX500_HWFCEN, 1131784b157SPhilippe Langlais .datalength_bits = 24, 1141784b157SPhilippe Langlais .sdio = true, 1151784b157SPhilippe Langlais .st_clkdiv = true, 1161784b157SPhilippe Langlais .blksz_datactrl16 = true, 1177d72a1d4SUlf Hansson .pwrreg_powerup = MCI_PWR_ON, 1184d1a3a0dSUlf Hansson .signal_direction = true, 1191784b157SPhilippe Langlais }; 1201784b157SPhilippe Langlais 121a6a6464aSLinus Walleij /* 122a6a6464aSLinus Walleij * This must be called with host->lock held 123a6a6464aSLinus Walleij */ 124a6a6464aSLinus Walleij static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 125a6a6464aSLinus Walleij { 1264956e109SRabin Vincent struct variant_data *variant = host->variant; 1274956e109SRabin Vincent u32 clk = variant->clkreg; 128a6a6464aSLinus Walleij 129a6a6464aSLinus Walleij if (desired) { 130a6a6464aSLinus Walleij if (desired >= host->mclk) { 131a6a6464aSLinus Walleij clk = MCI_CLK_BYPASS; 132399bc486SLinus Walleij if (variant->st_clkdiv) 133399bc486SLinus Walleij clk |= MCI_ST_UX500_NEG_EDGE; 134a6a6464aSLinus Walleij host->cclk = host->mclk; 135b70a67f9SLinus Walleij } else if (variant->st_clkdiv) { 136b70a67f9SLinus Walleij /* 137b70a67f9SLinus Walleij * DB8500 TRM says f = mclk / (clkdiv + 2) 138b70a67f9SLinus Walleij * => clkdiv = (mclk / f) - 2 139b70a67f9SLinus Walleij * Round the divider up so we don't exceed the max 140b70a67f9SLinus Walleij * frequency 141b70a67f9SLinus Walleij */ 142b70a67f9SLinus Walleij clk = DIV_ROUND_UP(host->mclk, desired) - 2; 143b70a67f9SLinus Walleij if (clk >= 256) 144b70a67f9SLinus Walleij clk = 255; 145b70a67f9SLinus Walleij host->cclk = host->mclk / (clk + 2); 146a6a6464aSLinus Walleij } else { 147b70a67f9SLinus Walleij /* 148b70a67f9SLinus Walleij * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 149b70a67f9SLinus Walleij * => clkdiv = mclk / (2 * f) - 1 150b70a67f9SLinus Walleij */ 151a6a6464aSLinus Walleij clk = host->mclk / (2 * desired) - 1; 152a6a6464aSLinus Walleij if (clk >= 256) 153a6a6464aSLinus Walleij clk = 255; 154a6a6464aSLinus Walleij host->cclk = host->mclk / (2 * (clk + 1)); 155a6a6464aSLinus Walleij } 1564380c14fSRabin Vincent 1574380c14fSRabin Vincent clk |= variant->clkreg_enable; 158a6a6464aSLinus Walleij clk |= MCI_CLK_ENABLE; 159a6a6464aSLinus Walleij /* This hasn't proven to be worthwhile */ 160a6a6464aSLinus Walleij /* clk |= MCI_CLK_PWRSAVE; */ 161a6a6464aSLinus Walleij } 162a6a6464aSLinus Walleij 1639e6c82cdSLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 164771dc157SLinus Walleij clk |= MCI_4BIT_BUS; 165771dc157SLinus Walleij if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 166771dc157SLinus Walleij clk |= MCI_ST_8BIT_BUS; 1679e6c82cdSLinus Walleij 168a6a6464aSLinus Walleij writel(clk, host->base + MMCICLOCK); 169a6a6464aSLinus Walleij } 170a6a6464aSLinus Walleij 1711c6a0718SPierre Ossman static void 1721c6a0718SPierre Ossman mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 1731c6a0718SPierre Ossman { 1741c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 1751c6a0718SPierre Ossman 1761c6a0718SPierre Ossman BUG_ON(host->data); 1771c6a0718SPierre Ossman 1781c6a0718SPierre Ossman host->mrq = NULL; 1791c6a0718SPierre Ossman host->cmd = NULL; 1801c6a0718SPierre Ossman 1811c3be369SRussell King pm_runtime_put(mmc_dev(host->mmc)); 1821c6a0718SPierre Ossman mmc_request_done(host->mmc, mrq); 1831c6a0718SPierre Ossman } 1841c6a0718SPierre Ossman 1852686b4b4SLinus Walleij static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 1862686b4b4SLinus Walleij { 1872686b4b4SLinus Walleij void __iomem *base = host->base; 1882686b4b4SLinus Walleij 1892686b4b4SLinus Walleij if (host->singleirq) { 1902686b4b4SLinus Walleij unsigned int mask0 = readl(base + MMCIMASK0); 1912686b4b4SLinus Walleij 1922686b4b4SLinus Walleij mask0 &= ~MCI_IRQ1MASK; 1932686b4b4SLinus Walleij mask0 |= mask; 1942686b4b4SLinus Walleij 1952686b4b4SLinus Walleij writel(mask0, base + MMCIMASK0); 1962686b4b4SLinus Walleij } 1972686b4b4SLinus Walleij 1982686b4b4SLinus Walleij writel(mask, base + MMCIMASK1); 1992686b4b4SLinus Walleij } 2002686b4b4SLinus Walleij 2011c6a0718SPierre Ossman static void mmci_stop_data(struct mmci_host *host) 2021c6a0718SPierre Ossman { 2031c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 2042686b4b4SLinus Walleij mmci_set_mask1(host, 0); 2051c6a0718SPierre Ossman host->data = NULL; 2061c6a0718SPierre Ossman } 2071c6a0718SPierre Ossman 2084ce1d6cbSRabin Vincent static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 2094ce1d6cbSRabin Vincent { 2104ce1d6cbSRabin Vincent unsigned int flags = SG_MITER_ATOMIC; 2114ce1d6cbSRabin Vincent 2124ce1d6cbSRabin Vincent if (data->flags & MMC_DATA_READ) 2134ce1d6cbSRabin Vincent flags |= SG_MITER_TO_SG; 2144ce1d6cbSRabin Vincent else 2154ce1d6cbSRabin Vincent flags |= SG_MITER_FROM_SG; 2164ce1d6cbSRabin Vincent 2174ce1d6cbSRabin Vincent sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 2184ce1d6cbSRabin Vincent } 2194ce1d6cbSRabin Vincent 220c8ebae37SRussell King /* 221c8ebae37SRussell King * All the DMA operation mode stuff goes inside this ifdef. 222c8ebae37SRussell King * This assumes that you have a generic DMA device interface, 223c8ebae37SRussell King * no custom DMA interfaces are supported. 224c8ebae37SRussell King */ 225c8ebae37SRussell King #ifdef CONFIG_DMA_ENGINE 226c8ebae37SRussell King static void __devinit mmci_dma_setup(struct mmci_host *host) 227c8ebae37SRussell King { 228c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 229c8ebae37SRussell King const char *rxname, *txname; 230c8ebae37SRussell King dma_cap_mask_t mask; 231c8ebae37SRussell King 232c8ebae37SRussell King if (!plat || !plat->dma_filter) { 233c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 234c8ebae37SRussell King return; 235c8ebae37SRussell King } 236c8ebae37SRussell King 23758c7ccbfSPer Forlin /* initialize pre request cookie */ 23858c7ccbfSPer Forlin host->next_data.cookie = 1; 23958c7ccbfSPer Forlin 240c8ebae37SRussell King /* Try to acquire a generic DMA engine slave channel */ 241c8ebae37SRussell King dma_cap_zero(mask); 242c8ebae37SRussell King dma_cap_set(DMA_SLAVE, mask); 243c8ebae37SRussell King 244c8ebae37SRussell King /* 245c8ebae37SRussell King * If only an RX channel is specified, the driver will 246c8ebae37SRussell King * attempt to use it bidirectionally, however if it is 247c8ebae37SRussell King * is specified but cannot be located, DMA will be disabled. 248c8ebae37SRussell King */ 249c8ebae37SRussell King if (plat->dma_rx_param) { 250c8ebae37SRussell King host->dma_rx_channel = dma_request_channel(mask, 251c8ebae37SRussell King plat->dma_filter, 252c8ebae37SRussell King plat->dma_rx_param); 253c8ebae37SRussell King /* E.g if no DMA hardware is present */ 254c8ebae37SRussell King if (!host->dma_rx_channel) 255c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 256c8ebae37SRussell King } 257c8ebae37SRussell King 258c8ebae37SRussell King if (plat->dma_tx_param) { 259c8ebae37SRussell King host->dma_tx_channel = dma_request_channel(mask, 260c8ebae37SRussell King plat->dma_filter, 261c8ebae37SRussell King plat->dma_tx_param); 262c8ebae37SRussell King if (!host->dma_tx_channel) 263c8ebae37SRussell King dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 264c8ebae37SRussell King } else { 265c8ebae37SRussell King host->dma_tx_channel = host->dma_rx_channel; 266c8ebae37SRussell King } 267c8ebae37SRussell King 268c8ebae37SRussell King if (host->dma_rx_channel) 269c8ebae37SRussell King rxname = dma_chan_name(host->dma_rx_channel); 270c8ebae37SRussell King else 271c8ebae37SRussell King rxname = "none"; 272c8ebae37SRussell King 273c8ebae37SRussell King if (host->dma_tx_channel) 274c8ebae37SRussell King txname = dma_chan_name(host->dma_tx_channel); 275c8ebae37SRussell King else 276c8ebae37SRussell King txname = "none"; 277c8ebae37SRussell King 278c8ebae37SRussell King dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 279c8ebae37SRussell King rxname, txname); 280c8ebae37SRussell King 281c8ebae37SRussell King /* 282c8ebae37SRussell King * Limit the maximum segment size in any SG entry according to 283c8ebae37SRussell King * the parameters of the DMA engine device. 284c8ebae37SRussell King */ 285c8ebae37SRussell King if (host->dma_tx_channel) { 286c8ebae37SRussell King struct device *dev = host->dma_tx_channel->device->dev; 287c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 288c8ebae37SRussell King 289c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 290c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 291c8ebae37SRussell King } 292c8ebae37SRussell King if (host->dma_rx_channel) { 293c8ebae37SRussell King struct device *dev = host->dma_rx_channel->device->dev; 294c8ebae37SRussell King unsigned int max_seg_size = dma_get_max_seg_size(dev); 295c8ebae37SRussell King 296c8ebae37SRussell King if (max_seg_size < host->mmc->max_seg_size) 297c8ebae37SRussell King host->mmc->max_seg_size = max_seg_size; 298c8ebae37SRussell King } 299c8ebae37SRussell King } 300c8ebae37SRussell King 301c8ebae37SRussell King /* 302c8ebae37SRussell King * This is used in __devinit or __devexit so inline it 303c8ebae37SRussell King * so it can be discarded. 304c8ebae37SRussell King */ 305c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 306c8ebae37SRussell King { 307c8ebae37SRussell King struct mmci_platform_data *plat = host->plat; 308c8ebae37SRussell King 309c8ebae37SRussell King if (host->dma_rx_channel) 310c8ebae37SRussell King dma_release_channel(host->dma_rx_channel); 311c8ebae37SRussell King if (host->dma_tx_channel && plat->dma_tx_param) 312c8ebae37SRussell King dma_release_channel(host->dma_tx_channel); 313c8ebae37SRussell King host->dma_rx_channel = host->dma_tx_channel = NULL; 314c8ebae37SRussell King } 315c8ebae37SRussell King 316c8ebae37SRussell King static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 317c8ebae37SRussell King { 318c8ebae37SRussell King struct dma_chan *chan = host->dma_current; 319c8ebae37SRussell King enum dma_data_direction dir; 320c8ebae37SRussell King u32 status; 321c8ebae37SRussell King int i; 322c8ebae37SRussell King 323c8ebae37SRussell King /* Wait up to 1ms for the DMA to complete */ 324c8ebae37SRussell King for (i = 0; ; i++) { 325c8ebae37SRussell King status = readl(host->base + MMCISTATUS); 326c8ebae37SRussell King if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 327c8ebae37SRussell King break; 328c8ebae37SRussell King udelay(10); 329c8ebae37SRussell King } 330c8ebae37SRussell King 331c8ebae37SRussell King /* 332c8ebae37SRussell King * Check to see whether we still have some data left in the FIFO - 333c8ebae37SRussell King * this catches DMA controllers which are unable to monitor the 334c8ebae37SRussell King * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 335c8ebae37SRussell King * contiguous buffers. On TX, we'll get a FIFO underrun error. 336c8ebae37SRussell King */ 337c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 338c8ebae37SRussell King dmaengine_terminate_all(chan); 339c8ebae37SRussell King if (!data->error) 340c8ebae37SRussell King data->error = -EIO; 341c8ebae37SRussell King } 342c8ebae37SRussell King 343c8ebae37SRussell King if (data->flags & MMC_DATA_WRITE) { 344c8ebae37SRussell King dir = DMA_TO_DEVICE; 345c8ebae37SRussell King } else { 346c8ebae37SRussell King dir = DMA_FROM_DEVICE; 347c8ebae37SRussell King } 348c8ebae37SRussell King 34958c7ccbfSPer Forlin if (!data->host_cookie) 350c8ebae37SRussell King dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 351c8ebae37SRussell King 352c8ebae37SRussell King /* 353c8ebae37SRussell King * Use of DMA with scatter-gather is impossible. 354c8ebae37SRussell King * Give up with DMA and switch back to PIO mode. 355c8ebae37SRussell King */ 356c8ebae37SRussell King if (status & MCI_RXDATAAVLBLMASK) { 357c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 358c8ebae37SRussell King mmci_dma_release(host); 359c8ebae37SRussell King } 360c8ebae37SRussell King } 361c8ebae37SRussell King 362c8ebae37SRussell King static void mmci_dma_data_error(struct mmci_host *host) 363c8ebae37SRussell King { 364c8ebae37SRussell King dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 365c8ebae37SRussell King dmaengine_terminate_all(host->dma_current); 366c8ebae37SRussell King } 367c8ebae37SRussell King 36858c7ccbfSPer Forlin static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 36958c7ccbfSPer Forlin struct mmci_host_next *next) 370c8ebae37SRussell King { 371c8ebae37SRussell King struct variant_data *variant = host->variant; 372c8ebae37SRussell King struct dma_slave_config conf = { 373c8ebae37SRussell King .src_addr = host->phybase + MMCIFIFO, 374c8ebae37SRussell King .dst_addr = host->phybase + MMCIFIFO, 375c8ebae37SRussell King .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 376c8ebae37SRussell King .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 377c8ebae37SRussell King .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 378c8ebae37SRussell King .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 379c8ebae37SRussell King }; 380c8ebae37SRussell King struct dma_chan *chan; 381c8ebae37SRussell King struct dma_device *device; 382c8ebae37SRussell King struct dma_async_tx_descriptor *desc; 38305f5799cSVinod Koul enum dma_data_direction buffer_dirn; 384c8ebae37SRussell King int nr_sg; 385c8ebae37SRussell King 38658c7ccbfSPer Forlin /* Check if next job is already prepared */ 38758c7ccbfSPer Forlin if (data->host_cookie && !next && 38858c7ccbfSPer Forlin host->dma_current && host->dma_desc_current) 38958c7ccbfSPer Forlin return 0; 39058c7ccbfSPer Forlin 39158c7ccbfSPer Forlin if (!next) { 392c8ebae37SRussell King host->dma_current = NULL; 39358c7ccbfSPer Forlin host->dma_desc_current = NULL; 39458c7ccbfSPer Forlin } 395c8ebae37SRussell King 396c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 39705f5799cSVinod Koul conf.direction = DMA_DEV_TO_MEM; 39805f5799cSVinod Koul buffer_dirn = DMA_FROM_DEVICE; 399c8ebae37SRussell King chan = host->dma_rx_channel; 400c8ebae37SRussell King } else { 40105f5799cSVinod Koul conf.direction = DMA_MEM_TO_DEV; 40205f5799cSVinod Koul buffer_dirn = DMA_TO_DEVICE; 403c8ebae37SRussell King chan = host->dma_tx_channel; 404c8ebae37SRussell King } 405c8ebae37SRussell King 406c8ebae37SRussell King /* If there's no DMA channel, fall back to PIO */ 407c8ebae37SRussell King if (!chan) 408c8ebae37SRussell King return -EINVAL; 409c8ebae37SRussell King 410c8ebae37SRussell King /* If less than or equal to the fifo size, don't bother with DMA */ 41158c7ccbfSPer Forlin if (data->blksz * data->blocks <= variant->fifosize) 412c8ebae37SRussell King return -EINVAL; 413c8ebae37SRussell King 414c8ebae37SRussell King device = chan->device; 41505f5799cSVinod Koul nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 416c8ebae37SRussell King if (nr_sg == 0) 417c8ebae37SRussell King return -EINVAL; 418c8ebae37SRussell King 419c8ebae37SRussell King dmaengine_slave_config(chan, &conf); 420c8ebae37SRussell King desc = device->device_prep_slave_sg(chan, data->sg, nr_sg, 421c8ebae37SRussell King conf.direction, DMA_CTRL_ACK); 422c8ebae37SRussell King if (!desc) 423c8ebae37SRussell King goto unmap_exit; 424c8ebae37SRussell King 42558c7ccbfSPer Forlin if (next) { 42658c7ccbfSPer Forlin next->dma_chan = chan; 42758c7ccbfSPer Forlin next->dma_desc = desc; 42858c7ccbfSPer Forlin } else { 429c8ebae37SRussell King host->dma_current = chan; 43058c7ccbfSPer Forlin host->dma_desc_current = desc; 43158c7ccbfSPer Forlin } 432c8ebae37SRussell King 43358c7ccbfSPer Forlin return 0; 43458c7ccbfSPer Forlin 43558c7ccbfSPer Forlin unmap_exit: 43658c7ccbfSPer Forlin if (!next) 43758c7ccbfSPer Forlin dmaengine_terminate_all(chan); 43805f5799cSVinod Koul dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 43958c7ccbfSPer Forlin return -ENOMEM; 44058c7ccbfSPer Forlin } 44158c7ccbfSPer Forlin 44258c7ccbfSPer Forlin static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 44358c7ccbfSPer Forlin { 44458c7ccbfSPer Forlin int ret; 44558c7ccbfSPer Forlin struct mmc_data *data = host->data; 44658c7ccbfSPer Forlin 44758c7ccbfSPer Forlin ret = mmci_dma_prep_data(host, host->data, NULL); 44858c7ccbfSPer Forlin if (ret) 44958c7ccbfSPer Forlin return ret; 45058c7ccbfSPer Forlin 45158c7ccbfSPer Forlin /* Okay, go for it. */ 452c8ebae37SRussell King dev_vdbg(mmc_dev(host->mmc), 453c8ebae37SRussell King "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 454c8ebae37SRussell King data->sg_len, data->blksz, data->blocks, data->flags); 45558c7ccbfSPer Forlin dmaengine_submit(host->dma_desc_current); 45658c7ccbfSPer Forlin dma_async_issue_pending(host->dma_current); 457c8ebae37SRussell King 458c8ebae37SRussell King datactrl |= MCI_DPSM_DMAENABLE; 459c8ebae37SRussell King 460c8ebae37SRussell King /* Trigger the DMA transfer */ 461c8ebae37SRussell King writel(datactrl, host->base + MMCIDATACTRL); 462c8ebae37SRussell King 463c8ebae37SRussell King /* 464c8ebae37SRussell King * Let the MMCI say when the data is ended and it's time 465c8ebae37SRussell King * to fire next DMA request. When that happens, MMCI will 466c8ebae37SRussell King * call mmci_data_end() 467c8ebae37SRussell King */ 468c8ebae37SRussell King writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 469c8ebae37SRussell King host->base + MMCIMASK0); 470c8ebae37SRussell King return 0; 471c8ebae37SRussell King } 47258c7ccbfSPer Forlin 47358c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 47458c7ccbfSPer Forlin { 47558c7ccbfSPer Forlin struct mmci_host_next *next = &host->next_data; 47658c7ccbfSPer Forlin 47758c7ccbfSPer Forlin if (data->host_cookie && data->host_cookie != next->cookie) { 478a3c76eb9SGirish K S pr_warning("[%s] invalid cookie: data->host_cookie %d" 47958c7ccbfSPer Forlin " host->next_data.cookie %d\n", 48058c7ccbfSPer Forlin __func__, data->host_cookie, host->next_data.cookie); 48158c7ccbfSPer Forlin data->host_cookie = 0; 48258c7ccbfSPer Forlin } 48358c7ccbfSPer Forlin 48458c7ccbfSPer Forlin if (!data->host_cookie) 48558c7ccbfSPer Forlin return; 48658c7ccbfSPer Forlin 48758c7ccbfSPer Forlin host->dma_desc_current = next->dma_desc; 48858c7ccbfSPer Forlin host->dma_current = next->dma_chan; 48958c7ccbfSPer Forlin 49058c7ccbfSPer Forlin next->dma_desc = NULL; 49158c7ccbfSPer Forlin next->dma_chan = NULL; 49258c7ccbfSPer Forlin } 49358c7ccbfSPer Forlin 49458c7ccbfSPer Forlin static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 49558c7ccbfSPer Forlin bool is_first_req) 49658c7ccbfSPer Forlin { 49758c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 49858c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 49958c7ccbfSPer Forlin struct mmci_host_next *nd = &host->next_data; 50058c7ccbfSPer Forlin 50158c7ccbfSPer Forlin if (!data) 50258c7ccbfSPer Forlin return; 50358c7ccbfSPer Forlin 50458c7ccbfSPer Forlin if (data->host_cookie) { 50558c7ccbfSPer Forlin data->host_cookie = 0; 50658c7ccbfSPer Forlin return; 50758c7ccbfSPer Forlin } 50858c7ccbfSPer Forlin 50958c7ccbfSPer Forlin /* if config for dma */ 51058c7ccbfSPer Forlin if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 51158c7ccbfSPer Forlin ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 51258c7ccbfSPer Forlin if (mmci_dma_prep_data(host, data, nd)) 51358c7ccbfSPer Forlin data->host_cookie = 0; 51458c7ccbfSPer Forlin else 51558c7ccbfSPer Forlin data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 51658c7ccbfSPer Forlin } 51758c7ccbfSPer Forlin } 51858c7ccbfSPer Forlin 51958c7ccbfSPer Forlin static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 52058c7ccbfSPer Forlin int err) 52158c7ccbfSPer Forlin { 52258c7ccbfSPer Forlin struct mmci_host *host = mmc_priv(mmc); 52358c7ccbfSPer Forlin struct mmc_data *data = mrq->data; 52458c7ccbfSPer Forlin struct dma_chan *chan; 52558c7ccbfSPer Forlin enum dma_data_direction dir; 52658c7ccbfSPer Forlin 52758c7ccbfSPer Forlin if (!data) 52858c7ccbfSPer Forlin return; 52958c7ccbfSPer Forlin 53058c7ccbfSPer Forlin if (data->flags & MMC_DATA_READ) { 53158c7ccbfSPer Forlin dir = DMA_FROM_DEVICE; 53258c7ccbfSPer Forlin chan = host->dma_rx_channel; 53358c7ccbfSPer Forlin } else { 53458c7ccbfSPer Forlin dir = DMA_TO_DEVICE; 53558c7ccbfSPer Forlin chan = host->dma_tx_channel; 53658c7ccbfSPer Forlin } 53758c7ccbfSPer Forlin 53858c7ccbfSPer Forlin 53958c7ccbfSPer Forlin /* if config for dma */ 54058c7ccbfSPer Forlin if (chan) { 54158c7ccbfSPer Forlin if (err) 54258c7ccbfSPer Forlin dmaengine_terminate_all(chan); 5438e3336b1SPer Forlin if (data->host_cookie) 54458c7ccbfSPer Forlin dma_unmap_sg(mmc_dev(host->mmc), data->sg, 54558c7ccbfSPer Forlin data->sg_len, dir); 54658c7ccbfSPer Forlin mrq->data->host_cookie = 0; 54758c7ccbfSPer Forlin } 54858c7ccbfSPer Forlin } 54958c7ccbfSPer Forlin 550c8ebae37SRussell King #else 551c8ebae37SRussell King /* Blank functions if the DMA engine is not available */ 55258c7ccbfSPer Forlin static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 55358c7ccbfSPer Forlin { 55458c7ccbfSPer Forlin } 555c8ebae37SRussell King static inline void mmci_dma_setup(struct mmci_host *host) 556c8ebae37SRussell King { 557c8ebae37SRussell King } 558c8ebae37SRussell King 559c8ebae37SRussell King static inline void mmci_dma_release(struct mmci_host *host) 560c8ebae37SRussell King { 561c8ebae37SRussell King } 562c8ebae37SRussell King 563c8ebae37SRussell King static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 564c8ebae37SRussell King { 565c8ebae37SRussell King } 566c8ebae37SRussell King 567c8ebae37SRussell King static inline void mmci_dma_data_error(struct mmci_host *host) 568c8ebae37SRussell King { 569c8ebae37SRussell King } 570c8ebae37SRussell King 571c8ebae37SRussell King static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 572c8ebae37SRussell King { 573c8ebae37SRussell King return -ENOSYS; 574c8ebae37SRussell King } 57558c7ccbfSPer Forlin 57658c7ccbfSPer Forlin #define mmci_pre_request NULL 57758c7ccbfSPer Forlin #define mmci_post_request NULL 57858c7ccbfSPer Forlin 579c8ebae37SRussell King #endif 580c8ebae37SRussell King 5811c6a0718SPierre Ossman static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 5821c6a0718SPierre Ossman { 5838301bb68SRabin Vincent struct variant_data *variant = host->variant; 5841c6a0718SPierre Ossman unsigned int datactrl, timeout, irqmask; 5851c6a0718SPierre Ossman unsigned long long clks; 5861c6a0718SPierre Ossman void __iomem *base; 5871c6a0718SPierre Ossman int blksz_bits; 5881c6a0718SPierre Ossman 58964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 5901c6a0718SPierre Ossman data->blksz, data->blocks, data->flags); 5911c6a0718SPierre Ossman 5921c6a0718SPierre Ossman host->data = data; 593528320dbSRabin Vincent host->size = data->blksz * data->blocks; 59451d4375dSRussell King data->bytes_xfered = 0; 5951c6a0718SPierre Ossman 5961c6a0718SPierre Ossman clks = (unsigned long long)data->timeout_ns * host->cclk; 5971c6a0718SPierre Ossman do_div(clks, 1000000000UL); 5981c6a0718SPierre Ossman 5991c6a0718SPierre Ossman timeout = data->timeout_clks + (unsigned int)clks; 6001c6a0718SPierre Ossman 6011c6a0718SPierre Ossman base = host->base; 6021c6a0718SPierre Ossman writel(timeout, base + MMCIDATATIMER); 6031c6a0718SPierre Ossman writel(host->size, base + MMCIDATALENGTH); 6041c6a0718SPierre Ossman 6051c6a0718SPierre Ossman blksz_bits = ffs(data->blksz) - 1; 6061c6a0718SPierre Ossman BUG_ON(1 << blksz_bits != data->blksz); 6071c6a0718SPierre Ossman 6081784b157SPhilippe Langlais if (variant->blksz_datactrl16) 6091784b157SPhilippe Langlais datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 6101784b157SPhilippe Langlais else 6111c6a0718SPierre Ossman datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 612c8ebae37SRussell King 613c8ebae37SRussell King if (data->flags & MMC_DATA_READ) 6141c6a0718SPierre Ossman datactrl |= MCI_DPSM_DIRECTION; 615c8ebae37SRussell King 616c8ebae37SRussell King /* 617c8ebae37SRussell King * Attempt to use DMA operation mode, if this 618c8ebae37SRussell King * should fail, fall back to PIO mode 619c8ebae37SRussell King */ 620c8ebae37SRussell King if (!mmci_dma_start_data(host, datactrl)) 621c8ebae37SRussell King return; 622c8ebae37SRussell King 623c8ebae37SRussell King /* IRQ mode, map the SG list for CPU reading/writing */ 624c8ebae37SRussell King mmci_init_sg(host, data); 625c8ebae37SRussell King 626c8ebae37SRussell King if (data->flags & MMC_DATA_READ) { 6271c6a0718SPierre Ossman irqmask = MCI_RXFIFOHALFFULLMASK; 6281c6a0718SPierre Ossman 6291c6a0718SPierre Ossman /* 630c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to 631c4d877c1SRussell King * transfer, trigger a PIO interrupt as soon as any data 632c4d877c1SRussell King * is available. 6331c6a0718SPierre Ossman */ 634c4d877c1SRussell King if (host->size < variant->fifohalfsize) 6351c6a0718SPierre Ossman irqmask |= MCI_RXDATAAVLBLMASK; 6361c6a0718SPierre Ossman } else { 6371c6a0718SPierre Ossman /* 6381c6a0718SPierre Ossman * We don't actually need to include "FIFO empty" here 6391c6a0718SPierre Ossman * since its implicit in "FIFO half empty". 6401c6a0718SPierre Ossman */ 6411c6a0718SPierre Ossman irqmask = MCI_TXFIFOHALFEMPTYMASK; 6421c6a0718SPierre Ossman } 6431c6a0718SPierre Ossman 64434177802SLinus Walleij /* The ST Micro variants has a special bit to enable SDIO */ 64534177802SLinus Walleij if (variant->sdio && host->mmc->card) 64634177802SLinus Walleij if (mmc_card_sdio(host->mmc->card)) 64734177802SLinus Walleij datactrl |= MCI_ST_DPSM_SDIOEN; 64834177802SLinus Walleij 6491c6a0718SPierre Ossman writel(datactrl, base + MMCIDATACTRL); 6501c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 6512686b4b4SLinus Walleij mmci_set_mask1(host, irqmask); 6521c6a0718SPierre Ossman } 6531c6a0718SPierre Ossman 6541c6a0718SPierre Ossman static void 6551c6a0718SPierre Ossman mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 6561c6a0718SPierre Ossman { 6571c6a0718SPierre Ossman void __iomem *base = host->base; 6581c6a0718SPierre Ossman 65964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 6601c6a0718SPierre Ossman cmd->opcode, cmd->arg, cmd->flags); 6611c6a0718SPierre Ossman 6621c6a0718SPierre Ossman if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 6631c6a0718SPierre Ossman writel(0, base + MMCICOMMAND); 6641c6a0718SPierre Ossman udelay(1); 6651c6a0718SPierre Ossman } 6661c6a0718SPierre Ossman 6671c6a0718SPierre Ossman c |= cmd->opcode | MCI_CPSM_ENABLE; 6681c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_PRESENT) { 6691c6a0718SPierre Ossman if (cmd->flags & MMC_RSP_136) 6701c6a0718SPierre Ossman c |= MCI_CPSM_LONGRSP; 6711c6a0718SPierre Ossman c |= MCI_CPSM_RESPONSE; 6721c6a0718SPierre Ossman } 6731c6a0718SPierre Ossman if (/*interrupt*/0) 6741c6a0718SPierre Ossman c |= MCI_CPSM_INTERRUPT; 6751c6a0718SPierre Ossman 6761c6a0718SPierre Ossman host->cmd = cmd; 6771c6a0718SPierre Ossman 6781c6a0718SPierre Ossman writel(cmd->arg, base + MMCIARGUMENT); 6791c6a0718SPierre Ossman writel(c, base + MMCICOMMAND); 6801c6a0718SPierre Ossman } 6811c6a0718SPierre Ossman 6821c6a0718SPierre Ossman static void 6831c6a0718SPierre Ossman mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 6841c6a0718SPierre Ossman unsigned int status) 6851c6a0718SPierre Ossman { 686f20f8f21SLinus Walleij /* First check for errors */ 687b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 688b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 6898cb28155SLinus Walleij u32 remain, success; 690f20f8f21SLinus Walleij 691c8ebae37SRussell King /* Terminate the DMA transfer */ 692c8ebae37SRussell King if (dma_inprogress(host)) 693c8ebae37SRussell King mmci_dma_data_error(host); 694c8ebae37SRussell King 695c8afc9d5SRussell King /* 696c8afc9d5SRussell King * Calculate how far we are into the transfer. Note that 697c8afc9d5SRussell King * the data counter gives the number of bytes transferred 698c8afc9d5SRussell King * on the MMC bus, not on the host side. On reads, this 699c8afc9d5SRussell King * can be as much as a FIFO-worth of data ahead. This 700c8afc9d5SRussell King * matters for FIFO overruns only. 701c8afc9d5SRussell King */ 702f5a106d9SLinus Walleij remain = readl(host->base + MMCIDATACNT); 7038cb28155SLinus Walleij success = data->blksz * data->blocks - remain; 7048cb28155SLinus Walleij 705c8afc9d5SRussell King dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 706c8afc9d5SRussell King status, success); 7078cb28155SLinus Walleij if (status & MCI_DATACRCFAIL) { 7088cb28155SLinus Walleij /* Last block was not successful */ 709c8afc9d5SRussell King success -= 1; 71017b0429dSPierre Ossman data->error = -EILSEQ; 7118cb28155SLinus Walleij } else if (status & MCI_DATATIMEOUT) { 71217b0429dSPierre Ossman data->error = -ETIMEDOUT; 713757df746SLinus Walleij } else if (status & MCI_STARTBITERR) { 714757df746SLinus Walleij data->error = -ECOMM; 715c8afc9d5SRussell King } else if (status & MCI_TXUNDERRUN) { 71617b0429dSPierre Ossman data->error = -EIO; 717c8afc9d5SRussell King } else if (status & MCI_RXOVERRUN) { 718c8afc9d5SRussell King if (success > host->variant->fifosize) 719c8afc9d5SRussell King success -= host->variant->fifosize; 720c8afc9d5SRussell King else 721c8afc9d5SRussell King success = 0; 7228cb28155SLinus Walleij data->error = -EIO; 7234ce1d6cbSRabin Vincent } 72451d4375dSRussell King data->bytes_xfered = round_down(success, data->blksz); 7251c6a0718SPierre Ossman } 726f20f8f21SLinus Walleij 7278cb28155SLinus Walleij if (status & MCI_DATABLOCKEND) 7288cb28155SLinus Walleij dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 729f20f8f21SLinus Walleij 730ccff9b51SRussell King if (status & MCI_DATAEND || data->error) { 731c8ebae37SRussell King if (dma_inprogress(host)) 732c8ebae37SRussell King mmci_dma_unmap(host, data); 7331c6a0718SPierre Ossman mmci_stop_data(host); 7341c6a0718SPierre Ossman 7358cb28155SLinus Walleij if (!data->error) 7368cb28155SLinus Walleij /* The error clause is handled above, success! */ 73751d4375dSRussell King data->bytes_xfered = data->blksz * data->blocks; 738f20f8f21SLinus Walleij 7391c6a0718SPierre Ossman if (!data->stop) { 7401c6a0718SPierre Ossman mmci_request_end(host, data->mrq); 7411c6a0718SPierre Ossman } else { 7421c6a0718SPierre Ossman mmci_start_command(host, data->stop, 0); 7431c6a0718SPierre Ossman } 7441c6a0718SPierre Ossman } 7451c6a0718SPierre Ossman } 7461c6a0718SPierre Ossman 7471c6a0718SPierre Ossman static void 7481c6a0718SPierre Ossman mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 7491c6a0718SPierre Ossman unsigned int status) 7501c6a0718SPierre Ossman { 7511c6a0718SPierre Ossman void __iomem *base = host->base; 7521c6a0718SPierre Ossman 7531c6a0718SPierre Ossman host->cmd = NULL; 7541c6a0718SPierre Ossman 7551c6a0718SPierre Ossman if (status & MCI_CMDTIMEOUT) { 75617b0429dSPierre Ossman cmd->error = -ETIMEDOUT; 7571c6a0718SPierre Ossman } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 75817b0429dSPierre Ossman cmd->error = -EILSEQ; 7599047b435SRussell King - ARM Linux } else { 7609047b435SRussell King - ARM Linux cmd->resp[0] = readl(base + MMCIRESPONSE0); 7619047b435SRussell King - ARM Linux cmd->resp[1] = readl(base + MMCIRESPONSE1); 7629047b435SRussell King - ARM Linux cmd->resp[2] = readl(base + MMCIRESPONSE2); 7639047b435SRussell King - ARM Linux cmd->resp[3] = readl(base + MMCIRESPONSE3); 7641c6a0718SPierre Ossman } 7651c6a0718SPierre Ossman 76617b0429dSPierre Ossman if (!cmd->data || cmd->error) { 7673b6e3c73SUlf Hansson if (host->data) { 7683b6e3c73SUlf Hansson /* Terminate the DMA transfer */ 7693b6e3c73SUlf Hansson if (dma_inprogress(host)) 7703b6e3c73SUlf Hansson mmci_dma_data_error(host); 7711c6a0718SPierre Ossman mmci_stop_data(host); 7723b6e3c73SUlf Hansson } 7731c6a0718SPierre Ossman mmci_request_end(host, cmd->mrq); 7741c6a0718SPierre Ossman } else if (!(cmd->data->flags & MMC_DATA_READ)) { 7751c6a0718SPierre Ossman mmci_start_data(host, cmd->data); 7761c6a0718SPierre Ossman } 7771c6a0718SPierre Ossman } 7781c6a0718SPierre Ossman 7791c6a0718SPierre Ossman static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 7801c6a0718SPierre Ossman { 7811c6a0718SPierre Ossman void __iomem *base = host->base; 7821c6a0718SPierre Ossman char *ptr = buffer; 7831c6a0718SPierre Ossman u32 status; 78426eed9a5SLinus Walleij int host_remain = host->size; 7851c6a0718SPierre Ossman 7861c6a0718SPierre Ossman do { 78726eed9a5SLinus Walleij int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 7881c6a0718SPierre Ossman 7891c6a0718SPierre Ossman if (count > remain) 7901c6a0718SPierre Ossman count = remain; 7911c6a0718SPierre Ossman 7921c6a0718SPierre Ossman if (count <= 0) 7931c6a0718SPierre Ossman break; 7941c6a0718SPierre Ossman 7951c6a0718SPierre Ossman readsl(base + MMCIFIFO, ptr, count >> 2); 7961c6a0718SPierre Ossman 7971c6a0718SPierre Ossman ptr += count; 7981c6a0718SPierre Ossman remain -= count; 79926eed9a5SLinus Walleij host_remain -= count; 8001c6a0718SPierre Ossman 8011c6a0718SPierre Ossman if (remain == 0) 8021c6a0718SPierre Ossman break; 8031c6a0718SPierre Ossman 8041c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8051c6a0718SPierre Ossman } while (status & MCI_RXDATAAVLBL); 8061c6a0718SPierre Ossman 8071c6a0718SPierre Ossman return ptr - buffer; 8081c6a0718SPierre Ossman } 8091c6a0718SPierre Ossman 8101c6a0718SPierre Ossman static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 8111c6a0718SPierre Ossman { 8128301bb68SRabin Vincent struct variant_data *variant = host->variant; 8131c6a0718SPierre Ossman void __iomem *base = host->base; 8141c6a0718SPierre Ossman char *ptr = buffer; 8151c6a0718SPierre Ossman 8161c6a0718SPierre Ossman do { 8171c6a0718SPierre Ossman unsigned int count, maxcnt; 8181c6a0718SPierre Ossman 8198301bb68SRabin Vincent maxcnt = status & MCI_TXFIFOEMPTY ? 8208301bb68SRabin Vincent variant->fifosize : variant->fifohalfsize; 8211c6a0718SPierre Ossman count = min(remain, maxcnt); 8221c6a0718SPierre Ossman 82334177802SLinus Walleij /* 82434177802SLinus Walleij * The ST Micro variant for SDIO transfer sizes 82534177802SLinus Walleij * less then 8 bytes should have clock H/W flow 82634177802SLinus Walleij * control disabled. 82734177802SLinus Walleij */ 82834177802SLinus Walleij if (variant->sdio && 82934177802SLinus Walleij mmc_card_sdio(host->mmc->card)) { 83034177802SLinus Walleij if (count < 8) 83134177802SLinus Walleij writel(readl(host->base + MMCICLOCK) & 83234177802SLinus Walleij ~variant->clkreg_enable, 83334177802SLinus Walleij host->base + MMCICLOCK); 83434177802SLinus Walleij else 83534177802SLinus Walleij writel(readl(host->base + MMCICLOCK) | 83634177802SLinus Walleij variant->clkreg_enable, 83734177802SLinus Walleij host->base + MMCICLOCK); 83834177802SLinus Walleij } 83934177802SLinus Walleij 84034177802SLinus Walleij /* 84134177802SLinus Walleij * SDIO especially may want to send something that is 84234177802SLinus Walleij * not divisible by 4 (as opposed to card sectors 84334177802SLinus Walleij * etc), and the FIFO only accept full 32-bit writes. 84434177802SLinus Walleij * So compensate by adding +3 on the count, a single 84534177802SLinus Walleij * byte become a 32bit write, 7 bytes will be two 84634177802SLinus Walleij * 32bit writes etc. 84734177802SLinus Walleij */ 84834177802SLinus Walleij writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 8491c6a0718SPierre Ossman 8501c6a0718SPierre Ossman ptr += count; 8511c6a0718SPierre Ossman remain -= count; 8521c6a0718SPierre Ossman 8531c6a0718SPierre Ossman if (remain == 0) 8541c6a0718SPierre Ossman break; 8551c6a0718SPierre Ossman 8561c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8571c6a0718SPierre Ossman } while (status & MCI_TXFIFOHALFEMPTY); 8581c6a0718SPierre Ossman 8591c6a0718SPierre Ossman return ptr - buffer; 8601c6a0718SPierre Ossman } 8611c6a0718SPierre Ossman 8621c6a0718SPierre Ossman /* 8631c6a0718SPierre Ossman * PIO data transfer IRQ handler. 8641c6a0718SPierre Ossman */ 8651c6a0718SPierre Ossman static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 8661c6a0718SPierre Ossman { 8671c6a0718SPierre Ossman struct mmci_host *host = dev_id; 8684ce1d6cbSRabin Vincent struct sg_mapping_iter *sg_miter = &host->sg_miter; 8698301bb68SRabin Vincent struct variant_data *variant = host->variant; 8701c6a0718SPierre Ossman void __iomem *base = host->base; 8714ce1d6cbSRabin Vincent unsigned long flags; 8721c6a0718SPierre Ossman u32 status; 8731c6a0718SPierre Ossman 8741c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 8751c6a0718SPierre Ossman 87664de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 8771c6a0718SPierre Ossman 8784ce1d6cbSRabin Vincent local_irq_save(flags); 8794ce1d6cbSRabin Vincent 8801c6a0718SPierre Ossman do { 8811c6a0718SPierre Ossman unsigned int remain, len; 8821c6a0718SPierre Ossman char *buffer; 8831c6a0718SPierre Ossman 8841c6a0718SPierre Ossman /* 8851c6a0718SPierre Ossman * For write, we only need to test the half-empty flag 8861c6a0718SPierre Ossman * here - if the FIFO is completely empty, then by 8871c6a0718SPierre Ossman * definition it is more than half empty. 8881c6a0718SPierre Ossman * 8891c6a0718SPierre Ossman * For read, check for data available. 8901c6a0718SPierre Ossman */ 8911c6a0718SPierre Ossman if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 8921c6a0718SPierre Ossman break; 8931c6a0718SPierre Ossman 8944ce1d6cbSRabin Vincent if (!sg_miter_next(sg_miter)) 8954ce1d6cbSRabin Vincent break; 8964ce1d6cbSRabin Vincent 8974ce1d6cbSRabin Vincent buffer = sg_miter->addr; 8984ce1d6cbSRabin Vincent remain = sg_miter->length; 8991c6a0718SPierre Ossman 9001c6a0718SPierre Ossman len = 0; 9011c6a0718SPierre Ossman if (status & MCI_RXACTIVE) 9021c6a0718SPierre Ossman len = mmci_pio_read(host, buffer, remain); 9031c6a0718SPierre Ossman if (status & MCI_TXACTIVE) 9041c6a0718SPierre Ossman len = mmci_pio_write(host, buffer, remain, status); 9051c6a0718SPierre Ossman 9064ce1d6cbSRabin Vincent sg_miter->consumed = len; 9071c6a0718SPierre Ossman 9081c6a0718SPierre Ossman host->size -= len; 9091c6a0718SPierre Ossman remain -= len; 9101c6a0718SPierre Ossman 9111c6a0718SPierre Ossman if (remain) 9121c6a0718SPierre Ossman break; 9131c6a0718SPierre Ossman 9141c6a0718SPierre Ossman status = readl(base + MMCISTATUS); 9151c6a0718SPierre Ossman } while (1); 9161c6a0718SPierre Ossman 9174ce1d6cbSRabin Vincent sg_miter_stop(sg_miter); 9184ce1d6cbSRabin Vincent 9194ce1d6cbSRabin Vincent local_irq_restore(flags); 9204ce1d6cbSRabin Vincent 9211c6a0718SPierre Ossman /* 922c4d877c1SRussell King * If we have less than the fifo 'half-full' threshold to transfer, 923c4d877c1SRussell King * trigger a PIO interrupt as soon as any data is available. 9241c6a0718SPierre Ossman */ 925c4d877c1SRussell King if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 9262686b4b4SLinus Walleij mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 9271c6a0718SPierre Ossman 9281c6a0718SPierre Ossman /* 9291c6a0718SPierre Ossman * If we run out of data, disable the data IRQs; this 9301c6a0718SPierre Ossman * prevents a race where the FIFO becomes empty before 9311c6a0718SPierre Ossman * the chip itself has disabled the data path, and 9321c6a0718SPierre Ossman * stops us racing with our data end IRQ. 9331c6a0718SPierre Ossman */ 9341c6a0718SPierre Ossman if (host->size == 0) { 9352686b4b4SLinus Walleij mmci_set_mask1(host, 0); 9361c6a0718SPierre Ossman writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 9371c6a0718SPierre Ossman } 9381c6a0718SPierre Ossman 9391c6a0718SPierre Ossman return IRQ_HANDLED; 9401c6a0718SPierre Ossman } 9411c6a0718SPierre Ossman 9421c6a0718SPierre Ossman /* 9431c6a0718SPierre Ossman * Handle completion of command and data transfers. 9441c6a0718SPierre Ossman */ 9451c6a0718SPierre Ossman static irqreturn_t mmci_irq(int irq, void *dev_id) 9461c6a0718SPierre Ossman { 9471c6a0718SPierre Ossman struct mmci_host *host = dev_id; 9481c6a0718SPierre Ossman u32 status; 9491c6a0718SPierre Ossman int ret = 0; 9501c6a0718SPierre Ossman 9511c6a0718SPierre Ossman spin_lock(&host->lock); 9521c6a0718SPierre Ossman 9531c6a0718SPierre Ossman do { 9541c6a0718SPierre Ossman struct mmc_command *cmd; 9551c6a0718SPierre Ossman struct mmc_data *data; 9561c6a0718SPierre Ossman 9571c6a0718SPierre Ossman status = readl(host->base + MMCISTATUS); 9582686b4b4SLinus Walleij 9592686b4b4SLinus Walleij if (host->singleirq) { 9602686b4b4SLinus Walleij if (status & readl(host->base + MMCIMASK1)) 9612686b4b4SLinus Walleij mmci_pio_irq(irq, dev_id); 9622686b4b4SLinus Walleij 9632686b4b4SLinus Walleij status &= ~MCI_IRQ1MASK; 9642686b4b4SLinus Walleij } 9652686b4b4SLinus Walleij 9661c6a0718SPierre Ossman status &= readl(host->base + MMCIMASK0); 9671c6a0718SPierre Ossman writel(status, host->base + MMCICLEAR); 9681c6a0718SPierre Ossman 96964de0289SLinus Walleij dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 9701c6a0718SPierre Ossman 9711c6a0718SPierre Ossman data = host->data; 972b63038d6SUlf Hansson if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 973b63038d6SUlf Hansson MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 974b63038d6SUlf Hansson MCI_DATABLOCKEND) && data) 9751c6a0718SPierre Ossman mmci_data_irq(host, data, status); 9761c6a0718SPierre Ossman 9771c6a0718SPierre Ossman cmd = host->cmd; 9781c6a0718SPierre Ossman if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 9791c6a0718SPierre Ossman mmci_cmd_irq(host, cmd, status); 9801c6a0718SPierre Ossman 9811c6a0718SPierre Ossman ret = 1; 9821c6a0718SPierre Ossman } while (status); 9831c6a0718SPierre Ossman 9841c6a0718SPierre Ossman spin_unlock(&host->lock); 9851c6a0718SPierre Ossman 9861c6a0718SPierre Ossman return IRQ_RETVAL(ret); 9871c6a0718SPierre Ossman } 9881c6a0718SPierre Ossman 9891c6a0718SPierre Ossman static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 9901c6a0718SPierre Ossman { 9911c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 9929e943021SLinus Walleij unsigned long flags; 9931c6a0718SPierre Ossman 9941c6a0718SPierre Ossman WARN_ON(host->mrq != NULL); 9951c6a0718SPierre Ossman 996019a5f56SNicolas Pitre if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 99764de0289SLinus Walleij dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 99864de0289SLinus Walleij mrq->data->blksz); 999255d01afSPierre Ossman mrq->cmd->error = -EINVAL; 1000255d01afSPierre Ossman mmc_request_done(mmc, mrq); 1001255d01afSPierre Ossman return; 1002255d01afSPierre Ossman } 1003255d01afSPierre Ossman 10041c3be369SRussell King pm_runtime_get_sync(mmc_dev(mmc)); 10051c3be369SRussell King 10069e943021SLinus Walleij spin_lock_irqsave(&host->lock, flags); 10071c6a0718SPierre Ossman 10081c6a0718SPierre Ossman host->mrq = mrq; 10091c6a0718SPierre Ossman 101058c7ccbfSPer Forlin if (mrq->data) 101158c7ccbfSPer Forlin mmci_get_next_data(host, mrq->data); 101258c7ccbfSPer Forlin 10131c6a0718SPierre Ossman if (mrq->data && mrq->data->flags & MMC_DATA_READ) 10141c6a0718SPierre Ossman mmci_start_data(host, mrq->data); 10151c6a0718SPierre Ossman 10161c6a0718SPierre Ossman mmci_start_command(host, mrq->cmd, 0); 10171c6a0718SPierre Ossman 10189e943021SLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 10191c6a0718SPierre Ossman } 10201c6a0718SPierre Ossman 10211c6a0718SPierre Ossman static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 10221c6a0718SPierre Ossman { 10231c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 10247d72a1d4SUlf Hansson struct variant_data *variant = host->variant; 1025a6a6464aSLinus Walleij u32 pwr = 0; 1026a6a6464aSLinus Walleij unsigned long flags; 102799fc5131SLinus Walleij int ret; 10281c6a0718SPierre Ossman 1029bc521818SUlf Hansson if (host->plat->ios_handler && 1030bc521818SUlf Hansson host->plat->ios_handler(mmc_dev(mmc), ios)) 1031bc521818SUlf Hansson dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1032bc521818SUlf Hansson 10331c6a0718SPierre Ossman switch (ios->power_mode) { 10341c6a0718SPierre Ossman case MMC_POWER_OFF: 103599fc5131SLinus Walleij if (host->vcc) 103699fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 10371c6a0718SPierre Ossman break; 10381c6a0718SPierre Ossman case MMC_POWER_UP: 103999fc5131SLinus Walleij if (host->vcc) { 104099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 104199fc5131SLinus Walleij if (ret) { 104299fc5131SLinus Walleij dev_err(mmc_dev(mmc), "unable to set OCR\n"); 104399fc5131SLinus Walleij /* 104499fc5131SLinus Walleij * The .set_ios() function in the mmc_host_ops 104599fc5131SLinus Walleij * struct return void, and failing to set the 104699fc5131SLinus Walleij * power should be rare so we print an error 104799fc5131SLinus Walleij * and return here. 104899fc5131SLinus Walleij */ 104999fc5131SLinus Walleij return; 105099fc5131SLinus Walleij } 105199fc5131SLinus Walleij } 10527d72a1d4SUlf Hansson /* 10537d72a1d4SUlf Hansson * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 10547d72a1d4SUlf Hansson * and instead uses MCI_PWR_ON so apply whatever value is 10557d72a1d4SUlf Hansson * configured in the variant data. 10567d72a1d4SUlf Hansson */ 10577d72a1d4SUlf Hansson pwr |= variant->pwrreg_powerup; 10587d72a1d4SUlf Hansson 10591c6a0718SPierre Ossman break; 10601c6a0718SPierre Ossman case MMC_POWER_ON: 10611c6a0718SPierre Ossman pwr |= MCI_PWR_ON; 10621c6a0718SPierre Ossman break; 10631c6a0718SPierre Ossman } 10641c6a0718SPierre Ossman 10654d1a3a0dSUlf Hansson if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 10664d1a3a0dSUlf Hansson /* 10674d1a3a0dSUlf Hansson * The ST Micro variant has some additional bits 10684d1a3a0dSUlf Hansson * indicating signal direction for the signals in 10694d1a3a0dSUlf Hansson * the SD/MMC bus and feedback-clock usage. 10704d1a3a0dSUlf Hansson */ 10714d1a3a0dSUlf Hansson pwr |= host->plat->sigdir; 10724d1a3a0dSUlf Hansson 10734d1a3a0dSUlf Hansson if (ios->bus_width == MMC_BUS_WIDTH_4) 10744d1a3a0dSUlf Hansson pwr &= ~MCI_ST_DATA74DIREN; 10754d1a3a0dSUlf Hansson else if (ios->bus_width == MMC_BUS_WIDTH_1) 10764d1a3a0dSUlf Hansson pwr &= (~MCI_ST_DATA74DIREN & 10774d1a3a0dSUlf Hansson ~MCI_ST_DATA31DIREN & 10784d1a3a0dSUlf Hansson ~MCI_ST_DATA2DIREN); 10794d1a3a0dSUlf Hansson } 10804d1a3a0dSUlf Hansson 1081cc30d60eSLinus Walleij if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1082f17a1f06SLinus Walleij if (host->hw_designer != AMBA_VENDOR_ST) 10831c6a0718SPierre Ossman pwr |= MCI_ROD; 1084cc30d60eSLinus Walleij else { 1085cc30d60eSLinus Walleij /* 1086cc30d60eSLinus Walleij * The ST Micro variant use the ROD bit for something 1087cc30d60eSLinus Walleij * else and only has OD (Open Drain). 1088cc30d60eSLinus Walleij */ 1089cc30d60eSLinus Walleij pwr |= MCI_OD; 1090cc30d60eSLinus Walleij } 1091cc30d60eSLinus Walleij } 10921c6a0718SPierre Ossman 1093a6a6464aSLinus Walleij spin_lock_irqsave(&host->lock, flags); 1094a6a6464aSLinus Walleij 1095a6a6464aSLinus Walleij mmci_set_clkreg(host, ios->clock); 10961c6a0718SPierre Ossman 10971c6a0718SPierre Ossman if (host->pwr != pwr) { 10981c6a0718SPierre Ossman host->pwr = pwr; 10991c6a0718SPierre Ossman writel(pwr, host->base + MMCIPOWER); 11001c6a0718SPierre Ossman } 1101a6a6464aSLinus Walleij 1102a6a6464aSLinus Walleij spin_unlock_irqrestore(&host->lock, flags); 11031c6a0718SPierre Ossman } 11041c6a0718SPierre Ossman 110589001446SRussell King static int mmci_get_ro(struct mmc_host *mmc) 110689001446SRussell King { 110789001446SRussell King struct mmci_host *host = mmc_priv(mmc); 110889001446SRussell King 110989001446SRussell King if (host->gpio_wp == -ENOSYS) 111089001446SRussell King return -ENOSYS; 111189001446SRussell King 111218a06301SLinus Walleij return gpio_get_value_cansleep(host->gpio_wp); 111389001446SRussell King } 111489001446SRussell King 111589001446SRussell King static int mmci_get_cd(struct mmc_host *mmc) 111689001446SRussell King { 111789001446SRussell King struct mmci_host *host = mmc_priv(mmc); 111829719445SRabin Vincent struct mmci_platform_data *plat = host->plat; 111989001446SRussell King unsigned int status; 112089001446SRussell King 11214b8caec0SRabin Vincent if (host->gpio_cd == -ENOSYS) { 11224b8caec0SRabin Vincent if (!plat->status) 11234b8caec0SRabin Vincent return 1; /* Assume always present */ 11244b8caec0SRabin Vincent 112529719445SRabin Vincent status = plat->status(mmc_dev(host->mmc)); 11264b8caec0SRabin Vincent } else 112718a06301SLinus Walleij status = !!gpio_get_value_cansleep(host->gpio_cd) 112818a06301SLinus Walleij ^ plat->cd_invert; 112989001446SRussell King 113074bc8093SRussell King /* 113174bc8093SRussell King * Use positive logic throughout - status is zero for no card, 113274bc8093SRussell King * non-zero for card inserted. 113374bc8093SRussell King */ 113474bc8093SRussell King return status; 113589001446SRussell King } 113689001446SRussell King 1137148b8b39SRabin Vincent static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1138148b8b39SRabin Vincent { 1139148b8b39SRabin Vincent struct mmci_host *host = dev_id; 1140148b8b39SRabin Vincent 1141148b8b39SRabin Vincent mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1142148b8b39SRabin Vincent 1143148b8b39SRabin Vincent return IRQ_HANDLED; 1144148b8b39SRabin Vincent } 1145148b8b39SRabin Vincent 11461c6a0718SPierre Ossman static const struct mmc_host_ops mmci_ops = { 11471c6a0718SPierre Ossman .request = mmci_request, 114858c7ccbfSPer Forlin .pre_req = mmci_pre_request, 114958c7ccbfSPer Forlin .post_req = mmci_post_request, 11501c6a0718SPierre Ossman .set_ios = mmci_set_ios, 115189001446SRussell King .get_ro = mmci_get_ro, 115289001446SRussell King .get_cd = mmci_get_cd, 11531c6a0718SPierre Ossman }; 11541c6a0718SPierre Ossman 1155aa25afadSRussell King static int __devinit mmci_probe(struct amba_device *dev, 1156aa25afadSRussell King const struct amba_id *id) 11571c6a0718SPierre Ossman { 11586ef297f8SLinus Walleij struct mmci_platform_data *plat = dev->dev.platform_data; 11594956e109SRabin Vincent struct variant_data *variant = id->data; 11601c6a0718SPierre Ossman struct mmci_host *host; 11611c6a0718SPierre Ossman struct mmc_host *mmc; 11621c6a0718SPierre Ossman int ret; 11631c6a0718SPierre Ossman 11641c6a0718SPierre Ossman /* must have platform data */ 11651c6a0718SPierre Ossman if (!plat) { 11661c6a0718SPierre Ossman ret = -EINVAL; 11671c6a0718SPierre Ossman goto out; 11681c6a0718SPierre Ossman } 11691c6a0718SPierre Ossman 11701c6a0718SPierre Ossman ret = amba_request_regions(dev, DRIVER_NAME); 11711c6a0718SPierre Ossman if (ret) 11721c6a0718SPierre Ossman goto out; 11731c6a0718SPierre Ossman 11741c6a0718SPierre Ossman mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 11751c6a0718SPierre Ossman if (!mmc) { 11761c6a0718SPierre Ossman ret = -ENOMEM; 11771c6a0718SPierre Ossman goto rel_regions; 11781c6a0718SPierre Ossman } 11791c6a0718SPierre Ossman 11801c6a0718SPierre Ossman host = mmc_priv(mmc); 11814ea580f1SRabin Vincent host->mmc = mmc; 1182012b7d33SRussell King 118389001446SRussell King host->gpio_wp = -ENOSYS; 118489001446SRussell King host->gpio_cd = -ENOSYS; 1185148b8b39SRabin Vincent host->gpio_cd_irq = -1; 118689001446SRussell King 1187012b7d33SRussell King host->hw_designer = amba_manf(dev); 1188012b7d33SRussell King host->hw_revision = amba_rev(dev); 118964de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 119064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1191012b7d33SRussell King 1192ee569c43SRussell King host->clk = clk_get(&dev->dev, NULL); 11931c6a0718SPierre Ossman if (IS_ERR(host->clk)) { 11941c6a0718SPierre Ossman ret = PTR_ERR(host->clk); 11951c6a0718SPierre Ossman host->clk = NULL; 11961c6a0718SPierre Ossman goto host_free; 11971c6a0718SPierre Ossman } 11981c6a0718SPierre Ossman 119952ca0f3aSRussell King ret = clk_prepare(host->clk); 12001c6a0718SPierre Ossman if (ret) 12011c6a0718SPierre Ossman goto clk_free; 12021c6a0718SPierre Ossman 120352ca0f3aSRussell King ret = clk_enable(host->clk); 120452ca0f3aSRussell King if (ret) 120552ca0f3aSRussell King goto clk_unprep; 120652ca0f3aSRussell King 12071c6a0718SPierre Ossman host->plat = plat; 12084956e109SRabin Vincent host->variant = variant; 12091c6a0718SPierre Ossman host->mclk = clk_get_rate(host->clk); 1210c8df9a53SLinus Walleij /* 1211c8df9a53SLinus Walleij * According to the spec, mclk is max 100 MHz, 1212c8df9a53SLinus Walleij * so we try to adjust the clock down to this, 1213c8df9a53SLinus Walleij * (if possible). 1214c8df9a53SLinus Walleij */ 1215c8df9a53SLinus Walleij if (host->mclk > 100000000) { 1216c8df9a53SLinus Walleij ret = clk_set_rate(host->clk, 100000000); 1217c8df9a53SLinus Walleij if (ret < 0) 1218c8df9a53SLinus Walleij goto clk_disable; 1219c8df9a53SLinus Walleij host->mclk = clk_get_rate(host->clk); 122064de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 122164de0289SLinus Walleij host->mclk); 1222c8df9a53SLinus Walleij } 1223c8ebae37SRussell King host->phybase = dev->res.start; 1224dc890c2dSLinus Walleij host->base = ioremap(dev->res.start, resource_size(&dev->res)); 12251c6a0718SPierre Ossman if (!host->base) { 12261c6a0718SPierre Ossman ret = -ENOMEM; 12271c6a0718SPierre Ossman goto clk_disable; 12281c6a0718SPierre Ossman } 12291c6a0718SPierre Ossman 12301c6a0718SPierre Ossman mmc->ops = &mmci_ops; 12317f294e49SLinus Walleij /* 12327f294e49SLinus Walleij * The ARM and ST versions of the block have slightly different 12337f294e49SLinus Walleij * clock divider equations which means that the minimum divider 12347f294e49SLinus Walleij * differs too. 12357f294e49SLinus Walleij */ 12367f294e49SLinus Walleij if (variant->st_clkdiv) 12377f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 12387f294e49SLinus Walleij else 12397f294e49SLinus Walleij mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1240808d97ccSLinus Walleij /* 1241808d97ccSLinus Walleij * If the platform data supplies a maximum operating 1242808d97ccSLinus Walleij * frequency, this takes precedence. Else, we fall back 1243808d97ccSLinus Walleij * to using the module parameter, which has a (low) 1244808d97ccSLinus Walleij * default value in case it is not specified. Either 1245808d97ccSLinus Walleij * value must not exceed the clock rate into the block, 1246808d97ccSLinus Walleij * of course. 1247808d97ccSLinus Walleij */ 1248808d97ccSLinus Walleij if (plat->f_max) 1249808d97ccSLinus Walleij mmc->f_max = min(host->mclk, plat->f_max); 1250808d97ccSLinus Walleij else 12511c6a0718SPierre Ossman mmc->f_max = min(host->mclk, fmax); 125264de0289SLinus Walleij dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 125364de0289SLinus Walleij 125434e84f39SLinus Walleij #ifdef CONFIG_REGULATOR 125534e84f39SLinus Walleij /* If we're using the regulator framework, try to fetch a regulator */ 125634e84f39SLinus Walleij host->vcc = regulator_get(&dev->dev, "vmmc"); 125734e84f39SLinus Walleij if (IS_ERR(host->vcc)) 125834e84f39SLinus Walleij host->vcc = NULL; 125934e84f39SLinus Walleij else { 126034e84f39SLinus Walleij int mask = mmc_regulator_get_ocrmask(host->vcc); 126134e84f39SLinus Walleij 126234e84f39SLinus Walleij if (mask < 0) 126334e84f39SLinus Walleij dev_err(&dev->dev, "error getting OCR mask (%d)\n", 126434e84f39SLinus Walleij mask); 126534e84f39SLinus Walleij else { 126634e84f39SLinus Walleij host->mmc->ocr_avail = (u32) mask; 126734e84f39SLinus Walleij if (plat->ocr_mask) 126834e84f39SLinus Walleij dev_warn(&dev->dev, 126934e84f39SLinus Walleij "Provided ocr_mask/setpower will not be used " 127034e84f39SLinus Walleij "(using regulator instead)\n"); 127134e84f39SLinus Walleij } 127234e84f39SLinus Walleij } 127334e84f39SLinus Walleij #endif 127434e84f39SLinus Walleij /* Fall back to platform data if no regulator is found */ 127534e84f39SLinus Walleij if (host->vcc == NULL) 12761c6a0718SPierre Ossman mmc->ocr_avail = plat->ocr_mask; 12779e6c82cdSLinus Walleij mmc->caps = plat->capabilities; 12785a092627SPer Forlin mmc->caps2 = plat->capabilities2; 12791c6a0718SPierre Ossman 12801c6a0718SPierre Ossman /* 12811c6a0718SPierre Ossman * We can do SGIO 12821c6a0718SPierre Ossman */ 1283a36274e0SMartin K. Petersen mmc->max_segs = NR_SG; 12841c6a0718SPierre Ossman 12851c6a0718SPierre Ossman /* 128608458ef6SRabin Vincent * Since only a certain number of bits are valid in the data length 128708458ef6SRabin Vincent * register, we must ensure that we don't exceed 2^num-1 bytes in a 128808458ef6SRabin Vincent * single request. 12891c6a0718SPierre Ossman */ 129008458ef6SRabin Vincent mmc->max_req_size = (1 << variant->datalength_bits) - 1; 12911c6a0718SPierre Ossman 12921c6a0718SPierre Ossman /* 12931c6a0718SPierre Ossman * Set the maximum segment size. Since we aren't doing DMA 12941c6a0718SPierre Ossman * (yet) we are only limited by the data length register. 12951c6a0718SPierre Ossman */ 12961c6a0718SPierre Ossman mmc->max_seg_size = mmc->max_req_size; 12971c6a0718SPierre Ossman 12981c6a0718SPierre Ossman /* 12991c6a0718SPierre Ossman * Block size can be up to 2048 bytes, but must be a power of two. 13001c6a0718SPierre Ossman */ 13011c6a0718SPierre Ossman mmc->max_blk_size = 2048; 13021c6a0718SPierre Ossman 13031c6a0718SPierre Ossman /* 13041c6a0718SPierre Ossman * No limit on the number of blocks transferred. 13051c6a0718SPierre Ossman */ 13061c6a0718SPierre Ossman mmc->max_blk_count = mmc->max_req_size; 13071c6a0718SPierre Ossman 13081c6a0718SPierre Ossman spin_lock_init(&host->lock); 13091c6a0718SPierre Ossman 13101c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 13111c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 13121c6a0718SPierre Ossman writel(0xfff, host->base + MMCICLEAR); 13131c6a0718SPierre Ossman 131489001446SRussell King if (gpio_is_valid(plat->gpio_cd)) { 131589001446SRussell King ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 131689001446SRussell King if (ret == 0) 131789001446SRussell King ret = gpio_direction_input(plat->gpio_cd); 131889001446SRussell King if (ret == 0) 131989001446SRussell King host->gpio_cd = plat->gpio_cd; 132089001446SRussell King else if (ret != -ENOSYS) 132189001446SRussell King goto err_gpio_cd; 1322148b8b39SRabin Vincent 132317ee083bSLinus Walleij /* 132417ee083bSLinus Walleij * A gpio pin that will detect cards when inserted and removed 132517ee083bSLinus Walleij * will most likely want to trigger on the edges if it is 132617ee083bSLinus Walleij * 0 when ejected and 1 when inserted (or mutatis mutandis 132717ee083bSLinus Walleij * for the inverted case) so we request triggers on both 132817ee083bSLinus Walleij * edges. 132917ee083bSLinus Walleij */ 1330148b8b39SRabin Vincent ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 133117ee083bSLinus Walleij mmci_cd_irq, 133217ee083bSLinus Walleij IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1333148b8b39SRabin Vincent DRIVER_NAME " (cd)", host); 1334148b8b39SRabin Vincent if (ret >= 0) 1335148b8b39SRabin Vincent host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 133689001446SRussell King } 133789001446SRussell King if (gpio_is_valid(plat->gpio_wp)) { 133889001446SRussell King ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 133989001446SRussell King if (ret == 0) 134089001446SRussell King ret = gpio_direction_input(plat->gpio_wp); 134189001446SRussell King if (ret == 0) 134289001446SRussell King host->gpio_wp = plat->gpio_wp; 134389001446SRussell King else if (ret != -ENOSYS) 134489001446SRussell King goto err_gpio_wp; 134589001446SRussell King } 134689001446SRussell King 13474b8caec0SRabin Vincent if ((host->plat->status || host->gpio_cd != -ENOSYS) 13484b8caec0SRabin Vincent && host->gpio_cd_irq < 0) 1349148b8b39SRabin Vincent mmc->caps |= MMC_CAP_NEEDS_POLL; 1350148b8b39SRabin Vincent 13511c6a0718SPierre Ossman ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 13521c6a0718SPierre Ossman if (ret) 13531c6a0718SPierre Ossman goto unmap; 13541c6a0718SPierre Ossman 13552686b4b4SLinus Walleij if (dev->irq[1] == NO_IRQ) 13562686b4b4SLinus Walleij host->singleirq = true; 13572686b4b4SLinus Walleij else { 13582686b4b4SLinus Walleij ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 13592686b4b4SLinus Walleij DRIVER_NAME " (pio)", host); 13601c6a0718SPierre Ossman if (ret) 13611c6a0718SPierre Ossman goto irq0_free; 13622686b4b4SLinus Walleij } 13631c6a0718SPierre Ossman 13648cb28155SLinus Walleij writel(MCI_IRQENABLE, host->base + MMCIMASK0); 13651c6a0718SPierre Ossman 13661c6a0718SPierre Ossman amba_set_drvdata(dev, mmc); 13671c6a0718SPierre Ossman 1368c8ebae37SRussell King dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1369c8ebae37SRussell King mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1370c8ebae37SRussell King amba_rev(dev), (unsigned long long)dev->res.start, 1371c8ebae37SRussell King dev->irq[0], dev->irq[1]); 1372c8ebae37SRussell King 1373c8ebae37SRussell King mmci_dma_setup(host); 13741c6a0718SPierre Ossman 13751c3be369SRussell King pm_runtime_put(&dev->dev); 13761c3be369SRussell King 13778c11a94dSRussell King mmc_add_host(mmc); 13788c11a94dSRussell King 13791c6a0718SPierre Ossman return 0; 13801c6a0718SPierre Ossman 13811c6a0718SPierre Ossman irq0_free: 13821c6a0718SPierre Ossman free_irq(dev->irq[0], host); 13831c6a0718SPierre Ossman unmap: 138489001446SRussell King if (host->gpio_wp != -ENOSYS) 138589001446SRussell King gpio_free(host->gpio_wp); 138689001446SRussell King err_gpio_wp: 1387148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1388148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 138989001446SRussell King if (host->gpio_cd != -ENOSYS) 139089001446SRussell King gpio_free(host->gpio_cd); 139189001446SRussell King err_gpio_cd: 13921c6a0718SPierre Ossman iounmap(host->base); 13931c6a0718SPierre Ossman clk_disable: 13941c6a0718SPierre Ossman clk_disable(host->clk); 139552ca0f3aSRussell King clk_unprep: 139652ca0f3aSRussell King clk_unprepare(host->clk); 13971c6a0718SPierre Ossman clk_free: 13981c6a0718SPierre Ossman clk_put(host->clk); 13991c6a0718SPierre Ossman host_free: 14001c6a0718SPierre Ossman mmc_free_host(mmc); 14011c6a0718SPierre Ossman rel_regions: 14021c6a0718SPierre Ossman amba_release_regions(dev); 14031c6a0718SPierre Ossman out: 14041c6a0718SPierre Ossman return ret; 14051c6a0718SPierre Ossman } 14061c6a0718SPierre Ossman 14076dc4a47aSLinus Walleij static int __devexit mmci_remove(struct amba_device *dev) 14081c6a0718SPierre Ossman { 14091c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 14101c6a0718SPierre Ossman 14111c6a0718SPierre Ossman amba_set_drvdata(dev, NULL); 14121c6a0718SPierre Ossman 14131c6a0718SPierre Ossman if (mmc) { 14141c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 14151c6a0718SPierre Ossman 14161c3be369SRussell King /* 14171c3be369SRussell King * Undo pm_runtime_put() in probe. We use the _sync 14181c3be369SRussell King * version here so that we can access the primecell. 14191c3be369SRussell King */ 14201c3be369SRussell King pm_runtime_get_sync(&dev->dev); 14211c3be369SRussell King 14221c6a0718SPierre Ossman mmc_remove_host(mmc); 14231c6a0718SPierre Ossman 14241c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14251c6a0718SPierre Ossman writel(0, host->base + MMCIMASK1); 14261c6a0718SPierre Ossman 14271c6a0718SPierre Ossman writel(0, host->base + MMCICOMMAND); 14281c6a0718SPierre Ossman writel(0, host->base + MMCIDATACTRL); 14291c6a0718SPierre Ossman 1430c8ebae37SRussell King mmci_dma_release(host); 14311c6a0718SPierre Ossman free_irq(dev->irq[0], host); 14322686b4b4SLinus Walleij if (!host->singleirq) 14331c6a0718SPierre Ossman free_irq(dev->irq[1], host); 14341c6a0718SPierre Ossman 143589001446SRussell King if (host->gpio_wp != -ENOSYS) 143689001446SRussell King gpio_free(host->gpio_wp); 1437148b8b39SRabin Vincent if (host->gpio_cd_irq >= 0) 1438148b8b39SRabin Vincent free_irq(host->gpio_cd_irq, host); 143989001446SRussell King if (host->gpio_cd != -ENOSYS) 144089001446SRussell King gpio_free(host->gpio_cd); 144189001446SRussell King 14421c6a0718SPierre Ossman iounmap(host->base); 14431c6a0718SPierre Ossman clk_disable(host->clk); 144452ca0f3aSRussell King clk_unprepare(host->clk); 14451c6a0718SPierre Ossman clk_put(host->clk); 14461c6a0718SPierre Ossman 144799fc5131SLinus Walleij if (host->vcc) 144899fc5131SLinus Walleij mmc_regulator_set_ocr(mmc, host->vcc, 0); 144934e84f39SLinus Walleij regulator_put(host->vcc); 145034e84f39SLinus Walleij 14511c6a0718SPierre Ossman mmc_free_host(mmc); 14521c6a0718SPierre Ossman 14531c6a0718SPierre Ossman amba_release_regions(dev); 14541c6a0718SPierre Ossman } 14551c6a0718SPierre Ossman 14561c6a0718SPierre Ossman return 0; 14571c6a0718SPierre Ossman } 14581c6a0718SPierre Ossman 14591c6a0718SPierre Ossman #ifdef CONFIG_PM 14601c6a0718SPierre Ossman static int mmci_suspend(struct amba_device *dev, pm_message_t state) 14611c6a0718SPierre Ossman { 14621c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 14631c6a0718SPierre Ossman int ret = 0; 14641c6a0718SPierre Ossman 14651c6a0718SPierre Ossman if (mmc) { 14661c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 14671c6a0718SPierre Ossman 14681a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 14691c6a0718SPierre Ossman if (ret == 0) 14701c6a0718SPierre Ossman writel(0, host->base + MMCIMASK0); 14711c6a0718SPierre Ossman } 14721c6a0718SPierre Ossman 14731c6a0718SPierre Ossman return ret; 14741c6a0718SPierre Ossman } 14751c6a0718SPierre Ossman 14761c6a0718SPierre Ossman static int mmci_resume(struct amba_device *dev) 14771c6a0718SPierre Ossman { 14781c6a0718SPierre Ossman struct mmc_host *mmc = amba_get_drvdata(dev); 14791c6a0718SPierre Ossman int ret = 0; 14801c6a0718SPierre Ossman 14811c6a0718SPierre Ossman if (mmc) { 14821c6a0718SPierre Ossman struct mmci_host *host = mmc_priv(mmc); 14831c6a0718SPierre Ossman 14841c6a0718SPierre Ossman writel(MCI_IRQENABLE, host->base + MMCIMASK0); 14851c6a0718SPierre Ossman 14861c6a0718SPierre Ossman ret = mmc_resume_host(mmc); 14871c6a0718SPierre Ossman } 14881c6a0718SPierre Ossman 14891c6a0718SPierre Ossman return ret; 14901c6a0718SPierre Ossman } 14911c6a0718SPierre Ossman #else 14921c6a0718SPierre Ossman #define mmci_suspend NULL 14931c6a0718SPierre Ossman #define mmci_resume NULL 14941c6a0718SPierre Ossman #endif 14951c6a0718SPierre Ossman 14961c6a0718SPierre Ossman static struct amba_id mmci_ids[] = { 14971c6a0718SPierre Ossman { 14981c6a0718SPierre Ossman .id = 0x00041180, 1499768fbc18SPawel Moll .mask = 0xff0fffff, 15004956e109SRabin Vincent .data = &variant_arm, 15011c6a0718SPierre Ossman }, 15021c6a0718SPierre Ossman { 1503768fbc18SPawel Moll .id = 0x01041180, 1504768fbc18SPawel Moll .mask = 0xff0fffff, 1505768fbc18SPawel Moll .data = &variant_arm_extended_fifo, 1506768fbc18SPawel Moll }, 1507768fbc18SPawel Moll { 15081c6a0718SPierre Ossman .id = 0x00041181, 15091c6a0718SPierre Ossman .mask = 0x000fffff, 15104956e109SRabin Vincent .data = &variant_arm, 15111c6a0718SPierre Ossman }, 1512cc30d60eSLinus Walleij /* ST Micro variants */ 1513cc30d60eSLinus Walleij { 1514cc30d60eSLinus Walleij .id = 0x00180180, 1515cc30d60eSLinus Walleij .mask = 0x00ffffff, 15164956e109SRabin Vincent .data = &variant_u300, 1517cc30d60eSLinus Walleij }, 1518cc30d60eSLinus Walleij { 1519cc30d60eSLinus Walleij .id = 0x00280180, 1520cc30d60eSLinus Walleij .mask = 0x00ffffff, 15214956e109SRabin Vincent .data = &variant_u300, 15224956e109SRabin Vincent }, 15234956e109SRabin Vincent { 15244956e109SRabin Vincent .id = 0x00480180, 15251784b157SPhilippe Langlais .mask = 0xf0ffffff, 15264956e109SRabin Vincent .data = &variant_ux500, 1527cc30d60eSLinus Walleij }, 15281784b157SPhilippe Langlais { 15291784b157SPhilippe Langlais .id = 0x10480180, 15301784b157SPhilippe Langlais .mask = 0xf0ffffff, 15311784b157SPhilippe Langlais .data = &variant_ux500v2, 15321784b157SPhilippe Langlais }, 15331c6a0718SPierre Ossman { 0, 0 }, 15341c6a0718SPierre Ossman }; 15351c6a0718SPierre Ossman 15369f99835fSDave Martin MODULE_DEVICE_TABLE(amba, mmci_ids); 15379f99835fSDave Martin 15381c6a0718SPierre Ossman static struct amba_driver mmci_driver = { 15391c6a0718SPierre Ossman .drv = { 15401c6a0718SPierre Ossman .name = DRIVER_NAME, 15411c6a0718SPierre Ossman }, 15421c6a0718SPierre Ossman .probe = mmci_probe, 15436dc4a47aSLinus Walleij .remove = __devexit_p(mmci_remove), 15441c6a0718SPierre Ossman .suspend = mmci_suspend, 15451c6a0718SPierre Ossman .resume = mmci_resume, 15461c6a0718SPierre Ossman .id_table = mmci_ids, 15471c6a0718SPierre Ossman }; 15481c6a0718SPierre Ossman 15491c6a0718SPierre Ossman static int __init mmci_init(void) 15501c6a0718SPierre Ossman { 15511c6a0718SPierre Ossman return amba_driver_register(&mmci_driver); 15521c6a0718SPierre Ossman } 15531c6a0718SPierre Ossman 15541c6a0718SPierre Ossman static void __exit mmci_exit(void) 15551c6a0718SPierre Ossman { 15561c6a0718SPierre Ossman amba_driver_unregister(&mmci_driver); 15571c6a0718SPierre Ossman } 15581c6a0718SPierre Ossman 15591c6a0718SPierre Ossman module_init(mmci_init); 15601c6a0718SPierre Ossman module_exit(mmci_exit); 15611c6a0718SPierre Ossman module_param(fmax, uint, 0444); 15621c6a0718SPierre Ossman 15631c6a0718SPierre Ossman MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 15641c6a0718SPierre Ossman MODULE_LICENSE("GPL"); 1565